JP2011142225A - Layout designing device and method for semiconductor integrated circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a layout designing device that can make parasitic capacitance, generated between internal wiring and a power supply terminal of a functional macro, small; and to provide a layout designing method for a semiconductor integrated circuit. <P>SOLUTION: The layout designing method for the semiconductor integrated circuit includes: arranging the functional macro having a semiconductor element as a first metal layer, internal wiring as a second metal layer, and a belt-like power supply terminal as a third metal layer on the semiconductor integrated circuit; determining an arrangement direction of the functional macro in reference to a library in which arrangement result information on the semiconductor integrated circuit and information on the functional macro are registered; arranging power supply connection wiring connected to the power supply terminal as a fourth metal layer so that a length direction thereof overlaps the power supply terminal when it is determined that the functional macro is rotated by 90° from a basic state; and arranging mesh-shaped power supply wiring as a fifth metal layer on the power supply connection wiring in a direction orthogonal to the power supply connection wiring. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a layout design apparatus and method for a semiconductor integrated circuit, and more particularly to a layout design apparatus and method for a semiconductor integrated circuit used to arrange a function macro on a semiconductor integrated circuit.

  In recent years, in a semiconductor integrated circuit equipped with a large number of function macros, the demand for flexibility in arrangement of function macros, particularly 90 degree rotation arrangement, has become very strong along with the necessity of reducing the chip area for cost reduction. .

  12 to 14 show embodiments of the prior art, FIG. 12 is a plan view showing the layout of the function macro 101, FIG. 13 is a plan view showing the overall layout, and FIG. 14 is a partially enlarged view of FIG. . Hereinafter, description will be given based on these drawings.

  12 and 13, a conventional semiconductor integrated circuit 141 includes a power supply wiring 102 for supplying a power supply voltage to the function macro 101, a first insulating film (not shown), a power supply terminal 131, Two insulating films (not shown) and a power supply wiring 105 for supplying a power supply voltage to the power supply wiring 102 are sequentially stacked. That is, the power supply wiring 102 is formed on the function macro 101, the power supply terminal 131 is formed on the power supply wiring 102 via the first insulating film, and the power supply wiring 5 is formed on the power supply terminal 131 via the second insulating film. Is formed. An opening (not shown) for connecting the power supply wiring 102 and the power supply terminal 131 is provided in the first insulating film, and an opening (for connecting the power supply terminal 131 and the power supply wiring 105 is provided in the second insulating film. (Not shown) is provided. The power supply line 102 includes a plurality of low potential side power supply lines 102G and a plurality of high potential side power supply lines 102V, and the power supply line 105 includes a plurality of low potential side power supply lines 105G and a plurality of high potential side power supply lines 105V. Become. The functional macro power supply terminal 131 includes a rectangular low potential power supply terminal 131G for connecting the low potential power supply wiring 102G and the low potential power supply wiring 105G, a high potential power supply wiring 102V, and a high potential power supply wiring 105V. Are connected to each other at equal intervals.

  As shown in FIG. 14, the power supply wiring 102 of the function macro 101 is formed of the third metal layer, the power supply terminal 131 is formed of the fourth metal layer, and the power supply wiring 105 of the semiconductor integrated circuit 141 is formed of the fifth metal layer. As shown in FIG. 14, even if the power supply terminal 131 provided in the function macro 101 rotates 90 degrees, the power supply wiring 105 of the semiconductor integrated circuit 141 has a size that allows two VDD / GND to be passed through, one in total. Therefore, the function macro 101 can be freely arranged on the semiconductor integrated circuit 141.

Japanese Patent No. 3390408 (FIGS. 1 to 3)

  However, as described above, even if the power supply terminal 131 provided in the function macro 101 of the prior art is rotated by 90 degrees, a total of two VDD / GND of the power supply wiring 105 of the semiconductor integrated circuit 141 are passed one by one. Further, the power supply terminal 131 includes a rectangular low-potential-side power supply terminal 131G that connects the low-potential-side power supply wiring 102G and the low-potential-side power supply wiring 105G, a high-potential-side power supply wiring 102V, and a high-potential-side. It is composed of rectangular high-potential-side power supply terminals 131V that connect the power supply wiring 105V, and a plurality of them are alternately arranged at equal intervals. Therefore, in the layout plan view, the signal wiring (not shown) on the function macro 101 laid on the second metal layer one layer below the power supply terminal 131 which is the third metal layer overlaps. The area is wide, and the parasitic capacitance generated between the power supply terminal 131 which is the third metal layer and the signal wiring on the functional macro 101 which is the second metal layer one layer below is increased, so that the propagation delay time of the signal wiring in the macro is increased. There is a problem that becomes larger.

  According to the semiconductor integrated circuit layout designing method of the present invention, a functional macro having a semiconductor element as a first metal layer, an internal wiring as a second metal layer, and a strip-shaped power supply terminal as a third metal layer is arranged on the semiconductor integrated circuit. A macro placement step, a placement direction determination step of judging a placement direction of the function macro with reference to a library in which placement result information of the semiconductor integrated circuit and information of the function macro are registered, and the function macro from a basic state If it is determined that it is rotated by 90 degrees, a power connection wiring generation step for arranging a power connection wiring to be connected to the power supply terminal and serving as a fourth metal layer so that its longitudinal direction overlaps the power supply terminal; A first power supply wiring generation step of disposing a mesh-like power supply wiring serving as a fifth metal layer in a direction perpendicular to the power supply connection wiring on the power supply connection wiring.

  The layout design apparatus for a semiconductor integrated circuit according to the present invention includes the placement result information of the semiconductor integrated circuit, a semiconductor element as the first metal layer, internal wiring as the second metal layer, and a strip-shaped power supply terminal as the third metal layer. A library in which function macro information is registered, a macro placement unit that refers to the library and places the function macro on a semiconductor integrated circuit, and a placement direction that refers to the library and determines the placement direction of the function macro When it is determined that the determination unit and the function macro are rotated 90 degrees from the basic state, the power supply wiring to be the fourth metal layer connected to the power supply terminal is connected to the power supply terminal in the longitudinal direction. A power connection wiring generation unit disposed so as to overlap with each other, and a mesh-shaped power source that forms a fifth metal layer on the power connection wiring in a direction perpendicular to the power connection wiring And a power supply wiring generation unit to arrange the line.

  Furthermore, a program according to the present invention causes a computer to execute the layout arrangement method described above.

  In the present invention, when it is determined that the function macro is rotated 90 degrees from the basic state, the power supply connection wiring serving as the fourth metal layer connected to the power supply terminal of the function macro has the longitudinal direction of the power supply wiring. Since they are arranged so as to overlap with the terminals, via holes can be formed to electrically connect the power terminals of the functional macro and the power connection wires of the fourth metal layer in the same direction.

  According to the present invention, it is possible to provide a layout design apparatus and a layout design method for a semiconductor integrated circuit capable of reducing the parasitic capacitance generated between the internal wiring of the functional macro and the power supply terminal.

1 is a diagram showing a layout design system for a semiconductor integrated circuit according to a first embodiment of the present invention; 1 is a schematic diagram showing a layout design apparatus for a semiconductor integrated circuit according to a first embodiment of the present invention; 2 is a flow chat showing a layout design method for a semiconductor integrated circuit according to the first exemplary embodiment of the present invention; FIG. 2 is a plan view showing a functional macro layout in Embodiment 1 of the present invention; In Embodiment 1 of this invention, it is a top view which shows the layout of the function macro of the state rotated 90 degree | times. It is a top view which shows the layout of a function macro periphery when the function macro concerning this Embodiment is arrange | positioned in the basic state. It is sectional drawing in the VII-VII line of FIG. An insulating film between the metal layers is omitted. It is a top view which shows the layout of a function macro periphery in the state by which the function macro 11 concerning Embodiment 1 of this invention was rotated 90 degree | times. It is sectional drawing in the VIIII-VIIII line of FIG. It is a flowchart which shows the layout design method concerning Embodiment 2 of this invention. It is a flowchart which shows the layout design method concerning Embodiment 3 of this invention. It is a top view which shows the layout of the conventional function macro 101. FIG. It is a top view which shows the conventional whole layout. It is an enlarged view which shows FIG. It is sectional drawing in the XV-XV line | wire of FIG.

  Hereinafter, specific embodiments to which the present invention is applied will be described in detail with reference to the drawings. In this embodiment, the present invention is applied to a layout design apparatus and method for a semiconductor integrated circuit in which function macros are arranged.

  In the layout design method of the semiconductor integrated circuit according to the present embodiment, even when the function macro 11 is rotated 90 degrees from the reference state, the shape of the function macro power supply terminal is not increased or the shape is changed. It is possible to connect the power supply without having to do so. Therefore, compared to the prior art, the parasitic capacitance generated at the intersection between the functional macro signal wiring and the power supply terminal is reduced, and the propagation delay time of the functional macro signal wiring can be reduced.

  FIG. 1 is a diagram showing a layout design system according to an embodiment of the present invention. As shown in FIG. 1, in the layout design system according to this exemplary embodiment, a processing apparatus 10 and a server 18 are connected via a network 20. The server 18 is connected to a processing apparatus 10 such as an engineering workstation via a network 20 such as the Internet. The processing device 10 is a computer including a CPU, a memory (ROM (Read Only Memory) and RAM (Random Access Memory)), and the like. The processing device 10 controls the entire device, and sends an execution program and a layout design result to the server 18. Is stored in the storage device 19 in a file format. In addition, the execution program and layout design result stored in the storage device 19 are read into the internal memory. The storage device 19 is an HDD (hard disk device) or the like, and is held in a server 18 that is provided for providing an execution program. The execution program stored in the storage device 19 is downloaded to the processing device 10 via the network 20. The downloaded program is stored in a local hard disk or a memory of the processing device 10 and executed.

  Next, a layout design apparatus for a semiconductor integrated circuit according to an embodiment of the present invention will be described. FIG. 2 is a schematic diagram showing a layout design apparatus for a semiconductor integrated circuit according to the present embodiment. The layout design apparatus according to the present embodiment is a program, and the blocks shown in the figure indicate modules that perform the respective processes.

  As shown in FIG. 2, the layout design apparatus for a semiconductor integrated circuit according to the present embodiment refers to the storage device (library) 19 described above, and includes a macro placement unit 21, a placement direction determination unit 22, and a power connection wiring generation unit. 23, and a power supply wiring generation unit 24.

  In the library 19 described above, information on the arrangement result of the semiconductor integrated circuit, information on the function macro having the semiconductor element as the first metal layer, the internal wiring as the second metal layer, and the strip-shaped power supply terminal as the third metal layer, etc. are registered. ing. In the present embodiment, the library 19 is provided in the server connected via the network 20 such as the Internet, but the processing apparatus 10 may store the library 19 as a matter of course.

  The macro placement unit 21 refers to the library 19 and places the function macro on the semiconductor integrated circuit. The arrangement direction determination unit 22 refers to the library 19 and determines the arrangement direction of the function macro. When the power connection wiring generation unit 23 determines that the function macro is rotated 90 degrees from the basic state, the power connection wiring that becomes the fourth metal layer connected to the power supply terminal has the longitudinal direction of the power supply wiring. Arrange them so that they overlap the terminals. The power supply wiring generation unit 24 arranges a mesh-shaped power supply wiring serving as a fifth metal layer in a direction perpendicular to the power supply connection wiring on the power supply connection wiring.

  First, the macro wiring arrangement unit refers to the library and arranges the function macro on the semiconductor integrated circuit at a predetermined position. Next, the arrangement direction determination unit 22 determines the arrangement direction of the function macro with reference to the library in which the arrangement result information of the semiconductor integrated circuit and the information of the function macro are registered. FIG. 4 shows the reference state of the function macro. The function macro has a predetermined direction. For example, the function macro has information such that the lower left point of the function macro is the origin of the figure as the function macro direction information. When the lower left origin portion is arranged at the upper right as shown in FIG. 5, for example, it can be seen that the function macro is rotated 90 degrees. Thereby, the direction of the function macro is determined. In the present embodiment, the function macro has been described as having direction information with the lower left point as the origin, but any of the upper right, upper left, and lower right points may be used as the origin, and the direction of the function macro Any other information may be used as long as the information can be determined.

  When the power connection wiring generation unit 23 determines that the function macro is rotated 90 degrees from the basic state, the power connection wiring connected to the power terminal is copied by copying the shape of the power terminal. It arrange | positions so that a longitudinal direction may overlap with the said power supply terminal. Finally, the power supply wiring generation unit 24 arranges the mesh-shaped power supply wiring that becomes the fifth metal layer in the direction orthogonal to the power supply connection wiring on the power supply connection wiring.

  Although the wiring directions of the first to fifth metal layers are predetermined, the arrangement direction of the functional macro can be arbitrary. That is, as shown in FIG. 4, when the power terminal of the functional macro of the third metal layer is in a strip shape, if the fourth metal layer is arranged in a direction orthogonal to the strip shape, contact can be made without any problem. When the longitudinal direction and the longitudinal direction of the wiring of the fourth metal layer are the same, contact with the power supply terminal cannot be made depending on the position of the wiring of the fourth metal layer. On the other hand, in the present embodiment, the power connection wiring generation unit 23 arranges the power connection wiring of the fourth metal layer so that the longitudinal direction thereof overlaps the power terminal, so that the contact between both is easily obtained. be able to.

  Hereinafter, the layout design method of the semiconductor integrated circuit according to the present embodiment will be specifically described. FIG. 3 is a flowchart showing the layout design method of the semiconductor integrated circuit according to the present embodiment. FIG. 4 is a plan view showing the function macro layout, and FIG. 5 is a plan view showing the layout of the function macro in a state rotated 90 degrees.

  The function macro 11 is composed of basic logic elements such as NAND gates and NOR gates, counters combining them, or basic logic circuits such as memories, and these elements are formed of a first metal layer. These basic logic circuits are arranged in the function macro 11 and have a second metal layer signal wiring 14 for connecting them and a third metal layer power supply terminal (power supply wiring) 13 for supplying power to them. Have. As shown in FIG. 4, the power supply terminal 13 of the function macro 11 according to the present embodiment is defined as a power supply terminal 13 of the function macro 11 in the form of a strip-shaped power supply wire that is elongated from end to end of the function macro 11. To do. As for the power supply terminal 13, the high potential side power supply terminal and the low potential side power supply terminal are alternately arranged (not shown).

  In the library 19, information on the shape of the power supply terminal 13 of the function macro 11, position information, and the like are also registered. For example, the direction of the function macro 11 can be recognized using the lower left end of the function macro 11 as a reference. FIG. 5 shows a state in which the function macros shown in FIG. 4 are rotated 90 degrees.

  As shown in FIG. 3, first, in step S1, function macros as shown in FIG. 4 are arranged.

  FIG. 6 is a plan view showing a layout around the function macro when the function macro according to the present embodiment is arranged in a basic state. As shown in FIG. 6, the power wiring 16 of the fourth metal layer is laid on the function macro 11, a via hole is installed (not shown), and is electrically connected to the power terminal 13. Further, the power wiring 17 of the fifth metal layer also passes over the function macro 11, and a via hole is provided at an intersection with the power wiring 16 (not shown) and connected to form a mesh-shaped power wiring structure. 7 is a cross-sectional view taken along line VII-VII in FIG. An insulating film between the metal layers is omitted. In order from the lower layer, the signal wiring (layer) 14 in the second metal layer, the macro power terminal 13 and the circulating power ring 15 in the third metal layer, the power wiring 16 in the fourth metal layer, and the power wiring 17 in the fifth metal layer Are stacked. Further, a macro-circulating power ring 15 is formed around the function macro 11, and the macro-circular power ring is disposed after the function macro has been disposed (step S2).

  Here, as shown in FIG. 6, the wiring direction of each metal layer is determined in advance. The power supply terminal 13 that is the third metal layer is in the horizontal direction, the power supply wiring 16 that is the fourth metal layer is the vertical direction that is perpendicular to the power supply terminal 13, and the power supply wiring 17 that is the fifth metal wiring is the power supply. It is assumed that the horizontal direction which is a direction orthogonal to the wiring 16 is determined. Since the wiring of each metal layer is set to be arranged perpendicular to the adjacent metal layer, a contact can be generated at the intersection. Therefore, the functional macro is basically in the direction in which the longitudinal direction of the power supply terminal 13 is in the horizontal direction, that is, the direction in which the longitudinal direction coincides with the longitudinal direction of the power supply wiring 17 of the fifth metal. Since it is orthogonal to the fourth metal in the basic state, it can be connected without any problem.

  On the other hand, consider a case where the function macro 11 is arranged as shown in FIG. In this case, the longitudinal direction of the power supply terminal 13 is oriented in the vertical direction. Therefore, if the power supply wiring 16 that is the fourth metal layer on the upper layer is arranged and wired as it is, both are arranged in parallel, and depending on the position of the power supply wiring 16, there is a possibility that the power supply terminal 13 cannot be contacted. Therefore, in the layout design method according to the present embodiment, the layout direction of the function macro 11 is determined with reference to the library 19 in step S3. Then, as shown in FIG. 5, it is determined whether the function macro 11 is rotated 90 degrees from the basic state (step S4). The library 19 has direction information only in the direction irrelevant to the shape of the function macro 11, and the direction of the function macro 11 can be determined by referring to this.

  When the function macro 11 is in a basic state, that is, when the longitudinal direction of the power supply terminal 13 is horizontal, the process proceeds to the next step S7, and mesh power supply wirings 16 and 17 are arranged. The power supply wiring 16 is also a power supply connection wiring connected to the power supply terminal 13. Further, on the function macro 11, a via hole for connecting the power supply wiring 16 and the power supply terminal 13 is formed in a portion where the power supply wiring 16 intersects the power supply terminal 13 (not shown). A via hole for connecting the two is formed (not shown), the power supply of the semiconductor integrated circuit is connected, and the power supply connection flow is completed.

  On the other hand, the case where it is determined in step S4 that the function macro has been rotated 90 degrees will be described. FIG. 8 is a plan view showing a layout around the function macro in a state where the function macro 11 according to the present embodiment is rotated 90 degrees. 9 is a cross-sectional view taken along the line VIIII-VIIII of FIG.

  If it is determined in step S4 that the function macro is rotated 90 degrees, the process proceeds to step 5. In step S <b> 5, the fourth metal layer power connection wiring 16 a connected to the power supply terminal 13 is arranged so that its longitudinal direction overlaps the power supply terminal 13. In this case, simply, the shape of the power terminal 13 may be copied and the power connection wiring 16 a having the same shape as the power terminal 13 may be disposed. Or you may arrange | position so that the center of the width direction of the power supply connection wiring 16a may overlap with the center of the width direction of the power supply terminal 13 simply.

  As a result, as shown in FIG. 9, the fourth metal power connection wiring 16 a is formed at the same location and in the same shape as the power terminal 13 provided with the third metal in the function macro 11. An insulating film between the metal layers is omitted. The macro signal wiring 14, macro power supply terminal 13, circular power supply ring 15, power supply connection wiring 16a, and power supply wiring 17 are laminated in order from the lower layer.

  Next, in step S6, the remaining power supply wiring (mesh-like wiring) is arranged. That is, since the power supply wiring of the fourth metal layer is generated in step S5, the power supply wiring 17 of the fifth metal layer is laid next. Then, on the function macro 11, via holes (not shown) connecting the respective layers are formed at portions where the power supply terminals 13 and the power supply connection wirings 16a and the power supply connection wirings 16a and the power supply wirings 17 intersect. To complete the power connection flow.

  In the present embodiment, as shown in FIG. 1, the function macro is rotated 90 degrees using the recognition information in steps S3 and S3 for recognizing the arrangement direction of the function macro 11 from the arrangement result information of the semiconductor integrated circuit. Step S4 for determining whether or not the function macro 11 is rotated 90 degrees and the figure of the power supply terminal 13 in the function macro 11 is copied and superimposed on one layer of the power supply terminal. Even when the function macro 11 is rotated 90 degrees and the function macro 11 is rotated 90 degrees, the fourth metal power line (the fourth metal power line ( Connection with the power connection wiring) becomes possible. Therefore, compared to the prior art, the parasitic capacitance generated at the intersection between the function macro signal wiring 14 and the power supply wiring 3 is reduced, and the propagation delay time of the function macro signal wiring can be reduced.

  Next, a second embodiment of the present invention will be described. FIG. 10 is a flowchart showing a layout design method according to the second exemplary embodiment of the present invention. In the first embodiment, the direction of the function macro 11 is recognized in step S3. However, in the present embodiment, step S8 is provided instead.

  As shown in FIG. 10, in the function macro arrangement direction recognition step 8 of the power connection flow, as the determination information that the function macro 11 is arranged by being rotated 90 degrees, the shape of the power terminal 13 in the function macro 11, That is, it is possible to recognize the arrangement direction of the function macro based on the information on the long side and the short side. In the function macro 90 degree rotation arrangement determination step S9, it is determined from the information of the function macro arrangement direction recognition step S8 whether or not the function macro 11 has been arranged by 90 degrees, and the function macro 11 has been arranged by 90 degrees. If the function macro 11 has not been rotated 90 degrees, the same mesh power supply wiring structure forming step as in the first embodiment is performed. Move on to S7.

  In the present embodiment, by examining the shape of the power supply terminal 13 of the function macro, even if the function macro has a different direction of the power supply terminal 13 and the longitudinal direction of the terminal is vertical, the method of steps S5 and S6 is performed. Thus, even if the power supply terminal of the functional macro 11 is formed in a strip shape, it is possible to make good contact with the power supply wiring of the fourth metal layer on the upper layer.

  Next, a third embodiment of the present invention will be described. FIG. 11 is a flowchart showing a layout design method according to the third exemplary embodiment of the present invention. In the first embodiment, the power supply connection wiring 16a is arranged by copying the power supply terminal 13. However, in the present embodiment, the wiring width is appropriately adjusted.

  Instead of step 5 in the first embodiment, a power connection wiring generation step S10 is provided. In this power connection wiring generation step S10, a semiconductor manufacturing process is performed between the power connection wiring 16a of the semiconductor integrated circuit and the power terminal 13 of the function macro 11, and between the power connection wiring 16a and the power wiring 17 of the semiconductor integrated circuit. Determines a predetermined intersection area. This crossing area requires a sufficient area to form a via hole for electrically connecting the two. Therefore, a via hole of an appropriate size can be formed between the power connection wire 16a and the power terminal 13, or a via hole of an appropriate size can be formed between the power connection wire 16a and the power wire 17. The line width of the power connection wiring 16a is adjusted. In this case, not only the power supply terminal 13 is copied, but also the wiring width determined by the semiconductor process design reference library information is expanded to generate the power supply connection wiring 16a of the semiconductor integrated circuit.

  In the third embodiment of the present invention, a via hole determined by the semiconductor manufacturing process can be provided, and an effect of suppressing a power supply voltage drop is achieved.

  Next, effects of the first to third embodiments of the present invention will be described. First, as a first effect, the parasitic capacitance generated at the intersection between the function macro signal line 14 and the power supply terminal 13 is reduced as compared with the conventional technique, and the propagation delay time of the function macro signal line can be reduced. .

  The reason for this is that when the function macro 11 is rotated 90 degrees and placed in the same shape as the power terminal 13 of the function macro 11 and copied in the same direction, the power connection to the power supply wiring of the semiconductor integrated circuit is provided on one layer. This is because the power supply terminal 13 can be made small because the wiring 16a is created and connected to the power supply.

The difference in the parasitic capacitance C between the conventional technique and the arrangement method of the present embodiment can be obtained by the following capacitance calculation formula for the parallel plate of metal. The area of the flat plate is the crossing area of the signal wiring 14 in the macro and the power supply terminal 13 in the function macro 11. The distance between the flat plates is the thickness of the insulating film between the macro signal wiring 14 and the power supply terminal 13 in the function macro 11, and the dielectric constant ε is a parameter determined by the material of the insulating film. The parallel plate capacitance calculation formula for obtaining the parasitic capacitance C is as follows.
C = εS / d [F] S: Plate area [m * m]
d: Distance between flat plates [m]
ε: dielectric constant

  The overlapping area of the signal line 14 in the macro and the power supply terminal 13 on the function macro 11 is Sb in the case of the conventional technique, Sa is the case of the present embodiment, and Cb is the parasitic capacitance of the conventional technique. When the parasitic capacitance of the form is Ca, each parasitic capacitance is obtained by the following equation.

  The parasitic capacitance Cb in the prior art is Cb = ε * Sb / d

  The parasitic capacitance Ca of the present invention is Ca = ε * Sa / d.

    Cb / Ca = (ε * Sb / d) / (ε * Sa / d)

                = Sb / Sa

  As described above, the parasitic capacitance value is the ratio of the area where the macro-internal signal wiring 14 and the functional macro power supply terminal 13 overlap. This is illustrated in FIGS. 7 and 15. 7 is a cross-sectional view taken along line VII-VII in FIG. 15 is a cross-sectional view taken along line XV-XV in FIG. Although the signal wiring 14 is not shown in FIG. 15, the same shape is shown in FIG. 15 for comparison with FIG. 7.

  As a second effect, even when the direction of the power supply terminal 13 is different depending on the shape of the function macro 11, the function macro 11 can be rotated 90 degrees and arranged. The reason is that the long and short sides of the shape of the power supply terminal 13 are examined from the function macro library to recognize the arrangement direction of the function macro.

  As a third effect, a power supply voltage drop can be suppressed. The reason for this is that when the power supply terminal 13 of the function macro 11 is copied and the power supply connection wiring 16a with the power supply wiring of the semiconductor integrated circuit is formed on one layer, the wiring width determined by the design reference library information of the semiconductor process is expanded. This is because the power supply connection wiring 16a of the semiconductor integrated circuit can be generated to generate an appropriate via hole.

  It should be noted that the present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the scope of the present invention.

  For example, in the above-described embodiment, the hardware configuration has been described. However, the present invention is not limited to this, and arbitrary processing may be realized by causing a CPU (Central Processing Unit) to execute a computer program. Is possible. In this case, the computer program can be provided by being recorded on a recording medium, or can be provided by being transmitted via the Internet or another transmission medium.

DESCRIPTION OF SYMBOLS 10 Processing apparatus 11 Function macro 13 Power supply terminal 14 Signal wiring 15 Macro power ring 16 Power supply wiring 16 Power supply wiring 16a Power supply wiring 17 Power supply wiring 18 Server 19 Library 20 Network 21 Macro arrangement | positioning part 22 Arrangement direction determination part 23 Power supply connection wiring Generation unit 24 Power supply line generation unit 90 Function macro 101 Function macro 102 Power supply line 102G Low potential side power supply line 102V High potential side power supply line 105 Power supply line 105G Low potential side power supply line 105V High potential side power supply line 131 Power supply terminal 131G Low potential side Power supply terminal 131V High potential side power supply terminal 141 Semiconductor integrated circuit

Claims (17)

A macro placement step of placing a functional macro having a semiconductor element as the first metal layer, an internal wiring as the second metal layer, and a strip-shaped power supply terminal as the third metal layer on the semiconductor integrated circuit;
An arrangement direction determination step of determining an arrangement direction of the function macro with reference to a library in which the arrangement result information of the semiconductor integrated circuit and the information of the function macro are registered;
When it is determined that the function macro is rotated 90 degrees from the basic state, the power supply connection wiring to be the fourth metal layer connected to the power supply terminal is arranged so that the longitudinal direction thereof overlaps the power supply terminal Power connection wiring generation process to
A layout design method for a semiconductor integrated circuit, comprising: a first power supply wiring generation step of arranging a mesh-shaped power supply wiring serving as a fifth metal layer in a direction perpendicular to the power supply connection wiring on the power supply connection wiring.   In the power connection wiring generation process, when it is determined that the function macro is rotated 90 degrees from the basic state, the shape of the power terminal is copied and placed on the power terminal so as to overlap the power connection wiring. The layout design method for a semiconductor integrated circuit according to claim 1, wherein the layout is performed.   3. The layout design method for a semiconductor integrated circuit according to claim 2, wherein in the power connection wiring generation step, the power connection wiring formed by copying the power terminal has the same shape and the same direction as the power terminal.   4. The semiconductor integrated circuit according to claim 1, wherein in the power connection wiring generation step, the center position in the width direction of the power terminal is aligned with the center position in the width direction of the power connection wiring. Layout design method.   If it is determined that the function macro has not rotated 90 degrees from the basic state, the power connection wiring connected to the power supply terminal is arranged in a direction perpendicular to the longitudinal direction of the power supply terminal, and the power connection 5. The layout design method for a semiconductor integrated circuit according to claim 1, further comprising a second power supply wiring generation step of arranging the mesh power supply wiring in a direction orthogonal to the wiring.   6. The layout design method for a semiconductor integrated circuit according to claim 1, wherein the basic state is a state in which the longitudinal direction of the power supply terminal is the same as the longitudinal direction of the mesh-shaped power supply wiring.   The power supply connection wiring generation step includes a first wiring width adjustment step of adjusting a width of the power supply connection wiring in order to form a via hole of a predetermined size between the power supply terminal and the power supply connection wiring. 7. A layout design method for a semiconductor integrated circuit according to any one of items 1 to 6.   The power connection wiring generation step includes a second wiring width adjustment step of adjusting a width of the power connection wiring in order to form a via hole of a predetermined size between the power connection wiring and the mesh power wiring. Item 7. A layout design method for a semiconductor integrated circuit according to any one of Items 1 to 6. The library has direction information only in directions not related to the shape of the function macro,
9. The layout design method for a semiconductor integrated circuit according to claim 1, wherein in the arrangement direction determination step, a direction of the function macro is determined based on the direction information. The library has information on the shape of the power supply terminal of the function macro,
9. The layout of a semiconductor integrated circuit according to claim 1, wherein, in the arrangement direction recognition step, the direction of the functional macro is determined from the long side and the short side based on information on the shape of the power supply terminal. Design method.   11. The layout design method for a semiconductor integrated circuit according to claim 1, further comprising a step of forming a macro-circular power supply ring surrounding the functional macro after the macro placement step. A library in which information on the arrangement result of a semiconductor integrated circuit and information on a function macro having a semiconductor element as a first metal layer, an internal wiring as a second metal layer, and a strip-shaped power supply terminal as a third metal layer;
A macro placement unit that refers to the library and places the function macro on a semiconductor integrated circuit;
An arrangement direction determination unit that refers to the library and determines an arrangement direction of the function macro;
When it is determined that the function macro is rotated 90 degrees from the basic state, the power supply connection wiring to be the fourth metal layer connected to the power supply terminal is arranged so that the longitudinal direction thereof overlaps the power supply terminal A power connection wiring generation unit
A layout design apparatus for a semiconductor integrated circuit, comprising: a power supply wiring generation unit that disposes a mesh power supply wiring serving as a fifth metal layer in a direction perpendicular to the power supply connection wiring on the power supply connection wiring.   When the arrangement direction determination unit determines that the function macro has not rotated 90 degrees from the basic state, the power supply wiring generation unit transmits the power supply connection wire connected to the power supply terminal in the longitudinal direction of the power supply terminal. 13. The layout design method for a semiconductor integrated circuit according to claim 12, wherein the mesh-shaped power supply wiring is disposed in a direction orthogonal to the power supply connection wiring and further in a direction orthogonal to the power connection wiring.   14. The layout design method for a semiconductor integrated circuit according to claim 12, wherein the basic state is a state in which the longitudinal direction of the power supply terminal is the same as the longitudinal direction of the mesh power supply wiring.   The said power supply wiring production | generation part adjusts the width | variety of the said power supply connection wiring in order to form a via hole of predetermined size between the said power supply terminal and the said power supply connection wiring. A method for designing a layout of a semiconductor integrated circuit.   The power supply wiring generation unit adjusts the width of the power supply connection wiring to form a via hole of a predetermined size between the power supply connection wiring and the mesh power supply wiring. The layout design method of the semiconductor integrated circuit as described. A program for causing a computer to execute a predetermined operation,
A macro placement step of placing a functional macro having a semiconductor element as the first metal layer, an internal wiring as the second metal layer, and a strip-shaped power supply terminal as the third metal layer on the semiconductor integrated circuit;
An arrangement direction determination step of determining an arrangement direction of the function macro with reference to a library in which the arrangement result information of the semiconductor integrated circuit and the information of the function macro are registered;
When it is determined that the function macro is rotated 90 degrees from the basic state, the power supply connection wiring to be the fourth metal layer connected to the power supply terminal is arranged so that the longitudinal direction thereof overlaps the power supply terminal Power connection wiring generation process to
A first power supply wiring generation step of arranging a mesh-like power supply wiring serving as a fifth metal layer on the power supply connection wiring in a direction perpendicular to the power supply connection wiring.

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