JP2011141756A - Cpu failure detection method and cpu failure detection device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To shorten a time required for the self diagnosis of an output part, and to detect a failure of a resource of a CPU. <P>SOLUTION: The CPU failure detection method includes a step in which predetermined processing by first algorithm is executed using a first resource, and its processing result is stored in a first buffer, a step in which predetermined processing by second algorithm is executed using a second resource, and its processing result is stored in a second buffer, a step in which the processing result stored in the first buffer is compared with the processing result stored in the second buffer, and when both of them agree with each other, the processing result stored in one of the buffers is outputted to the outside, but when there is no agreement between them, an abnormality detection error is outputted, and a step in which, in the case that the processing result has been outputted to the outside, the processing result outputted to the outside is compared with the processing result stored in any buffer, and when there is no agreement between them, an abnormality detection error is outputted. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a CPU failure detection technique, and more particularly, to a CPU failure detection method and a CPU failure detection apparatus that detect a CPU failure without duplicating the CPU itself.

  Regarding a method for preventing an erroneous output of a digital device, Patent Document 1 describes that software and an output unit are duplicated.

  FIG. 3 is a block diagram for conceptually explaining the invention described in Patent Document 1. In FIG. According to Patent Document 1, as shown in the figure, the CPU 1 is provided with two programs (software) P1 and P2, and the digital output units (DO) 2A and 2B are duplicated. Here, the software P1 and P2 may have the same algorithm, but may have different algorithms. Further, the execution timing of the software P1 and P2 is executed while shifting the time with respect to each other in consideration of a case where surge noise is applied.

  FIG. 4 is a flowchart showing an embodiment described in Patent Document 1. This shows two series of software processing, which is illustrated in the form of simultaneous parallel processing, but is processed in a time-sharing manner. Here, for example, the processing on the left side is assumed to start.

  That is, the control data 11 is received and converted into a format suitable for a predetermined algorithm by the received data conversion table 12A, and then software processing 1 is executed to obtain output data 13. At 14, the output data is checked, and when it is OK (good), it is output to DO-1 (CHT: check and transfer), the relay 15A is driven and its contact 151 is operated. After the processing so far is completed, the processing on the right side is executed in the same manner as described above, and if OK, output to DO-2, the relay 15B is driven and the contact 152 is operated.

  However, software processing 1 and software processing 2 have different algorithms, and therefore, tables used for converting data are also different (12A, 12B).

  Then, when both data are prepared, the logical product of the two is obtained, and when both coincide, the data is given to the utilization apparatus side as being correct.

Japanese Patent Laid-Open No. 5-27994

  The technique described in Patent Document 1 provides software processing and its output processing in a duplex manner with a software RAS (Reliability Availability Serviceability) function. As a result, the hardware cost is reduced and the mounting area is reduced as compared with the case where all the CPUs are duplicated.

  However, since the self-diagnosis of the output unit is also executed by each of the duplicated software, there is a problem that the self-diagnosis time is long. In addition, even if the algorithm of the duplicated software is changed, there is a problem that a failure of a resource such as a register in the CPU used for executing the software cannot be detected.

  SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to reduce the time required for self-diagnosis of an output unit and to detect a CPU resource failure in a method for detecting a CPU failure without duplicating the CPU itself. To do.

  In order to solve the above-described problem, a CPU failure detection method of the present invention includes a software execution unit that includes a plurality of resources and executes read software, a first buffer that selectively stores a processing result of the software execution unit, and A CPU failure detection method in a CPU including a second buffer and an output control unit, wherein the software execution unit performs a predetermined process by a first algorithm using a first resource among the resources. Executing and storing the processing result in the first buffer, and the software execution unit executes the predetermined processing according to a second algorithm using a second resource of the resources, and A step of storing a processing result in the second buffer; and a process in which the output control unit is stored in the first buffer. When the result is compared with the processing result stored in the second buffer and the two match, the processing result stored in one of the buffers is output to the outside, and the two do not match Includes a step of outputting an abnormality detection error, and when the processing result is output to the outside, the output control unit outputs the processing result output to the outside and the processing result stored in any of the buffers. And outputting an abnormality detection error if the two do not match.

  In the present invention, the same processing is performed using different algorithms and different resources, and the processing results of both are compared. Therefore, the failure detection capability in the CPU can be improved. In addition, since the actually output processing result is compared with the processing result stored in the buffer, duplication of the output unit for diagnosing the output unit is unnecessary, and self-diagnosis is possible. It only takes one time. Thereby, the time of the self-diagnosis of an output part can be shortened.

  In order to solve the above problems, a CPU failure detection apparatus of the present invention comprises a plurality of resources, a software execution unit that executes read software, a first buffer that selectively stores a processing result of the software execution unit, and The second buffer and the processing result stored in the first buffer are compared with the processing result stored in the second buffer. If the two match, the result is stored in one of the buffers. If the two do not match, an error detection error is output, and if the processing result is output to the outside, either the processing result output to the outside The output control unit that outputs an abnormality detection error if the two do not match, and the software execution unit Predetermined processing based on the rhythm is executed using the first resource of the resources, and the processing result is stored in the first buffer, and the software execution unit uses the second algorithm. A memory storing second software for executing the predetermined process using a second resource of the resources and storing the processing result in the second buffer.

  Here, the plurality of resources can include, for example, a plurality of registers.

  According to the present invention, in the method of detecting a CPU failure without duplicating the CPU itself, the time for self-diagnosis of the output unit is shortened, and a failure in CPU resources can be detected.

It is a block diagram which shows the structure of embodiment of this invention. It is a flowchart which shows the process sequence of embodiment of this invention. It is a block diagram for demonstrating the invention described in patent document 1 notionally. 10 is a flowchart showing an embodiment described in Patent Document 1.

  Embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing the configuration of the embodiment of the present invention.

  As shown in the figure, the CPU 100 includes a software execution unit 110, a buffer A 120A, a buffer B 120B, and an output control unit 130, executes the software A 210A and the software B 210B stored in the memory 200, and outputs a processing result. It has a configuration.

  Note that the CPU 100 is assumed to have the same RAS function as the conventional one. Further, the CPU 100 and the memory 200 in which the software A 210A and the software B 210B are stored can function as a CPU failure detection device.

  The software execution unit 110 reads the software A 210A and the software B 210B converted into the execution format, and performs an execution process according to each software. The software execution unit 110 has a resource group 112 such as a plurality of registers for performing software execution processing.

  In the execution process of software, which register is used and how the memory address range to be used is assigned is left to the description of the software executed by the software execution unit 110. The memory used for software execution may exist outside the CPU 100 or may be built in the CPU 100 as one of the resources of the software execution unit 110.

  The output result of the software execution unit 110 is selectively temporarily stored in the buffer A 120A functioning as the first buffer and the buffer B 120B functioning as the second buffer. Whether the data is stored in the buffer A 120A or the buffer B 120B is left to the description of the software executed by the software execution unit 110.

  The output control unit 130 outputs the processing result of the software execution unit 110 to the outside. At this time, if the processing result stored in the buffer A 120A does not match the processing result stored in the buffer B 120B, an abnormality detection error is output without outputting to the outside. Further, when the processing result actually output does not match the processing result stored in the buffer A 120A, an abnormality detection error is output.

  In order to perform these processes, the output control unit 130 includes a buffer comparison unit 131, an output unit 132, an output monitor unit 133, an output comparison unit 134, and an abnormality notification unit 135.

  The buffer comparison unit 131 compares the processing results stored in the buffer A 120A and the buffer B 120B, and determines whether or not they match. When it is determined that the two match, the output unit 132 is notified, and when it is determined that they do not match, the abnormality notification unit 135 is notified.

  When the buffer comparison unit 131 determines that the processing results stored in the buffer A 120A and the buffer B 120B match, the output unit 132 outputs the output result stored in the buffer A 120A to the outside.

  The output monitor unit 133 acquires the processing result actually output from the output unit 132.

  The output comparison unit 134 compares the actually output processing result acquired by the output monitor unit 133 with the processing result stored in the buffer A 120A, and determines whether or not they match. If it is determined that the two do not match, the abnormality notification unit 135 is notified.

  The abnormality notification unit 135 determines that the buffer comparison unit 131 determines that the processing results stored in the buffer A 120A and the buffer B 120B do not match, or the output comparison unit 134 determines that the processing result actually output is When it is determined that the processing result stored in the buffer A 120A does not match, an abnormality detection error is output.

  In the above configuration, the roles of the buffer A 120A and the buffer B 120B may be reversed.

  Software A 210A and software B 210B are software developed to perform the same processing, and are created in a format that can be interpreted by software execution unit 110. Software A 210A and software B 210B may be in a text format or an execution format. In the case of a text format, it is converted into an execution format when read by the software execution unit 110.

  Software A 210A and software B 210B perform the same processing, but software A 210A performs processing by algorithm A, and software B 210B is created to perform processing by algorithm B different from algorithm A.

  Here, the software A 210A functions as first software, and the algorithm A functions as a first algorithm. The software B 210B functions as second software, and the algorithm B functions as a second algorithm.

  The software A 210A and the software B 210B are created so as to perform processing using different resources. That is, the allocation of registers to be used is different between software A 210A and software B 210B.

  Here, the resource used by the software A 210A functions as a first resource, and the resource used by the software B 210B functions as a second resource.

  Next, the processing procedure of this embodiment is demonstrated with reference to the flowchart of FIG. When the process is started, first, the software execution unit 110 of the CPU 100 executes the software A 210A (S101). That is, the processing by algorithm A is performed using resource A.

  Then, the processing result by the software A 210A is stored in the buffer A 120A (S102).

  Next, the software execution unit 110 of the CPU 100 executes the software B 210B (S103). That is, the processing by algorithm B is performed using resource B.

  Then, the processing result by the software B 210B is stored in the buffer B 120B (S104).

  When the processing by the software A 210A and the software B 210B is completed, the buffer comparison unit 131 compares the processing results stored in the buffer A 120A and the buffer B 120B, and determines whether or not they match (S105).

  As a result, when the two do not match (S105: No), it is considered that a resource such as a register in the CPU 100 is out of order, so the abnormality notification unit 135 outputs an abnormality detection error and ends the processing. (S109). In this case, the processing result is not output to the outside.

  As described above, in this embodiment, the same processing is performed using different algorithms and different resources, and the processing results of both are compared. Therefore, the failure detection capability in the CPU 100 can be improved.

  On the other hand, if the two match (S105: Yes), the output unit 132 outputs the processing result stored in the buffer A 120A to the outside (S106). Of course, the processing result stored in the buffer B120B may be output.

  Then, the output monitor unit 133 acquires the processing result actually output from the output unit 132 (S107). Next, the output comparison unit 134 compares the actually output processing result with the processing result stored in the buffer A 120A, and determines whether or not they match (S108). Of course, the processing result stored in the buffer B120B may be compared.

  As a result, if the two do not match (S108: No), it is considered that the output unit 132 in the CPU 100 is out of order, so the abnormality notification unit 135 outputs an abnormality detection error and ends the processing ( S109).

  As described above, in the present embodiment, since the actually output processing result is compared with the processing result stored in the buffer, the output unit for diagnosing the output unit is duplicated. Is unnecessary, and self-diagnosis is completed only once. Thereby, the time of the self-diagnosis of an output part can be shortened.

  On the other hand, if the two match (S108: Yes), it is assumed that no abnormality has been detected by the CPU 100 and the process ends normally.

  As described above, according to the present embodiment, in the method of detecting a failure of the CPU without duplicating the CPU itself, the self-diagnosis time of the output unit is shortened, and the resources of the CPU such as a register are reduced. A failure can be detected.

  When the CPU incorporates a memory in addition to a register as a resource, a failure of the built-in memory can be detected by using different memory address ranges for the software A 210A and the software B 210B. . A failure can be detected in the same manner when other resources are included.

DESCRIPTION OF SYMBOLS 110 ... Software execution part, 112 ... Resource group, 120A ... Buffer A, 120B ... Buffer B, 130 ... Output control part, 131 ... Buffer comparison part, 132 ... Output part, 133 ... Output monitor part, 134 ... Output comparison part, 135 ... Abnormality notification unit, 200 ... Memory, 210A ... Software A, 210B ... Software B

Claims (3)

CPU failure in a CPU comprising a plurality of resources, a software execution unit that executes the loaded software, a first buffer and a second buffer that selectively store processing results of the software execution unit, and an output control unit A detection method,
The software execution unit executing a predetermined process by a first algorithm using the first resource of the resources, and storing the process result in the first buffer;
The software execution unit executing the predetermined processing by a second algorithm using a second resource of the resources, and storing the processing result in the second buffer;
The output control unit compares the processing result stored in the first buffer with the processing result stored in the second buffer, and if the two match, stores in one of the buffers Output the processed result to the outside, and if both do not match, output an abnormality detection error;
When the processing result is output to the outside, the output control unit compares the processing result output to the outside with the processing result stored in one of the buffers. And a step of outputting an abnormality detection error. A software execution unit that includes a plurality of resources and executes the loaded software;
A first buffer and a second buffer for selectively storing a processing result of the software execution unit;
The processing result stored in the first buffer is compared with the processing result stored in the second buffer, and if both match, the processing result stored in any buffer is Output to the outside, if both do not match, output an abnormality detection error, and when the processing result is output to the outside, the processing result output to the outside and stored in one of the buffers Output control unit that outputs an abnormality detection error when both do not match,
First software for causing the software execution unit to execute a predetermined process according to a first algorithm using a first resource of the resources and storing the processing result in the first buffer; A memory storing second software for causing the execution unit to execute the predetermined processing by the second algorithm using the second resource of the resources and storing the processing result in the second buffer. And a CPU failure detection device.   The CPU failure detection apparatus according to claim 2, wherein the plurality of resources include a plurality of registers.