JP2011139128A - Variable-length code decoding device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provided a variable-length code decoding device capable of decoding two variable-length codes within one clock cycle, and increasing processing speed in signal processing. <P>SOLUTION: The variable-length code decoding device includes an input buffer 102 into which first data composed of a Huffman code and a variable-length code comprising an additional bit are input, a code length table 104 for storing the total bit length of the variable-length code for all of patterns of the variable-length code, a first Huffman code detection unit 112 for referring to the code-length table, detecting the first variable-length code from the first data, and outputting the entire bit length of the first variable-length code, a first shift buffer 114 for shifting the first data left by the entire bit length to output second data, a second Huffman code detection unit 122 for referring to the code length table, detecting a second variable-length code from the second data and outputting the entire bit length of the second variable-length code, and a second shift buffer 124 for shifting the second data left by the entire bit length to output third data to the input buffer. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a variable-length code decoding apparatus.

  JPEG compressed data is data that has been subjected to variable length coding with a pair of a zero run length representing the number of consecutive zeros and a subsequent non-zero coefficient. At the time of encoding, a Huffman code is obtained using a combination of zero run length and non-zero coefficient. Further, an additional bit for specifying the magnitude of the non-zero coefficient, that is, the magnitude of the AC component is determined. As shown in FIG. 3, one variable length code is composed of a combination of a Huffman code and additional bits. FIG. 3 is an explanatory diagram showing a JPEG variable-length code.

  The Huffman code is a code in which a code having a short bit length is assigned to the combination of the zero run length and the bit length of the additional bits in descending order of appearance frequency. The additional bits are a bit string necessary for restoring ± (positive or negative) and amplitude of the non-zero coefficient following the zero run length.

  The decoding of the variable length code encoded as described above is as follows: 1) A Huffman code is detected from the variable length code. 2) An index representing the number of the detected Huffman code from the head code of the Huffman code table is derived. Next, 3) Referring to a table (R / S table) of combinations of zero run length + bit length (code length) of additional bits, the zero run length of the corresponding index and the bit length of additional bits are obtained. Thereafter, 4) a bit string (additional bits) having a bit length of additional bits is cut out from the bit string following the Huffman code, and a non-zero coefficient subsequent to consecutive zeros is calculated.

  The series of operations 1) to 4) relating to the decoding of the variable-length code has the same performance (decoding of one data / one clock or more) as that of the prior art, and has no separate circuit for a specific code. Will be described with reference to FIG. FIG. 4 is a block diagram showing a configuration of a conventional variable length code decoding apparatus 10.

  The Huffman code detector 14 receives compressed data composed of variable length codes from the input buffer 12 and refers to the head code table 24 to detect a Huffman code. The head code table 24 is a table that stores information on the head code of each bit length of the Huffman code and information on the position of the head code of each bit length from the head code of the Huffman code table. When the Huffman code is detected, an index (R / S index) indicating the number of the detected Huffman code from the head code of the Huffman code table and the bit length (code) of the detected Huffman code Long).

  Then, the Huffman code detector 14 outputs the R / S index of the detected Huffman code and the bit length of the detected Huffman code to the R / S decoder 18. In the case of the DC component, since the bit length (code length) of the additional bits is determined when the Huffman code is detected, the Huffman code detection unit 14 outputs the bit length of the additional bits to the R / S decoder 18.

  The first shift buffer 16 shifts the variable length code output from the input buffer 12 to the left by the bit length of the Huffman code detected by the Huffman code detection unit 14, cuts out the beginning of the additional bits, and generates the generated data Are output to the R / S decoder 18 and the second shift buffer 22.

  The R / S table 26 referred to by the R / S decoder 18 is a table that stores a combination of the zero run length and the bit length of the subsequent additional bits as a pair of information. In the R / S table 26, Huffman codes are arranged in the order in which Huffman codes are generated.

  Based on the input R / S index and the R / S table 26, the R / S decoder 18 can obtain information on the zero run length corresponding to the R / S index and the bit length of the additional bits. Then, the R / S decoder 18 calculates a non-zero coefficient following the zero run length, and outputs the non-zero coefficient together with the zero run length to an inverse quantization unit (not shown).

  The second shift buffer 22 shifts the data output from the first shift buffer 16 to the left by the bit length of the additional bits obtained by the R / S decoder 18 and outputs the generated data to the input buffer 12. .

  The input buffer 12 connects the end of the data output from the second shift buffer 22 and the beginning of the variable length code input to the variable length code decoding device 10 so as to form a continuous bit string. Then, the input buffer 12 outputs a bit string concatenated in the next clock cycle, and decodes one variable length code.

  With the above operation, one variable length code is decoded in one clock cycle, and decoding processing of one data / one clock or more becomes possible.

JP 2002-43949 A

  In recent years, an imaging apparatus such as a digital still camera has a higher processing speed than a variable-length code decoding apparatus for the purpose of shortening the time taken to display recorded JPEG data on a display unit. It has been demanded.

  Since the compressed data of JPEG is encoded as one variable length code with a pair of zero run length and the following non-zero coefficient, in the case of a variable length code having one or more zero run length, The coefficient data obtained by decoding is two or more. Therefore, if decoding of one variable length code can be completed in one clock cycle, decoding at double speed or higher is possible.

  However, in the case of a variable length code whose zero run length is 0, even if only a specific code can be processed in one clock cycle as in Patent Document 1 (Japanese Patent Laid-Open No. 2002-43949), it can be obtained by decoding. Only one coefficient data can be obtained. Therefore, it can only be decoded at the same speed.

  Further, in the configuration of FIG. 4, if two sets of the Huffman code detection unit 14 and the R / S decoder 18 are connected in a subordinate manner, two codes can be processed within one clock cycle. However, since the shift buffers 16 and 22 are connected in four stages, the operation clock frequency is lowered and the processing capability per unit time is not much different.

  Therefore, the present invention has been made in view of the above problems, and an object of the present invention is to decode two variable length codes within one clock cycle, thereby increasing the processing speed of signal processing. It is an object of the present invention to provide a new and improved variable length code decoding device that can be improved.

  In order to solve the above problems, according to an aspect of the present invention, an input buffer to which first data composed of a variable length code composed of a combination of a Huffman code and additional bits is input, and all of the variable length codes For the pattern, a code length table that stores all the bit lengths of the variable length code and the first data are input, and the first variable length code is detected from the first data by referring to the code length table A first Huffman code detection unit that outputs the entire bit length of the detected first variable length code, and the first data is input, the first data is shifted to the left by the entire bit length, and the generated second A first shift buffer that outputs data, and second data is input, a second variable length code is detected from the second data with reference to the code length table, and all bits of the detected second variable length code are detected Output length A variable length code comprising: a 2 Huffman code detection unit; and a second shift buffer that receives the second data, shifts the second data to the left by the entire bit length, and outputs the generated third data to the input buffer A decoding device is provided.

  With this configuration, the first data composed of the variable length code composed of the combination of the Huffman code and the additional bits is input to the input buffer, and the first data is input to the code length table in the first Huffman code detection unit. , The first variable length code is detected from the first data, and the entire bit length of the detected first variable length code is output. In the first shift buffer, the first data is input, the first data is shifted to the left by the entire bit length, and the generated second data is output. Next, in the second Huffman code detector, the second data is input, the code length table is referred to, the second variable length code is detected from the second data, and all of the detected second variable length codes are detected. The bit length is output. Then, the second data is input to the second shift buffer, the second data is shifted to the left by the entire bit length, and the generated third data is output to the input buffer. Here, the code length table is a table that stores all the bit lengths that are the bit lengths of the variable length codes for all the patterns of the variable length codes.

  The first Huffman code detector generates and outputs the first bit length of the Huffman code and the first R / S index with reference to the code length table, and the second Huffman code detector generates the code length table. Referring to the R / S table for generating and outputting the second bit length of the Huffman code and the second R / S index, and storing the combination of the zero run length and the bit length of the additional bits following the zero run length as a pair of information, The first data is input, the first data is shifted to the left by the first bit length of the Huffman code, the generated fourth data is output, the fourth data is input, and the first R The first R / S decoder that calculates the first zero run length and the first non-zero coefficient following the first zero run length from the fourth data with reference to the / S index and the R / S table The second data is input, the second data is shifted to the left by the second bit length of the Huffman code, the fourth data is output, and the fifth data is input to the second R A second R / S decoder that calculates a second non-zero coefficient following the second zero run length and the second zero run length from the fifth data with reference to the / S index and the R / S table is further provided.

  With this configuration, the first Huffman code detection unit refers to the code length table, generates and outputs the first bit length of the Huffman code and the first R / S index, and the second Huffman code detection unit With reference to the length table, the second bit length of the Huffman code and the second R / S index are generated and output. In the third shift buffer, the first data is input, the first data is shifted to the left by the first bit length of the Huffman code, and the generated fourth data is output. In the first R / S decoder, the fourth data The data is input, the first R / S index and the R / S table are referred to, and the first zero run length and the first non-zero coefficient following the first zero run length are calculated from the fourth data. Further, in the fourth shift buffer, the second data is input, the second data is shifted to the left by the second bit length of the Huffman code, and the generated fifth data is output. In the second R / S decoder, The fifth data is input, the second R / S index and the R / S table are referenced, and the second zero run length and the second non-zero coefficient following the second zero run length are calculated from the fifth data. The

  In order to solve the above problems, according to another aspect of the present invention, an input buffer to which first data composed of a variable length code composed of a combination of a Huffman code and additional bits is input, and a zero run length is 0. For the variable length code, the specific code table for storing all the bit lengths that are the bit length of the variable length code and the first data are input, and the first variable is referred to the first variable by referring to the specific code table. A first specific code detection unit that detects a long code and outputs the entire bit length of the detected first variable length code; a head code table that stores an index of a head code in each bit length of the Huffman code; 1 data is input, the Huffman code is detected from the first data with reference to the head code table, the first bit length of the detected Huffman code, and the first R / S index A first Huffman code detector for output, an R / S table for storing a combination of zero run length and the bit length of the subsequent additional bits as a pair of information, first data is input, and the first R / S index , Referring to the R / S table, the first R / S decoder for calculating the first zero run length and the first non-zero coefficient following the first zero run length from the first data, and the first data are input. When the specific code table is referenced, the first data is shifted to the left by the entire bit length of the first variable length code, and when the head code table is referenced, the first data is shifted by the first bit length of the Huffman code. When the first data is shifted to the left by an additional bit, the first data is shifted to the left by the bit length of the additional bit and the generated second data is output. And the second data is input, the second variable length code is detected from the second data with reference to the specific code table, and the entire bit length of the detected second variable length code is output. The code detector and the second data are input, the Huffman code is detected from the second data with reference to the head code table, and the second bit length of the detected Huffman code and the second R / S index are output. The second Huffman code detecting unit, the second data is input, the second R / S index and the R / S table are referred to, and the second data is followed by the second zero run length and the second zero run length. When the second data is input and the specific code table is referred to, the second data is shifted to the left by the entire bit length of the second variable length code. And leading sign table When the second data is referenced, the second data is shifted left by the second bit length of the Huffman code. When the head of the second data is an additional bit, the second data is shifted left by the bit length of the additional bit. And a variable-length code decoding device including a second shift buffer that outputs the generated third data.

With this configuration, first data composed of a variable-length code composed of a combination of a Huffman code and additional bits is input to the input buffer, and the first data is input to the specific code table in the first specific code detection unit. , The first variable length code is detected from the first data, and the entire bit length of the detected first variable length code is output. Here, the specific code table is a table that stores all the bit lengths that are the bit lengths of the variable length codes for the variable length codes having zero run length of zero. Further, in the Huffman code detector, the first data is input, the head code table is referenced, the Huffman code is detected from the first data, and the first bit length and the first R / S index of the detected Huffman code Is output. Here, the head code table is a table in which the index of the head code in each bit length of the Huffman code is stored. Further, in the first R / S decoder, the first data is input, the first R / S index and the R / S table are referenced, and the first zero run length and the first zero run length follow from the first data. A first non-zero coefficient is calculated. Here, the R / S table is a table that stores a combination of the zero run length and the bit length of the subsequent additional bits as a pair of information. In the first shift buffer, when the first data is input and the specific code table is referred to, the first data is shifted to the left by the entire bit length, and when the first code table is referred to, the first data is referred to. Is shifted to the left by the code length of the Huffman code, and when the top of the first data is an additional bit, the first data is shifted to the left by the bit length of the additional bit, and the generated second data is output. .
In the second specific code detector, the second data is input, the specific code table is referred to, the second variable length code is detected from the second data, and all the bits of the detected second variable length code are detected. The length is output. Furthermore, in the second Huffman code detection unit, the second data is input, the head code table is referenced, the Huffman code is detected from the second data, the second bit length of the detected Huffman code, A 2R / S index is output. In the second R / S decoder, the second data is input, the second R / S index and the R / S table are referenced, and the second data is followed by the second zero run length and the second zero run length. A second non-zero coefficient is calculated. When the second data is input and the specific code table is referred to in the second shift buffer, the second data is shifted to the left by the entire bit length of the second variable length code, and the head code table is referred to. When the second data is shifted to the left by the second bit length of the Huffman code, and the top of the second data is an additional bit, the second data is shifted to the left by the bit length of the additional bit and generated. The third data is output.

  As described above, according to the present invention, two variable length codes can be decoded within one clock cycle, and the processing speed of signal processing can be improved.

It is a block diagram which shows the structure of the variable-length code decoding apparatus 100 which concerns on the 1st Embodiment of this invention. It is a block diagram which shows the structure of the variable-length code decoding apparatus 200 which concerns on the 2nd Embodiment of this invention. It is explanatory drawing which shows the variable length code | symbol of JPEG. It is a block diagram which shows the structure of the conventional variable length code decoding apparatus.

  Exemplary embodiments of the present invention will be described below in detail with reference to the accompanying drawings. In addition, in this specification and drawing, about the component which has the substantially same function structure, duplication description is abbreviate | omitted by attaching | subjecting the same code | symbol.

(First embodiment)
A variable-length code decoding apparatus 100 according to the first embodiment of the present invention will be described with reference to FIG. FIG. 1 is a block diagram showing a configuration of a variable-length code decoding apparatus 100 according to this embodiment.

  The variable-length code decoding apparatus 100 includes a first Huffman code detection unit 112, a second Huffman code detection unit 122, a first shift buffer 114, a second shift buffer 124, a first R / S decoder 116, and a second R / S decoder 126, third shift buffer 118, fourth shift buffer 128, R / S table 106, code length table 104, and the like.

  The first Huffman code detection unit 112 and the second Huffman code detection unit 122 detect the Huffman code and generate parameters necessary for subsequent processing.

  The first R / S decoder 116 and the second R / S decoder 126 refer to the parameters generated by the first Huffman code detection unit 112, the second Huffman code detection unit 122, and the R / S table 106, and zero. Run lengths (first zero run length, second zero run length) and non-zero coefficients (first coefficient, second coefficient) are calculated and output.

  The first shift buffer 114 and the second shift buffer 124 shift the data to the left by the bit length (all bit lengths) of the variable length code (Huffman code + additional bits) and output the generated data.

  The third shift buffer 118 and the fourth shift buffer 128 shift the data to the left by the bit length of the Huffman code (Huffman code length) and output the data.

  The R / S table 106 is a table that stores a combination of zero run lengths and bit lengths of additional bits following the zero run lengths as a pair of information. In the R / S table 106, Huffman codes are arranged in the order in which Huffman codes are generated.

  The code length table 104 stores bit lengths for all patterns of combinations of Huffman codes and additional bits (variable length codes). Here, the bit length of the combination of Huffman code and additional bits (variable length code) is also referred to as the total bit length. For example, the code length table 104 stores a bit length for each of 162 patterns in the case of a JPEG luminance AC component and a color difference AC component.

  Next, the operation of the variable length code decoding apparatus 100 according to this embodiment will be described.

  When compressed data including a variable length code (first variable length code) is input, the first Huffman code detection unit 112 detects the variable length code with reference to the code length table 104. The first Huffman code detection unit 112 refers to the code length table 104, and similarly to the conventional Huffman code detection, the bit length of the Huffman code included in the first variable length code, the R / S index, and the DC In the case of the variable length code of the component, the bit length of the additional bit of the DC component is generated. Furthermore, in the present embodiment, the first Huffman code detection unit 112 can generate the entire bit length of the variable length code by referring to the code length table 104.

  The first Huffman code detector 112 outputs the entire bit length to the first shift buffer 114, outputs the R / S index and the bit length of the additional bits of the DC component to the first R / S decoder 116, and outputs the Huffman code. The bit length is output to the third shift buffer 118.

  The first shift buffer 114 shifts the first variable length code output from the input buffer 102 to the left by the entire bit length of the variable length code detected by the first Huffman code detector 112. Then, the first shift buffer 114 outputs the generated data to the second Huffman code detection unit 122, the second shift buffer 124, and the fourth shift buffer 128 in the latter half.

  The third shift buffer 118 shifts the output of the first variable length code data from the input buffer 102 to the left by the bit length of the Huffman code detected by the first Huffman code detection unit 112, and outputs the first R / S Output to the decoder 116.

  Based on the R / S index output from the first Huffman code detection unit 112 and the R / S table 106, the first R / S decoder 116 has a zero run length corresponding to the R / S index and the bit length of the additional bits. Information can be obtained.

  Then, the first R / S decoder 116 calculates a non-zero coefficient (first coefficient) subsequent to the zero run length, and outputs the first zero run length and the first coefficient to an inverse quantization unit (not shown). To do. When the variable-length code is a DC component, a coefficient is calculated based on the bit length of the DC additional bits output from the first Huffman code detection unit 112, and the zero-run length is set to 0 and output.

  Since the first shift buffer 114 shifts the bit string for the first variable length code (for all bit lengths), the data input to the second Huffman code detector 122 starts from the second variable length code. Become.

  When the compressed data including the second variable length code is input, the second Huffman code detection unit 122 refers to the code length table 104 and detects the variable length code. The second Huffman code detection unit 122 refers to the code length table 104 and generates a Huffman code length, an R / S index, and an entire bit length included in the second variable length code. The second Huffman code detector 122 outputs the entire bit length to the second shift buffer 124, outputs the R / S index to the second R / S decoder 126, and outputs the Huffman code length to the fourth shift buffer 128.

  The second shift buffer 124 shifts the second variable length code output from the first shift buffer 114 to the left by the entire bit length of the variable length code detected by the second Huffman code detector 122, and generates the second variable length code. The processed data is output to the input buffer 102.

  The fourth shift buffer 128 shifts the first variable length code output from the first shift buffer 114 to the left by the bit length of the Huffman code detected by the second Huffman code detector 122, and generates data Is output to the second R / S decoder 126.

  The second R / S decoder 126, based on the R / S index output from the second Huffman code detector 122 and the R / S table 106, the zero run length corresponding to the R / S index and the bit length of the additional bits ( Code length) information can be obtained.

  Then, the second R / S decoder 126 calculates a non-zero coefficient (second coefficient) subsequent to the zero run length, and outputs the second zero run length and the second coefficient to the inverse quantization unit (inverse quantization unit). To do.

  The input buffer 102 connects the tail of the variable length code output from the second shift buffer 124 and the beginning of the variable length code input to the variable length code decoding apparatus 100 so as to form a continuous bit string. The input buffer 102 outputs a bit string in the next clock cycle, and decodes two variable length codes in one clock cycle.

  As described above, according to the present embodiment, two variable length codes can be decoded in one clock cycle, and at least double speed decoding processing can be realized.

(Second Embodiment)
Next, a variable-length code decoding apparatus 200 according to the second embodiment of the present invention will be described with reference to FIG. In the variable length code decoding apparatus 100 according to the first embodiment described above, the code length table 104 is prepared for all patterns of combinations of Huffman codes and additional bits (variable length codes). Therefore, there is a problem that the circuit scale becomes extremely large. On the other hand, according to the second embodiment of the present invention, the processing capability is the same, and the circuit scale is realistic. FIG. 2 is a block diagram showing a configuration of the variable length code decoding apparatus 200 according to the present embodiment.

  The specific code table 204 in this embodiment corresponds to the code length table 104 of the first embodiment corresponding to only a specific code (zero run length is 0). That is, the specific code table 204 stores all bit lengths for a pattern of a combination of Huffman codes and additional bits (variable length codes) in which the zero run length is 0.

  Further, the variable length code decoding apparatus 200 of the present embodiment further includes a first specific code processing unit 212, a second specific code processing unit 232, and a first bit length selection unit as compared with the configuration of the first embodiment. 224, a second bit length selection unit 244, a first output selection unit 226, and a second output selection unit 246.

  When the first specific code processing unit 212 and the second specific code processing unit 232 detect the specific code, the first specific code processing unit 212 and the second specific code processing unit 232 output the bit length (all bit lengths) of the specific code (Huffman code + additional bits) and the corresponding zero run length. Then, the bit length of the additional bits following the zero run length is obtained by referring to the specific code table 204. In addition, the first specific code processing unit 212 and the second specific code processing unit 232 calculate a non-zero coefficient following the zero run length, and output the non-zero coefficient together with the zero run length. Furthermore, the first specific code processing unit 212 and the second specific code processing unit 232 output a flag (SHIT) indicating that the specific code has been detected.

  The first Huffman code detection unit 214 and the second Huffman code detection unit 234 basically perform the same operation as the conventional Huffman code detection unit 14, but set a flag (NIT) indicating that a code other than the specific code has been detected. Output. The first R / S decoder 216 and the second R / S decoder 236 also basically perform the same operation as the conventional R / S decoder 18.

  The first bit length selection unit 224 selects and selects a significant bit length output from the first specific code processing unit 212, the first Huffman code detection unit 214, and the first R / S decoder 216. The obtained bit length is output to the first shift buffer 222. The first shift buffer 222 shifts the input variable length code data to the left according to the bit length output by the first bit length selection unit 224, and outputs the generated data. The same applies to the second bit length selection unit 244 and the second shift buffer 242.

  The first output selection unit 226 selects a significant zero run length and non-zero coefficient output from the first specific code processing unit 212 and the first R / S decoder 216, and selects the selected zero run length. The coefficient is output to an inverse quantization unit (not shown). The same applies to the second output selection unit 246. Desired processing can be performed by connecting two sets of the three processing circuits of the specific code processing unit, the Huffman code detection unit, and the R / S decoder.

  Next, the operation of the variable length code decoding apparatus 200 according to this embodiment will be described.

  First, a case where the variable length code output from the input buffer 202 is a specific code will be described. When the variable length code output from the input buffer 202 is a specific code, two variable length codes are processed within the clock cycle.

  The first variable length code that is the specific code is processed by the first specific code processing unit 212 with reference to the specific code table 204. Then, the first bit length selection unit 224 selects the entire bit length based on the first variable length code based on the flag (SHIT). The first output selection unit 226 selects the zero run length and non-zero coefficient based on the first variable length code based on the flag (SHIT). As a result, the full bit length, zero run length, and non-zero coefficient based on the first variable length code are output.

  The first shift buffer 222 shifts the first variable length code output from the input buffer 202 to the left by the entire bit length of the first variable length code detected by the first specific code processing unit 212. Then, the first shift buffer 222 outputs the generated data to the second specific code processing unit 232, the second Huffman code detection unit 234, the second R / S decoder 236, and the second shift buffer 242 in the latter half. .

  The first output selection unit 226 outputs the zero run length and non-zero coefficient decoded from the first variable length code to the inverse quantization unit (not shown), and the decoding of the first variable length code is completed. To do.

  When the second variable length code is also a specific code following the first variable length code, the second specific code processing unit 232 refers to the specific code table 204 and is output from the first shift buffer 222. The second variable length code is decoded. The zero run length and non-zero coefficient obtained by decoding are output from the second output selection unit 246 to an inverse quantization unit (not shown) based on the flag (SHIT). Based on the flag (SHIT), the second shift buffer 242 detects all the second variable length codes detected by the second specific code processing unit 232 from the second variable length code output from the first shift buffer 222. Shift left by the bit length. Then, the second shift buffer 242 outputs the generated data to the input buffer 202.

  The input buffer 202 connects the tail of the variable length code output from the second shift buffer 242 and the beginning of the variable length code input to the variable length code decoding apparatus 200 so as to form a continuous bit string. The bit string generated by concatenation is output from the input buffer 202 in the next clock cycle.

  When the second variable length code following the first variable length code is other than the specific code, the second Huffman code detection unit 234 refers to the head code table 206 and refers to the R / S index and the bits of the Huffman code. Print the length.

  The R / S index is output after being delayed by one clock in the D flip-flop (D-FF) 252 because the first R / S decoder 216 performs decoding in the next clock cycle. The second shift buffer 242 uses the second variable length code Huffman code detected by the second Huffman code detector 234 to detect the second variable length code output from the first shift buffer 222 based on the flag (NHIT). Shifting to the left by the length, the beginning of the additional bits is cut out and output to the input buffer 202. Then, it is output from the input buffer 202 in the next clock cycle.

  In the next clock cycle, the R / S table 208 is referred to, the first R / S decoder 216 decodes the zero run length and the non-zero coefficient, and the first output selection unit 226 based on the flag (NHIT). To the inverse quantization unit (not shown). At this time, the NHIT from the second Huffman code detector 234 is delayed by one clock in the D-FF 254 and output in order to cause the first output selector 226 to select the output of the first R / S decoder 216.

  When the first variable length code is not a specific code, the first Huffman code detection unit 214 obtains the R / S index and the Huffman code length of the detected Huffman code. Then, the first shift buffer 222 shifts the variable length code output from the input buffer 202 to the left by the bit length of the Huffman code. At this time, nothing is output from the first output selection unit 226.

  Referring to the R / S table 208, the second R / S decoder 236 calculates a zero run length and a non-zero coefficient based on the R / S index and the data output from the first shift buffer 222. Then, the second output selection unit 246 outputs the second zero run length and the second coefficient to the inverse quantization unit (not shown). The second shift buffer 242 shifts the data output from the first shift buffer 222 to the left by the bit length of the additional bits, and outputs the generated data to the input buffer 202. The input buffer 202 connects the end of the data output from the second shift buffer 242 and the beginning of the variable length code data input to the variable length code decoding apparatus 100 so as to form a continuous bit string. Then, the input buffer 202 outputs a bit string in the next clock cycle, and decodes one variable length code.

  As described above, according to the present embodiment, an increase in circuit scale can be suppressed, and two variable length codes can be decoded within one clock cycle, that is, a decoding process can be performed at a double speed at least. Become.

  The preferred embodiments of the present invention have been described in detail above with reference to the accompanying drawings, but the present invention is not limited to such examples. It is obvious that a person having ordinary knowledge in the technical field to which the present invention pertains can come up with various changes or modifications within the scope of the technical idea described in the claims. Of course, it is understood that these also belong to the technical scope of the present invention.

10, 100, 200 Variable length code decoding device 12, 102, 202 Input buffer 14 Huffman code detector 16 First shift buffer 18 R / S decoder 22 Second shift buffer 24, 206 First code table 26, 208 R / S table 104 Code length table 106 R / S table 112, 214 First Huffman code detector 114, 222 First shift buffer 116, 216 First R / S decoder 118 Third shift buffer 122, 234 Second Huffman code detector 124, 242 Second shift buffer 126, 236 Second R / S decoder 128 Fourth shift buffer 204 Specific code table 212 First specific code processing unit 224 First bit length selection unit 226 First output selection unit 244 Second bit length selection unit 246 First 2-output selector

Claims (3)

An input buffer to which first data composed of a variable length code composed of a combination of a Huffman code and additional bits is input;
A code length table that stores all bit lengths that are bit lengths of the variable length codes for all patterns of the variable length codes;
The first data is input, the first variable length code is detected from the first data with reference to the code length table, and the detected all bit lengths of the first variable length code are output. A 1 Huffman code detector;
A first shift buffer that receives the first data, shifts the first data to the left by the entire bit length, and outputs the generated second data;
The second data is input, the second variable length code is detected from the second data with reference to the code length table, and the detected total bit length of the second variable length code is output. A 2 Huffman code detector;
A variable-length code decoding apparatus comprising: a second shift buffer that receives the second data, shifts the second data to the left by the entire bit length, and outputs the generated third data to the input buffer. The first Huffman code detection unit generates and outputs a first bit length of the Huffman code and a first R / S index with reference to the code length table,
The second Huffman code detection unit generates and outputs a second bit length of the Huffman code and a second R / S index with reference to the code length table,
An R / S table that stores a combination of a zero run length and a bit length of the subsequent additional bits as a pair of information;
A third shift buffer that receives the first data, shifts the first data to the left by the first bit length of the Huffman code, and outputs the generated fourth data;
The fourth data is input, the first R / S index and the R / S table are referred to, and the first zero run length and the first non-zero length following the first zero run length are referred to from the fourth data. A first R / S decoder for calculating a zero coefficient;
A fourth shift buffer that receives the second data, shifts the second data to the left by the second bit length of the Huffman code, and outputs the generated fifth data;
When the fifth data is input and the second R / S index and the R / S table are referenced, the second zero run length and the second non-zero run length following the second zero run length are referred to from the fifth data. The variable length code decoding apparatus according to claim 1, further comprising a second R / S decoder that calculates a zero coefficient. An input buffer to which first data composed of a variable length code composed of a combination of a Huffman code and additional bits is input;
For the variable length code with zero run length of 0, a specific code table that stores all bit lengths that are the bit length of the variable length code;
The first data is input, the first variable length code is detected from the first data with reference to the specific code table, and the detected total bit length of the first variable length code is output. 1 specific code detector;
A head code table storing an index of the head code in each bit length of the Huffman code;
The first data is input, the Huffman code is detected from the first data with reference to the head code table, and the first bit length of the detected Huffman code and the first R / S index are output. A first Huffman code detector;
An R / S table that stores a combination of a zero run length and a bit length of subsequent additional bits as a pair of information;
The first data is input, the first R / S index and the R / S table are referred to, the first zero run length and the first non-zero length following the first zero run length from the first data. A first R / S decoder for calculating a zero coefficient;
When the first data is input and the specific code table is referred to, the first data is left-shifted by the entire bit length of the first variable length code, and the head code table is referenced The first data is shifted to the left by the first bit length of the Huffman code, and when the head of the first data is an additional bit, the first data is shifted to the left by the bit length of the additional bit. A first shift buffer for outputting the generated second data;
The second data is input, the second variable length code is detected from the second data with reference to the specific code table, and the detected total bit length of the second variable length code is output. Two specific code detectors;
The second data is input, the Huffman code is detected from the second data with reference to the head code table, and the second bit length of the detected Huffman code and the second R / S index are output. A second Huffman code detector;
The second data is input, the second R / S index and the R / S table are referred to, the second zero run length from the second data and the second non-run length following the second zero run length. A second R / S decoder for calculating a zero coefficient;
When the second data is input and the specific code table is referenced, the second data is left-shifted by the entire bit length of the second variable length code, and the head code table is referenced The second data is shifted to the left by the second bit length of the Huffman code, and when the top of the second data is an additional bit, the second data is shifted to the left by the bit length of the additional bit. A variable-length code decoding apparatus comprising: a second shift buffer that outputs the generated third data.

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