JP2011137230A - Method for manufacturing self-organized nanostructured thin film by flocculation phenomenon - Google Patents
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- 239000010409 thin film Substances 0.000 title claims abstract description 99
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 43
- 238000000034 method Methods 0.000 title abstract description 49
- 230000016615 flocculation Effects 0.000 title abstract 2
- 238000005189 flocculation Methods 0.000 title abstract 2
- 238000010438 heat treatment Methods 0.000 claims abstract description 31
- 229910052751 metal Inorganic materials 0.000 claims abstract description 29
- 239000002184 metal Substances 0.000 claims abstract description 29
- 239000002086 nanomaterial Substances 0.000 claims abstract description 29
- 239000000758 substrate Substances 0.000 claims abstract description 23
- 239000004065 semiconductor Substances 0.000 claims abstract description 18
- 239000000126 substance Substances 0.000 claims abstract description 12
- 238000000151 deposition Methods 0.000 claims abstract description 11
- 239000013078 crystal Substances 0.000 claims abstract description 8
- 230000015572 biosynthetic process Effects 0.000 claims abstract description 6
- 230000002776 aggregation Effects 0.000 claims description 19
- 238000004220 aggregation Methods 0.000 claims description 12
- AXZKOIWUVFPNLO-UHFFFAOYSA-N magnesium;oxygen(2-) Chemical compound [O-2].[Mg+2] AXZKOIWUVFPNLO-UHFFFAOYSA-N 0.000 claims description 11
- CPLXHLVBOLITMK-UHFFFAOYSA-N magnesium oxide Inorganic materials [Mg]=O CPLXHLVBOLITMK-UHFFFAOYSA-N 0.000 claims description 9
- 239000000395 magnesium oxide Substances 0.000 claims description 9
- 229910052709 silver Inorganic materials 0.000 claims description 5
- 229910052737 gold Inorganic materials 0.000 claims description 4
- 229910052742 iron Inorganic materials 0.000 claims description 4
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 claims description 4
- 229910052763 palladium Inorganic materials 0.000 claims description 4
- 229910018072 Al 2 O 3 Inorganic materials 0.000 claims description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 3
- 229910052802 copper Inorganic materials 0.000 claims description 3
- 239000011521 glass Substances 0.000 claims description 3
- 229910052697 platinum Inorganic materials 0.000 claims description 3
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 3
- 229910052718 tin Inorganic materials 0.000 claims description 3
- 229910052723 transition metal Inorganic materials 0.000 claims description 3
- 150000003624 transition metals Chemical group 0.000 claims description 3
- 238000005530 etching Methods 0.000 abstract description 14
- 239000010408 film Substances 0.000 abstract description 13
- 230000006866 deterioration Effects 0.000 abstract description 3
- 230000008569 process Effects 0.000 description 22
- 238000005054 agglomeration Methods 0.000 description 7
- 238000002488 metal-organic chemical vapour deposition Methods 0.000 description 5
- 238000001451 molecular beam epitaxy Methods 0.000 description 5
- 230000008859 change Effects 0.000 description 4
- 150000002739 metals Chemical class 0.000 description 4
- 238000004544 sputter deposition Methods 0.000 description 4
- 239000003989 dielectric material Substances 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 238000007740 vapor deposition Methods 0.000 description 3
- 230000015556 catabolic process Effects 0.000 description 2
- 238000006731 degradation reaction Methods 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 230000007613 environmental effect Effects 0.000 description 2
- 238000002474 experimental method Methods 0.000 description 2
- 238000003306 harvesting Methods 0.000 description 2
- 230000009467 reduction Effects 0.000 description 2
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 1
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 1
- 229910052799 carbon Inorganic materials 0.000 description 1
- 238000003486 chemical etching Methods 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000010894 electron beam technology Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 238000001755 magnetron sputter deposition Methods 0.000 description 1
- 238000001465 metallisation Methods 0.000 description 1
- 239000002105 nanoparticle Substances 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 231100000614 poison Toxicity 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
- 238000001338 self-assembly Methods 0.000 description 1
- 238000004904 shortening Methods 0.000 description 1
- 239000004332 silver Substances 0.000 description 1
- 230000002269 spontaneous effect Effects 0.000 description 1
- 230000003746 surface roughness Effects 0.000 description 1
- 230000008646 thermal stress Effects 0.000 description 1
- 238000000427 thin-film deposition Methods 0.000 description 1
- 239000003440 toxic substance Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02436—Intermediate layers between substrates and deposited layers
- H01L21/02439—Materials
- H01L21/02491—Conductive materials
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B82—NANOTECHNOLOGY
- B82B—NANOSTRUCTURES FORMED BY MANIPULATION OF INDIVIDUAL ATOMS, MOLECULES, OR LIMITED COLLECTIONS OF ATOMS OR MOLECULES AS DISCRETE UNITS; MANUFACTURE OR TREATMENT THEREOF
- B82B1/00—Nanostructures formed by manipulation of individual atoms or molecules, or limited collections of atoms or molecules as discrete units
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
- H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
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Abstract
Description
本発明は誘電体、半導体、金属などの薄膜のナノ構造の製造方法に関するもので、具体的には凝集現象（agglomeration phenomenon）を用いて誘電体、半導体、金属などの薄膜の自己組織化によるナノ構造薄膜を製造する方法及びその方法により製造されるナノ構造薄膜に関するものである。 The present invention relates to a method for manufacturing a nanostructure of a thin film such as a dielectric, semiconductor, or metal. Specifically, the nanostructure is obtained by self-organization of a thin film such as a dielectric, semiconductor, or metal using an agglomeration phenomenon. The present invention relates to a method for producing a structural thin film and a nanostructure thin film produced by the method.
近年、電子通信機器などの小型化によって、電子部品の集積化に対する関心が高まっている。このための優先課題の一つは、薄膜工程での素子の微細化と、それに関わる費用の節減である。数マイクロ、若しくは数ナノメーターのスケールにパターン化された誘電体薄膜の場合、エネルギー・ハーベスト（Energy harvest）技術などの分野に使用されている。ナノスケールの規模で高度にパターン化された半導体薄膜の場合、その優れた光学特性や電気的特性のため、半導体レーザーや素子として使用されている。
現代の電子部品の基盤的なMOSFET（モスフェット：Metal-Oxide-Semiconductor Field-Effect Transistor（電界効果トランジスタ））工程を例に挙げると、一つのMOSFET構造を製造するためには、薄膜蒸着や蝕刻の工程を数回繰り返す必要がある。
この蝕刻工程においてナノスケールの大きさでパターンを製造するためには、光蝕刻法や電子ビーム蝕刻法などが現在用いられている。このような過程を経て生み出されるナノ・パターン薄膜の製造にはコストが掛かるばかりでなく、作業工程の長時間化、作業中に使用される有毒物質の排出、化学変化による薄膜特性の低下などが問題点として指摘されており、これらの問題点を解決するために多様な代替手法が模索されている。
また、既存のボトム-アップ（Bottom-up）方式を用いた自己組織化ナノ薄膜形成技術の大半は、分子線エピタキシャル(MBE)装置や有機金属気相成長（MOCVD/MOVPE）装置を使用したものである。MBEで製造される自己組織化されたナノ構造薄膜は質が良く歩留まりが高い。しかし、蒸着速度が遅く、大きな基板を用いる事ができないなど生産性が悪く、且つ超高真空を維持させる必要があるためコストの面でも問題がある。MOCVDを用いた場合、MBEに比べ生産性は向上するが、利用できる成膜温度や基板・原料ガスに制約があること、低温での膜の質が悪いこと、有機金属に含まれる炭素が不純物として混入し易く膜の均一性が悪いこと等、利便性や歩留まり等の面で問題がある。
In recent years, interest in integration of electronic components has increased due to the miniaturization of electronic communication devices and the like. One of the priority issues for this purpose is the miniaturization of elements in the thin film process and the associated cost savings. In the case of a dielectric thin film patterned on the scale of several micrometers or several nanometers, it is used in fields such as energy harvesting (Energy harvesting) technology. In the case of a semiconductor thin film highly patterned on a nanoscale scale, it is used as a semiconductor laser or device because of its excellent optical characteristics and electrical characteristics.
Taking the basic MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) process of modern electronic components as an example, in order to manufacture a single MOSFET structure, thin film deposition or etching is required. It is necessary to repeat the process several times.
In order to manufacture a pattern with a nano-scale size in this etching process, a light etching method, an electron beam etching method, or the like is currently used. The manufacturing of nano-patterned thin films produced through these processes is not only costly, but also increases the work process time, discharges toxic substances used during work, and degrades thin film properties due to chemical changes. It has been pointed out as a problem, and various alternative methods are being sought for solving these problems.
In addition, most of the existing self-organized nano thin film formation technology using the bottom-up method uses molecular beam epitaxy (MBE) equipment and metal organic chemical vapor deposition (MOCVD / MOVPE) equipment. It is. The self-assembled nanostructured thin film produced by MBE has good quality and high yield. However, the deposition rate is slow, the productivity is poor, such as the inability to use a large substrate, and there is a problem in terms of cost because it is necessary to maintain an ultra-high vacuum. When MOCVD is used, productivity is improved compared to MBE, but there are restrictions on the available film formation temperature, substrate and source gas, poor film quality at low temperatures, and carbon contained in organic metals is an impurity. There are problems in terms of convenience, yield, etc., such as being easy to be mixed and having poor uniformity of the film.
本発明は、前記したように既存の薄膜製造工程で行われている蝕刻工程又はボトム-アップ方式を用いた自己組織化ナノ薄膜形成技術の問題点である高コスト、製造工程の複雑化や長時間化、膜の質の低下などを解決するためのものである。本発明においては、 誘電体、半導体、金属などの薄膜を自己組織化させるために、凝集現象が起こる特定の物質を中間層として選択して蒸着させることによって、薄膜固有の特性の低下を止め、蝕刻工程などの複雑な工程を要しない、高度に制御されたナノ構造薄膜を製造することができる方法、及びその方法により製造されたナノ薄膜構造を提供することを目的とする。 As described above, the present invention is a problem of the etching process performed in the existing thin film manufacturing process or the self-organized nano thin film forming technique using the bottom-up method, which is a high cost, a complicated manufacturing process and a long process. This is to solve the problem of time reduction and film quality degradation. In the present invention, in order to self-assemble thin films such as dielectrics, semiconductors, and metals, a specific substance that causes an agglomeration phenomenon is selected and deposited as an intermediate layer, thereby stopping the degradation of the characteristics inherent to the thin film, An object of the present invention is to provide a method capable of producing a highly controlled nanostructure thin film that does not require a complicated process such as an etching process, and a nanothin film structure produced by the method.
前記課題を解決するために、本発明においては以下の手段を提供する。
第1の態様は
（１）単結晶又は非結晶基板上に金属又は半導体薄膜を蒸着させてなるシード層（seed layer）を形成する工程、
（２）前記シード層上に凝集現象が起こる金属を蒸着させてなる中間層（buffer layer）を形成する工程、
（３）前記中間層の形成後、200〜400 ℃の温度で熱処理してパターンを形成する工程、及び
（４）前記パターン上に誘電体、半導体、又は金属を蒸着させてなるターゲット層 （target layer）を形成する工程を含む自己組織化されたナノ構造薄膜の製造方法である。
第２の態様は、前記凝集現状が起こる金属がAu、Ag、Cu、Pt、Pd及びSnで構成された群から選ばれることを特徴とする第1の態様に記載のナノ構造薄膜の製造方法である。
第３の態様は、前記熱処理が300〜400 ℃で行われることを特徴とする第1又は２態様に記載のナノ構造薄膜の製造方法である。
第４の態様は、前記熱処理が2〜8時間行われることを特徴とする第１〜３態様に記載のナノ構造薄膜の製造方法である。
第５の態様は、前記基板がガラス基板、シリコン酸化物基板、酸化マグネシウム（MgO）基板及び酸化アルミニウム（Al2O3）基板で構成された群から選ばれることを特徴とする第１〜４態様に記載のナノ構造薄膜の製造方法である。
第６の態様は、前記シード層を構成する物質が遷移金属であることを特徴とする第１〜５態様に記載のナノ構造薄膜の製造方法である。
第７の態様は、前記シード層を構成する物質がFe又はTiであることを特徴とする第１〜６態様に記載のナノ構造薄膜の製造方法である。
第８の態様は、前記シード層の厚さが0 nmを超え、2 nm以下であることを特徴とする第１〜７態様に記載のナノ構造薄膜の製造方法である。
第９の態様は、前記中間層の厚さが1〜10 nmであることを特徴とする第１〜８態様に記載のナノ構造薄膜の製造方法である。
第１０の態様は、前記中間層の厚さが2〜8 nmであることを特徴とする第１〜９態様に記載のナノ構造薄膜の製造方法である。
第１１の態様は、前記ターゲット層の厚さが0 nmを超え、30 nm以下であることを特徴とする第１〜１０態様に記載のナノ構造薄膜の製造方法である。
第１２の態様は、第１〜１１態様に記載のナノ構造薄膜の製造方法によって製造されたナノ構造薄膜である。
In order to solve the above problems, the present invention provides the following means.
The first aspect is (1) a step of forming a seed layer by depositing a metal or semiconductor thin film on a single crystal or amorphous substrate,
(2) forming an intermediate layer (buffer layer) formed by depositing a metal on which the aggregation phenomenon occurs on the seed layer;
(3) a step of forming a pattern by heat treatment at a temperature of 200 to 400 ° C. after the formation of the intermediate layer; and (4) a target layer obtained by depositing a dielectric, semiconductor, or metal on the pattern. A method for producing a self-assembled nanostructured thin film comprising the step of forming a layer).
2nd aspect WHEREIN: The metal in which the said aggregation present condition occurs is chosen from the group comprised from Au, Ag, Cu, Pt, Pd, and Sn, The manufacturing method of the nanostructure thin film as described in 1st aspect characterized by the above-mentioned It is.
A third aspect is the method for producing a nanostructured thin film according to the first or second aspect, wherein the heat treatment is performed at 300 to 400 ° C.
A 4th aspect is a manufacturing method of the nano structure thin film as described in the 1st-3rd aspect characterized by performing the said heat processing for 2 to 8 hours.
In a fifth aspect, the substrate is selected from the group consisting of a glass substrate, a silicon oxide substrate, a magnesium oxide (MgO) substrate, and an aluminum oxide (Al 2 O 3 ) substrate. It is the manufacturing method of the nanostructure thin film as described in an aspect.
A sixth aspect is the method for producing a nanostructured thin film according to the first to fifth aspects, wherein the substance constituting the seed layer is a transition metal.
A seventh aspect is the method for producing a nanostructured thin film according to the first to sixth aspects, wherein the material constituting the seed layer is Fe or Ti.
The eighth aspect is the method for producing a nanostructured thin film according to the first to seventh aspects, wherein the seed layer has a thickness of more than 0 nm and 2 nm or less.
A ninth aspect is the method for producing a nanostructured thin film according to the first to eighth aspects, wherein the thickness of the intermediate layer is 1 to 10 nm.
A tenth aspect is the method for producing a nanostructured thin film according to the first to ninth aspects, wherein the intermediate layer has a thickness of 2 to 8 nm.
An eleventh aspect is the method for producing a nanostructured thin film according to the first to tenth aspects, wherein the thickness of the target layer is more than 0 nm and not more than 30 nm.
A twelfth aspect is a nanostructured thin film manufactured by the method for manufacturing a nanostructured thin film according to the first to eleventh aspects.
本発明はスパッタリング装置などの汎用性の高い装置を用い、ボトム-アップ（Bottom-up）方式でナノ構造薄膜を製造するものである。既存のトップ-ダウン（Top-down）方式のナノ構造薄膜製造工程では一般にエッチングやリソグラフィー法による蝕刻工程が行われているが、本発明の方法を用いる事により、そのような二次的な蝕刻工程を必要としない。従って、現在一般的に使用されているトップ-ダウン方式と比較すると、以下のような効果が得られる。
（1）作業工程の単純化及び作業時間の短縮化
（2）(1)の効果に伴うコストの低減化
（3）既存の手法による蝕刻工程では有害物質が排出されるが、本発明の方法ではそのような有害物質は排出されず、環境影響値を低くできる。
（4）蝕刻工程では化学変化によって薄膜に損傷を与え、薄膜特性の低下を生じることがあるが、本発明の方法ではそのような化学変化による薄膜の劣化はみられない。
（5）本発明の方法で用いるシード層や中間層の物質を変えることやそれらの膜厚を変えること、また、熱処理温度や熱処理時間を制御すること等によって、ナノ構造薄膜の表面形状を比較的容易に制御することができる。
（6）本発明の方法ではMBEやMOCVDといった製造方法を用いずに汎用性の高いスパッタリング法でボトム-アップ型自己組織化ナノ薄膜を製造できる。スパッタリング法では、（i）比較的低温で細部まで緻密な薄膜を形成できること、（ii）生産性に優れていること、更に装置の値段がMBEやMOCVDに比べ安価でランニングコストも安く、（iii）経済的に優れている等の利便性がある。
以上、本発明の方法が普及した場合、高機能なナノ構造薄膜作製が比較的容易に、且つ低コスト、低環境負荷で作製できることになる。
The present invention is to manufacture a nanostructured thin film by a bottom-up method using a highly versatile apparatus such as a sputtering apparatus. In the existing top-down nano-structure thin film manufacturing process, an etching process using an etching or lithography method is generally performed. By using the method of the present invention, such a secondary etching process is performed. No process is required. Therefore, the following effects can be obtained as compared with the top-down method that is generally used at present.
(1) Simplification of work process and shortening of work time (2) Reduction of cost due to the effects of (1) (3) Although the harmful substances are discharged in the etching process by the existing method, the method of the present invention Then, such harmful substances are not discharged, and the environmental impact value can be lowered.
(4) In the etching process, a chemical change may damage the thin film and cause a deterioration of the thin film characteristics. However, in the method of the present invention, the thin film is not deteriorated by such a chemical change.
(5) Compare the surface shapes of nanostructured thin films by changing the seed layer and intermediate layer materials used in the method of the present invention, changing their film thickness, and controlling the heat treatment temperature and time. Can be controlled easily.
(6) In the method of the present invention, a bottom-up type self-assembled nano thin film can be manufactured by a highly versatile sputtering method without using a manufacturing method such as MBE or MOCVD. In the sputtering method, (i) it is possible to form a dense thin film at a relatively low temperature, (ii) it is excellent in productivity, and the cost of the apparatus is lower than that of MBE and MOCVD, and the running cost is lower (iii ) There are conveniences such as being economically superior.
As described above, when the method of the present invention is widespread, a highly functional nanostructure thin film can be manufactured relatively easily, at low cost, and with low environmental load.
本発明のナノ構造薄膜の製造方法においては、単結晶または非晶質の基板上に金属又は半導体薄膜からなるシード層を蒸着させ、凝集現状が起こる特定の金属中間層からなる下地層薄膜を蒸着させた後、所定の温度で所定の時間その薄膜を熱処理すると、薄膜内で自発的なパターン化が起こる。形成されたパターン上に誘電体、半導体、金属などを蒸着させると、下地層で形成されたパターンの形態を維持したナノサイズで独立したドット形状のような特殊な形状を有するナノ・パターン構造の機能性薄膜を形成することができる。本発明は、既存のトップ-ダウン方式を用いてパターン化する蝕刻工程を代替することができる方法であり、また物理的・化学的な蝕刻工程に伴う薄膜構造の損傷等による特性の低下を防ぐことができる。
以下、本発明による自己組織化されたナノ・パターン構造薄膜の製造工程を示す。図１を用いて、本発明の実施の形態について、詳細に説明する。
工程（1）：スパッタリング蒸着法を用いて、図１に示したように単結晶又は非結晶基板（100）上に金属、又は半導体を厚さ数 nmで蒸着させて、シード層（200）を形成する。
上記基板を構成する物質の例としてはガラス、シリコン酸化物（SiO2）、酸化マグネシウム（MgO）や酸化アルミニウム（Al2O3）が挙げられる。酸化マグネシウム基板、又は酸化アルミニウム基板であることが好ましい。
上記シード層（200）は後に蒸着される中間層（300）の自己組織化を効率よく起こすことができる。シード層（200）を構成する物質の例としては、金属又は半導体が挙げられるが、Fe、Tiなどの遷移金属が好ましい。また、シード層の膜厚によって、次の段階で蒸着される中間層の凝集傾向が変化するので、シード層の膜厚に合わせて、中間層の膜厚を最適に選択することが必要である。シード層（200）の厚さは0 nmを超え、3 nm以下であることが好ましく、0 nmを超え、2 nm以下であることがより好ましい。
工程（2）：工程（1）のシード層（200）上に凝集現状が起こる金属を厚さ数nmで蒸着させて中間層（300）を形成する。
上記中間層（300）には、凝集現象を引き起こし易い金属物質が利用される。そのような金属の例としてはAu、Ag、Cu、Pt、Pd、Snなどが挙げられるが、Au又はAgであることが好ましい。中間層（300）の厚さは1〜10 nmであることが好ましく、2〜8 nmであることがより好ましく、3〜6 nmがさらに好ましい。中間層（300）の膜厚はシード層（200）の膜厚と関連性を持ち、金属の中間層（300）の凝集形態を決定する重要な要因である。
工程（3）：工程（2）の後、所定温度及び所定時間で熱処理（P100）を行う。熱処理過程中に熱応力によって中間層（300）の金属の凝集現状が引き起こされる。熱処理の温度及び時間は可変的なもので、これらの二つの変数を調節することで最終的な凝集形態が決定される。よって、熱処理温度及び熱処理時間を調節してそれらパターン間の距離や密度（個数／面積）及び個々のパターンの高さ及びその大きさ（形状又はサイズ）を微細に制御することができる。
熱処理温度を室温、200〜500 ℃に設定し、個々の温度によって、中間層（300）の凝集形態を制御する。熱処理（P100）は200〜400 ℃で行うことが好ましく、250〜400 ℃で行うことがより好ましく、300〜400 ℃で行うことがさらに好ましく、350 ℃で行うことが特に好ましい。熱処理（P100）する時間は上記温度で1〜10 時間であり、好ましくは2〜8 時間である。熱処理（P100）の間、中間層（300）の凝集過程が発生し、熱処理後に自己組織化によりパターン化された薄膜（310）が形成する。
工程（4）：工程（3）で凝集現状によりパターン化された薄膜（310）の上に目的とする誘電体、半導体、金属などの薄膜（400）を蒸着させ、ターゲット層を形成することにより最終的にナノ・パターン構造を持つ機能性薄膜（500）を形成する。上記蒸着は工程（3）の蒸着温度と同じ温度で行われることが好ましい。
最上部に蒸着されるターゲット層の膜厚も、最終的なナノ構造の形態を決める重要な因子の一つであるため、薄膜の特性を顧慮し、可変的に設定する。ターゲット層の膜厚は0 nmを超え、30 nm以下であることが好ましい。
図2には、本発明による製造方法で製造された自己組織化されたナノ構造薄膜を原子力間顕微鏡で観察した実際の像が図示されている。薄膜の全体が自己組織化されて三次元のナノ・パターン構造が形成されていることが確認できた。
In the method for producing a nanostructured thin film of the present invention, a seed layer made of a metal or semiconductor thin film is vapor-deposited on a single crystal or amorphous substrate, and an underlayer thin film made of a specific metal intermediate layer in which agglomeration occurs occurs. Then, when the thin film is heat-treated at a predetermined temperature for a predetermined time, spontaneous patterning occurs in the thin film. When dielectrics, semiconductors, metals, etc. are deposited on the formed pattern, a nano-pattern structure with a special shape such as a nano-sized independent dot shape that maintains the shape of the pattern formed by the underlayer A functional thin film can be formed. The present invention is a method that can replace the existing etching process using the top-down method, and prevents the deterioration of the characteristics due to the damage of the thin film structure accompanying the physical and chemical etching process. be able to.
Hereinafter, a manufacturing process of a self-organized nano-patterned thin film according to the present invention will be described. The embodiment of the present invention will be described in detail with reference to FIG.
Step (1): Using a sputtering vapor deposition method, as shown in FIG. 1, a metal or semiconductor is deposited on a single crystal or amorphous substrate (100) at a thickness of several nm, and a seed layer (200) is formed. Form.
Examples of the substance constituting the substrate include glass, silicon oxide (SiO 2 ), magnesium oxide (MgO), and aluminum oxide (Al 2 O 3 ). A magnesium oxide substrate or an aluminum oxide substrate is preferable.
The seed layer (200) can efficiently cause self-assembly of an intermediate layer (300) to be deposited later. Examples of the material constituting the seed layer (200) include metals and semiconductors, and transition metals such as Fe and Ti are preferable. Moreover, since the aggregation tendency of the intermediate layer deposited in the next stage changes depending on the film thickness of the seed layer, it is necessary to optimally select the film thickness of the intermediate layer according to the film thickness of the seed layer. . The thickness of the seed layer (200) is more than 0 nm and preferably 3 nm or less, more preferably more than 0 nm and 2 nm or less.
Step (2): The intermediate layer (300) is formed by vapor-depositing a metal having an agglomeration state with a thickness of several nanometers on the seed layer (200) in the step (1).
For the intermediate layer (300), a metal substance that easily causes an agglomeration phenomenon is used. Examples of such a metal include Au, Ag, Cu, Pt, Pd, and Sn, and Au or Ag is preferable. The thickness of the intermediate layer (300) is preferably 1 to 10 nm, more preferably 2 to 8 nm, and further preferably 3 to 6 nm. The film thickness of the intermediate layer (300) is related to the film thickness of the seed layer (200), and is an important factor for determining the aggregation form of the metal intermediate layer (300).
Step (3): After the step (2), heat treatment (P100) is performed at a predetermined temperature and a predetermined time. During the heat treatment process, thermal stress causes the metal agglomeration of the intermediate layer (300). The temperature and time of the heat treatment are variable, and the final aggregation form is determined by adjusting these two variables. Therefore, the distance and density (number / area) between the patterns, the height and the size (shape or size) of each pattern can be finely controlled by adjusting the heat treatment temperature and the heat treatment time.
The heat treatment temperature is set to room temperature, 200 to 500 ° C., and the aggregation form of the intermediate layer (300) is controlled by each temperature. The heat treatment (P100) is preferably performed at 200 to 400 ° C, more preferably 250 to 400 ° C, further preferably 300 to 400 ° C, and particularly preferably 350 ° C. The time for the heat treatment (P100) is 1 to 10 hours, preferably 2 to 8 hours, at the above temperature. During the heat treatment (P100), an aggregation process of the intermediate layer (300) occurs, and a thin film (310) patterned by self-organization is formed after the heat treatment.
Step (4): By depositing a target dielectric, semiconductor, metal or other thin film (400) on the thin film (310) patterned according to the current state of aggregation in Step (3) to form a target layer Finally, a functional thin film (500) having a nano-pattern structure is formed. It is preferable that the said vapor deposition is performed at the same temperature as the vapor deposition temperature of a process (3).
The thickness of the target layer deposited on the top is also one of the important factors that determine the final nanostructure form, and is therefore variably set in consideration of the properties of the thin film. The thickness of the target layer is preferably more than 0 nm and 30 nm or less.
FIG. 2 shows an actual image obtained by observing the self-assembled nanostructure thin film manufactured by the manufacturing method according to the present invention with an atomic force microscope. It was confirmed that the entire thin film was self-assembled to form a three-dimensional nano-pattern structure.
以下本発明の実施例を説明するが、本発明の範囲はこれらの実施例に限定されるものではない。 Examples of the present invention will be described below, but the scope of the present invention is not limited to these examples.
本発明によって、凝集現象を用いて自己組織化された金属のナノ構造薄膜を以下のように製造した。各層の蒸着は全て同一のマグネトロンスパッタ装置内で行った。MgO (001) 単結晶の基板上にFeのシード層を0〜2 nmの厚さで蒸着させた。また、Feシード層上にAu中間層を蒸着させた。その後、真空中で熱処理（300〜450 ℃）を行った。熱処理の後、一様なパターンで凝集された中間層の上に目的とする機能性薄膜層（ターゲット層）としてFeとPdの層を交互に蒸着させ、膜厚を3〜30 nmとした。
以下、表を使用して、凝集現象を用いた自己組織化された薄膜の形成において、シード層の厚さ、中間層の厚さ、ターゲット層の厚さを変化させた場合の蒸着終了後のターゲット層薄膜の表面の粗さ（平均自乗粗さ）、形成されたパターンの高さ、パターン間距離などを比較した。
下記表 1はAu中間層（4 nm）の膜厚を固定し、Feシード層の厚さだけを変化させた場合に形成される薄膜表面パターンの形状を比較したものである。
[表 1] Feシード層の膜厚による薄膜のナノ構造の変化（Au中間層の膜厚は4 nmに固定し、350 ℃で3 時間熱処理を施した場合）
[表 2] Au中間層の膜厚による薄膜のナノ構造の変化（Feシード層の膜厚は1 nmに固定し、350 ℃で3 時間熱処理を施した場合）
[表 3] ターゲット（FePd）層の膜厚による薄膜のナノ構造の変化（Feシード層の膜厚は1 nm、Au中間層の膜厚は4 nmに固定し、350 ℃で3 時間熱処理を施した場合）
Hereinafter, in the formation of a self-assembled thin film using the aggregation phenomenon using the table, the thickness of the seed layer, the thickness of the intermediate layer, and the thickness of the target layer are changed after the deposition is completed. The surface roughness of the target layer thin film (mean square roughness), the height of the formed pattern, the distance between patterns, and the like were compared.
Table 1 below compares the shape of the thin film surface pattern formed when the thickness of the Au intermediate layer (4 nm) is fixed and only the thickness of the Fe seed layer is changed.
[Table 1] Changes in the nanostructure of the thin film depending on the thickness of the Fe seed layer (when the thickness of the Au intermediate layer is fixed at 4 nm and heat-treated at 350 ° C for 3 hours)
[Table 2] Changes in the nanostructure of the thin film depending on the thickness of the Au intermediate layer (when the thickness of the Fe seed layer is fixed at 1 nm and heat-treated at 350 ° C for 3 hours)
[Table 3] Changes in the nanostructure of the thin film depending on the thickness of the target (FePd) layer (Fe seed layer thickness is fixed to 1 nm, Au intermediate layer thickness is fixed to 4 nm, and heat treatment is performed at 350 ° C for 3 hours. If applied)
下記表 4〜6は、独立した実験を２回行い、その平均値を表したものであること以外、他の条件は実施例１と同様にして、実験を実施した結果を記載したものである。実施例１のパターン間距離の代わりにドットの密度を計算して記載したものである。また、表 7はFeシード層（1 nm）とAu中間層（4 nm）、FePdターゲット層（30 nm）の膜厚を固定し、熱処理温度だけを変化させた場合に形成される薄膜表面パターンの形状を比較したものである。
[表 4] Feシード層の膜厚による薄膜のナノ構造の変化（Au中間層の膜厚は4 nmに固定し、350 ℃で3 時間熱処理を施した場合）
[表 5] Au中間層の膜厚による薄膜のナノ構造の変化（Feシード層の膜厚は1 nmに固定し、350 ℃で3 時間熱処理を施した場合）
[Table 4] Changes in the nanostructure of the thin film depending on the thickness of the Fe seed layer (when the thickness of the Au intermediate layer is fixed at 4 nm and heat-treated at 350 ° C for 3 hours)
[Table 5] Changes in the nanostructure of the thin film depending on the thickness of the Au intermediate layer (when the thickness of the Fe seed layer is fixed at 1 nm and heat-treated at 350 ° C for 3 hours)
MgO（001）単結晶の基板上にTiのシード層を2 nmの厚さで蒸着させた。また、Ti シード層上にAg中間層を蒸着させた。その後、真空中で熱処理（350 ℃）した。なお、この実施例においてはターゲット層は蒸着させていない。これ以外の条件は実施例１と同様に行った。
下記表8及び9はTiシード層（2 nm）及びAg中間層（4 ｎm又は５ nm）の膜厚を固定し、熱処理時間を変化させた場合に形成される薄膜表面パターンの形状を比較したものである。
[表 8] 熱処理時間による薄膜のナノ構造の変化（Tiシード層（2 nm）及びAg中間層（4 nm）の膜厚を固定し、350 ℃で熱処理を施した場合）
下記表10はTiシード層（2 nm）、熱処理温度及び時間（350 ℃、4 時間）を固定し、Ag中間層の厚さだけを変化させた場合に形成される薄膜表面パターンの形状を比較したものである。
[表 10] Ag中間層の膜厚による薄膜のナノ構造の変化（Tiシード層（2 nm）の膜厚を固定し、350 ℃で4時間熱処理を施した場合）
Tables 8 and 9 below compare the shapes of the thin film surface patterns formed when the thickness of the Ti seed layer (2 nm) and Ag intermediate layer (4 nm or 5 nm) is fixed and the heat treatment time is changed. Is.
[Table 8] Change in thin film nanostructure with heat treatment time (when Ti seed layer (2 nm) and Ag intermediate layer (4 nm) are fixed and heat treatment is performed at 350 ° C)
Table 10 below compares the shape of the thin film surface pattern formed when the Ti seed layer (2 nm), heat treatment temperature and time (350 ° C, 4 hours) are fixed, and only the thickness of the Ag intermediate layer is changed. It is a thing.
[Table 10] Changes in the nanostructure of the thin film depending on the thickness of the Ag intermediate layer (when the thickness of the Ti seed layer (2 nm) is fixed and heat treated at 350 ° C for 4 hours)
100・・・基板
P100・・・・熱処理工程
200・・・シード層
300・・・中間層
310・・・自己組織化によりパターン化された薄膜
400・・・ターゲット層
500・・・薄膜の全体が自己組織化されたナノ・パターン構造
100 ... Board
P100 ... Heat treatment process
200 ... Seed layer
300 ・ ・ ・ middle layer
310 ・ ・ ・ Thin film patterned by self-organization
400 ・ ・ ・ Target layer
500 ・ ・ ・ Nano-pattern structure in which the entire thin film is self-organized
Claims (12)
（２）前記シード層上に凝集現象が起こる金属を蒸着させてなる中間層（buffer layer）を形成する工程、
（３）前記中間層の形成後、200〜400 ℃の温度で熱処理してパターンを形成する工程、及び
（４）前記パターン上に誘電体、半導体、又は金属を蒸着させてなるターゲット層（target layer）を形成する工程を含む自己組織化されたナノ構造薄膜の製造方法。 (1) forming a seed layer formed by vapor-depositing a metal or semiconductor thin film on a single crystal or amorphous substrate;
(2) forming an intermediate layer (buffer layer) formed by depositing a metal on which the aggregation phenomenon occurs on the seed layer;
(3) a step of forming a pattern by heat treatment at a temperature of 200 to 400 ° C. after the formation of the intermediate layer; and (4) a target layer (target) formed by depositing a dielectric, a semiconductor, or a metal on the pattern. A method for producing a self-assembled nanostructured thin film comprising the step of forming a layer).
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| JPH0786282A (en) * | 1993-09-20 | 1995-03-31 | Oki Electric Ind Co Ltd | Wiring forming method |
| JP2008108924A (en) * | 2006-10-26 | 2008-05-08 | Matsushita Electric Works Ltd | Compound semiconductor light-emitting element, illumination apparatus employing the same and manufacturing method of compound semiconductor light-emitting element |
| WO2009113195A1 (en) * | 2008-03-13 | 2009-09-17 | 大陽日酸株式会社 | Catalyst material for producing brushy carbon nanostructure, process for producing catalyst material, brushy carbon nanostructure, and process for producing the same |
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| JPH0585773A (en) * | 1991-09-26 | 1993-04-06 | Central Glass Co Ltd | Formation of finely rugged coating film on surface of substrate |
| JPH0786282A (en) * | 1993-09-20 | 1995-03-31 | Oki Electric Ind Co Ltd | Wiring forming method |
| JP2008108924A (en) * | 2006-10-26 | 2008-05-08 | Matsushita Electric Works Ltd | Compound semiconductor light-emitting element, illumination apparatus employing the same and manufacturing method of compound semiconductor light-emitting element |
| WO2009113195A1 (en) * | 2008-03-13 | 2009-09-17 | 大陽日酸株式会社 | Catalyst material for producing brushy carbon nanostructure, process for producing catalyst material, brushy carbon nanostructure, and process for producing the same |
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