JP2011136244A - Game machine - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reliably use a counter value latched on the basis of winning by the entry of a game ball in game control, in a game machine where the value of a counter for counting clock signals is a random number value. <P>SOLUTION: In the game machine for executing an auxiliary game corresponding to the passing of a game ball to a start area, a game control means includes: a counter means for performing a counting operation on the basis of the clock signals; a counter value-holding means for fetching and holding the value counted by the counter means on the basis of the detected result of a start winning detection means; an interruption processing execution means for executing interruption processing on the basis of interruption signals generated at every predetermined interval of time; a counter value storage means for storing the counter value acquired by the counter value-holding means; an interruption processing execution means; and a counter value acquisition means. The interruption processing execution means includes a random number value storage means and a counter value initialization means. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention provides a game value according to winning in a winning area in a starting area and a gaming area provided with a plurality of winning areas, executes an auxiliary game in accordance with the passing of a game ball to the starting area, and assists The present invention relates to a gaming machine provided with a game control means for giving a privilege to a player in response to a special result of the game.

  Conventionally, a winning entrance called a start winning opening has been provided in the gaming area on the game board, and a random number is obtained based on the winning of the hit ball to the starting winning opening, and the winning determination is made, and based on the winning result A gaming machine that provides a predetermined profit (for example, a so-called jackpot game) to a player has become widespread.

  In such a gaming machine, the reference clock of the CPU responsible for controlling the game is counted by software, and the value of this soft counter is acquired as a random number for determining a jackpot or the like when winning at the start winning opening Yes. In some cases, the clock is counted not by software but by hardware (counter circuit) and the count value is used as a random number.

  Specifically, a random number including an oscillator that generates a clock signal having a predetermined frequency, a counter circuit that counts (counts) the clock signal generated by the oscillator, and a latch circuit that latches a counter value counted by the counter circuit. A generation circuit is provided. Then, the value of the counter circuit is extracted and latched by the latch circuit when the start prize is generated.

  Further, when the game control microcomputer detects that a start winning has occurred, it reads the counter value latched by the latch circuit and stores the counter value in a predetermined area of the RAM. The counter value stored in the RAM becomes a random value used for the jackpot determination. As an invention in which the game control microcomputer performs the jackpot determination based on the random number value stored in a predetermined area of the RAM as described above, there is one disclosed in Patent Document 1, for example.

JP 2007-89978 A

  However, in the gaming machine described in Patent Document 1, the random number generation circuit is provided as an external circuit of the game control microcomputer, and the condition for latching the counter value and the reading of the latched counter value are performed. The counter value is set separately, and the counter value is latched every time the latch signal is output. Therefore, if the latch circuit malfunctions due to noise on the latch signal after the latch signal is generated based on the start prize and the counter value is latched and is read into the microcomputer, the start prize is There is a possibility that the counter value latched at a timing unrelated to the occurrence of the occurrence of the error will be acquired as a random number.

  Furthermore, until the latched counter value is read into the microcomputer, the update timing of the counter value is predicted, the latch signal is manipulated illegally, and the desired counter value is forcibly latched and won, etc. There is a new problem that there is a risk of fraud, and there is an urgent need to resolve such a problem.

  The present invention has been made paying attention to the problems as described above. In a gaming machine in which the value of a counter that counts a clock signal is a random value used for determining a big hit or the like, an erroneous random number value is stored due to noise. An object of the present invention is to make it possible to prevent use of the counter value latched based on the winning of a game ball and ensure that it can be used in game control, and to make illegal activities difficult.

The invention described in claim 1
A game area provided with a start area and a plurality of winning portions, a start winning detection means for detecting a game ball passing through the start area, and a game value according to winning in the winning section in the gaming area, In a gaming machine comprising a game control means for executing an auxiliary game in response to the passage of a game ball to the starting area and granting a privilege to a player when the auxiliary game has a special result,
The game control means includes
Counter means for counting in a predetermined range based on a clock signal of a predetermined period;
Counter value holding means for capturing and holding the counter value counted by the counter means based on the detection result of the start winning detection means;
Interrupt processing execution means for executing interrupt processing based on an interrupt signal generated every predetermined time;
Counter value storage means for storing a counter value acquired from the counter value holding means;
Counter value acquisition means for acquiring the counter value held by the counter value holding means based on the detection result from the start winning detection means and storing it in the counter value storage means;
The interrupt processing execution means includes
Random value storage for storing a counter value stored in the counter value storage means as a random value used in the control of the auxiliary game when a predetermined condition is established based on a detection result from the start winning detection means Means,
Counter value initialization means for setting the stored value of the counter value storage means to a predetermined value after the random value storage means stores the counter value stored in the counter value storage means as a random value. It is characterized by being.

  Here, the “starting area” refers to a starting gate for giving a starting condition for a special figure variation display game, a starting winning opening for giving a prize ball together with the starting condition, and a starting gate for giving a starting condition for a general figure changing display game. Including. The “auxiliary game” is a variable display game using a display device or a display. The “special result” is a game result called a so-called jackpot combination. The “timer interrupt process execution means” can be constituted by a CPU and a program executed by the CPU. “When the predetermined condition is satisfied” means that the upper limit is not reached when the upper limit is set for the number of start winnings that can be stored.

  According to the first aspect of the present invention, the counter means performs a counting operation based on a clock signal having a predetermined period, and the counter value as the counted value is stored in the counter value holding means based on the detection result of the start winning detection means. The counter value acquisition means acquires and holds the counter value held by the counter value holding means based on the detection result of the start winning detection means, and stores it in the storage means. The counter value stored in the storage means is stored as a random value used by the random number storage means included in the interrupt processing execution means in the control of the auxiliary game based on the detection result of the start winning detection means. As a result, even if the counter value holding means erroneously captures the counter value due to the influence of noise or the like, it is possible to prevent an erroneous random number value from being acquired and stored. Furthermore, since the random value storage means includes counter value initialization means for setting the stored value of the counter value storage means to a predetermined value after storing the counter value stored in the counter value storage means as a random value, Even when the random number latch interrupt processing is not performed due to some trouble such as a circuit failure, it is possible to prevent the acquired counter value from being stored as a random number value redundantly. As a result, when the value held in the latch random number area immediately before corresponds to the big hit, it is possible to prevent the big hit from occurring.

The invention according to claim 2 is the gaming machine according to claim 1,
A counter value change prohibiting unit that prohibits rewriting of the counter value held in the counter value holding unit until the counter value held in the counter value holding unit is acquired by the counter value acquiring unit;
The counter value change prohibiting means includes:
Latch prohibiting means for prohibiting the counter value from being taken into the counter value holding means on the condition that the counter value holding means has taken in the counter value;
Latch permitting means for permitting the counter value holding means to take in the counter value on the condition that the counter value holding means has acquired the counter value held by the counter value holding means,
The latch permission means includes
After the value held by the counter value holding unit is cleared, the counter value holding unit is allowed to take in the counter value.

According to the second aspect of the present invention, the counter value change prohibiting unit prohibits the change until the counter value fetched by the counter value holding unit is acquired by the counter value acquiring unit. Thus, it is possible to more reliably prevent the counter value at the wrong timing from being acquired. Further, it is possible to prevent the CPU from acquiring an illegal counter value due to an illegal act, and it is possible to be strong against the illegality.
According to the second aspect of the present invention, the counter value acquisition unit clears the value held by the counter value holding unit after the counter value acquisition unit acquires the counter value, so that the circuit malfunctions and the counter value is latched. Even when it is not performed, it is possible to prevent the acquired counter value from being acquired in duplicate. As a result, when the value held in the counter value holding means immediately before is equivalent to the big hit, it is possible to prevent the big hit from occurring continuously.

In the above invention,
The counter means performs a counting operation in response to the rise or fall of the clock signal, and the counter value holding means takes in the counter value counted by the counter means in response to the fall or rise of the clock signal. Also good.

  In this way, the counter value is prevented from being latched at the timing when the value of the counter circuit changes, and the counter value is accurately latched in the latch register.

In the above invention,
The game control means includes
Clock signal supply means for supplying the system clock signal and the random number clock signal as separate clock signals;
A clock signal selection unit that selects any one of a system clock signal and a random number clock signal supplied from the clock signal supply unit and supplies the selected clock signal to the counter unit;
The counter means may update the counter value based on the clock signal selected by the clock signal selection means.

  In this way, it is difficult to determine from which external clock value the counter value is updated, and it becomes difficult to specify the update timing of the counter means for generating random numbers, making it difficult to perform fraud. it can.

In the above invention,
The clock signal selection means includes
A clock signal comparison and determination means for comparing the frequency of the random number clock signal with the frequency of the system clock signal and determining whether the frequency of the random number clock signal is lower than the frequency of the system clock signal;
Clock signal supply stopping means for stopping supply of the clock signal to the counter means when the clock signal comparison determining means determines that the frequency of the random number clock signal is lower than the frequency of the system clock signal; May be included.

  In this way, it is possible to prevent an unauthorized person from trying to acquire an unauthorized random number value by performing an unauthorized operation on the clock input terminal.

  According to the present invention, in a gaming machine in which the value of the counter that counts the clock signal is a random value that is used for determination such as jackpot, the value of the counter that counts the clock signal is the random value that is used for determination such as jackpot. In the gaming machine, it is possible to prevent an erroneous random number value from being stored due to noise and to reliably use the counter value latched based on the winning of the game ball in the game control. In addition, there is an effect that it is possible to make the illegal act difficult.

It is a front view showing one embodiment of a gaming machine provided with a pachinko gaming machine to which the gaming machine according to the present invention is applied. It is a rear view which shows the structural example of the back surface of the game machine of embodiment. It is a front view showing an example of a game board in the gaming machine of the embodiment. It is a block diagram which shows the structural example of the control system provided in the back surface of the game machine of embodiment. It is a block diagram which shows the structural example of the microcomputer for games which comprises the game control apparatus of the control system of FIG. FIG. 6 is a block diagram illustrating a configuration example of a random number generation circuit and a clock generator provided in the gaming microcomputer of FIG. 5. 7 is a timing chart showing a relationship between a counter circuit update timing and a counter value latch timing in the random number generation circuit of FIG. 6; 7 is a flowchart showing a specific procedure of latch register holding control performed by the random number control device of the random number generation circuit of FIG. 6. It is a flowchart which shows the specific procedure of the control at the time of the latch data reading performed by the random number control apparatus of the random number generation circuit of FIG. It is a flowchart which shows the specific procedure of the hard random number clock monitoring control performed by the random number control apparatus of the random number generation circuit of FIG. It is a flowchart which shows the first half part of an example of the specific procedure of a main process among the game controls performed by the game microcomputer of a game control apparatus. It is a flowchart which shows the second half part of an example of the specific procedure of a main process among the game controls performed by the game microcomputer of a game control apparatus. It is a flowchart which shows an example of the specific procedure of a timer interruption process among the game controls performed by the game microcomputer of a game control apparatus. It is a flowchart which shows an example of the specific procedure of the special figure game process performed during the timer interruption process of FIG. It is a flowchart which shows an example of the specific procedure of the start port SW2 monitoring process of 1st Example of 1st invention performed during the special figure game process of FIG. It is a flowchart which shows the procedure of the start port SW2 monitoring process in 2nd Example of 1st invention. It is a flowchart which shows an example of the specific procedure of the random number latch interruption process in 3rd Example of 1st invention. It is a flowchart which shows the procedure of the start port SW2 monitoring process in 3rd Example of 1st invention. It is a flowchart which shows an example of the specific procedure of the random number latch interruption process performed based on the start winning detection in the Example of 2nd invention, 3rd invention. It is a flowchart which shows an example of the specific procedure of start port SW2 monitoring process in the Example of the 2nd invention and 3rd invention performed during the special figure game process of FIG. It is a flowchart which shows an example of the specific procedure of the random number latch interruption process performed based on the start winning detection in the Example of 4th invention. It is explanatory drawing which shows the structural example of the start opening prize memory | storage area | region in the Example of the 4th invention used in the random number latch interruption process of FIG. It is a flowchart which shows the outline of the procedure of the start port SW monitoring process in the Example of the 4th invention performed during the special figure game process of FIG. It is a flowchart which shows an example of the specific procedure of the start port 1SW monitoring process in the Example of the 4th invention performed during the start port SW monitoring process of FIG. It is a flowchart which shows an example of the specific procedure of the start port 2SW monitoring process in the Example of the 4th invention performed during the start port SW monitoring process of FIG. It is a flowchart which shows an example of the specific procedure of the random number latch interruption process performed based on the start winning detection in 1st Example of 5th invention. It is a flowchart which shows an example of the specific procedure of the start port SW2 monitoring process in the Example of the 5th invention performed during the special figure game process of FIG. It is a flowchart which shows an example of the procedure of the random number latch interruption process performed based on the start winning detection in 2nd Example of 5th invention.

  DESCRIPTION OF EXEMPLARY EMBODIMENTS Hereinafter, preferred embodiments of the invention will be described with reference to the drawings.

  FIG. 1 is an explanatory diagram of a gaming apparatus according to an embodiment of the present invention.

  The gaming device according to the present embodiment includes a card unit 70 into which a storage medium for storing a valuable value such as the number of gaming media (the number of gaming balls) held by the player or the amount of money that can be converted to the gaming media, and the game device. A gaming machine 10 capable of executing and paying out gaming media is provided.

  The gaming machine 10 includes a main body frame (outer frame) 11 and a front frame 12, and the front frame 12 is assembled to the main body frame (outer frame) 11 via a hinge 13 so as to be openable and closable. A game board 50 (see FIG. 3) is stored in a storage portion (not shown) formed on the front side of the front frame 12. A glass frame 15 having a cover glass (transparent member) that covers the front surface of the game board 50 is attached to the front frame 12.

  Around the cover glass of the glass frame 15, there is provided a decorative member 16 provided with a light emitting device composed of a lamp, LED, or the like. An illumination unit 17 having a light emitting device is also provided above the glass frame 15. When these light-emitting devices emit light according to a predetermined mode, decorative light emission that enhances the effect of the game and light emission that indicates a game state are emitted.

  Further, an error notification LED 18 is provided on the right side of the lighting unit 17 for notifying the hall clerk of the occurrence of an error in the gaming machine 10 and the opening of the front frame 12. A speaker 19 that emits sound (for example, sound effects) is provided on the lower left side of the glass frame 12.

  An opening / closing panel 20 and a fixed panel 30 are provided at the lower part of the front frame 12, and an upper plate 21 for supplying a game ball to a hitting ball launching device (not shown) is provided on the opening / closing panel 20. Are provided with a select switch 22 and an operation switch 23 for receiving an operation input from the player. Further, the fixed panel 30 is provided with an ashtray 31, a lower plate 32, an operation unit 33 of a ball striking device, and the like. Further, the lower tray 32 is provided with a lower tray ball removing mechanism 34 for discharging the game balls stored in the lower tray 32.

  In the gaming apparatus of this embodiment, the ball hitting device launches the gaming ball supplied from the upper plate 21 by the player turning the operation unit 33. Further, when the player operates the select switch 22, the contents of the effect of the variable display game on the display device 61 (see FIG. 3) provided in the center of the game board can be selected. Furthermore, when the player operates the operation switch 23, in the variable display game executed on the display device 61, an effect in which the player's operation is intervened can be performed.

  A ball lending button 26 that is operated when a player borrows a game medium and a discharge button 27 that is operated to discharge a prepaid card from the card unit 70 are provided on the upper right portion of the upper plate 21. Between these buttons 26 and 27, a balance display unit 28 for displaying the balance of the prepaid card is provided.

  A card insertion slot 71 into which a card such as a prepaid card or a membership card can be inserted is provided at the lower part of the card unit 70 disposed adjacent to the left side of the gaming machine 10. A card such as a prepaid card or a member card stores identification information of the card, member information of the owner (player) of the card, a balance, and the like. The membership information includes the card owner's address, name, age, occupation, and the like.

  When a card such as a prepaid card or a membership card is inserted into the card insertion slot 71, information stored in the card is read out by an internal card reader / writer. Of the read information, the card balance is displayed on the balance display section 28 of the gaming machine 10 and the balance display section 72 provided near the center of the card unit 70.

  Above the balance display part 72, a bill insertion slot 73 into which a bill can be inserted is provided, and the amount of the bill inserted into the bill insertion slot 73 is stored as a balance on the card. An operation display unit 74 is provided above the bill insertion slot 73. The operation display unit 74 changes the emission color corresponding to the operation state of the card unit 70.

  Next, the configuration of the back side of the gaming machine 10 will be described with reference to FIG. FIG. 2 is a rear view of the gaming machine 10 of the present embodiment.

  A frame-like back mechanism board 40 having a substantially square opening at the center is attached to the back side of the gaming machine 10, specifically, the back of the front frame 12. A ball storage unit 41 that stores game balls replenished from a replenishment device (not shown) provided in the island facility and that causes the stored game balls to flow down is disposed above the back mechanism board 40. On the side of the back mechanism board 40 (the right side in FIG. 2), the ball discharge unit 42 that pays out the game balls flowing down from the ball storage unit 41 to the upper plate 21 and the lower plate 32 disposed in front of the game machine. Is arranged.

  In the central portion of the back mechanism board 40, there are a game control device 100 that controls the game in an integrated manner, and an effect control device 150 that controls the effect of the variable display game based on the effect control command transmitted from the game control device 100. The game control device 100 is provided with an inspection device connection terminal 107 connected to the inspection device.

  Under the back mechanism board 40, a payout control device 200 for controlling the operation of the ball discharge unit 42 based on data transmitted from the game control device 100, and a power supply device 160 are disposed. The payout control device 200 is provided with an inspection device connection terminal 217 connected to the inspection device and an error number display 43 that displays the type of error that has occurred in the payout control device 200 in numbers. A card unit connection terminal 170 for connecting the gaming machine 10 to the card unit 70 is provided on the right side of the power supply device 160.

  Next, the game board 50 will be described with reference to FIG. FIG. 3 is a front view of the game board 50 of the present embodiment.

  On the surface of the game board 50, a substantially circular game area 51 surrounded by guide rails 53 is formed. The game area 51 is configured by resin side cases 52 and guide rails 53 provided on each side of the game board 50.

  In the game area 51, a center case 60 provided with a display device 61 is disposed substantially at the center. The display device 61 is attached to a recess provided in the center case 60 at a position deeper than the front surface of the center case 60. That is, the center case 60 surrounds the display area of the display device 61 and is formed so as to protrude forward from the display surface of the display device 61.

  The display device 61 is configured by a device having a display screen such as an LCD (Liquid Crystal Display) or a CRT (CRT). In the area (display area) where the image of the display screen can be displayed, a plurality of pieces of identification information (special symbols) and a character that produces a special figure variation display game are displayed. Although there is only one display screen, it can be considered that there are a plurality of (for example, three) variable display areas. In each variable display area, special symbols assigned as identification information are variablely displayed (variably displayed). A special figure variation display game is played. In addition, an image based on the progress of the game (for example, jackpot display, fanfare display, ending display, etc.) is displayed on the display screen.

  A normal symbol starting gate 54 is provided on the left side of the center case 60. Three general winning openings 55 are arranged on the lower left side of the center case 60, and one general winning opening 55 is arranged on the lower right side of the center case 60. In addition, a start winning port 56 is provided below the center case 60, and a start winning device 57 including an ordinary variable winning device 57a that can be opened and closed is disposed immediately below the start winning port 56.

  Further, below the start winning device 57, a special variable winning device (large winning port) 58 that can be converted into a state where the game ball is not accepted and a state where it is easy to accept depending on the variation result of the display device 61 is disposed. Also, on the upper right of the game board 50, a general map display 62 composed of a segment type display, a special map display 63, a light emission for displaying the number of unprocessed special map display games and the general map display game. A display unit 64 is provided. The general-purpose display 62 displays a variable display game that is performed when the game ball passes the normal symbol start gate 54. The special display 63 displays a variable display game that is performed when a game ball wins the start winning opening 56 or the start winning device 57.

  In the gaming machine 10 of the present embodiment, a game is played by launching a game ball (pachinko ball) from a launching device (not shown) toward the game area 51. The launched game balls flow down the game area 51 while changing the rolling direction by means of direction changing members such as obstacle nails and windmills arranged in various places in the game area 51, and the normal symbol start gate 54 and the general winning opening 55 The winning prize opening 56, the starting prize winning device 57 or the special variable prize winning device 58 is won, or it flows into the out port 59 provided at the bottom of the gaming area 51 and is discharged from the gaming area.

  The start winning device 57 includes a state in which a game ball is likely to win a prize and a state in which a game ball is difficult to win by opening and closing the normal variation winning device 57a. Normally, the normal variation winning device 57a is in a closed state, and the starting winning device 57 is in a state where it is difficult for a game ball to win. When the game ball passes through the normal symbol start gate 54, the normal figure display game is executed on the normal figure display device 62. When a win state occurs as a result of the general figure change display game, the normal fluctuation winning device 57a is opened. It is converted into a state, and the start winning device 57 is in a state where the game ball is easy to win.

  The winning of a game ball in the general winning opening 55 is detected by general winning opening switches 55a to 55n (see FIG. 4) provided in the general winning opening 55. The winning of the game ball to the start winning opening 56 is detected by the special figure start switch 56a (see FIG. 4), and the winning of the game ball to the start winning apparatus 57 is detected by the special figure start switch 57b. The special symbol random number counter value extracted by the passing timing of the game ball is stored as a special symbol winning memory in the special symbol storage area (a part of the RAM) in the game control device 100 for a predetermined number of times (for example, up to four times). Remembered to the limit. The stored number of special symbol winning memories is displayed on the special symbol winning memory number display section (composite storage display section) of the light emitting display unit 64 and the display device 61. Based on the special symbol winning or the memory thereof, the game control device 100 performs a special diagram variation display game on the special diagram display 63 and also performs a decoration special diagram variation display game as an effect display on the display device 61.

  When a game ball is won at the start winning opening 56 or the start winning device 57, the special symbol (identification information) composed of the numbers and the like is displayed on the left (first special symbol) and right (second) on the display device 61. Fluctuation display is started in the order of special symbol) and medium (third special symbol), and an image relating to the special symbol variation display game is displayed. That is, in the display device 61, a special symbol variation display game corresponding to the number of stored special symbol winning memories is performed, and various displays are produced to improve interest.

  As a result of the special figure variation display game, when the winning to the starting winning opening 56 or the starting winning device 57 is made at a predetermined timing (specifically, when the winning random number at the time of winning detection is a winning value). A specific result mode (special result mode) is derived from the display symbol, and the jackpot state is obtained. Specifically, in the special symbol winning memory display unit of the display device 61, the display device 61 stops at a single-digit special symbol that is a winning symbol, and the display device 61 stops in a state where three special symbols are aligned (a big winning symbol). To do. In response to this, the special variable prize winning device 58 is easy to accept a game ball from a closed state in which a game ball is not accepted for a predetermined time by driving a built-in large prize opening solenoid 58b (see FIG. 4). It is converted to the open state, and a privilege that the player can acquire many prize balls is given.

  The winning of a game ball to the special variation winning device 58 is detected by a count switch 58a (see FIG. 4). The passing of the game ball to the normal symbol start gate 54 is detected by a normal diagram start switch 54a (see FIG. 4). The normal symbol random number counter value extracted by the passing timing of the game ball is stored in the normal symbol storage area (a part of the RAM) in the game control device 100 as a normal symbol winning memory a predetermined number of times (for example, up to four times). Remembered to the limit. Then, the number of the memorized winning prize memories is displayed on a not-illustrated memorized winning prize memory number display section of the display device 61.

  When there is a general-purpose winning memory, the game control device 100 starts a general-game variable display game on the general-purpose winning memory display section based on the general-purpose winning memory. That is, when the passage detection to the normal symbol start gate 54 is performed at a predetermined timing (specifically, when the common random number counter value at the time of passage detection is a winning value), the common symbol winning memory number display is performed. The normal symbol displayed on the part stops in the hit state and enters the hit state. At this time, the normal variation winning device 57a is converted so as to be opened for a predetermined time by driving the built-in power solenoid 57c (see FIG. 4), so that the game ball starting winning device 57 is supplied to the starting winning device 57. Winning is allowed. The opening time of the normal variation winning device 57a is, for example, 2.9 seconds in the probability variation state and the variation time shortened state, and 0.5 seconds in the normal gaming state so that the opening mode changes according to the gaming state. Can be controlled.

  In this way, when a game ball wins the general winning opening 55, the start winning opening 56, 57, or the special variable winning device 58, the number of winning balls corresponding to the type of the winning winning port is controlled by the payout control device 200. From the dispensing unit 42 to the upper plate 21 or the lower plate 32 of the front frame 12.

  FIG. 4 is a block diagram of the control system of the gaming device according to the present embodiment.

  The gaming machine 10 includes a game control device 100. The game control device 100 includes a game microcomputer 110, an input I / F (Interface) 105, an output I / F (Interface) 106, and an inspection device connection terminal 107. The microcomputer 110 includes a CPU 111, a ROM (Read Only Memory) 112, and a RAM (Random Access Memory) 113.

  The CPU 111 is a main control device that controls the game in an integrated manner, and controls the game. The ROM 112 stores invariant information (program, fixed data, etc.) for game control. The RAM 113 is used as a work area that provides a work area for the CPU during game control.

  The gaming control device 100 is provided with an inspection device connection terminal 107, and an identification number set in the gaming microcomputer 110 can be output from the inspection device connection terminal 107. Accordingly, when the inspection device is connected to the inspection device connection terminal 107, the inspection device can identify the gaming machine 10. Further, the game control device 100 is connected to an external information terminal 108, and information related to the gaming machine 10 is sent via the external information terminal 108 to an information collection terminal or a game hall internal management device (not shown) installed in the game store. ).

  The game control device 100 includes various detection devices (special drawing start switches 56a and 57b, a general drawing start switch 54a, a count switch 58a, general winning opening switches 55a to 55n, an overflow switch 32a, a frame opening switch 12a, and a ball break switch 41a. ) Is input. The overflow switch 32a detects that a predetermined number or more of game balls are stored in the lower plate 32. The frame opening switch 12a detects that the front frame 12 is opened. The ball break switch 41a is disposed in the ball storage unit 41 and detects that the number of game balls stored in the ball storage unit 41 is equal to or less than a predetermined number.

  Detection signals from the various detection devices input to the game control device 100 are input to the CPU 111 via the input I / F 105, and the CPU 111 performs various processes such as a big hit lottery based on these signals. In addition, the CPU 111 receives the light emitting display unit 64, the general-purpose display 62, the special-purpose display 63, the general-purpose SOL (solenoid) 90, the special winning opening SOL (solenoid) 38, and the payout control device via the output I / F 106. A command signal is transmitted to 200 and the effect control device 150 to control the game in an integrated manner.

  Furthermore, the game control device 100 transmits a payout command signal to the payout control device 200 that controls the payout motor 42a of the ball payout unit 42, and also includes a change start command, a customer waiting demo command, a fanfare command, A probability information command, an error designation command, and the like are transmitted as an effect control command signal.

  Next, the payout control device 200 and the effect control device 150 will be described. The effect control device 150 controls the error notification LED 18, the speaker 19, and the display device 61 based on various signals input from the game control device 100.

  The payout control device 200 performs control for driving out the payout motor 42a of the payout unit 42 in accordance with the prize ball payout command signal from the game control device 100 so as to pay out the prize ball. In addition, the payout control device 200 drives the payout motor 42a of the payout unit 42 in accordance with the payout command signal transmitted from the game control device 100 based on the loan request signal from the card unit 70, and pays out the rental money. Control for.

  The payout control device 200 includes a gaming microcomputer 210, an input I / F (Interface) 215, an output I / F (Interface) 216, and an inspection device connection terminal 217. The gaming microcomputer 210 includes a CPU 211, a ROM 212, and a RAM 213. .

  The CPU 211 is a control device that comprehensively controls payout, and controls payout control. The ROM 212 stores invariant information (program, data, etc.) for payout control. The RAM 213 is used as a work area during payout control.

  The CPU 211 receives signals from the payout ball detection switch 42b in the payout unit 42, the overflow switch 32a, the frame opening switch 12a as the bias detection switch, the ball break switch 41a, and the error release switch 44 via the input I / F 215. Entered. Further, the CPU 211 outputs drive signals for the payout motor 42 a, the firing control device 180, the error number display 43 and the like in the payout unit 42 via the output I / F 216.

  The error release switch 44 is operated by the store clerk of the amusement store to cancel the error state when the cause of the error generated by the store clerk of the amusement store is resolved when an error occurs in the payout control device 200. It is a switch. The launch control device 180 controls a launch device for launching a game ball into the game area 51. The error number display 43 is disposed on the back side of the payout control device 200 and displays the type of error that has occurred in the payout control device 200 so as to be specified.

  Note that the game control device 100, the effect control device 150, and the payout control device 200 are connected to the power supply device 160. The power supply device 160 includes a backup power supply 161 and a RAM clear switch 162. The backup power supply 161 supplies power to the game control device 100, the effect control device 150, and the payout control device 200 even in the event of a power failure (it may not be supplied to the effect control device 150). The RAM clear switch 162 is a switch that forcibly initializes information stored in the RAM 113 in the game control device 100 and the RAM 213 in the payout control device 200.

  Further, when the ball lending button 26 provided on the gaming machine 10 is operated, the card unit 70 obtains the valuable value for the gaming ball lent from the valuable value stored in the card such as the prepaid card or the membership card. The value of the value obtained by the subtraction is displayed on the balance display unit 28 of the gaming machine 10. Further, when a discharge button 27 provided on the gaming machine 10 is operated, the card unit 70 discharges the card inserted into the card insertion slot 71.

  FIG. 5 is a block diagram showing a more specific configuration of the game microcomputer (game arithmetic processing device) 110 constituting the game control device 100, and FIG. 6 is a block diagram showing a specific configuration of the random number generation circuit. It is. A conventional gaming microcomputer has a random number generation circuit configured and connected as an external circuit, whereas the gaming microcomputer of this embodiment has a significant feature in that it includes a random number generation circuit. is there.

  The gaming microcomputer 110 of this embodiment is divided into a game control block 110A for performing game control and a management block 110B for managing information. One element constituting each circuit block described below is provided on a semiconductor substrate. It is formed as a semiconductor integrated circuit (amusement chip).

  The game control block 110A includes a CPU core 111, a program ROM 112, a work RAM 113, an external bus interface 114, a bus switching circuit 115, a decryption / ROM writing circuit 116, a mirrored RAM 117, an interrupt controller 118 as an interrupt control circuit, and a boot block 119. , A reset interrupt control circuit 120, an address decoder 121, an output control circuit 122, a clock generator 123, a random number generation circuit 124, and a HW parameter ROM 125. These functional blocks and the management block 110B are connected by a CPU bus 126.

  The CPU core 111 includes various register groups, an arithmetic / logic unit (ALU), an instruction register (IR), a decoder, a program counter (PC), a stack pointer (SP), a data bus connecting them, an address bus, and various control units. In the core, for example, configured with Z80 architecture. The CPU core 111 implements various functions necessary for controlling the gaming machine 10 by software by loading and executing the game control program stored in the program ROM 112.

  The work RAM 113 corresponds to the main memory of the CPU core 111, and is composed of, for example, a high-speed semiconductor device such as an S-RAM. The work RAM 113 is used as a work area (work area) when executing processing based on the game program in the game block 110A. The work RAM 113 can be provided with a battery backup function using a dedicated terminal assigned to one of the terminal groups of the gaming microcomputer 110, and the stored contents even after the gaming machine 10 is turned off. Hold. In addition, the work RAM 113 is controlled so that the chip enable is prohibited and permitted by a protection circuit (not shown), and is read and written while the chip enable is prohibited (when power is not supplied to the gaming machine 10). None of this can be done.

  The external bus interface 114 is a circuit for performing input / output control of various signals such as a memory request signal, an input / output request signal, a memory write signal, a memory read signal, and a mode signal with an external device. The bus switching circuit 115 is a circuit that performs bus switching to enable input / output of address signals and data signals between an external bus (not shown) and the CPU bus 126 in the chip. For example, when the memory write signal WR is activated while the memory request signal MREQ or the input / output request signal IORQ is activated, an external data signal can be written to a predetermined external I / O, and the memory read signal RD is activated. Then, an external data signal can be taken in from a predetermined external I / O.

  The decryption / ROM writing circuit 116 decrypts data sent after being encrypted, generates a voltage necessary for writing to the electrically programmable program ROM 112 and the HW parameter ROM 125, and controls timing. Circuit. For example, when an external data signal is given from the outside while sequentially incrementing the external address signal while the mode signal MODE is active, it becomes a writing mode to the program ROM 112 and is made by a game machine manufacturer or a third party organization. A game program can be written. However, if the write end code is recorded in a predetermined area of the HW parameter ROM 125 described later after the game program has been written to the program ROM 112, the game program cannot be written to the program ROM 112 thereafter.

  The mirrored RAM 117 stores information obtained by copying information stored in the user work area when the clock falls (if the CPU core is Z80, processing is executed when the clock rises, and thus the mirrored RAM 117 can move in synchronization. Not so).

  The interrupt control circuit 118 is a circuit that makes an interrupt request to the CPU core 111 in response to an interrupt request signal from the outside, and sends a control signal to a circuit (for example, a random number generation circuit) inside the chip. is there. The reset interrupt control circuit 120 resets the CPU core 111 in response to a reset signal input from the outside, and generates a signal for setting various resources inside the gaming microcomputer 110 to an initial state. Circuit.

  The boot block 119 includes a ROM for storing a boot program. When the system of the gaming microcomputer 110 is reset, the boot program starts up and performs a predetermined simple check. If the boot ROM is normal, the protection setting process is executed, and then the process is transferred to a predetermined address of the game program (a predetermined address in the address space of the CPU 111 (generally, the first address 0000h in the address space)).

  The address decoder 121 decodes the address information of the CPU bus 126 and controls the output control circuit 122 according to the decoding result. The clock generator 123 generates an operation clock and a counter clock to be supplied to each block in the gaming microcomputer 110 including the CPU core 111 based on the system clock MCLK and the random number clock EXCLK supplied from the outside. .

  The random number generation circuit 124 is a circuit for generating a random number used for determination of a big hit. The conventional gaming microcomputer has a built-in one that is configured as an external circuit and adds a specific function. It is a thing. The random number generation circuit 124 will be described in detail later with reference to FIG. The HW parameter ROM 125 is used to record the write end code for prohibiting program writing to the program ROM 112 and to set parameters specific to the user system (hardware). It is constituted by a memory (for example, EPROM, EEPROM, flash memory, etc.) that can be written to.

  The management block 110B includes a management program ROM 131, a management work RAM 132, a bus monitor circuit 133, an ID property memory 134, a management control circuit 135, an external communication control circuit 136, and a local bus 137 that connects these circuit blocks. In addition, the bus monitor circuit 133 is connected to both the local bus 137 and the CPU bus 126 of the game control block 110A, so that data can be transmitted to and received from the CPU core 111 via the CPU bus 126. ing.

  The management work RAM 132 is used as a storage area for temporarily storing information of the game control block 110A read via the bus monitor circuit 133. The bus monitor circuit 133 monitors the state of the CPU bus 126. When the CPU bus 126 is not used by the CPU core 111, the program ROM 112 and the user work of the game control block 110A are connected via the CPU bus 126 as necessary. The RAM 113 and the like are accessed, and necessary data (game program, contents of the user work RAM 113, etc.) are taken into the management block 113B.

  In the ID property memory 134, a unique ID (unique information) used for identification of the gaming microcomputer 110 and determination of legitimacy is written. This unique ID is stored in the bus 137 and the external communication control circuit 136. Via a management device (hall computer) outside the gaming machine. This allows the management device to monitor the unique ID of the gaming machine. Specifically, if the unique ID set in advance in the gaming machine does not match the unique ID read by the management device, the management device disables input / output of various signals. Then, it becomes impossible to input / output signals between the various devices connected to the game control device 100 (for example, the big winning opening solenoid 58b and the normal variation winning opening solenoid 57c) and the subordinate control device and the CPU core 111. However, it becomes clear that an abnormality has occurred in the gaming machine due to the fact that the player cannot operate or the decorative lamp does not light.

  In addition to the unique ID, information such as a game type code, a rank code, a manufacturer number, a model code, and an inspection number is written in the ID property memory 134. The game type code is information for distinguishing pachinko gaming machines, throttle machines, and the like, and is represented by, for example, “P” for pachinko gaming machines and “G” for throttle machines. The rank code is a model rank code of the gaming machine 1 (a code for distinguishing between the first type and the second type), a manufacturer number, or a manufacturer ID (or manufacturer code) for identifying the manufacturer of the gaming machine 1. is there. The model code is a product code of the gaming machine 1 set by the manufacturer. The inspection number (or verification code) is a number given to the gaming machine 1 that has passed the inspection by the third party organization.

  Further, the ID property memory 134 includes a ROM and a RAM, and the contents of the ROM are copied to the RAM. That is, the unique ID, game type code, rank code, manufacturer number, model code, and inspection number are stored in the ROM, and are copied to the RAM. The copy timing is performed when the gaming machine is turned on or when the gaming microcomputer 110 is reset, for example, in an initialization process executed by the management block 110B immediately after the system reset.

  The control circuit 135 controls the operation of the management block 110B and has a buffer memory. For example, the control circuit 135 monitors the operation of the CPU core 11 via the bus monitor circuit 133, and copies the contents stored in the user work RAM 113 of the game block 110A to the mirrored RAM 117 during non-operation. Further, the contents of the ID property memory 134 of the management block 110B are transferred to the outside in response to a request from the inspection apparatus, and the program in the user program ROM 112 is sent to the outside via the bus monitor circuit 133 in response to a program request. Or transfer. The buffer memory is used for timing adjustment at the time of transfer.

  The external communication control circuit 136 communicates with an information collection terminal device and an ID inspection device provided outside the gaming machine. For example, when an information collection terminal device is connected, in response to a request from the information collection terminal device, the storage contents of the management work RAM 132 and ID property memory 134 are transferred to the requesting information collection terminal device. When the ID inspection device is connected, at least information on the unique ID stored in the ID property memory 134 is transferred to the requesting ID inspection device in response to a request from the ID inspection device.

  Next, the details of the random number generation circuit 124 built in the gaming microcomputer 110 of the present embodiment and a circuit (clock generator 123) related to the circuit will be described with reference to FIG.

  The clock generator 123 further divides a frequency dividing circuit 231 that divides an externally supplied random number clock EXCLK, a frequency dividing circuit 232 that divides the system clock MCLK, and a clock divided by the frequency dividing circuit 232 And a CTC (counter timer circuit) circuit 233 that generates a signal for frequency-dividing and interrupting the CPU core 111 with a predetermined period. The clocks φ1 and φ2 respectively divided by the frequency dividing circuit 231 and the frequency dividing circuit 232 are supplied to the random number generation circuit 124. In this embodiment, the frequency dividing ratios of the frequency dividing circuits 231 and 232 are the same (both are divided by 1/2).

  The random number generation circuit 124 includes a random number control circuit 240 that controls the entire random number generation circuit, a random number initial value setting register 241 in which an initial value of random numbers is set by the CPU core 111 via the CPU bus 126, and a random number circuit activation register 242. And a counter circuit 243. When a predetermined value is set in the random number circuit activation register 242 by the CPU core 111, the random number control circuit 240 is configured to start control of random number generation. The count range of the counter circuit 243 can be selected from a range of 8 bits (FFh) to 16 bits (FFFFh) by setting a predetermined value in the HW parameter ROM. The random number control circuit 240 has a built-in selection circuit 252 that determines the magnitude of the frequencies of the clocks φ1 and φ2 divided by the frequency dividing circuits 231 and 232, and switches between and shuts off the clock. The counter circuit 243 is caused to perform a counting operation based on this clock. When a plurality of types of random numbers are required, a plurality of counter circuits 243 are provided, and the random number initial value setting register 241 can be configured to set different initial values for each counter circuit.

  Further, the random number generation circuit 124 artificially generates three latch registers 245, 247, and 249 that take in and hold the value of the counter circuit 243, and a start winning detection signal to the counter circuit 243. Latch register trigger circuits 244, 246, and 248 for generating a trigger signal for latching the value of. The latch register trigger circuits 244, 246, and 248 can be configured by registers. The latch registers 245, 247, and 249 normally latch the value of the counter circuit 243 based on the latch signal generated by the random number control circuit 240, but the CPU core 111 supplies a predetermined value to the latch register trigger circuits 244, 246, and 248. Is set, the latch trigger signal is generated, and the value of the counter circuit 243 is latched in the latch registers 245, 247, and 249.

  In this embodiment, as shown in FIG. 7, the counter circuit 243 is updated (counted up) by the rising edge of the clock φ1 (or φ2) divided by the frequency dividing circuit 231 or 232, while the clock φ1 (φ2 ), That is, the clock / φ1 (/ φ2) having a phase difference of 180 ° is used as the latch timing signal, so that the counter value is not latched at the timing when the value of the counter circuit changes.

  The random number control circuit 240 receives the latch signals LAT0, LAT1, and LAT2 from the interrupt controller 118, and causes the latch registers 245, 247, and 249 to latch the counter based on the inputs of the latch signals LAT0, LAT1, and LAT2. Control signal is generated. In this embodiment, the start winning detection signals DET0 and DET1 from the special drawing start switches 56a and 57b are input to the interrupt controller 118, and the value of the counter circuit 243 is latched to the latch registers 245 and 247 each time a start winning is detected. Latched to either Specifically, the interrupt controller 118 detects the start winning detection signal DET continuously over 256 clocks (25.6 μs: when EXCLK or MCLK = 20 MHz is input) with the clock signal supplied to the counter circuit 243. The latch signal LAT is output to the random number control circuit 240 at the timing. The random number control circuit 240 does not latch the counter value at the timing when the latch signal LAT is input, but any one of the latch registers 245, 247, and 249 at the rising edge of the clock signal immediately after the latch signal LAT is input. The counter value is latched in the corresponding register.

  Although not particularly limited, in this embodiment, a signal of the start port switch 1 is input to DET0 (LAT0), and when the signal is input, the counter value is latched in the latch register 245. A signal of the start port switch 2 is input to DET1 (LAT1), and when the signal is input, the counter value is latched in the latch register 247. Of the three inputs of the interrupt controller 118, one DET2 (LAT2) and the latch register 249 are provided so as to be compatible with a gaming machine in which three starting winning holes are provided in the gaming area. It is treated as a spare in gaming machines.

  Instead of the interrupt controller, a control register writable from the outside may be provided, and a counter value latch signal may be generated in response to the writing to the control register. When a control register is provided, a predetermined bit of the control register is set by the start winning detection signals DET0 and DET1, and an interrupt signal is input to the interrupt controller 118. The interrupt controller 118 performs the same control as described above. You may comprise so that it may perform.

  Further, the random number generation circuit 124 includes a status register 250 for informing the CPU core 111 of the internal state of the random number generation circuit 124 and a random number circuit initialization register 251 for initializing the random number generation circuit 124. The status register 250 is provided with a latch permission flag that permits or prohibits the latching of the counter value to the latch registers 245, 247, and 249. By setting this flag, the latch of the counter value is permitted and the flag is set. The latch can be prohibited by clearing it. In this embodiment, the latch permission flag is provided corresponding to each of the latch registers 245, 247, and 249, and is configured to be able to control permission / prohibition of latch for each register. The status register 250 is rewritten by the random number control circuit 240 so that the CPU 111 can only read and cannot write. As a result, it is possible to prevent an illegal act of rewriting the program and causing the CPU to acquire an illegal random number value.

  FIG. 8 shows a latch control procedure of the counter value to the latch register by the random number control circuit 240. In this control, first, it is determined whether any of the latch signals LAT0, LAT1, and LAT2 is input (step S101). If any of the latch signals LAT0, LAT1, and LAT2 is input, the status It is determined whether the latch permission flag of the register 250 is set (step S102). If there is no latch signal input or if there is a latch signal and the latch permission flag is not set, the control is terminated, and if it is determined in step S102 that the latch permission flag is set, the counter circuit 243 The counter value is read and stored in the corresponding latch register (any one of 245, 247, and 249) (steps S103 and S104). Subsequently, the corresponding latch permission flag of the status register 250 is set to a prohibited state, and the control is terminated (step S105).

  FIG. 9 shows a control procedure when the random number control circuit 240 reads latch data. In this control, first, it is determined whether or not the CPU core 111 has read data in the latch register (any one of 245, 247, and 249) (step S111), and when data (counter value) is read, The data in the latch register is cleared, the corresponding latch permission flag in the status register 250 is set to the permitted state, and the control is terminated (steps S112 and S113). By reading the data in the latch register, clearing it, and setting the latch enable flag to the enabled state, the counter value is no longer latched due to some sort of malfunction such as a circuit failure. There is no risk of duplicate counter values being acquired. As a result, when the value held in the counter value holding means immediately before corresponds to the big hit, it is possible to prevent the big hit from occurring continuously.

  In this embodiment, the random number control circuit 240 latches the counter value in the latch register by external start winning detection signals DET0 and DET1. On the other hand, when the start winning detection signal DET0 or DET1 is input to the microcomputer, the CPU core 111 determines that the data (counter value) in the latch register 245 or 247 is a big hit if a predetermined condition is satisfied by the program processing. Read as a random value for. The latch permission flag of the status register 250 is set to the latch prohibited state until the value of the counter is latched in the latch register and is read by the CPU.

  Therefore, by performing the control as described above, even if noise is applied to the latch signals LAT0, LAT1, and LAT2 input to the random number control circuit 240, the counter value of the counter circuit 243 is erroneously latched in the latch register. Is not (overwritten), and the CPU does not read an incorrect counter value (random number value).

  In addition, in a conventional game control circuit in which a random number generation circuit is connected as an external circuit, if a player gives a latch signal at a timing different from the original start winning detection signal by an unauthorized operation, an incorrect counter value (disturbance) In this embodiment, even if the start winning detection signals DET0 and DET1 are illegally input and the counter value is latched in the latch register, the latch data is not read by the CPU. The counter value is latched in the latch register by the start winning detection signals DET0 and DET1 that are normally generated and read by the CPU. As a result, it is difficult to acquire an erroneous random number value due to fraud, and the counter value latched based on the start winning can be reliably used in the game control.

  FIG. 10 shows a procedure of hard random number clock monitoring control by the random number control circuit 240. In this control, it is determined whether the random number clock EXCLK supplied from the outside is input to the clock generator 123 (step S121). Here, when EXCLK is input, the frequency of EXCLK and the frequency of MCLK are compared to determine whether the frequency of EXCLK is higher or not, and when it is higher, the frequency of EXCLK is equal to the frequency of MCLK. It is determined whether or not it is smaller than 1.5 times (steps S122 and S123).

  Only when both conditions are satisfied, the clock φ1 obtained by dividing EXCLK by 1/2 by the clock generator 123 is supplied to the counter circuit 243 to update the counter value (step S124). If the condition is not satisfied, MCLK is supplied to the counter circuit 243, and the system operation and the counter circuit operation are performed with the same clock. The determinations in steps S122 and S123 are actually made based on the clocks φ1 and φ2 divided by the clock generator 123. Whether the frequency of EXCLK is higher than the frequency of MCLK can be determined by providing counters for counting the respective clocks and operating them for the same time to determine the magnitude of the counter value.

  As described above, the counter circuit 243 that gives a random number value is updated only when the clocks EXCLK and MCLK satisfy a predetermined condition, so that an unauthorized person performs an illegal operation on the clock input terminal and performs an illegal operation. Even if it tries to acquire a random value, it can be prevented. In addition, since the clocks φ1 and φ2 are compared and the higher frequency clock is selected and supplied to the counter circuit 243, it becomes difficult to specify the update timing of the counter circuit 243 that generates random numbers, which is illegal. Can be made difficult to do.

  Note that the frequencies of the clocks φ1 and φ2 are compared, the clock with the higher frequency is selected and supplied to the counter circuit 243, and the clock with the lower frequency is supplied to a circuit other than the counter circuit 243 as an operation clock. You may comprise as follows. By counting the counter circuit 243 with the clock with the higher frequency, and latching the counter value into the latch register with the clock with the lower frequency, the target value is latched with an illegal operation than the reverse case. Can make it difficult.

  In this embodiment, when it is determined in steps S122 and S123 that the condition is not satisfied, MCLK is supplied to the counter circuit 243. However, when it is determined that the condition is not satisfied, MCLK is supplied. Further, the supply of EXCLK may not be performed to the counter circuit, and the counter circuit may be disabled.

  Note that it is possible to select either EXCLK or MCLK by providing a clock selection register in the random number generation circuit and setting a predetermined value in the clock selection register via the HW parameter ROM.

  Next, game control executed by the game microcomputer (referred to as game microcomputer) 110 of the game control apparatus 100 will be described.

  The control process by the gaming microcomputer 110 mainly includes a main process shown in FIGS. 11 and 12 and a timer interrupt process shown in FIG. 13 performed at a predetermined time period (for example, every 2 msec).

  The main process is started when the power is turned on. In this main process, as shown in FIG. 11, first, an interrupt prohibition process (step S1) is performed, and then an interrupt vector setting process (step S1) for setting a jump destination vector address to be executed when an interrupt occurs. S2), a stack pointer setting process (step S3) for setting a stack pointer that is the start address of an area in which a value of a register or the like is saved when an interrupt occurs, and an interrupt mode setting process (step S4) for setting an interrupt processing mode. )I do.

  Next, access to a readable / writable RWM (read / write memory) such as RAM or EEPROM is permitted, and all output ports are set to OFF (no output) (steps S5 and S6). Thereafter, it is determined whether or not the clear switch 162 of the backup memory in the power supply device 160 is turned on (step S7). If the clear switch is off, in step S8, after checking the data in the power failure check area in the RWM, check the code for checking whether or not the power failure is restored and the normal / abnormal data called checksum. (Steps S9 and S10).

  If it is determined in step S9 that the power failure has been restored and it is determined in step S10 that the checksum is normal, in step S11, an initial value at the time of power failure recovery is set in the readable / writable RWM, and then the game frame state is set. The memory area in which such data is stored is cleared, a power failure recovery command is transmitted to other control devices (steps S12 and S13), and the process proceeds to step S17 in FIG. On the other hand, if it is determined in step S9 that the power failure has not been restored, or if the checksum is determined to be abnormal in step S10, the read / writeable RWM in use is cleared in step S14. Then, after the initial value at power-on is saved in the RWM, processing for transmitting a power-on command to other control devices (steps S15 and S16) is performed, and the process proceeds to step S17 in FIG.

  If it is determined in step S7 that the clear switch is on, the process jumps to step S14 to clear the read / writeable RWM being used, save the initial value at power-on in the RWM, and so on. Processing for transmitting a power-on command to the control device (steps S15 and S16) is performed, and the process proceeds to step S17 in FIG.

  In step S17, an interrupt timer is started. In next step S18, a code for starting the circuit is set in the random number circuit starting register 242 (see FIG. 6) in the random number generating circuit, and the random number generating circuit 124 is started. Thereafter, interruption is temporarily prohibited (step S19), and an initial value random number update process (step S20) is performed to update the initial value of a random number such as a jackpot determination random number and destroy the temporal regularity of the random number. Then, processing for permitting interruption (step S21) and processing for checking data in the power failure inspection area (step S22) are performed. Then, a determination is made as to whether or not a power failure has occurred (step S23). If no power failure has occurred (No), the process returns to the processing for prohibiting the above-described interrupt (step S19), and steps S19 to S23 are performed. Repeat the process.

  On the other hand, if it is determined in step S23 that a power failure has occurred (Yes), processing for temporarily prohibiting interruption (step S24), processing for turning off all output ports (step S25), and clearing the power failure inspection area The process (step S26) to perform is performed. After that, the process of saving the power failure recovery inspection area check data in the power failure recovery inspection area (step S27) and the process of calculating the checksum when the RWM is turned off (step S28) are performed, and access to the RWM is prohibited. After performing the process (step S29) to be performed, it waits for the power supply of the gaming machine to be cut off. In this way, the check data is saved in the power failure recovery inspection area, and the checksum at power-off is calculated to determine whether the information stored in the RWM is correctly backed up before power-off. This can be determined when the power is turned on again.

  Next, the timer interrupt process in FIG. 13 will be described. This timer interrupt process is started, for example, every 2 ms when a periodic timer interrupt signal generated by the CTC circuit 233 in the clock generator 123 is input. When a timer interrupt occurs in the gaming microcomputer 110, the timer interrupt process of FIG. 13 is started.

  When the timer interrupt process is started, a register saving process (step S30) is performed in which a value held in a predetermined register is first transferred to the RAM. Next, an input process (step S31) for capturing inputs from various sensors (special drawing start switches 56a and 57b, a general drawing start switch 54a, a frame opening switch 12a, a ball break switch 41a, etc.) is performed. Then, based on the output data set in various processes, an output process (step S32) for performing drive control of an actuator such as a solenoid (large winning opening SOL10b, general electric power SOL7b) or the like is performed. As for the input from the switch for detecting the winning and passing of the game ball, the input port is read every 2 ms in the input process of step S31, the chattering removal state is analyzed, and the switch level state is 0. When it changes from 1 to 1, the switch is turned on. Further, in the input process of step S31, as a method of eliminating chattering for the input of the switch when acquiring the input port state, the port state of the switch to be analyzed is read out from the input port for each interrupt and extracted. If the continuous data for two interrupts match, the state is set to a normal port state. Then, the state is determined as the level state and the level state is updated. If the data does not match, the previous level state is continued. Further, the rising edge is updated according to the change of the level state. At this time, the updated rising edge is stored in the RAM. The above processing is performed in all the switches that detect winning and passing of game balls.

  Next, command transmission processing (step S33) and random number update processing (step S34) for outputting commands set in the transmission buffer in various processings to the effect control device 150 and the payout control device 200 are performed. In this random number update process (step S34), the jackpot determination random number for determining the hit loss of the special figure variation display game and the big hit symbol random number for determining the jackpot symbol of the special figure variation display game are updated (taken in). I do. In addition, a winning random number for determining the hit variation of the normal figure fluctuation display game and a fluctuation pattern random number for determining the fluctuation pattern in the special figure fluctuation display game are updated (taken in).

  Next, a special drawing start switch 56a, 57b, an ordinary drawing start switch 54a, a winning opening switch 55a ... 55n, a winning opening switch for monitoring whether there is a normal signal input from the count switch 58a, and monitoring errors. / An error monitoring process (step S35) is performed. Also, a special figure game process (step S36) for performing a process related to the special figure variation display game and a general figure game process (step S37) for performing a process related to the common figure variation display game are performed.

  Next, segment LED editing processing (step S38) is performed (step S38), which is provided in the gaming machine 10 and drives the segment LEDs that display various information about the game to display desired contents. Then, external information editing processing (step S39) for setting a signal to be output to the external management apparatus in the output buffer is performed. Subsequently, the process of declaring the end of the interrupt (step S40) is performed, the process of restoring the saved register data (step S41), the process of permitting the interrupt (step S42), and the timer interrupt The process ends.

  Next, details of the special figure game process (step S36) in the timer interrupt process of FIG. 13 will be described with reference to FIG.

  As shown in FIG. 14, in the special game process, first, the winning (special drawing start SW1, SW2) is monitored and the winning detection is performed on the normal variable winning device 57 having the start winning port 56 and the second starting winning port. The start port switch monitoring process (step S361) for acquiring and storing various random number values based on the above is executed. The start port switch monitoring process includes a start port SW1 monitoring process (start port switch 1 monitoring process) for monitoring the winning of the start winning port 56 and a start port SW2 monitoring process (starting) for monitoring the winning to the normal variation winning device 57. Mouth switch 2 monitoring process). Thereafter, a count switch monitoring process (step S362) for monitoring the input from the count switch 58a in the special variable winning device 58 and counting the number of inputs is executed.

  Next, it is determined whether or not the game process timer set in each process relating to the execution of the special figure variation display game has expired (step S363). If it is determined that the game process timer has not timed up (No), the special figure variation control process (step S375) relating to the control of the special figure variation display game is performed and the special figure game process is terminated. In addition, in the determination of whether or not the game processing timer has expired (step S363), if it is determined that the game processing timer has expired (Yes), the game provided for reasonably progressing the game A game branching process (step S364) for selecting a process to be executed next based on the process number is performed.

  In the game branching process (step S364), when it is determined that the game process number is “0”, the special symbol variation start is monitored, the special symbol variation start setting, the effect setting, or the special graphic routine processing A special figure routine process (step S365) for setting information necessary for performing the process is performed. Further, in the game branching process (step S364), when it is determined that the game process number is “1”, the special figure first half fluctuation start process (step for setting information related to the first half fluctuation time of the special figure fluctuation display game) S366) is performed. The first half variation time is a period from the start of the special figure variation display game to the occurrence of the reach state. On the other hand, in the game branching process (step S364), when it is determined that the game process number is “2”, the special figure latter half fluctuation start process (step for setting information related to the latter half fluctuation time of the special figure fluctuation display game) (step S364). S367) is performed. The second half variation time is a period from the occurrence of the reach state to the end of the special figure variation display game.

  Also, in the game branching process (step S364), when it is determined that the game process number is “3”, the updating of the symbol and the symbol during the variation of the decorative special symbol variation display game executed on the display device 61 are temporarily performed. A special figure changing process (step S368) for performing control such as changing again after stopping is performed. Also, in the game branching process (step S364), when it is determined that the game process number is “4”, a special figure display process (step for setting a final symbol stop timing in the special figure variation game) S369) is performed.

  Further, in the game branching process (step S364), when it is determined that the game process number is “5”, the sound effect in the special gaming state (big hit), the light emission drive of the lighting unit 17, a predetermined interval (for example, 1 second) A fanfare / interval process (step S370) is performed for performing a plurality of opening operation processes of the special variable winning device 58 (large winning opening) sandwiching the.

  Further, in the game branching process (step S364), when it is determined that the game process number is “6”, a special winning opening opening process (step S371) is performed. In the special prize opening opening process (step S371), if the special gaming state is not the final round, information necessary for performing the fanfare / interval processing (step S370) is set, and the special gaming state is the final round. If there is, the setting of the command for the special game state end screen and the setting of information necessary for performing the next big winning opening remaining ball process (step S372) are performed.

  Further, in the game branching process (step S364), when it is determined that the game process number is “7”, all the game balls remaining in the big prize opening after the big prize opening is closed are detected by the count switch 58a. The winning ball remaining ball processing (step S372) for setting the time until the time is performed. Further, in the game branching process (step S364), when it is determined that the game process number is “8”, the special game state is terminated and the special figure routine process (step S365) is performed. A jackpot ending process (step S373) for setting necessary information is performed.

  Furthermore, after performing each of the above-described processes based on the game process number, the table data saving process (step S374) for saving various set data is performed, and then a process such as updating the game process timer is performed. A control process (step S375) is performed to end the special figure game process.

  Next, details of the first embodiment of the first invention of the start port SW2 monitoring process (start port switch 2 monitoring process) executed in the start port switch monitoring process (step S361) of FIG. 14 will be described with reference to FIG. I will explain.

  In the start port SW2 monitoring process (start port switch 2 monitoring process), first, it is determined whether or not the normal variation winning device 57 is in operation, that is, the open state in which the normal variation winning device 57 is activated and the game ball can be won. It is determined whether or not (step S611). In this determination, when the normal variation winning device is in operation (Yes), the process jumps to step S613 to determine whether the start port switch 2 (57b) is on. If it is determined in step S611 that the normally variable winning device is not in operation (No), it is determined in the next step whether or not the number of illegal winnings is an upper limit (step S612). In the determination of the start port switch in step S613, the presence or absence of the rising edge corresponding to the start port switch stored in the RAM in the input process in step S31 of FIG. ", It is determined that the switch state is ON, and when the updated rising edge is" NONE ", it is determined that the switch state is OFF.

  The normally variable winning device 57 cannot win game balls in the closed state, and can win game balls only in the open state. Therefore, when a game ball wins in a closed state, it is a case where some abnormality or fraud occurs, and when there is a game ball won in such a closed state, the number is counted as an illegal winning number. ing. Then, in determining whether or not the number of illegal winnings is an upper limit value (step S612), it is determined whether or not the number of illegal winnings counted in this way is equal to or greater than a predetermined upper limit value. In this determination, when the number of illegal winnings is the upper limit (Yes), the start port SW monitoring process is terminated. That is, in this case, the start memory is not generated. If it is determined in step S612 that the number of illegal winnings is not the upper limit (No), it is determined in step S613 whether the start port switch 2 (57b) is on.

  If it is determined in step S613 that the start port switch 2 is not on, the start port SW2 monitoring process is terminated. On the other hand, if it is determined in step S613 that the start port switch 2 is on, the process proceeds to step S614, and a start port signal output count update process for updating the number of winning game balls to the normal variation winning device 57 ( Step S614) is performed.

  Next, it is determined whether or not the starting memory number is the upper limit value (step S615). If the starting memory number is not the upper limit value (No) in this determination, the starting memory number is determined in the next step S616. After the increment (+1), the value of the latch register (245, 247, 249) is acquired as a big hit random value and stored in a predetermined area of the RAM (113) (step S617).

  Thereafter, a process of acquiring the big hit symbol random number and storing it in the RAM (step S618), and a process of acquiring the fluctuation pattern random number and storing it in the RAM (step S619). Further, the decorative special figure start memory number command to be transmitted to the effect control device 150 is set in the transmission circuit, and the start port SW2 monitoring process is terminated (step S620).

  If it is determined in step S615 that the start memory number is the upper limit value (Yes), that is, if no more start memory can be stored, the process proceeds to step S621, where the latch registers (245, 247, 249) is obtained, that is, only reading is performed, and the start port SW2 monitoring process is terminated. Even when the starting memory number is the upper limit value, the value of the latch register (245, 247, 249) is acquired, and as described in the latch data reading control process in FIG. When this is done, the counter value can be taken into the latch register from the counter circuit.

  Further, in the starting port switch monitoring process (step S361) of FIG. 14, the starting port SW1 monitoring process (starting port switch 1 monitoring process) is executed following the above-described starting port switch 2 monitoring process. The start port switch 1 monitoring process is substantially the same as the start port switch 2 monitoring process.

  The difference between the start port switch 2 monitoring process and the start port switch 1 monitoring process is that, in the start port switch 1 monitoring process, whether or not the normal variation winning device 57 in step S611 of the start port switch 2 monitoring process of FIG. In step 613, the start port switch 1 (56a) is turned on instead of the start port switch 2 (57b). The point is whether or not there is a determination.

  FIG. 16 shows a second embodiment of the first invention of the start port SW2 monitoring process (start port 2 monitoring process) executed in the start port switch monitoring process (step S361) of FIG. The difference between the start port switch 2 monitoring process in FIG. 16 and the start port switch 2 monitoring process in FIG. 15 is that the start port switch 2 monitoring process in FIG. 15 determines the start memory number in step S615 as an upper limit value or not. The process of acquiring the value of the latch register (step S621) to be executed when it is determined as “Yes” (step S621) is performed before the determination as to whether or not the start memory number in step S615 is the upper limit in the start port switch 2 monitoring process of FIG. It is in the point that it tries to do.

  Also in the start port switch 2 monitoring process (start port SW2 monitoring process) of this embodiment, when the start winning memory reaches the upper limit number, the counter value held in the latch register as the counter value holding means becomes a big hit random number or the like. Therefore, when the start winning is detected next time, the counter value is permitted to be taken into the latch register from the counter circuit, and the desired counter value is set when the start winning memorized number becomes smaller than the upper limit number. The counter value is stored in the counter value holding means. Further, if the start winning memorized number has reached the upper limit number, the acquired counter value is not stored in the start winning memorizing means (RAM), so that the determination by the wrong counter value is avoided. Further, in this embodiment, since the value of the latch register is acquired before determining whether or not the start memory number is the upper limit value, the counter value read from the latch register is stored in the start winning storage means. Will be held in a predetermined area (buffer) until the data is read, and it is possible to avoid the idle reading that simply reads the counter value and does not hold it anywhere like the embodiment of FIG. Can be eliminated.

  Next, a third embodiment of the first invention of the start port SW2 monitoring process (start port 2 monitoring process) executed in the start port switch monitoring process (step S361) of FIG. 14 will be described with reference to FIGS. It explains using. In the third embodiment, a random number latch interrupt process as shown in FIG. 17 is provided as one of interrupt processes for the CPU 111. Then, when the number of times of input of the hard latch signal updated during this interrupt processing is monitored during the start port switch monitoring processing of FIG. 18, when there is an abnormality, the counter value of the counter circuit is latched again in the latch register. There is a feature in making it.

  In this embodiment, based on the start winning detection signal (DET0 to DET2) being input to the interrupt controller 118, a signal (hard latch signal) LAT0 instructing the latch supplied from the interrupt controller 118 to the random number control circuit 240. When .about.LAT2 is input to the CPU 111, the random number latch interrupt process of FIG. 17 is started. Instead of the hard latch signals LAT0 to LAT2 supplied to the random number control circuit 240, a signal output from the random number control circuit 240 to the latch register may be input to the CPU 111 as an interrupt signal to start processing.

  When this random number latch interrupt processing is started, the interrupt is first prohibited, and the values held in various registers in the gaming microcomputer 110 are saved to the stack area in the RAM 113, and then the number of hard latch signal inputs is updated. (Increment) (steps S81 to S83). Thereafter, the end of the interrupt is declared and the value of the register saved in step S82 is restored to the original register, and then the interrupt is permitted and the process is terminated (steps S84 to S86).

  In the starting port SW2 monitoring process (starting port switch 2 monitoring process) in FIG. 18, first, it is determined whether or not the normal variation winning device 57 is in operation, that is, the normal variation winning device 57 is activated and a game ball can be won. It is determined whether or not it is in the open state (step S631). In this determination, when the normal variation winning device is in operation (Yes), the process jumps to step S633 to determine whether or not the start port switch 2 (57b) is on. If it is determined in step S631 that the normally variable winning device is not in operation (No), it is determined in the next step whether or not the number of illegal winnings is an upper limit (step S632).

  The normally variable winning device 57 cannot win game balls in the closed state, and can win game balls only in the open state. Therefore, when a game ball wins in a closed state, it is a case where some abnormality or fraud occurs, and when there is a game ball won in such a closed state, the number is counted as an illegal winning number. ing. In the determination of whether or not the number of illegal winnings is the upper limit (step S632), it is determined whether or not the number of illegal winnings counted in this way is equal to or greater than a predetermined upper limit. In this determination, when the number of illegal winnings is the upper limit (Yes), the start port SW monitoring process is terminated. That is, in this case, the start memory is not generated. If it is determined in step S632 that the number of illegal winnings is not the upper limit (No), it is determined in step S633 whether the start port switch 2 (57b) is on.

  If it is determined in step S633 that the start port switch 2 is not on, the start port SW2 monitoring process is terminated. On the other hand, if it is determined in step S633 that the start port switch 2 is ON, the process proceeds to step S634, and a latch register value acquisition process (step S634) is performed. Next, a start port signal output number updating process for updating the number of winnings of game balls to the normal variation winning device 57 is performed.

  Subsequently, it is determined whether or not the start memory number is the upper limit value (step S636). If the start memory number is the upper limit value in this determination, the monitoring process is terminated and the start memory number is not the upper limit value. If this is the case, in the next step S637, the number of start-port switches and the number of hard latch signal inputs are compared to determine whether or not the number of hard latch signal inputs is abnormal. Here, the abnormality of the hard latch signal input count is a case where the hard latch signal input count is considerably larger than the start opening switch count. The number of hard latch signal inputs compared to the number of start port switches when a false start detection signal is input due to noise or a false start detection signal is input by the player to illegally generate a big hit. Therefore, by making the determination in step S637, it is possible to prevent malfunction and fraud due to noise as described above.

  If it is determined in step S637 that there is an abnormality (Yes), one of the latch register trigger circuits 244, 246, 248 (see FIG. 6) is set in the next step S638, and a latch signal is generated by software processing. With this latch signal, the value of the counter circuit 243 is latched in one of the latch registers 245, 247, and 249. In step S639, the value of the latch register is acquired, and the process proceeds to step S640. On the other hand, if it is determined in step S637 that there is no abnormality (No), the process jumps to step S640. In step S640, the register value acquired in step S633 or the register value acquired in step S639 is stored in the RAM as a big hit random number.

  After that, after updating (incrementing) the starting memory number in step S641, processing for acquiring the big hit symbol random number and storing it in the RAM (step S642), processing for acquiring the fluctuation pattern random number and storing it in the RAM (step S643) is performed. Further, a process for setting a decoration special figure start memory number command to be transmitted to the effect control device 150 is performed in the transmission circuit (step S644), and the start port SW2 monitoring process is terminated.

  Further, in the starting port switch monitoring process (step S361) of FIG. 14, the starting port SW1 monitoring process (starting port switch 1 monitoring process) is executed following the above-described starting port switch 2 monitoring process. The start port switch 1 monitoring process is substantially the same as the start port switch 2 monitoring process.

  The difference between the start port switch 2 monitoring process and the start port switch 1 monitoring process is that in the start port switch 1 monitoring process, the normal variation winning device 57 in step S631 of the start port switch 2 monitoring process of FIG. 18 is operating. In step S632, the start opening switch 1 (56a) is turned on instead of the start opening switch 2 (57b). The point is whether or not there is a determination.

  FIG. 19 shows a random number latch interrupt as one of the interrupt processes executed based on the signal input from the outside separately from the timer interrupt process (FIG. 13) in the second and third embodiments. The processing procedure is shown.

  This random number latch interrupt processing is a signal (hard latch signal) that instructs the latch supplied from the interrupt controller 118 to the random number control circuit 240 based on the input of the start winning detection signal (DET0 to DET2) to the interrupt controller 118. ) It is started when LAT0 to LAT2 are input to the CPU 111. Instead of the hard latch signals LAT0 to LAT2 supplied to the random number control circuit 240, a signal output from the random number control circuit 240 to the latch register may be input to the CPU 111 as an interrupt signal to start processing.

  When this random number latch interrupt process is started, the interrupt is first prohibited and the values held in the various registers in the gaming microcomputer 110 are saved to the stack area in the RAM 113, and then the latch registers (245, 247, 249) is acquired, and the acquired value is stored in a latch random number area which is a buffer area in the RAM (steps S51 to S54). Thereafter, the end of the interrupt is declared and the value of the register saved in step S52 is restored to the original register, and then the interrupt is permitted and the process is terminated (steps S55 to S57).

  Next, the details of the start port switch 2 monitoring process (step S361) in the second and third embodiments of the special invention game process of FIG. 14 executed in the start port SW monitoring process (step S361) are shown in FIG. 20 will be described.

  In the start port SW2 monitoring process (start port switch 2 monitoring process), first, it is determined whether or not the normal variation winning device 57 is in operation, that is, the open state in which the normal variation winning device 57 is activated and the game ball can be won. It is determined whether or not (step S611). In this determination, when the normal variation winning device is in operation (Yes), the process jumps to step S613 to determine whether the start port switch 2 (57b) is on. If it is determined in step S611 that the normally variable winning device is not in operation (No), it is determined in the next step whether or not the number of illegal winnings is an upper limit (step S612).

  The normally variable winning device 57 cannot win game balls in the closed state, and can win game balls only in the open state. Therefore, when a game ball wins in a closed state, it is a case where some abnormality or fraud occurs, and when there is a game ball won in such a closed state, the number is counted as an illegal winning number. ing. In step S612, it is determined whether or not the number of illegal prizes thus counted is equal to or greater than a predetermined upper limit value. In this determination, when the number of illegal winnings is the upper limit value (Yes), the start port SW2 monitoring process is terminated. That is, in this case, the start memory is not generated. If it is determined in step S612 that the number of illegal winnings is not the upper limit (No), it is determined in step S613 whether the start port switch 2 (57b) is on.

  If it is determined in step S613 that the start port switch 2 is not on, the start port SW2 monitoring process is terminated. On the other hand, if it is determined in step S613 that the start port switch 2 is on, the process proceeds to step S614 to start the start port signal for updating the number of winning game balls to the start winning port 56 and the normal variation winning device 57. An output count update process (step S614) is performed.

  Next, it is determined whether or not the starting memory number is the upper limit value (step S615). If the starting memory number is not the upper limit value (No) in this determination, the starting memory number is determined in the next step S616. After the increment (+1), the value stored in the latch random number area in the RAM in step S54 in FIG. 15 is stored in the predetermined area in the RAM (113) as the big hit random number value (step S617). Then, a predetermined loss value (fixed value) is stored in the latch random number area (step S618). Instead of storing the lost value, the stored value may be cleared to “all 0” or set to a fixed value such as “all 1”. Thus, by storing a fixed value in the latch random number area after storing it as a random number value, even if the random number latch interrupt processing is not performed due to some trouble such as a circuit failure, the acquired counter value is duplicated. Thus, it can be prevented from being stored as a random value. As a result, when the value held in the latch random number area immediately before corresponds to the big hit, it is possible to prevent the big hit from occurring. Note that step S618 may be omitted.

  Thereafter, a process of acquiring the big hit symbol random number and storing it in the RAM (step S619), and a process of acquiring the fluctuation pattern random number and storing it in the RAM (step S620). Furthermore, the process of setting the decoration special figure start memory number command to be transmitted to the effect control device 150 is set in the transmission circuit (step S621), and the start port SW2 monitoring process is terminated. Further, when it is determined in step S615 that the start memory number is the upper limit value (Yes), that is, when the start memory cannot be stored any more, the start port SW2 monitoring process is terminated.

  Further, in the starting port switch monitoring process (step S361) of FIG. 14, the starting port SW1 monitoring process (starting port switch 1 monitoring process) is executed following the above-described starting port switch 2 monitoring process. The start port switch 1 monitoring process is substantially the same as the start port switch 2 monitoring process.

  The difference between the start port switch 2 monitoring process and the start port switch 1 monitoring process is that, in the start port switch 1 monitoring process, the normal variation winning device 57 in step S611 of the start port switch 2 monitoring process of FIG. 20 is operating. In step 613, the start port switch 1 (56a) is turned on instead of the start port switch 2 (57b). The point is whether or not there is a determination.

  Based on the input of the start detection signal from the outside, the value of the counter circuit 243 is latched in the latch registers 245, 247, and 249 in the random number generation circuit 124, and then the value held in the latch register in the timer interrupt processing is used as the random number value. In the case of acquisition, noise is generated in the random number generation circuit 124 between the input of the start detection signal and the start of the timer interrupt process, and the value of the counter circuit 243 is erroneously set to the latch registers 245, 247, and 249 by the noise. If the counter value is latched by any of the above, there is a possibility that the counter value taken into the latch register due to noise is acquired as a random value by the CPU.

  However, as in the above embodiment, the value held in the latch register is acquired as a random value by the random number latch interrupt process of FIG. 15 executed by the CPU based on the input of the start detection signal, and the timer interrupt process thereafter. By storing the random number value already acquired in the start port switch 2 monitoring process executed in step 2 as a regular random number value, it is latched by noise generated between the input of the start detection signal and the start of the timer interrupt process. It is possible to prevent an erroneous random number value from being used for the determination.

  FIG. 21 shows a procedure of random number latch interrupt processing as one of interrupt processing executed based on signal input from the outside separately from the timer interrupt processing (FIG. 13) in the embodiment of the fourth invention. Has been. In the flowchart of FIG. 21, the game board is provided with two start winning openings (56 and 57 in FIG. 3), so that different types of variable display games are executed depending on the winning at each start winning opening. When game control is set, when a start winning occurs after the process by one timer interrupt is finished and the next timer interrupt process is started (2 msec in the embodiment), The winning order can be distinguished and memorized. In the following description, the start winning port 56 is referred to as “start port 1”, and the start winning device 57 is referred to as “start port 2”. The latch registers 245 and 247 are also fixed to the start port 1 and the start port 2 corresponding to the start winning ports. In this way, for example, the special figure 1 fluctuates by winning the start opening 1, and the special figure 2 fluctuates by winning the starting opening 2. When performing game control with different game values, it is possible to prevent a wrong game value from being given by accurately determining the winning order.

  This random number latch interrupt processing is a signal (hard latch signal) LAT0 instructing the latch supplied from the interrupt controller 118 to the random number control circuit 240 based on the start winning detection signal DET0 or DET1 being input to the interrupt controller 118. Alternatively, it is started by inputting LAT1 to the CPU 111. Instead of the hard latch signals LAT0 and LAT1 supplied to the random number control circuit 240, a signal output from the random number control circuit 240 to the latch register may be input to the CPU 111 as an interrupt signal to start processing.

  When this random number latch interrupt processing is started, the interrupt is first prohibited and the values held in the various registers in the gaming microcomputer 110 are saved to the stack area in the RAM 113, and then the corresponding latch register 245 or 247 is stored. Is acquired (steps S51 to S53). Subsequently, it is determined by referring to the latch permission flag of the status register 250 corresponding to the latch register 245 whether or not the latch register 245 is prohibited from latching (step S54). This is because the prohibition flag is set when the counter value is latched based on the start winning.

  If it is determined in step S54 that it is “latching prohibited” (Yes), the starting port number of the starting port 1 is acquired in the next step S55, and if it is determined that it is not “latching prohibited” (No), In step S56, the start port number of the start port 2 is acquired. The starting port number may be stored in the ROM, or may be stored in a predetermined area of the RAM in the program initialization process. Thereafter, the “previous start opening prize information area” and “rear start opening prize information area” in the start opening prize information storage area as shown in FIG. 22 prepared in the RAM (113) are examined, and the data is “0”. It is determined whether or not (step S57).

  Here, if the data are both “0” (Yes), the starting port number acquired in step S55 is stored in the “starting port number information” column of the “first starting port winning information area” in FIG. (Step S58), the value of the latch register acquired in Step S53 is divided and stored in the “Random number (upper)” and “Random number (lower)” fields of the “First starting entry prize information area” in FIG. 22 (Step S59). . On the other hand, if it is determined in step S57 that the data is not “0” (No), the process proceeds to step S60, and the starting port number information acquired in step S55 or S56 is “first starting port winning information area” “ It is determined whether or not it matches the “starting port number information”. Here, if the numbers match, the value of the latch register acquired in step S53 is overwritten in the “random number (upper)” and “random number (lower)” fields of the “pre-start opening prize information area” (step S61). ). Thus, even when the latch register latches the counter value due to noise, the value of the latch register acquired by the random number latch interrupt process can be stored.

  If it is determined in step S60 that the numbers do not match (No), the starting port number acquired in step S55 is set in the “starting port number information” in the “rear starting port winning information area” in FIG. (Step S62), and the value of the latch register acquired in step S53 is stored separately in the "Random number (upper)" and "Random number (lower)" fields of the "Rear start opening prize information area" in FIG. (Step S63). Thereafter, after the end of the interrupt is declared in step S64, the value of the register saved in step S52 is restored to the original register, and then the interrupt is permitted and the process is terminated (steps S65 and S66). By performing the processing as described above, even when a game ball wins in succession at the start port 1 and the start port 2, the counter values latched in the latch registers in accordance with the order are accurately stored as each random number value. be able to.

  Next, the details of the start port switch monitoring process (step S361) in the embodiment of the fourth invention executed in the special figure game process of FIG. 14 will be described with reference to FIGS.

  As shown in FIG. 23, in the start port SW monitoring process (start port switch monitoring process), first, data is stored in the “first start port winning information area” and “rear starting start winning information area” in FIG. It is determined whether or not (step S601). If the data is not stored, the monitoring process is terminated. If the data is stored, the “start port number information” in the “previous start port winning information area” is started in the next step S602. It is determined whether the mouth 1 or not. When the “start port number information” is the start port 1, the start port SW1 monitoring process S610 (FIG. 24) is executed, and then the start port SW2 monitoring process S630 (FIG. 25) is executed. When “information” is not the start port 1, that is, the start port 2, the start port SW2 monitoring process S630 (FIG. 25) is executed, and then the start port SW1 monitoring process S610 (FIG. 24) is executed. The difference between the start port SW1 monitoring process S610 (FIG. 24) and the start port SW2 monitoring process S630 (FIG. 25) is that the start port SW1 monitoring process S610 (FIG. 24) is different from the start port SW2 monitoring process S630 (FIG. 25). This is the point that the determination in step S611 and the determination in step S612 that are performed first do not exist. First, the start port SW2 monitoring process S630 will be described.

  In the start port SW2 monitoring process S630, as shown in FIG. 25, first, it is determined whether or not the normal variation winning device 57 is in operation, that is, the normal variation winning device 57 is activated and the game ball can be won. It is determined whether or not (step S611). In this determination, when the normally variable winning device is operating (Yes), the process jumps to step S613 to determine whether or not the start port switches (56a, 57b) are on. If it is determined in step S611 that the normally variable winning device is not in operation (No), it is determined in the next step whether or not the number of illegal winnings is an upper limit (step S612).

  The normally variable winning device 57 cannot win game balls in the closed state, and can win game balls only in the open state. Therefore, when a game ball wins in a closed state, it is a case where some abnormality or fraud occurs, and when there is a game ball won in such a closed state, the number is counted as an illegal winning number. ing. In step S612, it is determined whether or not the number of illegal prizes thus counted is equal to or greater than a predetermined upper limit value. In this determination, when the number of illegal winnings is the upper limit value (Yes), the start port SW2 monitoring process is terminated. That is, in this case, the start memory is not generated. If it is determined in step S612 that the number of illegal winnings is not the upper limit (No), it is determined in step S613 whether or not the start port switches (56a, 57b) are on.

  If it is determined in step S613 that the start port switch is not on, the start port SW2 monitoring process is terminated. On the other hand, if it is determined in step S613 that the start port switch is on, the process proceeds to step S614, and a start port signal output for updating the number of winning game balls to the start winning port 56 and the normal variation winning device 57 is updated. Update the number of times.

  Next, it is determined whether or not the starting memory number is the upper limit value (step S615). If it is determined in this determination that the starting memory number is the upper limit value (Yes), that is, starting memory is further stored. If it cannot be stored, the start port SW2 monitoring process is terminated.

  If it is determined in step S615 that the starting memory number is not the upper limit value (No), the starting memory number is incremented (+1) in the next step S616, and then the “first starting port winning information area” in FIG. Similarly, the value stored in the random number area is stored as a big hit random number value in a predetermined area in the RAM (113) (step S617). Then, the value stored in the “rear start opening prize information area” is shifted to the “previous start opening prize information area” and stored, and the “rear start opening prize information area” after the shift is cleared (the stored value is “ 0 ”(steps S618 and S619).

  Here, if significant values are stored in the “previous start opening prize information area” and the “rear start opening prize information area”, the stored value of the “following start opening prize information area” is “previous start opening prize information area”. The shift to the “winning information area” is cleared, and the “post-start opening winning information area” is cleared. In the case where a significant value is stored only in the “pre-start opening prize information area”, the value of the “post-start opening prize information area” is originally “0”, which is the “pre-start opening prize information area”. By shifting to, the “preliminary start opening prize information area” is cleared. In addition, when the start port SW2 monitoring process is performed after the start port SW1 monitoring process, the “rear start port winning information area” is cleared after the shift in the start port SW1 monitoring process, and the “after By shifting the value (“0”) of the “start opening prize information area” to the “previous starting opening prize information area”, the “previous start opening prize information area” is cleared.

  After the above process, a process of acquiring the jackpot symbol random number and storing it in the RAM (step S620), a process of acquiring the fluctuation pattern random number and storing it in the RAM (step S621), and further transmitting the decoration feature to the effect control device 150. The process of setting the figure start memory number command in the transmission circuit is performed (step S622), and the start port SW2 monitoring process is terminated.

  As described above, by reading the value in the start opening prize information storage area, storing it as a big hit random number value, and then clearing it, there is no possibility of acquiring the acquired random number value in duplicate. Thereby, when the random number value stored in the start opening prize information storage area immediately before corresponds to the big hit, it is possible to prevent the big hit from being generated. In addition, after shifting the value of the “next start opening prize information area” to the “previous start opening prize information area”, by clearing the “after start opening prize information area”, the information of the “first start opening prize information area” is changed. The clearing operation is omitted, the counter value (random number) reading operation is simplified, the processing speed is increased, and the program capacity can be reduced. Further, it is possible to prevent a malfunction in which the counter value (random number) once acquired is acquired again.

  FIG. 26 shows a procedure of random number latch interrupt processing as one of interrupt processing executed based on signal input from the outside separately from the timer interrupt processing (FIG. 13) in the first embodiment of the fifth invention. It is shown.

  This random number latch interrupt processing is a signal (hard latch signal) that instructs the latch supplied from the interrupt controller 118 to the random number control circuit 240 based on the input of the start winning detection signal (DET0 to DET2) to the interrupt controller 118. ) It is started when LAT0 to LAT2 are input to the CPU 111. Instead of the hard latch signals LAT0 to LAT2 supplied to the random number control circuit 240, a signal output from the random number control circuit 240 to the latch register may be input to the CPU 111 as an interrupt signal to start processing.

  When this random number latch interrupt process is started, interrupts are first prohibited and the values held in the various registers in the gaming microcomputer 110 are saved to the stack area in the RAM 113 (steps S51 and S52). Then, a delay timer including a soft timer provided in the RAM 113 or the like is updated (+1), and it is determined whether or not the delay timer has expired (steps S53 and S54). If the delay timer has not expired, the process returns to step S53 to update the timer. When the delay timer expires, the process proceeds to step S55, the counter value held in the latch registers (245, 247, 249) is acquired, and the acquired value is latched as a buffer area in the RAM. Store in the random number area.

  Next, the counter value acquired in step S55 is added to the value of the delay timer, and the added value is set in the delay timer (steps S56 and S57). Thereafter, the end of the interrupt is declared and the value of the register saved in step S52 is restored to the original register, and then the interrupt is permitted and the process is terminated (steps S55 to S57). Since the counter value acquired in step S55 is different every time, the values obtained by adding the acquired counter value to the delay timer value are set in the delay timer as in steps S56 and S57, so that steps S53 and S54 are performed. The time required to exit, that is, the delay time can be made random. As a result, even if it is attempted to illegally acquire the counter value of the latch register, it is difficult to specify the acquisition timing, and illegal activities can be prevented.

  Next, details of the start port switch monitoring process (step S361) in the embodiment of the fifth invention executed in the start port switch monitoring process (step S361) of the special figure game process of FIG. 14 will be described with reference to FIG. To do.

  In the start port SW2 monitoring process (start port switch 2 monitoring process), first, it is determined whether or not the normal variation winning device 57 is in operation, that is, the open state in which the normal variation winning device 57 is activated and the game ball can be won. It is determined whether or not (step S611). In this determination, when the normal variation winning device is in operation (Yes), the process jumps to step S613 to determine whether the start port switch 2 (57b) is on. If it is determined in step S611 that the normally variable winning device is not in operation (No), it is determined in the next step whether or not the number of illegal winnings is an upper limit (step S612).

  The normally variable winning device 57 cannot win game balls in the closed state, and can win game balls only in the open state. Therefore, when a game ball wins in a closed state, it is a case where some abnormality or fraud occurs, and when there is a game ball won in such a closed state, the number is counted as an illegal winning number. ing. In step S612, it is determined whether or not the number of illegal prizes thus counted is equal to or greater than a predetermined upper limit value. In this determination, when the number of illegal winnings is the upper limit (Yes), the start port SW monitoring process is terminated. That is, in this case, the start memory is not generated. If it is determined in step S612 that the number of illegal winnings is not the upper limit (No), it is determined in step S613 whether the start port switch 2 (57b) is on.

  If it is determined in step S613 that the start port switch 2 is not on, the start port SW2 monitoring process is terminated. On the other hand, if it is determined in step S613 that the start port switch 2 is on, the process proceeds to step S614 to start the start port signal for updating the number of winning game balls to the start winning port 56 and the normal variation winning device 57. Perform output count update processing.

  Next, it is determined whether or not the starting memory number is the upper limit value (step S615). If the starting memory number is not the upper limit value (No) in this determination, the starting memory number is determined in the next step S616. After the increment (+1), the value acquired in step S55 of FIG. 26 and stored in the latch random number area in the RAM is stored in the predetermined area in the RAM (113) as the big hit random number value (step S617). Then, a predetermined loss value (fixed value) is stored in the latch random number area (step S618). Instead of storing the lost value, the stored value may be cleared to “all 0” or set to “all 1”. Thus, by storing a fixed value in the latch random number area after storing it as a random number value, even if the random number latch interrupt processing is not performed due to some trouble such as a circuit failure, the acquired counter value is duplicated. Thus, it can be prevented from being stored as a random value. As a result, when the value held in the latch random number area immediately before corresponds to the big hit, it is possible to prevent the big hit from occurring.

  Thereafter, a process of acquiring the big hit symbol random number and storing it in the RAM (step S619), and a process of acquiring the fluctuation pattern random number and storing it in the RAM (step S620). Furthermore, the process of setting the decoration special figure start memory number command to be transmitted to the effect control device 150 is set in the transmission circuit (step S621), and the start port SW monitoring process is terminated. If it is determined in step S615 that the start memory number is the upper limit value (Yes), that is, if no more start memory can be stored, the start port SW2 monitoring process is terminated.

  Further, in the starting port switch monitoring process (step S361) of FIG. 14, the starting port SW1 monitoring process (starting port switch 1 monitoring process) is executed following the above-described starting port switch 2 monitoring process. The start port switch 1 monitoring process is substantially the same as the start port switch 2 monitoring process.

  The difference between the start port switch 2 monitoring process and the start port switch 1 monitoring process is that in the start port switch 1 monitoring process, the normal variation winning device 57 in step S611 of the start port switch 2 monitoring process of FIG. 27 is operating. In step 613, the start port switch 1 (56a) is turned on instead of the start port switch 2 (57b). The point is whether or not there is a determination.

  Based on the input of the start detection signal from the outside, the value of the counter circuit 243 is latched in the latch registers 245, 247, and 249 in the random number generation circuit 124, and then the value held in the latch register in the timer interrupt processing is used as the random number value. In the case of acquisition, noise is generated in the random number generation circuit 124 between the input of the start detection signal and the start of the timer interrupt process, and the value of the counter circuit 243 is erroneously set to the latch registers 245, 247, and 249 by the noise. If the counter value is latched by any of the above, there is a possibility that the counter value taken into the latch register due to noise is acquired as a random value by the CPU.

  However, as in the above embodiment, the value held in the latch register is acquired as a random value by the random number latch interrupt process of FIG. 26 executed by the CPU based on the input of the start detection signal, and the timer interrupt process thereafter. By storing the random number value already acquired in the start port switch 2 monitoring process executed in step 2 as a regular random number value, it is latched by noise generated between the input of the start detection signal and the start of the timer interrupt process. It is possible to prevent an erroneous random number value from being used for the determination.

  FIG. 28 shows the procedure of random number latch interrupt processing in the second embodiment of the fifth invention.

  In the random number latch interrupt process of FIG. 26, the counter value acquired from the latch register is stored as a random number and added to the delay timer, whereas the random number latch interrupt process of FIG. 28 is added to the delay timer. A value and a value used as a random number are acquired from different latch registers. In applying this embodiment, when data is set in the latch register trigger circuits 244, 246 and 248, a trigger signal for latching the value of the counter circuit 243 in the corresponding latch register is generated. It is necessary that the trigger signal is also supplied to the CPU 111 to be a pseudo start winning detection signal for executing the random number latch interrupt process.

  When this random number latch interrupt process is started, interrupts are first prohibited and the values held in the various registers in the gaming microcomputer 110 are saved in the stack area in the RAM 113 (steps S61 and S62). Next, with reference to the latch permission flag corresponding to the latch register (latch 1) 247 of the status register 250, it is determined whether there is latched data (counter value) (step S63). When the random number latch interrupt processing is started for the first time, it is determined that there is no data (No), and in the next step S64, the counter value latched in the latch register (latch 0) 245 is acquired and the value is delayed. The timer is set (step S65).

  Then, the delay timer is updated (+1), and it is determined whether or not the delay timer has expired (steps S66 and S67). If the delay timer has not expired, the process returns to step S66 to update the timer. When the delay timer expires, the process proceeds to step S68 to set data in the latch register trigger circuit 246 and generate a trigger signal for causing the latch register (latch 1) 247 to latch the counter value. Thereafter, the end of the interrupt is declared and the value of the register saved in step S62 is restored to the original register, and then the interrupt is permitted and the process is terminated (steps S71 to S73).

  When the trigger signal is generated in step S68, the value of the counter circuit 243 is latched in the latch register (latch 1) 247 by the random number generation circuit 124, and the pseudo start winning detection signal is supplied to the CPU 111. Random number latch interrupt processing starts. In step S63, it is determined that there is data (Yes), the process proceeds to step S69, the counter value held by the latch register (latch 1) 247 is acquired, and the acquired value is a buffer area in the RAM. Store in the latch random number area. Thereafter, the end of the interrupt is declared and the value of the register saved in step S62 is restored to the original register, and then the interrupt is permitted and the process is terminated (steps S71 to S73).

  In this embodiment, since the counter value acquired in step S64 is different every time, it is necessary to set the value obtained by adding the acquired counter value to the value of the delay timer in the delay timer so as to exit steps S66 and S67. The time or delay time can be random. When the delay timer expires, a pseudo start winning detection signal is generated and the value of the counter circuit is latched in another latch register, which is acquired as a random number. As a result, even if it is attempted to illegally acquire the counter value of the latch register, it is difficult to specify the acquisition timing, and illegal activities can be prevented.

  FIG. 28 is a flowchart when the start winning detection signal DET0 is input and the hard latch signal LAT0 for latching the value of the counter circuit 243 in the latch register (latch 0) 245 is generated based on the start winning detection signal DET0. When the start winning detection signal DET1 is input, “Latch 1” in Steps S63, S68, and S69 of FIG. 28 is replaced with “Latch 0”, and “Latch 0” in Step S64 is replaced with “Latch 1”. This can be dealt with by performing processing according to a similar flowchart.

  Although the invention made by the present inventor has been specifically described based on the embodiments, the embodiments disclosed herein are illustrative and non-restrictive in every respect. The scope of the present invention is shown not by the above description of the invention but by the scope of claims, and is intended to include all modifications within the scope and meaning equivalent to the scope of claims.

  For example, in the embodiment, the latch permission flag is provided in the status register 250 to control the latching of the counter value to the latch register. However, when the latch signal is input, the counter value is transferred to the destination. When the value is “0000h”, the counter value is stored in the register. When the register value is not “0000h”, the counter value is not stored in the register. By doing so, the latch register may be prevented from being overwritten. In this way, the status register can be omitted.

  Further, by providing a flag indicating prohibition / permission of latch in the status register, the value of the counter circuit can be prevented in the latch register at an incorrect timing due to noise. Therefore, the software processing shown in FIGS. 20 and 21 is applied. In this case, the random number generation circuit 124 may omit the prevention of erroneous latching of the counter value by hardware using the latch permission flag of the status register 250. However, it is possible to realize a gaming microcomputer that is more resistant to noise by applying both prevention of erroneous latching of the counter value by hardware and prevention of erroneous latching of the counter value by software.

  The present invention is not limited to a pachinko gaming machine in which a game ball as a game medium is rented out by a card unit, and can also be applied to a gaming machine such as an arrangement ball gaming machine, a sparrow ball gaming machine, and a slot machine.

DESCRIPTION OF SYMBOLS 10 Game machine 11 Main body frame 12 Front frame 13 Hinge 15 Glass frame 16 Decoration member 17 Illumination unit 18 Error notification LED
DESCRIPTION OF SYMBOLS 19 Speaker 20 Opening and closing panel 21 Upper plate 26 Ball lending button 27 Eject button 28 Balance display part 30 Fixed panel 31 Ashtray 32 Lower plate 34 Lower plate ball removal mechanism 41 Ball storage unit 42 Ball discharge unit (discharge device)
50 game board 51 game area 54 normal symbol start gate 55 general winning opening control device 56 starting winning port 57 starting winning device 57a normal variable winning device 56a, 57b start switch (start winning detection means)
58 Special variation winning device 59 Out port 61 Display device 70 Card unit 100 Game control device 110 Microcomputer for game (game control means)
124 random number generation circuit 150 production control device 160 power supply device 161 backup power supply 200 payout control device 240 random number control circuit 243 counter circuit (counter means)
244 Latch register trigger circuit 245, 247, 249 Latch register (counter value holding means)
250 Status register (Counter value change prohibition means)
252 selection circuit (clock selection means)

Claims (2)

A game area provided with a start area and a plurality of winning portions, a start winning detection means for detecting a game ball passing through the start area, and a game value according to winning in the winning section in the gaming area, In a gaming machine comprising a game control means for executing an auxiliary game in response to the passage of a game ball to the starting area and granting a privilege to a player when the auxiliary game has a special result,
The game control means includes
Counter means for counting in a predetermined range based on a clock signal of a predetermined period;
Counter value holding means for capturing and holding the counter value counted by the counter means based on the detection result of the start winning detection means;
Interrupt processing execution means for executing interrupt processing based on an interrupt signal generated every predetermined time;
Counter value storage means for storing a counter value acquired from the counter value holding means;
Counter value acquisition means for acquiring the counter value held by the counter value holding means based on the detection result from the start winning detection means and storing it in the counter value storage means;
The interrupt processing execution means includes
Random value storage for storing a counter value stored in the counter value storage means as a random value used in the control of the auxiliary game when a predetermined condition is established based on a detection result from the start winning detection means Means,
Counter value initialization means for setting the stored value of the counter value storage means to a predetermined value after the random value storage means stores the counter value stored in the counter value storage means as a random value. A gaming machine characterized by A counter value change prohibiting unit that prohibits rewriting of the counter value held in the counter value holding unit until the counter value held in the counter value holding unit is acquired by the counter value acquiring unit;
The counter value change prohibiting means includes:
Latch prohibiting means for prohibiting the counter value from being taken into the counter value holding means on the condition that the counter value holding means has taken in the counter value;
Latch permitting means for permitting the counter value holding means to take in the counter value on the condition that the counter value holding means has acquired the counter value held by the counter value holding means,
The latch permission means includes
2. The gaming machine according to claim 1, wherein after the value held by the counter value holding means is cleared, the counter value holding means is allowed to take in the counter value.

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