JP2011134242A - Method and program for verifying circuit design - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a verification method and verification program of circuit design, which can improve the quality of a circuit by detecting the deadlock of a state machine. <P>SOLUTION: A plurality of state machines depending on each other are taken out from a circuit description as a verification object (OPA), and transitions of the plurality of taken-out state machines are synthesized to generate one transition diagram (OPB), and a first verification property for verifying whether each state in the generated transition diagram can be transited to an idle state or not is generated (OPC), and the generated first verification property is inserted to the plurality of taken-out state machines to perform formal verification (OPD and OPE), and if violation is found in the first verification property as a result of the formal verification performed by inserting the first verification property to the plurality of taken-out state machines, a second verification property for verifying whether a deadlock occurs in an actual circuit or not is generated from the first verification property (OPF). <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a circuit design verification method and a verification program.

  In recent years, with the progress of semiconductor integrated circuit manufacturing technology, the degree of circuit integration on a semiconductor substrate has been improved, and various circuits have been mounted on the same semiconductor chip.

  Conventionally, in the logic circuit design verification method, for example, after a verification item is extracted, a checker is manually created, and simulation verification or formal verification is performed using the checker.

  Conventionally, there have been proposed an LSI design verification apparatus capable of shortening the time required for property verification, and an LSI design verification method for optimizing inter-module interface specifications by verifying properties for each module.

JP 2008-181210 A JP 2003-196342 A

  As described above, in the conventional logic circuit design verification method, for example, after a verification item is extracted, a checker is manually created, and simulation verification or formal verification is performed using the checker.

  However, with such a verification method, it is difficult to create a checker for detecting a deadlock in the state machine, and when the verification item is extracted, the verification item is leaked and the state machine is verified. There was also a fear of not being broken. As a result, it has been difficult to detect a deadlock in a state machine.

  According to the circuit design verification method of one embodiment, a plurality of state machines having mutual dependencies are extracted from a circuit description to be verified, and a transition diagram is synthesized by combining the transitions of the extracted state machines. Generate.

  Furthermore, a first verification property for verifying whether or not each state of the generated transition diagram can transition to an idle state is generated, and the generated first verification property is inserted into the plurality of extracted state machines to formally Perform verification.

  If a violation is found in the first verification property as a result of the formal verification, a second verification property for verifying whether a deadlock occurs in an actual circuit is generated from the first verification property.

  The disclosed circuit design verification method and verification program have the effect of detecting deadlocks in the state machine and improving the quality of the circuit.

It is a block diagram which shows an example of the system which verifies the circuit design of one Example. It is a figure for demonstrating an example of the operation | movement in the circuit design verification system of FIG. It is a block diagram which shows an example of the hardware constitutions of the circuit design verification system of FIG. It is a figure for demonstrating an example of the process which takes out the circuit description of a state machine. It is a figure for demonstrating an example of the production | generation process of a 1st verification property. It is a figure for demonstrating an example of the production | generation process of a 2nd verification property. It is a figure for demonstrating an example of the verification process performed by inserting a 2nd verification property. It is a figure for demonstrating one Example at the time of extracting the state machine which has a mutual dependency. It is a figure which shows an example of the transition diagram produced | generated by combining the transition of two state machines shown in FIG.

  Hereinafter, embodiments of a circuit design verification method and a verification program will be described in detail with reference to the accompanying drawings.

  FIG. 1 is a block diagram showing an example of a system for verifying a circuit design according to an embodiment. FIG. 2 is a diagram for explaining an example of an operation in the circuit design verification system of FIG.

  In FIG. 1, reference numeral 100 is a circuit description, 101 is a state machine extraction circuit, 102 is a state machine database, 103 is a synthetic transition diagram generation device, 104 is a synthetic state machine transition diagram database, and 105 is a first verification property generation. The device is shown.

  Here, the circuit description 100 may be, for example, a program level circuit description based on RTL (Register Transfer Level) or a gate level circuit description.

  Further, reference numeral 106 denotes a first verification property database, 107 denotes a formal verification device, 108 denotes a second verification property generation device, 109 denotes a second verification property database, and 110 denotes a verification device.

  As shown in FIG. 2, when the processing operation starts, in operation OPA, the state machine extraction circuit 101 extracts (extracts) a state machine having a mutual dependency from the logic circuit (circuit description 100) to be verified. Then, the operation proceeds to operation OPB. The extracted state machine is stored in the state machine database 102.

  Here, the state machines having a dependency relationship with each other represent, for example, those in which each state machine inputs and outputs a signal that is a transition condition directly or through the logic of a combinational circuit. .

  Next, in operation OPB, a transition diagram is generated by synthesizing the transitions of the state machine extracted by the combined transition diagram generation device 103. The generated synthesized state machine transition diagram is stored in the synthesized state machine transition diagram database 104.

  Further, proceeding to operation OPC, the first verification property generation device 105 generates a property (first verification property: property A) indicating whether or not each state of the transition diagram can be returned to the idle state (IDLE state). To proceed to operation OPD. The generated first verification property is stored in the first verification property database 106.

  In the operation OPD, the formal verification device 107 inserts the first verification property (property A) into the plurality of extracted state machines and performs formal verification (formal verification of the synthesized state machine in which the first verification property is incorporated). )I do.

  Further, proceeding to operation OPE, it is determined whether or not a violation (Error) is found in the first verification property (property A) by the formal verification of the synthetic state machine in which the first verification property is incorporated.

  In operation OPE, when it is determined that a violation is found in the first verification property by the formal verification of the synthetic state machine in which the first verification property is incorporated, the operation proceeds to operation OPF, and it is determined that no violation is found. The process is terminated.

  In operation OPF, a second verification property for verifying whether or not a deadlock occurs in the actual circuit is generated from the first verification property determined by the second verification property generation device 108 to be violated. Proceed to OPG. The generated second verification property is stored in the second verification property database 109.

  In operation OPG, the verification device 110 performs verification by inserting the second verification property (property B) into the circuit description to be verified. Here, the verification performed by the verification apparatus 110 is formal verification or simulation.

  Then, in operation OPG, if the second verification property is found not to be violated as a result of the verification performed by inserting the second verification property into the circuit description to be verified, the extracted plurality of state machines must generate a deadlock. Determine and end the process.

  FIG. 3 is a block diagram showing an example of a hardware configuration of the circuit design verification system of FIG. In FIG. 3, reference numeral 200 denotes a bus, 201 denotes a CPU, 202 denotes a memory unit, 203 denotes a display unit, and 204 denotes an output unit.

  Reference numeral 205 denotes an input unit, 206 denotes a communication unit, 207 denotes a storage device, 208 denotes a driver, and 209 denotes a storage medium.

  Thus, the circuit design verification system can be realized by a general-purpose computer, and the circuit design verification program is executed by such a computer.

  The circuit design verification program is provided via the driver 208 by a storage medium (portable recording medium) 209 such as an optical disk such as a CD-ROM or DVD, or a magnetic disk or magnetic tape, for example.

  Alternatively, the communication unit 206 is connected to the Internet or the like, a circuit design verification program is stored in the storage device 207 via the bus 200, and the stored program is executed.

  FIG. 4 is a diagram for explaining an example of processing for extracting the circuit description of the state machine, and details an example of the operation OPA in FIG. 2 performed by the state machine extracting apparatus 101 in FIG.

  As shown in FIG. 4, when the process of extracting the circuit description of the state machine starts, all the state machines in the target circuit description are extracted in operation OPH, and the process proceeds to operation OPI.

  Further, in operation OPI, the transition condition signal of each state machine is extracted and the operation proceeds to operation OPJ.

  In the operation OPJ, only the extracted state machines and the state machines that are mutually dependent in the extracted transition condition signal of each state machine are extracted.

  The state machine extracted in this way is stored in the state machine database 102 in FIG. 1 as described above.

  FIG. 5 is a diagram for explaining an example of the first verification property generation process, and details an example of the operation OPC in FIG. 2 performed by the first verification property generation apparatus 105 in FIG. .

  That is, the composite transition diagram generation device 103 generates one transition diagram in which transitions of a plurality of state machines are combined, and whether or not all states can transition to the idle state (IDLE state) from the composite transition diagram. A first verification property to be verified is generated.

  As shown in FIG. 5, when the generation process of the first verification property is started, the IDLE state is specified from each state in operation OPK, and the process proceeds to operation OPL.

  In the operation OPL, all the states other than the IDLE state are enumerated, and further, the operation OPM is advanced to a property (first verification property: property A) that becomes always (IDLE state → each enumerated state → IDLE state). create.

  The first verification property generated in this way is stored in the first verification property database 106 in FIG. 1 as described above.

  FIG. 6 is a diagram for explaining an example of the generation process of the second verification property, and details an example of the operation OPF in FIG. 2 performed by the second verification property generation apparatus 108 in FIG. .

  In other words, the first verification property (property A) is incorporated in the state machine having the mutual dependency extracted by the operation OPJ in FIG. 4, and the formal verification is performed by the formal verification device 107 in FIG. .

  As a result of the formal verification by the formal verification device 107, if any of the first verification properties is violated, it is verified whether a deadlock occurs in the actual logic circuit from the first verification property of the violation. A second verification property (property B) is generated.

  Here, the verification of whether or not a deadlock occurs in the actual logic circuit corresponds to the verification of whether or not the state transits to the state of the first verification property where the violation is found.

  As shown in FIG. 6, when the generation process of the second verification property is started, the first verification property having the violation is extracted in operation OPN, and the process proceeds to operation OPO.

  In the operation OPO, the “enumerated state” portion is extracted from the property (first verification property: property A) which is always (IDLE state → each enumerated state → IDLE state).

  Further, the process proceeds to operation OPP to create a second verification property (property B) that is never (“enumerated states”), and ends the process.

  The second verification property generated in this way is stored in the second verification property database 109 in FIG. 1 as described above.

  Then, the second verification property (property B) stored in the second verification property database 109 is incorporated in the circuit description to be verified and verified by the verification device 110 in FIG.

  FIG. 7 is a diagram for explaining an example of the verification process performed by inserting the second verification property, and details an example of the operation OPG in FIG. 2 performed by the verification device 110 in FIG. .

  As shown in FIG. 7, when the verification process performed by inserting the second verification property is started, the generated property is incorporated into the verification environment in operation OPQ, and the process proceeds to operation OPR.

  In operation OPR, the verification apparatus 110 verifies the entire circuit and ends the processing.

  Here, the verification by the verification device 110 is, for example, formal verification or simulation. A deadlock is detected by performing formal verification or simulation verification on the entire target circuit.

  In the above, each operation may be each step in the flowchart.

  FIG. 8 is a diagram for explaining an embodiment in which state machines having mutual dependencies are extracted. FIG. 8A shows “A State machine”, and FIG. Indicates "B State machine".

  Here, in FIGS. 8A and 8B, the reference symbol “I” represents the IDLE state (idle state), “W” represents the WRITE state (write state), and “R” represents Indicates the READY state (ready state).

  That is, FIG. 8A shows “A State machine” that transitions between IDLE state “I” and WRITE state “W”, and FIG. 8B shows IDLE state “I”, WRITE state “. Shows "B State machine" transitioning between "W" and READY state "R".

  In the “B State machine” shown in FIG. 8B, e = A State == I & a and b = B State == W & ˜f & ˜h are established.

  FIG. 9 is a diagram showing an example of a transition diagram generated by combining the transitions of the two state machines shown in FIG. 8 (FIGS. 8A and 8B). In FIG. 9, since the combination of the IDLE states of the state machines in FIGS. 8A and 8B is “AI & BI”, “AI & BI” represents the IDLE state.

  All the states are extracted from FIG. 9, and a property for verifying whether it is possible to return from one state to the IDLE state is generated.

property1: assert always ({(AI &BI); ~ (AI & BI) [*]; (AW & BW)} | =>
{~ (AI & BI) [*]; (AI &BI)});
property2: assert always ({(AI &BI); ~ (AI & BI) [*]; (AW & BR)} | =>
{~ (AI & BI) [*]; (AI &BI)});
property3: assert always ({(AI &BI); ~ (AI & BI) [*]; (AI & BW)} | =>
{~ (AI & BI) [*]; (AI &BI)});
property4: assert always ({(AI &BI); ~ (AI & BI) [*]; (AW & BI)} | =>
{~ (AI & BI) [*]; (AI &BI)});

  Properties 1 to 4 correspond to the first verification property (property A), and are inserted into the extracted state machines having a mutual dependency (a plurality of extracted state machines) to perform formal verification.

  At this time, for example, when formal verification performed by incorporating property4 results in Error, that is, as a result of formal verification performed by incorporating property4, a violation is found in the first verification property (property A) think of.

  Here, since the state machine has no restriction on the operation condition of the signal that is the transition condition of each state, there is a possibility that the state machine has transitioned to a state that does not transition. Therefore, it is verified whether or not deadlock occurs in an actual circuit.

That is, from property4, property5 (second verification) that verifies whether a deadlock occurs in the actual circuit (circuit description to be verified) as described below (whether the transition is made to the property state in which the error occurred). Property (property B)).
property5: assert never {(AW &BI)};

  If formal verification or simulation verification incorporating property 5 is performed on the circuit description to be verified, it is possible to detect a circuit in which the state machine transition is deadlocked.

  That is, the quality of the circuit can be improved by detecting the deadlock of the state machine.

  The description with reference to FIGS. 8 and 9 is merely an example, and it goes without saying that the present embodiment can be applied to the case where a plurality of state machines having various interdependencies are extracted. Nor.

  The circuit design verification method described above can also be provided as a program executed by the hardware configuration (computer) shown in FIG. 3 described above.

DESCRIPTION OF SYMBOLS 100 Circuit description 101 State machine extraction circuit 102 State machine database 103 Synthetic transition diagram production | generation apparatus 104 Synthetic state machine transition diagram database 105 1st verification property production | generation apparatus 106 1st verification property database 107 Formal verification apparatus 108 2nd verification property production | generation apparatus 109 Second verification property database 110 Verification device 200 Bus 201 CPU
202 Memory Unit 203 Display Unit 204 Output Unit 205 Input Unit 206 Communication Unit 207 Storage Device 208 Driver 209 Storage Medium

Claims (5)

Extract multiple state machines that have mutual dependencies from the circuit description to be verified,
A transition diagram is generated by combining the transitions of the extracted state machines,
Generating a first verification property for verifying whether or not each state of the generated transition diagram can transition to an idle state;
The generated first verification property is inserted into the extracted state machines to perform formal verification,
As a result of the formal verification performed by inserting the first verification property into the extracted plurality of state machines, if a violation is found in the first verification property, a deadlock occurs in the actual circuit from the first verification property. A circuit design verification method, characterized by generating a second verification property for verifying whether or not an error occurs. The verification method according to claim 1,
As a result of the formal verification performed by inserting the first verification property into the plurality of extracted state machines, if the violation is not found in the first verification property, the extracted plurality of state machines A circuit design verification method characterized in that it does not occur. The verification method according to claim 1, further comprising:
A circuit design verification method, wherein the generated second verification property is inserted into the circuit description to be verified to perform formal verification or simulation. The verification method according to claim 3, further comprising:
As a result of the formal verification or simulation performed by inserting the second verification property into the circuit description to be verified, if the second verification property is found to be violated, the extracted plurality of state machines generate a deadlock. If the second verification property is not violated, it is determined that the extracted plurality of state machines do not cause a deadlock. On the computer,
A procedure for extracting a plurality of state machines that have mutual dependencies from the circuit description to be verified,
A procedure for generating a transition diagram by combining the transitions of the extracted state machines;
Generating a first verification property for verifying whether each state of the generated transition diagram can transition to an idle state;
Inserting the generated first verification property into the extracted plurality of state machines to perform formal verification;
As a result of the formal verification performed by inserting the first verification property into the extracted plurality of state machines, if a violation is found in the first verification property, a deadlock occurs in the actual circuit from the first verification property. And a procedure for generating a second verification property for verifying whether or not the error occurs.

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