JP2011128709A - Information processor and method for processing processor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an information processor and a method of processing the processor can achieving a stable operation by reducing the possibility of an intermittent failure. <P>SOLUTION: The information processor includes: an instruction fetch means for fetching an instruction; an instruction decode means for decoding the fetched instruction; a plurality of execution circuits for executing the decoded instruction; and an instruction control means. When an instruction with the high possibility of the occurrence of any failure is decoded, the instruction control means confirms whether the execution circuit is electrically stable, and when the execution circuit is electrically stable, the instruction control means makes the execution circuit execute the pertinent instruction. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to an information processing apparatus and a processing method for a processor, and more particularly to an information processing apparatus (such as a processor) and a processing method for a processor capable of realizing stable operation by reducing the possibility of intermittent failure.

  A technique is known in which, when an intermittent failure is detected, a pseudo cache miss is performed to invalidate the operation and minimize the influence of the intermittent failure.

  Patent Document 1 discloses a technology in which the data processor 2 detects an abnormality of an instruction while reading and executing an instruction included in the sections A to C of the instruction flow, and stops execution of the subsequent instructions when the abnormality is detected. (FIG. 15). The data processor 142 of Patent Document 1 includes a subtraction circuit 147 and an accumulator 148 as an arithmetic circuit for detecting an illegal attack. The subtraction circuit 147 subtracts the instruction code held in the instruction register 145 from the value held in the accumulator 148 and returns the subtraction result to the accumulator 148. When the subtraction circuit becomes zero, the subtraction circuit 147 sets a zero flag and supplies it to the control circuit 149. When the control circuit 149 detects a zero flag in the set state in a predetermined instruction execution section, the control circuit 149 stops the instruction execution or enters a specific infinite loop to stop the original program execution.

JP2008-287449

  However, Patent Document 1 has a problem that a program is not completely executed when an intermittent failure occurs. Further, Patent Document 1 has a problem that it is not possible to specify an instruction that causes the same intermittent failure that will occur in the future.

  An object of the present invention is to provide an information processing apparatus and a processor processing method capable of reducing the possibility of intermittent failure and realizing stable operation.

An information processing apparatus of the present invention includes an instruction fetch unit that fetches an instruction, an instruction decode unit that decodes a fetched instruction, a plurality of execution circuits that execute the decoded instruction,
Instruction control means for checking whether an execution circuit is electrically stable when an instruction having a high possibility of occurrence of a failure is decoded, and causing the execution circuit to execute the instruction when the instruction is electrically stable And.

  According to the processor processing method of the present invention, when an instruction fetch step for fetching an instruction, an instruction decode step for decoding the fetched instruction, and an instruction having a high possibility of occurrence of a failure are decoded, the execution circuit is electrically It has a first determination step for determining whether or not it is stable, and an instruction execution step for causing the execution circuit to execute the instruction when it is electrically stable.

  The present invention has an effect that a stable operation can be realized by reducing the possibility of an intermittent failure by executing an instruction that is likely to cause a failure only when the execution circuit is stable.

FIG. 1 is a diagram showing the inside of a processor according to the first embodiment of the present invention. 4 is a flowchart showing an outline of operation of the fetch decoding unit 1. 3 is a flowchart showing an outline of the operation of an instruction scheduling unit 21. 3 is a flowchart showing an outline of operation of a non-core unit 3. It is the figure which showed the inside of a processor in detail. It is a figure which shows the command sequence of the command which should be performed. It is a figure which shows the data of failure location usage instruction DB12. It is a figure which shows the command information sent to the command control part 11 from the command decoding means 102. It is a figure which shows the information sent to the failure location use command detection means 37 from the adder 30. FIG. It is a figure which shows the information sent to the multiplier 31 failure location use command detection means 37. FIG. It is a figure which shows the data of failure location use command DB12 when an intermittent failure generate | occur | produces with the ADD command. It is a figure which shows the data of failure location usage instruction DB12. It is a figure which shows the data sent from the instruction decoding means 102 to the instruction control part 11. It is a block diagram which shows the 2nd Embodiment of this invention. It is a block diagram which shows the related technology of this invention.

  First, a first embodiment of the present invention will be described. In the present embodiment, a processor will be described as an example of the information processing apparatus.

  FIG. 1 is a diagram showing the inside of the processor of this embodiment. The processor 10 includes a fetch decoding unit 1, a processor core unit 2, and a non-core unit 3.

  The fetch decoding unit 1 has a function of holding an instruction, fetching and decoding the instruction, and sending the instruction to the processor core unit 2. In general, a branch prediction mechanism is also included.

  The fetch decode unit 1 determines an instruction cache 103 in which instructions are stored, an instruction fetch unit 101 that fetches instructions, an instruction decode unit 102 that decodes instructions, and whether to send an instruction to the processor core unit 2 An instruction control unit 11 for executing the failure, and a failure part use instruction DB (Data Base) 12 which is a database storing instruction types related to failures that have occurred in the past.

An example of data stored in the failure part use instruction DB 12 is shown in FIG. A valid bit field 7-1 and an instruction type field 7-2 are provided. In FIG. 11, the instruction type field 7-2 is "ADD instruction", and the corresponding valid bit field 7-1 is "1". This means that an intermittent failure has occurred in the past due to an ADD instruction. Note that the configuration of the failure part use instruction DB 12 is not limited to this.
The instruction cache 103 is the same as the instruction cache of a general processor, for example, a 128 KB / line, 2-way set associative 64 KB size cache.

  The processor core unit 2 performs preprocessing (execution schedule management, etc.) for executing instructions, and executes non-core unit execution circuits 30-35 (adder 30, multiplier 31, divider 32, address calculation means 33, It has a function of sending instructions to the CPU control circuit 34 and the data cache 35). The processor core unit 2 includes an instruction scheduling unit 21, an operation instruction RS (Reservation Station) 22, a memory system instruction RS (Reservation Station) 22, and a control system instruction RS (Reservation Station) 24.

  The operation instruction RS22 is a buffer for waiting for operands, generally called a reservation station. The arithmetic instruction RS22 registers the instruction distributed from the instruction scheduling means 21, selects an executable instruction, and sends it to the adder 30, the multiplier 31, the divider 32, etc. according to the instruction type. The arithmetic instruction RS22 mainly executes an integer / floating point arithmetic instruction or a logical operation, but the configuration may be divided into an integer / floating point, or a plurality of them may be provided.

  The memory command RS23 is a buffer for waiting for operands, generally called a reservation station. The memory system instruction RS23 registers the instruction distributed from the instruction scheduling unit 21, selects an executable instruction, and sends the instruction to the address calculation unit 33. The memory system instruction RS23 mainly processes load / store instructions to the memory. It may be divided into a plurality of RSs.

  The control system instruction RS24 is a buffer for waiting for operands, generally called a reservation station, registers the instruction distributed from the instruction scheduling means 21, selects an executable instruction, and sends the instruction to the CPU. The data is sent to the control circuit 34. The control system command RS24 mainly handles commands for controlling the entire CPU, such as a CPU status flag operation command, an operation mode operation command, and a CPU performance counter operation command. It may be divided into a plurality of RSs.

  The non-core unit 3 includes an instruction end detection means 36, a failure part use instruction detection means 37, and a plurality of execution circuits 30-35. The non-core unit 3 includes an adder 30, a multiplier 31, a divider 32, an address calculation unit 33, a CPU control circuit 34, and a data cache 35 as execution circuits. Each execution circuit is provided with a flag, and the flag stores whether or not an intermittent failure has occurred in the circuit in the past. The adder 30 includes a flag 301, the multiplier 31 includes a flag 311, the address calculation unit 33 includes a flag 331, the CPU control circuit 34 includes a flag 341, the divider 32 includes a flag 321, and the data cache 35 Includes a flag 351.

  The instruction end detection means 36 performs a process generally called retirement processing, determines whether or not the executed instructions can end without contradiction in order, and if it is possible to complete the instruction, Informs the scheduling means 21 of the end of the instruction.

  The failure part use command detection means 37 specifies which command caused the intermittent failure when the intermittent failure is detected. Therefore, the failure part use instruction detecting unit 37 can notify the failure part use instruction DB 12 of the type of instruction that may use the failure circuit.

  Next, an outline of the operation of the fetch decoding unit 1 will be described using a flowchart. FIG. 2 is a flowchart showing an outline of the operation of the fetch decoding unit.

  The instruction fetch unit 101 fetches an instruction from the instruction cache 103 and sends it to the instruction decoding unit 102 (step S201). The instruction decoding unit 102 refers to the failure part use instruction DB 12 and checks whether the instruction type is registered in the failure part use instruction DB 12 (step S202).

  Then, the instruction decoding unit 102 determines whether or not the instruction control unit 11 is a decoded instruction and an instruction registered in the failure part use instruction DB 12 (whether or not the instruction has caused an intermittent failure in the past). Is sent (step S203). FIG. 8 shows an example of instruction information. The command information includes a valid bit field 8-1, a command field 8-2, and an intermittent failure field 8-3. The instruction information in FIG. 8 means that both the ADD instruction and the MULT instruction have not caused an intermittent failure in the past and are valid information. Details will be described later.

  In this embodiment, the instruction decoding unit 102 is configured to be able to send a maximum of four instructions to the instruction control unit 11 as one packet or one frame, but is not limited to this.

  The instruction control unit 11 determines whether or not the instruction received from the instruction decoding unit 102 is an instruction related to a failure that has occurred in the past based on the instruction information (step S204). In the case of an instruction related to a failure that has occurred in the past, the instruction control unit 11 inquires the instruction scheduling unit 21 about the execution circuit. Then, the instruction control unit 11 refers to the execution circuit information sent from the instruction scheduling unit 21 (step S205), and holds the instruction until it can be confirmed that the execution circuit to be used is electrically stable. (Step S206, Step S207). When it is confirmed that the execution circuit is electrically stable, the instruction control unit 11 sends the instruction to the instruction scheduling means (step S208).

  In this embodiment, “electrically stable” means a state in which all preceding instructions of the instruction determined to be “related to a failure that occurred in the past” in step S204 have been completed. It is not limited to.

  On the other hand, if the instruction received from the instruction decoding unit 102 is not an instruction related to a failure that has occurred in the past, the instruction control unit 11 does not hold the instruction and sends it to the instruction scheduling unit 21 (steps S204 and S208).

  Next, an operation outline of the instruction scheduling unit 21 will be described using a flowchart. FIG. 3 is a flowchart showing an outline of the operation of the instruction scheduling means 21.

  The instruction scheduling unit 21 performs an operand dependency analysis and an end order guarantee operation called an instruction queue or a reorder buffer, which is performed in a general processor.

  When the instruction scheduling unit 21 receives an inquiry about the information of the execution circuit from the instruction control unit 11 (step S300), the instruction scheduling unit 21 checks whether all the preceding instructions have been completed (step S301). When all the preceding instructions have been completed, the instruction scheduling means 21 notifies the instruction control unit 11 that the circuit is stable (steps S302 and S303).

  Then, when receiving an instruction from the instruction control unit 11, the instruction scheduling unit 21 sends the instruction to the execution pipeline (step S305). Specifically, the instruction scheduling means 21 classifies and sends out the operation instruction RS22, the memory system instruction RS23, and the control system instruction RS24 for each instruction type. The arithmetic instruction RS22, the memory system instruction RS23, and the control system instruction RS24 each select an executable instruction and send the instruction to the execution circuit 30-35 of the non-core unit 3 (step S306).

  On the other hand, when the instruction scheduling unit 21 receives an instruction without receiving an inquiry about the information of the execution circuit from the instruction control unit 11 (steps S300 and S304), the instruction scheduling unit 21 sends the instruction to the execution pipeline (step S305). . Specifically, the instruction scheduling means 21 classifies and sends out the operation instruction RS22, the memory system instruction RS23, and the control system instruction RS24 for each instruction type. The arithmetic instruction RS22, the memory system instruction RS23, and the control system instruction RS24 each select an executable instruction and send the instruction to the execution circuit 30-35 of the non-core unit 3 (step S306).

  In the present embodiment, the instruction scheduling unit 21 holds information indicating whether or not the instruction has been completed, but the present invention is not limited to this.

  Next, the operation | movement outline | summary of the non-core part 3 is demonstrated using a flowchart. FIG. 4 is a flowchart showing an outline of the operation of the non-core unit. In particular, steps S400 to S405 are an outline of the operation of each execution circuit.

  First, an outline of the operation of each execution circuit will be described. Although the contents of arithmetic processing are different in each execution circuit, other operations are the same.

  The case of the adder 30 will be described.

  The adder 30 performs a floating point / fixed point addition operation. Internally, failure detection circuits such as parity check and duplication are included.

  When a failure occurs (step S400), the adder 30 checks whether the flag 301 is lit (step S401). If the flag 301 has already been lit, the adder 30 determines that a fixed failure has occurred, and indicates that the instruction type information (that is, the added instruction type information) being executed at the time of the failure is a fixed failure. Is sent to the failure part use command detection means 37 (step S402). Then, the failure part use instruction detection unit 37 performs failure processing such as system stop (step S410).

  On the other hand, if the flag 301 is not lit when a failure occurs, it means that the failure is the first, so the adder 30 determines that an intermittent failure has occurred and turns on the flag 301. Then, the type information of the command that was being executed when the failure occurred (that is, the added command type information) and the information indicating that there is an intermittent failure are sent to the failure part use command detection means 37 (steps S403 and S404). Then, the failure part use instruction detection unit 37 registers that an intermittent failure has occurred in the failure part use instruction DB 12 (step S409), and the adder 30 notifies the instruction end detection unit 36 that the execution of the instruction has ended. Send (step S405).

  FIG. 9 shows an example of information that the adder 30 sends to the failure part use command detection means 37 when a fixed failure occurs. The information in FIG. 9 includes a valid bit field 9-1, an instruction type field 9-2, and a fixed fault field 9-3. In FIG. 9, the valid bit field is “1”, which means that it is valid information. Further, the fixed failure field 9-3 is “0”, which means that no fixed failure has occurred.

  Next, the case of the multiplier 31 (step S400 to step S405, step S409, step S410) will be described.

  The multiplier 31 performs a floating point / fixed point multiplication operation. Internally, failure detection circuits such as parity check and duplication are included.

  When a failure occurs (step S400), the multiplier 31 checks whether or not the flag 311 is already lit (step S401). If the flag 311 has already been lit, the multiplier 31 determines that a fixed failure has occurred, and indicates that the instruction type information (that is, the multiplication instruction type information) being executed at the time of the failure and the fixed failure are present. Is sent to the failure part use command detection means 37 (step S402). Then, the failure part use instruction detection unit 37 performs failure processing such as system stop (step S410).

  On the other hand, if the flag 311 is not lit when a failure occurs, it means that the failure is the first, so the multiplier 31 determines that an intermittent failure has occurred and turns on the flag 311. Then, the type information of the instruction that was being executed when the failure occurred (that is, the multiplication command type information) and the information indicating that there is an intermittent failure are sent to the failure part use command detection means 37 (steps S403 and S404). Then, the failure part use instruction detection unit 37 registers that an intermittent failure has occurred in the failure part use instruction DB 12 (step S409), and the multiplier 31 notifies the instruction end detection unit 36 that the execution of the instruction has ended. Send (step S405).

  Note that the information that the multiplier 31 sends to the failure part use command detection means 37 when a fixed failure occurs is the same as that in the case of the adder 30, and a detailed description thereof will be omitted.

  Next, the case of the divider 32 (step S400 to step S405, step S409, step S410) will be described.

  The divider 32 performs a floating point / fixed point division operation. Internally, failure detection circuits such as parity check and duplication are included.

  When a failure occurs (step S400), the divider 32 checks whether the flag 321 is already lit (step S401). When the flag 321 has already been lit, the divider 32 determines that a fixed failure has occurred, and indicates that the instruction type information (that is, division instruction type information) being executed at the time of the failure and the fixed failure are present. Is sent to the failure part use command detection means 37 (step S402). Then, the failure part use instruction detection unit 37 performs failure processing such as system stop (step S410).

  On the other hand, if the flag 321 is not lit when the failure occurs, it means that the failure is the first, so the divider 32 determines that an intermittent failure has occurred and turns on the flag 321. Then, the type information (that is, the division command type) of the instruction being executed at the time of the failure and the information indicating that there is an intermittent failure are sent to the failure part use command detection means 37 (steps S403 and S404). Then, the failure part use instruction detection unit 37 registers that an intermittent failure has occurred in the failure part use instruction DB 12 (step S409), and the divider 32 notifies the instruction end detection unit 36 that the execution of the instruction has ended. Send (step S405).

  Note that the information that the divider 32 sends to the failure part use command detection means 37 when a fixed failure occurs is the same as that in the case of the adder 30, and therefore detailed description thereof is omitted.

  Next, the case of the address calculation means 33 (step S400 to step S405, step S409, step S410) will be described.

  The address calculation means 33 performs address calculation for memory access. Internally, failure detection circuits such as parity check and duplication are included.

  When a failure is detected (step S400), the address calculation means 33 checks whether the flag 331 has already been lit (step S401). If the flag 331 has already been lit, the address calculation means 33 determines that a fixed fault has occurred, and the instruction type information (that is, the memory system instruction type information) that was being executed at the time of the fault and the fixed fault. Information indicating the presence is sent to the failure part use command detection means 37 (step S402). Here, when the address calculation is executed, an instruction is transferred to the data cache 35, and an actual memory access operation is performed.

  On the other hand, if the flag 331 is not lit when the failure occurs, it means that the failure is the first, so the address calculation means 33 determines that an intermittent failure has occurred and turns on the flag 331. At the same time, the type information (that is, the memory type command type information) of the instruction being executed at the time of the failure and the information indicating the intermittent failure are sent to the failure part use command detection means 37 (steps S403 and S404). Then, the failure part use instruction detection unit 37 registers that an intermittent failure has occurred in the failure part use instruction DB 12 (step S409), and the address calculation unit 33 indicates that the execution of the instruction has been completed. (Step S405).

  Note that the information that the multiplier 31 sends to the failure part use command detection means 37 when a fixed failure occurs is the same as that in the case of the adder 30, and a detailed description thereof will be omitted.

  Next, the case of the data cache 35 (step S400 to step S405, step S409, step S410) will be described.

  The data cache 35 is the same as a data cache in a general processor, and mainly performs data load / store operations. Internally, failure detection circuits such as parity check and duplexing are included.

  When a failure occurs (step S400), the data cache 35 checks whether the flag 351 is already lit (step S401). If the flag 351 has already been lit, the data cache 35 determines that a fixed failure has occurred, and the type information of the instruction being executed at the time of the failure (that is, the memory system instruction type information) and the fixed failure. Information indicating this is sent to the failure part use command detection means 37 (step S402).

  On the other hand, if the flag 351 is not lit when a failure occurs, it means that the failure is the first, so the data cache 35 determines that an intermittent failure has occurred and turns on the flag 351. Then, the type information of the instruction that was being executed when the failure occurred (that is, the memory type command type information) and the information indicating that there is an intermittent failure are sent to the failure part use command detection means 37 (steps S403 and S404). The failure part use instruction detection unit 37 registers that an intermittent failure has occurred in the failure part use instruction DB 12 (step S409), and the divider 35 notifies the instruction end detection unit 36 that the execution of the instruction has been completed. Send (step S405).

  Note that the information that the data cache 35 sends to the faulty part use command detection means 37 when a fixed fault occurs is the same as that of the adder 30, and a detailed description thereof will be omitted.

  Next, the case of the CPU control circuit 34 (step S400 to step S405, step S409, step S410) will be described.

  The CPU control circuit 34 mainly executes instructions for controlling the entire CPU, such as a CPU status flag operation instruction, an operation mode operation instruction, and a CPU performance counter operation instruction. Internally, failure detection circuits such as parity check and duplexing are included.

  When a failure occurs (step S400), the CPU control circuit 34 checks whether the flag 341 has already been lit (step S401). If the flag 341 has already been lit, the CPU control circuit 34 determines that a fixed failure has occurred, and the type information (that is, CPU control system command type information) of the instruction being executed at the time of the failure and the fixed failure. Is sent to the failure part use command detection means 37 (step S402).

  On the other hand, if the flag 341 is not lit, it means that the failure is the first, so the CPU control circuit 34 determines that an intermittent failure has occurred, turns on the flag 341, Information on the type of instruction being executed at the time of occurrence (ie, CPU control type instruction type information) and information indicating an intermittent failure are sent to the failure part use instruction detection means 37 (steps S403 and S404). Then, the failure part use instruction detection unit 37 registers that an intermittent failure has occurred in the failure part use instruction DB 12 (step S409), and the CPU control circuit 34 indicates that the execution of the instruction has been completed. (Step S405).

  Note that the information that the CPU control circuit 34 sends to the failure part use command detection means 37 when a fixed failure occurs is the same as that in the case of the adder 30, and therefore detailed description thereof is omitted.

  Next, the operation from step S406 to step S408 will be described.

  When each execution circuit 30-35 sends an instruction completion instruction execution to the instruction end detection means 36 (step S405), the instruction end detection means 36 performs a process generally called retirement processing (step S406). In the retirement processing, it is determined whether “there is no contradiction in the order of executed instructions” or “it may be terminated as it is”. If the instruction may be completed completely, the instruction end detection unit 36 notifies the instruction scheduling unit 21 of the end of the instruction (steps S407 and S408).

  In the present embodiment, the failure processing is performed in S410. However, the present invention is not limited to this, and can be used as it is.

  Next, the operation of the entire processor will be described in detail with reference to the flowcharts shown in FIGS. 2 to 4 and FIG. FIG. 5 is a diagram showing the inside of the processor shown in FIG. 1 in more detail. In the present embodiment, description will be made assuming that the instruction shown in FIG. 6 is executed. Hereinafter, an example in which a failure occurs in the adder 30 as a result of executing the command of FIG. 6 in which no intermittent failure has occurred in the past will be described.

  The instruction fetch unit 101 fetches the ADD instruction and the MULT instruction shown in FIG. The instruction fetch unit 101 sends the instruction fetched via the path 131 to the instruction decoding unit 102 (step S201).

  The instruction decoding unit 102 refers to the failure part use instruction DB 12 via the path 132 (step S202). In the present embodiment, since no intermittent failure has occurred in the past, the data read from the failure part use instruction DB 12 is empty as shown in FIG. 7 (the valid bit field 7-1 is not lit). Is).

  Therefore, the instruction decoding unit 102 passes the instruction information shown in FIG. 8 to the instruction control unit 11 via the path 143 without stopping the instruction (step S203).

  In the command information, a valid bit field 8-1 indicating a valid bit indicates whether or not the command is valid. When the valid bit is “1”, it indicates that the command is valid. An instruction field 8-2 indicates an instruction type. The command information field 8-3 indicates whether or not the command indicated in the command field has caused an intermittent failure in the past. “1” means that an intermittent failure is caused, and “0” means that an intermittent failure is not caused.

  In the present embodiment, since the past failure history is not stored in the instruction information of FIG. 8 (because all the intermittent failure fields 8-3 are “0”), the instruction control unit 11 stores the fetched instruction. The data is sent as it is to the instruction scheduling means 21 (step S208).

  Since the instruction scheduling unit 21 receives the instruction without receiving an inquiry about the information of the execution circuit from the instruction control unit 11 (step S304), the operation instruction RS22, the memory system instruction RS23, and the control are controlled according to the type of the transmitted instruction The instruction is distributed to any of the system instructions RS24 (step S305). In this embodiment, since both the ADD instruction and the MULT instruction are operation instructions, the instruction scheduling unit 21 sends both instructions to the operation instruction RS22 via the path 250.

  Then, the operation instruction RS22 sends an ADD instruction to the adder 30 and sends a MULT instruction to the multiplier 31 (step S306).

  Next, arithmetic processing is performed in the adder 30.

  When an illegal result is detected by the duplication check or the like (step S400), the adder 30 checks the value of the flag 301 (step S401). The value of the flag 301 is 0 (the flag is not lit), which indicates that “a fault has not occurred in this circuit in the past”. Therefore, the adder 30 determines that this is the first failure (intermittent failure). Then, the adder 30 sends the command type information (added command type information) and information indicating that there is an intermittent failure to the failure part use command detection means 37 and sets the flag 301 to “1” (set the flag 301 to (Step S403, step S404).

  FIG. 9 shows information sent from the adder 30 to the failure part use command detection means 37 in S404. The valid bit field 9-1 indicates the validity of the information, and “1” means that it is valid information. The instruction type field 9-2 indicates the instruction type (in this case, the ADD instruction) that caused the failure. The fixed failure field 9-3 indicates whether or not there is a fixed failure, and is “0” for a fixed failure and “1” for an intermittent failure.

  On the other hand, assuming that no failure has occurred in the MULT instruction executed by the multiplier 31, the multiplier 31 sends the information shown in FIG. 10 to the failure part use instruction detecting means 37 (step S410). In FIG. 10, since the valid bit field 9-1 is “0”, the failure part use command detection means 4 ignores this information.

  After step S404, the failure part use instruction detection unit 37 registers the information shown in FIG. 9 in the failure part use instruction DB 12 via the path 41 (step S409), and also indicates that the instruction has been completed. 36 is notified (step S405). In S409, information indicating that “the intermittent failure has occurred in the past with the ADD command” is registered in the failure part use command detection means DB12 as shown in FIG.

  Thereafter, the instruction end detection unit 36 performs retirement processing (step S406), and if it can be completed, the instruction end detection unit 36 notifies the instruction scheduling unit 21 of the end of the instruction (steps S407 and S408). ).

  In this embodiment, the job is aborted or restarted by checkpoint restart. However, the present invention is not limited to this, and a mechanism such as restart / reexecution by hardware rewinding of the job can be incorporated. It is.

  Next, the operation when the instruction sequence shown in FIG. 12 is executed following the above-described instruction execution of FIG. 6 will be described. FIG. 11 shows command information in the failure part use command DB 12 at the start of operation.

  Of the instructions shown in FIG. 12, since the first two DIV instructions are executed by the divider 32, the past failure in the adder 30 is not affected, but the third instruction ADD instruction is intermittent. An intermittent failure prevention operation for preventing failure is performed.

  First, the instruction fetch means 101 fetches an instruction from the instruction cache 103 via the path 130, and sends the instruction to the instruction decoding means 102 via the path 133 (step S201).

  The instruction decoding unit 102 can decode a maximum of four instructions. The instruction decoding means 102 first decodes the first four instructions in the instruction sequence shown in FIG. As shown in FIG. 11, “information indicating the possibility of failure operation of the ADD instruction” is already registered in the failure part use instruction DB 12 (step S202). Therefore, the instruction decoding means 102 is shown in FIG. Information (information indicating that an intermittent failure has occurred in the ADD instruction) and the decoded instruction are sent to the instruction control unit 11 (step S203). Note that the information in each field in FIG. 13 is the same as the information in each field in FIG.

  Based on the received information (information shown in FIG. 13), the instruction control unit 11 passes the first two instructions (two DIV instructions) in which the intermittent failure field 8-3 of the instruction information is “0” to the path 134. To the instruction scheduling means 21 (step S204, step S208). On the other hand, since the intermittent failure field 8-3 corresponding to the ADD instruction that is the third instruction is “1”, the instruction control unit 11 determines that the instruction is related to a failure that has occurred in the past, and the instruction scheduling means 21 To obtain information on the execution circuit (step S205).

  The instruction control unit 11 determines whether or not the execution circuit to be used is electrically stable (step S206), and outputs an ADD instruction and subsequent instructions (MULT instruction) until it is electrically stable. The instruction control unit 11 is made to wait (step S207).

  In the present embodiment, the state where all the instructions prior to the ADD instruction are finished is regarded as an electrically stable state.

  After becoming electrically stable, the instruction control unit 11 sends an ADD instruction to the instruction scheduling means 21. Since the intermittent failure field 8-3 corresponding to the MULT instruction in the instruction information is “0”, the instruction control unit 11 also sends the MULT instruction to the instruction scheduling means 21 following the ADD instruction (step S208).

In the case of the DIV instruction which is the first two instructions, the instruction scheduling unit 21 receives the DIV instruction without receiving an inquiry about the information of the execution circuit from the instruction control unit 11 (steps S300 and S304). Upon receiving the two DIV instructions, the instruction scheduling means 21 sends them to the operation instruction RS22, and the operation instruction RS22 sends the two DIV instructions to the execution circuit of the non-core unit 3 (step S306).
Then, before receiving the ADD instruction which is the third instruction, the instruction scheduling means 21 receives an inquiry about the information of the execution circuit (step S300). The instruction scheduling unit 21 receives the ADD instruction and the MULT instruction from the instruction control unit 11 in the order of the ADD instruction → the MULT instruction (step S304).

  The instruction schedule means 21 sends the ADD instruction and the MULT instruction to the operation instruction RS22 (step S305). The operation instruction RS22 sends an ADD instruction to the adder 30 and sends a MULT instruction to the multiplier 31 (step S306).

  When the execution process is performed in each execution circuit (divider 32, adder 30, multiplier 31) without any failure, each execution circuit receives instruction type information (two division instruction types, addition instruction type, (Multiplication instruction type) and information indicating that no failure has occurred are sent to the failure part use instruction detection means 37 (steps S400 and S410).

  Then, each execution circuit notifies the instruction end detection means 36 that the instruction has ended (step S405). Thereafter, the instruction end detection means 36 performs retirement processing (step S406). If the process can be terminated, the command end detection unit 36 notifies the command scheduling unit 21 of the end of the command (steps S407 and S408).

  As described above, in this embodiment, an instruction that may cause an intermittent failure (ADD instruction in the case of this embodiment) is executed when all the preceding instructions are finished and are in an electrically stable state. . As a result, the risk of intermittent failure can be greatly reduced, and stable operation can be realized.

  In addition, a circuit having a history regarding an instruction that has caused an intermittent failure, that is, a storage unit (failure part use instruction DB 12) that stores information on an instruction type that has caused a failure in the past, the instruction control unit 11 includes: Based on the instruction type information, it is determined whether or not an instruction having a high possibility of failure has been decoded. As a result, it is possible to identify an instruction that causes the same intermittent failure that will occur in the future, reduce its risk, and achieve stable operation.

  FIG. 14 is a block diagram showing a second embodiment of the present invention.

  The information processing apparatus 50 according to the second embodiment includes an instruction fetch unit 51 that fetches an instruction, an instruction decode unit 52 that decodes a fetched instruction, a plurality of execution circuits 53-1 to 53-4, and instruction control. Circuit 54. Although FIG. 14 shows four execution circuits as a plurality of execution circuits, the present invention is not limited to this.

  Each execution circuit 53 executes the instruction decoded by the instruction decoding means 52. The instruction control circuit 54 is connected to the instruction decoding means 52 and the plurality of execution circuits 53.

  When an instruction having a high possibility of failure is decoded by the instruction decoding means 52, the instruction control circuit 54 checks whether or not the execution circuit 53 that executes the decoded instruction is electrically stable. If the instruction is stable, the instruction is executed by the execution circuit.

  Here, the case of being electrically stable is, for example, a case where execution of all preceding instructions for an instruction with a high possibility of occurrence of a failure is not limited to this.

  In the second embodiment of the present invention, an instruction that may cause an intermittent failure is executed in an electrically stable state. As a result, the risk of intermittent failure can be greatly reduced, and stable operation can be realized.

  The embodiment of the present invention may be a processor processing method described in the following supplementary notes.

  (Supplementary Note 1) When an instruction fetch step for fetching an instruction, an instruction decode step for decoding the fetched instruction, and an instruction having a high possibility of occurrence of a failure, is the execution circuit electrically stable? A first determination step for determining whether or not, an instruction execution step for causing the execution circuit to execute the instruction when electrically stable, a flag lighting step for lighting a flag when a failure occurs, and the flag When a failure occurs in a state where the light is not lit, a third determination step for determining that an intermittent failure has occurred, and when it is determined that an intermittent failure has occurred in the third determination step, the intermittent failure occurs. And a registering step of registering the information of the instruction type that has been made in the storage means.

  (Supplementary note 2) The processor processing method according to supplementary note 1, further comprising a fourth determination step of determining that a fixed failure has occurred when a failure occurs when the flag is turned on.

(Supplementary note 3) When an instruction scheduling means manages an instruction execution state in each execution circuit and an instruction having a high possibility of occurrence of a failure is decoded, whether or not the execution circuit is electrically stable An inquiry step for querying the instruction scheduling means,
The processing method of the processor according to appendix 1 or 2, characterized by comprising:

  (Supplementary Note 4) Whether or not an execution circuit is electrically stable when an instruction fetch step for fetching an instruction, an instruction decode step for decoding the fetched instruction, and an instruction with a high possibility of occurrence of a failure are decoded A first determination step for determining whether or not the instruction execution step for causing the execution circuit to execute the instruction when it is electrically stable, and management for managing instruction execution states in the execution circuits by the instruction scheduling means And an inquiry step for inquiring of the instruction scheduling means whether or not the execution circuit is electrically stable when an instruction having a high possibility of occurrence of a failure is decoded. .

DESCRIPTION OF SYMBOLS 1 Fetch code part 10 Processor 101 Instruction fetch means 102 Instruction decode means 103 Instruction cache 11 Instruction control part 12 Fault location use instruction DB
2 Processor Unit 21 Instruction Scheduling Means 22 Arithmetic Instruction RS
23 Memory system instruction RS
24 Control system command RS
3 Non-core part 30 Adder 301 Flag 31 Multiplier 311 Flag 32 Divider 321 Flag 33 Address calculation means 331 Flag 332 Path 34 CPU control circuit 341 Flag 35 Data cache 351 Flag 36 Instruction end use instruction detection means 37 371-383 path 130-134 path 211 path 250-257 path 142 data processor 143 data bus 144 data buffer register 145 instruction register 146 instruction decoder 147 subtractor 148 accumulator 149 control circuit 1411 program counter 1412 general-purpose register circuit 1413 arithmetic circuit 51 instruction Fetch means 52 Instruction decode means 53-1 to 53-4 Execution circuit 54 Instruction control circuit

Claims (10)

Instruction fetch means for fetching instructions;
Instruction decoding means for decoding the fetched instruction;
A plurality of execution circuits for executing the decoded instructions;
When an instruction having a high possibility of occurrence of a failure is decoded, it is confirmed whether or not the execution circuit is electrically stable. If the instruction is electrically stable, the instruction is executed by the execution circuit. Control means;
An information processing apparatus comprising: The information processing apparatus according to claim 1, wherein the instruction control unit determines that the instruction is electrically stable when execution of all preceding instructions for an instruction having a high possibility of occurrence of a failure is completed. Comprising storage means for storing information on the instruction type that caused the failure in the past,
3. The information processing apparatus according to claim 1, wherein the instruction control unit determines whether or not an instruction having a high possibility of a failure has been decoded based on the instruction type information. Each execution circuit has a flag,
4. Each of the execution circuits turns on the flag when a failure occurs, and determines that an intermittent failure has occurred when a failure occurs when the flag is not lit. The information processing apparatus according to any one of the above. 5. The information according to claim 4, further comprising means for registering, in the storage means, information on an instruction type that caused the intermittent failure when it is determined that the intermittent failure has occurred in each of the execution circuits. Processing equipment. 6. The information processing apparatus according to claim 4, wherein, when a failure occurs when the flag is lit, each execution circuit determines that a fixed failure has occurred. Scheduling means for managing an instruction execution state in each execution circuit;
7. The instruction control unit according to claim 1, wherein when an instruction having a high possibility of occurrence of a failure is decoded, the instruction control unit inquires of the scheduling unit whether or not the execution circuit is electrically stable. The information processing apparatus according to any one of the above. An instruction fetch step for fetching instructions;
An instruction decoding step for decoding the fetched instruction;
A first determination step of determining whether or not the execution circuit is electrically stable when an instruction having a high possibility of occurrence of a failure is decoded;
An instruction execution step for causing the execution circuit to execute the instruction when it is electrically stable;
A processor processing method characterized by comprising: 9. The processor according to claim 8, wherein in the first determination step, it is determined that the operation is electrically stable when execution of all preceding instructions with respect to an instruction having a high possibility of occurrence of failure is completed. Processing method. A storage step of storing in the storage means information on the instruction type that caused the failure in the past;
A second determination step of determining whether or not an instruction having a high possibility of occurrence of a failure has been decoded based on the information of the instruction type;
10. The processing method of a processor according to claim 8 or 9, characterized by comprising:

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