JP2011127168A - Plasma cvd device - Google Patents

Plasma cvd device Download PDF

Info

Publication number
JP2011127168A
JP2011127168A JP2009285599A JP2009285599A JP2011127168A JP 2011127168 A JP2011127168 A JP 2011127168A JP 2009285599 A JP2009285599 A JP 2009285599A JP 2009285599 A JP2009285599 A JP 2009285599A JP 2011127168 A JP2011127168 A JP 2011127168A
Authority
JP
Japan
Prior art keywords
film
thin film
forming
substrate
insulating
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2009285599A
Other languages
Japanese (ja)
Inventor
Nozomi Ikuji
望 生地
Tatsuhiro Taguchi
竜大 田口
Takeshi Mishina
健 三科
Atsufumi Ogishi
厚文 大岸
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shimadzu Corp
Original Assignee
Shimadzu Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shimadzu Corp filed Critical Shimadzu Corp
Priority to JP2009285599A priority Critical patent/JP2011127168A/en
Publication of JP2011127168A publication Critical patent/JP2011127168A/en
Pending legal-status Critical Current

Links

Images

Landscapes

  • Chemical Vapour Deposition (AREA)
  • Formation Of Insulating Films (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To eliminate inconvenience due to deposition of insulation film, in particular, uneven film thickness and the generation of abnormal discharge, with a simple constitution. <P>SOLUTION: A plasma CVD device 1 includes parallel flat plate electrodes 5 in a vacuum chamber 3 connected with a gas supply mechanism 7 and a gas discharge mechanism 9, wherein the parallel flat plate electrodes 5 is constituted of a high-frequency electrode 5A connected with an alternate power source PS via a matching box MB and a grounded counter electrode 5B via a matching box MB. Such maintenance that insulation material 11 deposited on the surfaces of the parallel flat plate electrodes 5 is covered with a conductive film 15 and is made conductive is performed. The maintenance is performed by depositing the conductive film, for example, amorphous silicon (a-Si) film or SiN film having a refractive index of at least 2.3 while there is no substrate on a substrate holder (the counter electrode) 5B. Thereafter, deposition treatment of the substrate is performed and, thereby, the insulation film having an even thickness can be provided. <P>COPYRIGHT: (C)2011,JPO&amp;INPIT

Description

本発明は、プラズマCVD成膜方法およびプラズマCVD装置に関する。特に本発明は、プラズマCVD成膜方法における、異常放電を抑制する方法および膜厚均一化方法に関する。   The present invention relates to a plasma CVD film forming method and a plasma CVD apparatus. In particular, the present invention relates to a method for suppressing abnormal discharge and a method for uniformizing film thickness in a plasma CVD film forming method.

一般的な容量結合型のプラズマCVD装置は、真空チャンバと、放電のための平行平板電極と、放電用ガス供給機構と、ガス排気機構と、数十kHz〜数十MHzの交流電源と、マッチングボックスとより構成される(例えば、特許文献1参照)。   A general capacitively coupled plasma CVD apparatus is matched with a vacuum chamber, parallel plate electrodes for discharge, a discharge gas supply mechanism, a gas exhaust mechanism, and an AC power source of several tens to several tens of MHz. It is comprised with a box (for example, refer patent document 1).

プラズマ放電負荷を発生させるための平行平板電極と交流電源との間に挿入されたマッチングボックス(特許文献1の図2,段落[0002]参照)は、交流電源側の出力インピーダンスと、マッチングボックスの入力インピーダンスが複素共役の関係を維持するよう、可変インダクタおよび可変キャパシタを有している。マッチングボックスは、ガス流量・圧力・チャンバ3の汚れ等に起因して動的に変動するプラズマ放電負荷に対応して、可変キャパシタおよび可変インダクタを調整することによりインピーダンスマッチングを行う。そのことにより、平行平板電極5のプラズマ放電電極側からの反射電力をなくして一定の電力をプラズマ放電負荷に供給し、それによって、安定したプラズマ放電を可能としている。   The matching box (see FIG. 2, paragraph [0002] of Patent Document 1) inserted between the parallel plate electrode for generating the plasma discharge load and the AC power source is the output impedance of the AC power source side and the matching box. A variable inductor and a variable capacitor are provided so that the input impedance maintains a complex conjugate relationship. The matching box performs impedance matching by adjusting a variable capacitor and a variable inductor in response to a plasma discharge load that dynamically varies due to gas flow rate, pressure, contamination of the chamber 3, and the like. As a result, the reflected power from the plasma discharge electrode side of the parallel plate electrode 5 is eliminated and a constant power is supplied to the plasma discharge load, thereby enabling stable plasma discharge.

対向電極は基板ホルダを兼ねており、この基板ホルダ上に基板を載置し、ガス供給機構から反応ガスを供給し、ガス排気機構により真空チャンバ内の圧力を所定圧に保ち、平行平板電極に交流電源から交流電力を供給してプラズマ放電を起こし、反応ガスに生成したプラズマを作用させ、反応性生物を基板表面に絶縁膜を成膜する。   The counter electrode also serves as a substrate holder. The substrate is placed on the substrate holder, the reaction gas is supplied from the gas supply mechanism, and the pressure in the vacuum chamber is maintained at a predetermined pressure by the gas exhaust mechanism. An AC power is supplied from an AC power source to cause plasma discharge, causing plasma generated in the reaction gas to act, and forming an insulating film on the substrate surface with reactive organisms.

特開2007−227816号公報JP 2007-227816 A

しかしながら、従来から知られている容量結合型のプラズマCVD装置では、成膜処理の時間・回数が経過するのに伴ってプラズマ放電電極上および対向電極(少なくともその露出面、すなわち基板が載置されない表面部分)上に絶縁物が逐次堆積していく。その結果、薄膜の膜厚が不均一になったり、異常放電を起したりするおそれがある。   However, in a conventionally known capacitively coupled plasma CVD apparatus, as the time and the number of film forming processes elapse, the plasma discharge electrode and the counter electrode (at least the exposed surface, that is, the substrate is not placed). Insulators are successively deposited on the surface portion. As a result, the film thickness of the thin film may become non-uniform or abnormal discharge may occur.

発明者等は上述した現象を鋭意研究し、以下のような所見を得た。
電極表面の絶縁物の堆積量は、ガス密度や電極形状の影響を受けて電極の場所によって異なり、堆積量が多い点は高インピーダンスとなり、堆積量が少ない点は低インピーダンスとなる。そのため、低インピーダンス領域は電流が流れやすくなり、高インピーダンス領域に比べてプラズマ密度が高くなり、成膜レートが高くなる。その結果、成膜レートが平行平板電極の場所によって異なる。
The inventors diligently studied the phenomenon described above and obtained the following findings.
The amount of the insulator deposited on the electrode surface is affected by the gas density and the electrode shape, and varies depending on the location of the electrode. Therefore, current flows easily in the low impedance region, and the plasma density is higher than that in the high impedance region, and the deposition rate is increased. As a result, the film formation rate varies depending on the location of the parallel plate electrodes.

図10は絶縁物の堆積による成膜レートの分布の悪化を説明する概念図であり、マッチングボックス、交流電源、ガス供給機構およびガス排気機構は省略し、反応室内の対向電極上に基板が存在しない状態での平行平板電極の表面に堆積した絶縁物の状態を示す。   FIG. 10 is a conceptual diagram for explaining the deterioration of the film formation rate distribution due to the deposition of an insulator. The matching box, AC power supply, gas supply mechanism, and gas exhaust mechanism are omitted, and the substrate exists on the counter electrode in the reaction chamber. The state of the insulator deposited on the surface of the parallel plate electrode in a non-operating state is shown.

図10に示すように、平行平板電極105の両端側から中央部に向かって堆積絶縁物111の厚さが徐々に増加しており、これにともなってプラズマ密度Dが中央部で低く、両端部に向かって高くなっている。このため中央部では成膜レートが低くなり、一方両端部では成膜レートが高くなり、均一な成膜レートが得られない。その結果、製品の薄膜の膜厚が不均一になってしまう。   As shown in FIG. 10, the thickness of the deposited insulator 111 gradually increases from both ends of the parallel plate electrode 105 toward the center, and accordingly, the plasma density D is low at the center and both ends. It is getting higher towards. For this reason, the film formation rate is low at the center, while the film formation rate is high at both ends, and a uniform film formation rate cannot be obtained. As a result, the film thickness of the product thin film becomes non-uniform.

また、例えばプラズマCVDを利用して半導体素子のパッシベーション膜を形成する成膜装置、特に結晶系シリコンの太陽電池の反射防止膜を形成する装置の場合などのように、反応チャンバにおいて一度に多数の基板を基板ホルダ上に配置して絶縁膜の成膜を繰り返すと、基板ホルダの基板で覆われない部分には絶縁物が堆積して行く。   In addition, for example, in the case of a film forming apparatus that forms a passivation film of a semiconductor element using plasma CVD, particularly an apparatus that forms an antireflection film of a crystalline silicon solar cell, a large number of the reaction chamber is used at a time. When the substrate is placed on the substrate holder and the formation of the insulating film is repeated, an insulator is deposited on the portion of the substrate holder that is not covered with the substrate.

図11はこの状態を模式的に示す。図11に示すように、基板ホルダ105B上に配置された複数の基板S同士の間に、すなわち基板Sに覆われない基板ホルダ表面には、成膜を繰り返すと絶縁物111が堆積し、凹凸のある基板ホルダ表面となる。   FIG. 11 schematically shows this state. As shown in FIG. 11, the insulator 111 is deposited between the plurality of substrates S arranged on the substrate holder 105B, that is, on the surface of the substrate holder that is not covered with the substrate S, when the film formation is repeated. It becomes the substrate holder surface with.

また、過剰な電流が流れた場合に局所的な高密度放電を引き起こす。図12は異常放電ADを説明する概念図であり、マッチングボックス、交流電源、ガス供給機構およびガス排気機構は省略し、反応室内の対向電極上に基板が存在しない状態での平行平板電極の表面に堆積した絶縁物の状態を示す。   In addition, when an excessive current flows, local high-density discharge is caused. FIG. 12 is a conceptual diagram for explaining abnormal discharge AD, where the matching box, AC power supply, gas supply mechanism, and gas exhaust mechanism are omitted, and the surface of the parallel plate electrode in the state where the substrate does not exist on the counter electrode in the reaction chamber. Shows the state of the deposited insulator.

図12に示すように、平行平板電極105に絶縁物が一様に堆積した場合に、電極端部の電界の強い部分である高周波電極105Aの端部105Cとアースシールド113との間で局所的なアーク放電を引き起こすことがある。また、絶縁物111はキャパシタとなり絶縁物の表面には電荷が貯まるため、貯まった電荷が放電によって一気に放出された場合に、局所的なアーク放電を引き起こす。このような局所的な高密度放電やアーク放電のような異常放電ADは、図示しない基板(に形成する薄膜の膜厚分布を著しく劣化させる。特に絶縁物のコーナー部111Aにおいてこの現象は著しい。また、異常放電ADは高周波電極105Aやアースシールド113に付着した絶縁膜を剥離させ、パーティクルの発生源となる。   As shown in FIG. 12, when an insulator is uniformly deposited on the parallel plate electrode 105, it is locally between the end portion 105 </ b> C of the high-frequency electrode 105 </ b> A that is a strong electric field portion of the electrode end portion and the earth shield 113. May cause serious arc discharge. Further, since the insulator 111 becomes a capacitor and charges are stored on the surface of the insulator, when the stored charges are released at once by discharge, a local arc discharge is caused. Such abnormal discharge AD such as local high-density discharge or arc discharge significantly deteriorates the film thickness distribution of the thin film formed on the substrate (not shown). This phenomenon is particularly remarkable in the corner portion 111A of the insulator. In addition, the abnormal discharge AD peels off the insulating film attached to the high-frequency electrode 105A and the earth shield 113, and becomes a particle generation source.

以上の所見に基づいて本発明者等は、以下の請求項1〜9の発明を創案した。
(1)請求項1の発明は、電極を用いた容量結合型プラズマCVDによって基板の表面に薄膜を形成するプラズマCVD成膜方法において、前記基板の表面へ薄膜を形成する薄膜形成工程と、前記薄膜形成工程で前記基板の表面に薄膜を形成した後、前記基板が無い状態で前記薄膜と比較して導電性の高い薄膜を前記電極の表面に生成する導電性薄膜形成工程とを有することを特徴とする。
(2)請求項2の発明は、電極を用いた容量結合型プラズマCVDによって基板の表面に薄膜を形成するプラズマCVD装置において、前記基板の表面へ薄膜を形成する薄膜形成手段と、前記薄膜形成手段による一定量の薄膜を前記基板の表面に形成した後、前記基板が無い状態で前記薄膜と比較して導電性の高い薄膜を前記電極の表面に生成する導電性薄膜生成手段とを備えたことを特徴とする。
(3)請求項3の発明は、平行平板電極にて放電を行い、基板の表面に窒化シリコン薄膜を成膜するプラズマCVD成膜方法において、前記基板の表面へ屈折率2.3未満の窒化シリコン薄膜を形成する薄膜形成工程と、前記基板の表面へ一定量の窒化シリコン薄膜を形成した後に、基板が無い状態で、アモルファスシリコン(以下、a−Si)または屈折率2.3以上の窒化シリコン膜を前記平行平板電極の表面に生成する窒化シリコン薄膜形成工程とを有することを特徴とする。
(4)請求項4の発明は、平行平板電極にて放電を行い、基板の表面に窒化シリコン薄膜を成膜するプラズマCVD装置において、前記基板表面へ屈折率2.3未満の窒化シリコン薄膜を形成する薄膜形成手段と、前記基板表面へ一定量の窒化シリコン薄膜を形成した後に、前記基板が無い状態で、アモルファスシリコン(a−Si)または屈折率2.3以上の窒化シリコン膜を前記平行平板電極の表面に生成する窒化シリコン薄膜形成手段とを備えたことを特徴とする。
(5)請求項5の発明は、平行平板電極にて放電を行い、基板に絶縁性薄膜を成膜するプラズマCVD装置を用いる絶縁性薄膜の成膜方法であって、前記基板に絶縁膜を成膜する絶縁膜成膜工程と、前記平行平板電極の表面のメンテナンスが必要であるか否かを判断する判断工程と、前記判断工程において前記メンテナンスが必要であると判断された場合に、前記基板が無い状態で前記平行平板電極の表面に導電膜を成膜する導電膜成膜工程とを備えることを特徴とする。
(6)請求項6の発明は、請求項5に記載の絶縁性薄膜成膜方法において、さらに、異常放電の発生を検出する異常放電発生検出工程を備え、前記判断工程における前記メンテナンスが必要であるか否かの判断を、前記異常放電の発生の有無に基づいて行うことを特徴とする。
(7)請求項7の発明は、請求項5に記載の絶縁性薄膜成膜方法において、さらに、あらかじめ連続して行われる成膜処理の回数を設定する限界成膜回数設定工程を備え、前記判断工程における前記メンテナンスが必要であるか否かの判断を、前記限界成膜回数設定工程において設定された限界成膜回数の到達により行うことを特徴とする。
(8)請求項8の発明は、請求項5に記載の絶縁性薄膜成膜方法において、さらに、絶縁膜の膜厚検査工程を備え、前記判断工程における前記メンテナンスが必要であるか否かの判断を、前記膜厚検査工程において設定された膜厚の到達により行うことを特徴とする。
(9)請求項9の発明は、請求項6に記載の絶縁性薄膜成膜方法において、前記絶縁膜成膜工程と、前記異常放電発生検出工程と、前記導電膜成膜工程とを繰り返すことを特徴とする。
(10)請求項10の発明は、請求項5〜9のいずれか一項に記載の絶縁性薄膜成膜方法において、前記絶縁性薄膜は屈折率2.3未満のSiN膜であり、前記導電膜はa−Si膜または屈折率2.3以上のSiN膜であることを特徴とする。
Based on the above findings, the present inventors have created the inventions of the following claims 1 to 9.
(1) The invention of claim 1 is a plasma CVD film forming method for forming a thin film on the surface of a substrate by capacitively coupled plasma CVD using an electrode, and a thin film forming step for forming a thin film on the surface of the substrate; After forming a thin film on the surface of the substrate in the thin film forming step, the method includes a conductive thin film forming step for generating a thin film on the surface of the electrode having a higher conductivity than the thin film without the substrate. Features.
(2) The invention of claim 2 is a plasma CVD apparatus for forming a thin film on the surface of the substrate by capacitively coupled plasma CVD using electrodes, and a thin film forming means for forming a thin film on the surface of the substrate, and the thin film formation And a conductive thin film generating means for generating a thin film having higher conductivity on the surface of the electrode in the absence of the substrate after forming a certain amount of thin film on the surface of the electrode. It is characterized by that.
(3) The invention of claim 3 is a plasma CVD film forming method in which discharge is performed with parallel plate electrodes and a silicon nitride thin film is formed on the surface of the substrate. A thin film forming step for forming a silicon thin film, and after forming a certain amount of silicon nitride thin film on the surface of the substrate, amorphous silicon (hereinafter a-Si) or nitriding with a refractive index of 2.3 or more without a substrate And a silicon nitride thin film forming step for forming a silicon film on the surface of the parallel plate electrode.
(4) The invention of claim 4 is a plasma CVD apparatus in which a silicon nitride thin film is formed on the surface of a substrate by discharging with parallel plate electrodes. After forming a certain amount of silicon nitride thin film on the substrate surface after forming a thin film forming means to be formed, amorphous silicon (a-Si) or a silicon nitride film having a refractive index of 2.3 or more is formed in parallel without the substrate. And a silicon nitride thin film forming means formed on the surface of the plate electrode.
(5) The invention of claim 5 is a method for forming an insulating thin film using a plasma CVD apparatus in which discharge is performed with parallel plate electrodes to form an insulating thin film on a substrate, and the insulating film is provided on the substrate. An insulating film forming step for forming a film, a determining step for determining whether or not maintenance of the surface of the parallel plate electrode is necessary, and when it is determined that the maintenance is required in the determining step, And a conductive film forming step of forming a conductive film on the surface of the parallel plate electrode without a substrate.
(6) The invention of claim 6 is the method for forming an insulating thin film according to claim 5, further comprising an abnormal discharge occurrence detecting step for detecting the occurrence of abnormal discharge, and the maintenance in the determining step is required. The determination of whether or not there is is performed based on the presence or absence of occurrence of the abnormal discharge.
(7) The invention according to claim 7 is the method for forming an insulating thin film according to claim 5, further comprising a limit film formation number setting step for setting the number of film formation processes performed continuously in advance, Whether or not the maintenance is necessary in the determination step is determined by reaching the limit number of film formations set in the limit film formation number setting step.
(8) The invention according to claim 8 is the method for forming an insulating thin film according to claim 5, further comprising a step of inspecting the thickness of the insulating film, and whether or not the maintenance in the determination step is necessary. The determination is made by reaching the film thickness set in the film thickness inspection step.
(9) The invention of claim 9 is the method for forming an insulating thin film according to claim 6, wherein the insulating film forming step, the abnormal discharge occurrence detecting step, and the conductive film forming step are repeated. It is characterized by.
(10) The invention of claim 10 is the method of forming an insulating thin film according to any one of claims 5 to 9, wherein the insulating thin film is a SiN film having a refractive index of less than 2.3, and the conductive The film is an a-Si film or a SiN film having a refractive index of 2.3 or more.

本発明によれば、プラズマCVD装置に追加の部品または装置を設けることなく、電極に付着した絶縁膜の悪影響を抑制することができる。   According to the present invention, it is possible to suppress the adverse effect of the insulating film attached to the electrode without providing an additional component or apparatus in the plasma CVD apparatus.

本発明のプラズマCVD装置の概略構成図である。It is a schematic block diagram of the plasma CVD apparatus of this invention. 本発明の一実施の形態による導電膜成膜処理を説明するフローチャートである。It is a flowchart explaining the electrically conductive film film-forming process by one embodiment of this invention. 本発明の他の実施の形態による導電膜成膜処理を説明するフローチャートである。It is a flowchart explaining the electrically conductive film film-forming process by other embodiment of this invention. 本発明のメンテナンス工程を説明する工程図である。It is process drawing explaining the maintenance process of this invention. 本発明の一実施の形態によるプラズマCVD装置の概念図である。1 is a conceptual diagram of a plasma CVD apparatus according to an embodiment of the present invention. 本発明の一実施の形態によるプラズマCVD装置の概念図である。1 is a conceptual diagram of a plasma CVD apparatus according to an embodiment of the present invention. 絶縁膜の成膜工程を示す工程図である。It is process drawing which shows the film-forming process of an insulating film. 本発明の絶縁膜成膜方法により得られた絶縁膜の膜厚分布を示すグラフである。It is a graph which shows the film thickness distribution of the insulating film obtained by the insulating film forming method of this invention. 本発明の絶縁膜成膜方法により得られた絶縁膜のVdcの変化を示すグラフである。It is a graph which shows the change of Vdc of the insulating film obtained by the insulating film forming method of this invention. 従来装置における絶縁物の堆積による成膜レートの分布の悪化を説明する概念図である。It is a conceptual diagram explaining the deterioration of the film-forming rate distribution by the deposit of the insulator in a conventional apparatus. 従来装置における平行平板電極上の絶縁物の堆積状況を説明する概念図である。It is a conceptual diagram explaining the deposition condition of the insulator on the parallel plate electrode in a conventional apparatus. 従来装置における平行平板電極上に堆積した絶縁物による異常放電の発生の様子を説明する概念図である。It is a conceptual diagram explaining the mode of generation | occurrence | production of the abnormal discharge by the insulator deposited on the parallel plate electrode in a conventional apparatus.

以下、図面を参照して本発明の実施の形態によるプラズマCVD装置を説明する。以下の図面の記載において、図面は模式的なものであり、必ずしも現実のものを忠実に表現するものではなく、各部品、要素等の相対的位置関係は、説明の便宜上のものである。また、図面相互間においても互いの寸法の関係や比率が必ずしも同じではない。   A plasma CVD apparatus according to an embodiment of the present invention will be described below with reference to the drawings. In the following description of the drawings, the drawings are schematic and do not necessarily faithfully represent the actual ones, and the relative positional relationship of each component, element, etc. is for convenience of explanation. Also, the dimensional relationships and ratios are not necessarily the same between the drawings.

図1は本発明の一実施の形態にかかるプラズマCVD装置を示す概念図である。図に示すように、プラズマCVD装置1は、真空チャンバ3内に平行平板電極5を備える。この平行平板電極5は、マッチングボックスMBを介して交流電源PSに接続された高周波電極5Aと、接地された対向電極(基板ホルダとも呼ぶ)5Bから構成される。高周波電極5Aと対向電極5Bの電極間距離は場所によらず一定の距離に保たれる。真空チャンバ3にはガス供給機構7とガス排気機構9とが接続されている。プラズマCVD装置1は、また、制御装置10、検出器12、スイッチ14を備える。制御装置は、プログラムを展開・実行し、あるいは各種演算を行うCPU16と、成膜シーケンスおよび後述する本発明のメンテナンスのシーケンスを実行するプログラムを格納したROM18を備えている。   FIG. 1 is a conceptual diagram showing a plasma CVD apparatus according to an embodiment of the present invention. As shown in the figure, the plasma CVD apparatus 1 includes a parallel plate electrode 5 in a vacuum chamber 3. The parallel plate electrode 5 includes a high-frequency electrode 5A connected to an AC power source PS through a matching box MB and a grounded counter electrode (also referred to as a substrate holder) 5B. The distance between the high-frequency electrode 5A and the counter electrode 5B is kept constant regardless of the location. A gas supply mechanism 7 and a gas exhaust mechanism 9 are connected to the vacuum chamber 3. The plasma CVD apparatus 1 also includes a control device 10, a detector 12, and a switch 14. The control device includes a CPU 16 that develops and executes a program or performs various calculations, and a ROM 18 that stores a program for executing a film forming sequence and a maintenance sequence of the present invention described later.

ガス供給機構7には流量調節計(図示しない)が設けられ、成膜中のガス供給量を一定に保ち、一方、ガス排気機構9にはガス調圧弁(図示しない)が備えられ、制御装置10の制御により真空チャンバ3内の圧力を一定且つ一様に保つ。これにより、真空チャンバ3内のガス分布が一様に保たれる。電極間距離、ガス分布が場所によらずに一様に保たれることによって、プラズマ放電負荷が一様となり、局所的に過剰な電流が流れることなく、安定した正規グロー放電を可能にしている。   The gas supply mechanism 7 is provided with a flow rate controller (not shown) to keep the gas supply amount constant during film formation, while the gas exhaust mechanism 9 is provided with a gas pressure regulating valve (not shown). The pressure in the vacuum chamber 3 is kept constant and uniform by the control of 10. Thereby, the gas distribution in the vacuum chamber 3 is kept uniform. The distance between the electrodes and the gas distribution are kept constant regardless of the location, the plasma discharge load becomes uniform, and stable normal glow discharge is possible without excessive local current flowing. .

プラズマ放電負荷を発生させるための平行平板電極5と交流電源PSとの間に挿入されたマッチングボックスMBは、ガス流量・圧力・チャンバ3の汚れ等に起因して動的に変動するプラズマ放電負荷に対応して、可変キャパシタおよび可変インダクタを調整することによりインピーダンスマッチングを行う。そのことにより、平行平板電極5のプラズマ放電電極5A側からの反射電力をなくして一定の電力をプラズマ放電負荷に供給し、それによって、安定したプラズマ放電を可能としている。   The matching box MB inserted between the parallel plate electrode 5 for generating the plasma discharge load and the AC power supply PS is a plasma discharge load that dynamically varies due to gas flow rate, pressure, contamination of the chamber 3, and the like. Corresponding to the above, impedance matching is performed by adjusting the variable capacitor and the variable inductor. As a result, the reflected power from the plasma discharge electrode 5A side of the parallel plate electrode 5 is eliminated, and constant power is supplied to the plasma discharge load, thereby enabling stable plasma discharge.

本発明の一実施の形態によれば、図1に示すプラズマCVD装置1を用いて、下記のシーケンスに従って成膜を行う。図2は、本発明の一実施の形態による絶縁性薄膜成膜方法を説明するフローチャートである。   According to one embodiment of the present invention, film formation is performed using the plasma CVD apparatus 1 shown in FIG. 1 according to the following sequence. FIG. 2 is a flowchart for explaining an insulating thin film forming method according to an embodiment of the present invention.

図2に示すように、成膜プロセスは装置起動(ステップS1)後、ガス供給機構7およびガス排気機構9の給排気の調節(流速、圧力等)、図示しないヒーターによる温度調節などを行い、成膜環境を整える(ステップS2)。次いで、基板Sを基板ホルダ上に載置し、交流電源PSによりプラズマ放電負荷を高周波電極5Aにかけて、プラズマを発生させ、ガス供給機構7から導入された反応ガスにプラズマを作用させて材料ガスを反応させ、反応生成物(絶縁物)を基板Sの表面に堆積させ、絶縁膜が成膜された基板を真空チャンバ3から取り出して絶縁性薄膜を成膜する(ステップS3)。成膜を一回行うごとに成膜回数カウンタを1だけインクリメントする(C=C+1)(ステップS4)。次いで、この絶縁膜成膜工程における成膜回数Cが所定の限界成膜回数Rcに達したかを判断する(ステップS5)。すなわち、ステップS5において、メンテナンスが必要か否かを判断する。   As shown in FIG. 2, in the film formation process, after the apparatus is started (step S1), the supply / exhaust of the gas supply mechanism 7 and the gas exhaust mechanism 9 (flow rate, pressure, etc.), temperature adjustment with a heater (not shown), etc. are performed. A film forming environment is prepared (step S2). Next, the substrate S is placed on the substrate holder, a plasma discharge load is applied to the high-frequency electrode 5A by the AC power source PS, plasma is generated, and the plasma is caused to act on the reaction gas introduced from the gas supply mechanism 7, thereby supplying the material gas. Reaction is performed to deposit a reaction product (insulator) on the surface of the substrate S, and the substrate on which the insulating film is formed is taken out of the vacuum chamber 3 to form an insulating thin film (step S3). Each time a film is formed, the film formation counter is incremented by 1 (C = C + 1) (step S4). Next, it is determined whether the number of film formations C in this insulating film formation process has reached a predetermined limit number of film formations Rc (step S5). That is, in step S5, it is determined whether maintenance is necessary.

この判断は次のようにして行われる。成膜工程を繰り返した場合にそれ以後の成膜された製品の薄膜の膜厚分布が初めて許容範囲を超えて不均一になる回数を求め、安全を見込んでそれ以下の適切な値に設定された限界成膜回数値をあらかじめ設定しておき、成膜工程が行われた回数の値(C)をこの所定の限界成膜回数値(Rc)と比較する。   This determination is made as follows. When the film forming process is repeated, the number of times the film thickness distribution of the film after that is formed exceeds the permissible range for the first time and is non-uniform, and the value is set to an appropriate value below that for safety reasons. The limit number of times of film formation is set in advance, and the value (C) of the number of times the film formation process has been performed is compared with the predetermined limit number of film formation value (Rc).

C<Rcのときは、平行平板電極のメンテナンスが不要であると判断され(ステップS5,NO)、C=Rcのときは、平行平板電極のメンテナンスが必要である(ステップS5、YES)と判断され、ステップS7に進み、生産(成膜)が中止され、ついでステップS8において導電膜の成膜(メンテナンス)が行われる。   When C <Rc, it is determined that maintenance of the parallel plate electrode is not required (step S5, NO), and when C = Rc, it is determined that maintenance of the parallel plate electrode is required (step S5, YES). In step S7, the production (film formation) is stopped, and in step S8, the conductive film is formed (maintenance).

ステップS5において、C<Rcのときは、ステップS6に進み、異常放電の発生の有無を判断する。異常放電の発生は、図1の検出器(公知の放電検出器)14によりアーク放電の有無その他の指標を検知することによって行われる。異常放電の発生が検知されなかったとき(ステップS6,NO)は、ステップS3に戻り、絶縁膜の成膜(生産)を続行する。一方、異常放電の発生が検知されたときは(ステップS6,YES)、ステップS7に進み、絶縁膜の成膜(生産)を中止し、さらにステップS8に進み、平行平板電極5の電極面のメンテナンスを行う。   In step S5, when C <Rc, the process proceeds to step S6 to determine whether or not abnormal discharge has occurred. The occurrence of abnormal discharge is performed by detecting the presence or absence of arc discharge and other indicators by the detector (known discharge detector) 14 of FIG. When the occurrence of abnormal discharge is not detected (step S6, NO), the process returns to step S3 and the film formation (production) of the insulating film is continued. On the other hand, when the occurrence of abnormal discharge is detected (YES in step S6), the process proceeds to step S7, the film formation (production) of the insulating film is stopped, and the process further proceeds to step S8, where the electrode surface of the parallel plate electrode 5 is covered. Perform maintenance.

このメンテナンスは、基板ホルダである対向電極5B上に基板が存在しない状態で導電膜を成膜することによって行われる。導電膜は、製品の薄膜よりも導電性の高い材料を用いて成膜される。   This maintenance is performed by forming a conductive film on the counter electrode 5B, which is a substrate holder, in a state where no substrate exists. The conductive film is formed using a material having higher conductivity than the thin film of the product.

図4は、メンテナンスの工程を模式的に説明する工程図である。図4(a)は対向電極5B上に基板Sを相互に距離をおいて複数個並べた状態を示す平面図である。図4(b)は図4(a)の基板に絶縁膜を成膜する工程を繰返し、対向電極5Bの基板が載置されない電極表面上に絶縁物11が堆積した状態を示す断面図である。基板が載置される位置の電極表面にはこの絶縁物の堆積が見られず、電極表面は凹凸状になる。図4(c)は図4(b)の状態の対向電極5Bに対して導電膜15を成膜し、絶縁物11を完全に覆った状態を示す断面図である。一方、図4(d)は高周波電極5Aの電極表面を示す平面図である。図4(e)は、基板ホルダ上に基板Sを載置して基板Sに対して絶縁膜の成膜を繰り返したため高周波電極5Aの電極表面にも絶縁物が堆積した状態を示す断面図である。図4(f)は、図4(e)の絶縁物11の上に全面的に誘電体膜を成膜した状態を示す断面図である。このようにして、高周波電極5Aおよび対向電極5Bのメンテナンスが行われる。   FIG. 4 is a process diagram schematically illustrating a maintenance process. FIG. 4A is a plan view showing a state in which a plurality of substrates S are arranged at a distance from each other on the counter electrode 5B. FIG. 4B is a cross-sectional view showing a state in which the insulator 11 is deposited on the electrode surface on which the substrate of the counter electrode 5B is not placed by repeating the step of forming an insulating film on the substrate of FIG. . The insulator is not deposited on the surface of the electrode where the substrate is placed, and the electrode surface is uneven. FIG. 4C is a cross-sectional view showing a state in which the conductive film 15 is formed on the counter electrode 5B in the state of FIG. 4B and the insulator 11 is completely covered. On the other hand, FIG. 4D is a plan view showing the electrode surface of the high-frequency electrode 5A. FIG. 4E is a cross-sectional view showing a state in which an insulator is deposited also on the electrode surface of the high-frequency electrode 5A because the substrate S is placed on the substrate holder and an insulating film is repeatedly formed on the substrate S. is there. FIG. 4F is a cross-sectional view showing a state in which a dielectric film is entirely formed on the insulator 11 shown in FIG. In this way, maintenance of the high-frequency electrode 5A and the counter electrode 5B is performed.

本発明の絶縁性薄膜の製造方法において使用可能な絶縁膜の例としては、窒化シリコン膜(SiN)、酸化シリコン膜(SiO)、および酸化窒化シリコン膜(SiO)が挙げられる。これらの絶縁膜はシラン(SiH)、酸素(O)、窒素(N)、水素(H)、アンモニア(NH)から製品の薄膜の組成に応じて選ばれた反応ガスをプラズマの存在下に反応させて製造される。窒化シリコン膜が好ましい。 Examples of the insulating film that can be used in the method for manufacturing an insulating thin film of the present invention include a silicon nitride film (SiN x ), a silicon oxide film (SiO x ), and a silicon oxynitride film (SiO x N y ). . These insulating films are plasmas of reactive gases selected from silane (SiH 4 ), oxygen (O 2 ), nitrogen (N 2 ), hydrogen (H 2 ), and ammonia (NH 3 ) according to the composition of the product thin film. It is produced by reacting in the presence of A silicon nitride film is preferred.

メンテナンスに用いられる導電膜の材料としては、製品の薄膜よりも導電性が高いものであれば使用可能である。アモルファスシリコン(以下、「a−Si」という)および窒化シリコンが導電膜の材料として好ましい。a−Siの場合は、堆積したa−Siが光照射下で導電性を示すため、プラズマ放電の光照射によって導電膜となる。また、窒化シリコン膜は屈折率が2.3未満であると絶縁性が高いが、屈折率を2.3以上とすると導電性が高まる。このため、屈折率2.3以上の窒化シリコン薄膜を成膜した場合も、a−Siを成膜した場合と同様の導電化作用が得られる。   As the material of the conductive film used for maintenance, any material having higher conductivity than the product thin film can be used. Amorphous silicon (hereinafter referred to as “a-Si”) and silicon nitride are preferable as the material of the conductive film. In the case of a-Si, the deposited a-Si exhibits conductivity under light irradiation, and thus becomes a conductive film by light irradiation of plasma discharge. In addition, the silicon nitride film has a high insulating property when the refractive index is less than 2.3, but the conductivity is increased when the refractive index is 2.3 or more. For this reason, even when a silicon nitride thin film having a refractive index of 2.3 or more is formed, the same conductive effect as that obtained when a-Si is formed can be obtained.

メンテナンスは、例えば、次のように行われる。平行平板電極5に絶縁物が堆積し、対向電極5B上に基板Sが載置されていない状態で、例えば、次の条件で行われる。すなわち、真空チャンバ内に材料ガスを一定流量で供給し、真空チャンバ内の圧力を一定(例えば、300〜800Pa)に保った状態で、平行平板電極5に高周波電圧(例えば、300〜600W)を印加し、基板温度を一定温度(例えば、300〜670℃)でプラズマCVDを利用して、導電性の高いa−Siもしくは屈折率2.3以上の窒化シリコン薄膜を、平行平板電極5に成膜する。a−Siについては、材料ガスにシラン、水素、窒素を用い、屈折率2.3以上の窒化シリコン薄膜については材料ガスにシラン、アンモニア、水素を用いる。   The maintenance is performed as follows, for example. For example, the following conditions are used in a state where an insulator is deposited on the parallel plate electrode 5 and the substrate S is not placed on the counter electrode 5B. That is, a high frequency voltage (for example, 300 to 600 W) is applied to the parallel plate electrodes 5 while supplying a material gas at a constant flow rate in the vacuum chamber and keeping the pressure in the vacuum chamber constant (for example, 300 to 800 Pa). By applying plasma CVD at a constant substrate temperature (for example, 300 to 670 ° C.), a highly conductive a-Si or silicon nitride thin film having a refractive index of 2.3 or more is formed on the parallel plate electrodes 5. Film. For a-Si, silane, hydrogen, and nitrogen are used for the material gas, and for a silicon nitride thin film having a refractive index of 2.3 or more, silane, ammonia, and hydrogen are used for the material gas.

堆積したa−Siは、光照射下で導電性を示すため、SiN膜成膜中はプラズマ放電の光照射により導電膜となる。平行平板電極5が導電膜に覆われることにより、場所によるプラズマインピーダンスの差がなく、局所的な過剰電流が流れなくなるため、局所的なアーク放電や高密度放電の異常放電を抑えることができる。窒化シリコン膜は屈折率が2.3より小さくなると絶縁性が高くなるが、屈折率を2.3以上とすると導電性が高まるため、屈折率2.3以上の窒化シリコン薄膜を成膜した場合も、a−Si成膜した場合と同様の作用が得られる。   Since the deposited a-Si exhibits conductivity under light irradiation, it becomes a conductive film by light irradiation of plasma discharge during the formation of the SiN film. Since the parallel plate electrode 5 is covered with the conductive film, there is no difference in plasma impedance depending on the location, and local excessive current does not flow. Therefore, local arc discharge and abnormal discharge such as high-density discharge can be suppressed. When the refractive index of the silicon nitride film is smaller than 2.3, the insulating property is increased. However, when the refractive index is set to 2.3 or higher, the conductivity is increased. Therefore, when a silicon nitride thin film having a refractive index of 2.3 or higher is formed. In this case, the same effect as that obtained when the a-Si film is formed can be obtained.

再び図2を参照すると、ステップS5で限界成膜回数に達した(C=Rc)と判断されるか、またはステップS6で異常放電の発生が検知される(すなわちメンテナンスが必要であると判断される)と、ステップS7で製品である絶縁膜の生産がいったん中止され、ステップS8で導電膜が成膜される。これにより、絶縁性堆積物11が、導電膜15で覆われる。このメンテナンスが終了すると、ステップS9に進み、成膜回数カウンタのカウントがリセットされ、C=0となる。そして、ステップS2に戻り、絶縁膜の成膜準備をし、ステップS3で絶縁膜を成膜する。このようにして絶縁膜の成膜(生産)が行われる。   Referring to FIG. 2 again, it is determined in step S5 that the limit number of film formation has been reached (C = Rc), or the occurrence of abnormal discharge is detected in step S6 (that is, it is determined that maintenance is necessary). In step S7, production of the insulating film as a product is temporarily stopped, and a conductive film is formed in step S8. As a result, the insulating deposit 11 is covered with the conductive film 15. When this maintenance is completed, the process proceeds to step S9, where the count of the film formation counter is reset, and C = 0. Then, returning to step S2, preparation for forming an insulating film is performed, and an insulating film is formed in step S3. In this way, the insulating film is formed (produced).

図3は、本発明の別の実施の形態による絶縁性薄膜成膜方法を説明するフローチャートである。図3に示すフローチャートは、図2に示すフローチャートにおけるステップS4およびS5をステップS4AおよびS5Aに置き換え、ステップS9をなくした以外は図2と同様である。図2に示すフローチャートによる成膜方法では、メンテナンスが必要か否かの判断は絶縁膜成膜工程における成膜回数Cが所定の限界成膜回数Rcに達したかを判断することで行われたが、図3に示すフローチャートによる成膜方法では、メンテナンスが必要か否かは、絶縁膜成膜工程において平行平板電極上に堆積した絶縁物の膜厚が所定の膜厚(値)に到達したか否かをもって判断される。このため、ステップS4Aにおいて、成膜(生産)中に例えば光学式の膜厚測定装置を用いて好ましくはリアルタイムで成膜の膜厚を検査し、ステップS5Aにおいて、検査により得られた膜厚値(D)が予め設定された所定値(Dc)に到達したか否かが判断される。   FIG. 3 is a flowchart for explaining an insulating thin film forming method according to another embodiment of the present invention. The flowchart shown in FIG. 3 is the same as FIG. 2 except that steps S4 and S5 in the flowchart shown in FIG. 2 are replaced with steps S4A and S5A, and step S9 is eliminated. In the film formation method according to the flowchart shown in FIG. 2, whether or not maintenance is necessary is determined by determining whether the number of film formations C in the insulating film formation process has reached a predetermined limit number of film formations Rc. However, in the film formation method according to the flowchart shown in FIG. 3, whether or not maintenance is necessary depends on whether the film thickness of the insulator deposited on the parallel plate electrode in the insulating film formation process reaches a predetermined film thickness (value). It is judged by whether or not. Therefore, in step S4A, the film thickness of the film is preferably inspected in real time using, for example, an optical film thickness measuring device during film formation (production), and the film thickness value obtained by the inspection in step S5A. It is determined whether (D) has reached a predetermined value (Dc) set in advance.

D<Dcのときは、平行平板電極のメンテナンスが不要であると判断され(ステップS5A,NO)、図2に示すフローチャートによる場合と同様に、プロセスはステップS6に進む。D=Dcのときは、平行平板電極のメンテナンスが必要である(ステップS5A、YES)と判断され、ステップS7に進み、生産(成膜)が中止され、ついでステップS8において導電膜の成膜(メンテナンス)が行われる。ステップS8で誘電膜の成膜が行われた後、プロセスはステップS2に戻り、絶縁膜を成膜するための成膜準備が行われ、プロセスが繰り返される。   When D <Dc, it is determined that maintenance of the parallel plate electrode is unnecessary (step S5A, NO), and the process proceeds to step S6 as in the case of the flowchart shown in FIG. When D = Dc, it is determined that the parallel plate electrode needs to be maintained (step S5A, YES), the process proceeds to step S7, the production (film formation) is stopped, and then the conductive film is formed (step S8). Maintenance) is performed. After the dielectric film is formed in step S8, the process returns to step S2, preparation for film formation for forming the insulating film is performed, and the process is repeated.

図5および図6はそれぞれ、本発明の一実施の形態によるプラズマCVD装置の概念図であって、基板ホルダである対向電極5B上に堆積された絶縁性堆積物11を覆うように導電膜15を設けた状態を示す。ただし、図5および図6においては、制御装置10、検知器12、スイッチ14は、図示を省略した。導電膜15を設けたことにより、電荷は導電膜15の表面を容易に移動し均一に分布することができる。なお、導電膜15は一面に成膜させ、絶縁堆積物11が露出している部分がないようにする。これによって、電極ホルダ上の位置によらず均一に電荷が分布し、電荷の局所集中が生じない。   FIG. 5 and FIG. 6 are conceptual diagrams of a plasma CVD apparatus according to an embodiment of the present invention, respectively, in which the conductive film 15 covers the insulating deposit 11 deposited on the counter electrode 5B which is a substrate holder. The state where is provided. However, in FIG. 5 and FIG. 6, illustration of the control device 10, the detector 12, and the switch 14 is omitted. By providing the conductive film 15, charges can easily move on the surface of the conductive film 15 and be distributed uniformly. Note that the conductive film 15 is formed on one surface so that there is no portion where the insulating deposit 11 is exposed. As a result, charges are evenly distributed regardless of the position on the electrode holder, and local concentration of charges does not occur.

したがって、図5または図6に示すように、メンテナンス終了後のプラズマCVD装置を用いて、図2のステップS3において新たに基板を導入し、絶縁膜の成膜を行うと、プラズマ密度が偏ることがないため、均一な膜厚の絶縁膜を成膜することができる。また、対向電極5B上に堆積した絶縁物にコーナー部が存在しても導電膜に覆われるため、異常放電が発生することがない。このため、安定したプラズマ放電が得られ、基板表面上に均一な膜厚の絶縁膜を形成することができる。   Therefore, as shown in FIG. 5 or FIG. 6, when a substrate is newly introduced in step S3 of FIG. 2 and an insulating film is formed using the plasma CVD apparatus after completion of maintenance, the plasma density is biased. Therefore, an insulating film with a uniform thickness can be formed. Further, even if there is a corner portion in the insulator deposited on the counter electrode 5B, it is covered with the conductive film, so that abnormal discharge does not occur. For this reason, stable plasma discharge can be obtained, and an insulating film having a uniform thickness can be formed on the substrate surface.

上述のように、本発明のCVD装置およびCVD成膜方法では、基板表面に絶縁膜の成膜を繰返し、異常放電が検知されるか、あるいは所定の成膜回数または平行電極面上に堆積した絶縁物の所定の膜厚が到達されることを指標に、平行平板電極5A,5B上の堆積絶縁物の上に導電膜を成膜してメンテナンスを行う。その結果、特別の部品、装置を設けることなく、平行平板電極の対抗面に堆積してくる絶縁物の膜厚分布に対する悪影響を取り除くことができる。   As described above, in the CVD apparatus and the CVD film forming method of the present invention, the insulating film is repeatedly formed on the substrate surface, abnormal discharge is detected, or the film is deposited on the predetermined number of film formations or on the parallel electrode surface. Maintenance is performed by forming a conductive film on the deposited insulator on the parallel plate electrodes 5A and 5B, using the index that the predetermined thickness of the insulator is reached. As a result, an adverse effect on the film thickness distribution of the insulator deposited on the opposing surface of the parallel plate electrode can be eliminated without providing any special parts or devices.

[比較例1]
上述したように図1に示すCVD装置1は図2に示すメンテナンス機能をオンオフすることができる。そこで、図1に示すCVD装置1のメンテナンス機能をオフにして、図7(a)〜(d)に示す手順に従ってまず電極表面に絶縁膜を成膜し、その後、基板表面に絶縁膜を形成した。
[Comparative Example 1]
As described above, the CVD apparatus 1 shown in FIG. 1 can turn on and off the maintenance function shown in FIG. Therefore, the maintenance function of the CVD apparatus 1 shown in FIG. 1 is turned off, and an insulating film is first formed on the electrode surface in accordance with the procedure shown in FIGS. 7A to 7D, and then the insulating film is formed on the substrate surface. did.

図7(a)は、基板Sを載せない状態の真空チャンバ3内の対向電極5Bを示す。まず、この対向電極5Bの表面に対して、標準レシピで屈折率2.0(屈折率2.3未満)の高絶縁性のSiN膜の成膜を繰返し行い、対向電極5B上に十分にSiN膜11aを成膜した(図7(b))。このとき、高周波電極5Aの表面にも屈折率2.0のSiN膜11aが成膜される。絶縁物11aの堆積量は、ガス密度や電極形状の影響を受けて電極の場所によって異なり、平行平板電極5A,5Bの表面の絶縁膜の厚みは一様ではない。このようにして、基板表面に絶縁膜を繰り返し成膜した際の平行平板電極5の表面状態を再現した。   FIG. 7A shows the counter electrode 5B in the vacuum chamber 3 in a state where the substrate S is not placed. First, a highly insulating SiN film having a refractive index of 2.0 (less than 2.3) is repeatedly formed on the surface of the counter electrode 5B using a standard recipe, and a sufficient amount of SiN is sufficiently formed on the counter electrode 5B. A film 11a was formed (FIG. 7B). At this time, a SiN film 11a having a refractive index of 2.0 is also formed on the surface of the high-frequency electrode 5A. The amount of the insulator 11a deposited varies depending on the location of the electrode due to the influence of the gas density and the electrode shape, and the thickness of the insulating film on the surfaces of the parallel plate electrodes 5A and 5B is not uniform. In this way, the surface state of the parallel plate electrode 5 when the insulating film was repeatedly formed on the substrate surface was reproduced.

このように一様でないSiN膜11aで覆われた対向電極5Bの上に基板Sを載せ(図7(c))、この基板Sの表面に、屈折率2.0、膜厚80nmが得られるように調整されたSiN膜成膜条件で成膜した(図7(d))。膜厚分布Dtは10.58%であった。   The substrate S is placed on the counter electrode 5B covered with the nonuniform SiN film 11a as described above (FIG. 7C), and a refractive index of 2.0 and a film thickness of 80 nm are obtained on the surface of the substrate S. The film was formed under the SiN film formation conditions adjusted as described above (FIG. 7D). The film thickness distribution Dt was 10.58%.

図1に示すCVD装置1を用いて、比較例1と同様にして標準レシピで対向電極5B上に屈折率2.0のSiN膜11aを成膜した(図7(b))。このとき、高周波電極5Aの表面にも屈折率2.0のSiN膜11aが成膜される。このようにして、成膜工程を繰返し実施した後の平行平板電極5の状態を模擬的に再現した。この状態で、図1のCVD装置1のメンテナンス機能を用いて次のようにメンテナンスを行った。   Using the CVD apparatus 1 shown in FIG. 1, a SiN film 11a having a refractive index of 2.0 was formed on the counter electrode 5B by a standard recipe in the same manner as in Comparative Example 1 (FIG. 7B). At this time, a SiN film 11a having a refractive index of 2.0 is also formed on the surface of the high-frequency electrode 5A. Thus, the state of the parallel plate electrode 5 after repeatedly performing the film-forming process was simulated. In this state, maintenance was performed as follows using the maintenance function of the CVD apparatus 1 of FIG.

対向電極5B上に基板を載置しない状態で、プラズマCVD装置1の真空チャンバ3内にシランおよび窒素を一定流量で供給する。真空チャンバ3内の圧力を一定に保った状態で、高周波電極5Aに定電流制御された交流電源PSから高周波電圧を印加し、絶縁膜11aの付着した対向電極5B上にa−Si膜15aを成膜した。対向電極5Bの絶縁膜11aを導電性のa−Si15Aで覆うことによって、対向電極5Bを一定の厚みの導電性薄膜で覆った(図7(e))。このとき、高周波電極5Aの表面にもa−Si15Aが成膜される。絶縁堆積物11aはa−Si膜15aで覆われ、このa−Si膜はSiN薄膜の成膜中のプラズマ放電の光照射により導電膜となるため、SiN薄膜の成膜中に電荷が局所に集中することがなくなり、プラズマの生成が均一になる。その結果、基板Sを載せて基板表面に絶縁膜としてSiN薄膜を形成した場合、その膜厚が均一になる。   Silane and nitrogen are supplied into the vacuum chamber 3 of the plasma CVD apparatus 1 at a constant flow rate without placing the substrate on the counter electrode 5B. With the pressure in the vacuum chamber 3 kept constant, a high frequency voltage is applied to the high frequency electrode 5A from a constant current controlled AC power supply PS, and the a-Si film 15a is formed on the counter electrode 5B to which the insulating film 11a is adhered. A film was formed. By covering the insulating film 11a of the counter electrode 5B with conductive a-Si 15A, the counter electrode 5B was covered with a conductive thin film having a certain thickness (FIG. 7E). At this time, a-Si 15A is also formed on the surface of the high-frequency electrode 5A. The insulating deposit 11a is covered with an a-Si film 15a, and this a-Si film becomes a conductive film by light irradiation of plasma discharge during the formation of the SiN thin film, so that charges are locally generated during the formation of the SiN thin film. Concentration is eliminated and plasma generation becomes uniform. As a result, when the substrate S is placed and a SiN thin film is formed as an insulating film on the substrate surface, the film thickness becomes uniform.

実際、図7(e)のa−Si膜15aの成膜後に、基板Sを対向電極5B上に載せ(図7(f))、再び標準成膜レシピに従って基板に屈折率2.0のSiN膜を成膜したところ(図7(g))、基板上のSiN膜の膜厚分布Dtは6.70%となり、平行平板電極内の基板に形成されたSiN膜の膜厚が均一化された。   Actually, after the formation of the a-Si film 15a of FIG. 7E, the substrate S is placed on the counter electrode 5B (FIG. 7F), and SiN having a refractive index of 2.0 is again applied to the substrate in accordance with the standard film formation recipe. When the film was formed (FIG. 7 (g)), the film thickness distribution Dt of the SiN film on the substrate was 6.70%, and the film thickness of the SiN film formed on the substrate in the parallel plate electrode was made uniform. It was.

図8は、a−Si膜を成膜する前および後に成膜した基板上のSiN膜の膜厚の分布を示す図である。図8(a)は、平行平板電極5の表面にa−Si膜を成膜せずに基板表面にSiN薄膜を成膜した場合を示す。成膜レートは28.4mm/minであり、膜厚分布は10.58%であった。図8(b)は、平行平板電極5の表面にa−Si膜を成膜後に基板表面にSiN薄膜を成膜した場合を示す。成膜レートは30.3mm/minであり、膜厚分布は6.70%であった。   FIG. 8 is a diagram showing the distribution of the thickness of the SiN film on the substrate formed before and after forming the a-Si film. FIG. 8A shows a case where a SiN thin film is formed on the substrate surface without forming an a-Si film on the surface of the parallel plate electrode 5. The film formation rate was 28.4 mm / min, and the film thickness distribution was 10.58%. FIG. 8B shows a case where a SiN thin film is formed on the substrate surface after the a-Si film is formed on the surface of the parallel plate electrode 5. The film formation rate was 30.3 mm / min, and the film thickness distribution was 6.70%.

また、図9はa−Siコートの効果を示すグラフである。図9から明らかなように、基板に薄膜を成膜中の直流電圧Vdcの変動は、a−Si膜の成膜(メンテナンス)を行わずにSiN膜の成膜を続けた場合(図9、◆)、電極が高絶縁成膜(屈折率2.0のSiN)に覆われているために、Vdcが安定するまでの時定数が約150秒と長い。平行平板電極5の表面にa−Si膜を成膜した後は、第1回目の絶縁膜の成膜(図9、▲)、第2回目(図9、■)ともにVdcは迅速に安定していることが分かる。   FIG. 9 is a graph showing the effect of the a-Si coating. As is clear from FIG. 9, the fluctuation of the DC voltage Vdc during the formation of the thin film on the substrate occurs when the SiN film is continuously formed without performing the a-Si film formation (maintenance) (FIG. 9, ◆) Since the electrode is covered with a highly insulating film (SiN having a refractive index of 2.0), the time constant until Vdc becomes stable is as long as about 150 seconds. After the a-Si film is formed on the surface of the parallel plate electrode 5, Vdc is rapidly stabilized in both the first insulating film formation (FIG. 9, ▲) and the second (FIG. 9, ■). I understand that

[変形例1]
実施例1において、a−Si膜の成膜および屈折率2.3以上の窒化シリコン(SiN)膜の成膜を、シランの他に、窒素および水素、アンモニアを含むガス組成を用いて行った。実施例1とほぼ同様の結果が得られた。
[Modification 1]
In Example 1, the a-Si film and the silicon nitride (SiN) film having a refractive index of 2.3 or more were formed using a gas composition containing nitrogen, hydrogen, and ammonia in addition to silane. . A result almost similar to that of Example 1 was obtained.

図1に示すCVD装置1を用いて、比較例1と同様にして標準レシピで対向電極5B上に屈折率2.0のSiN膜11aを成膜した(図7(b))。このとき、高周波電極5Aの表面にも屈折率2.0のSiN膜11aが成膜される。このようにして、成膜工程を繰返し実施した後の平行平板電極5の状態を模擬的に再現した。この状態で、図1のCVD装置1のメンテナンス機能を用いて次のようにメンテナンスを行った。実施例1と異なる点は、導電性薄膜としてa−siに代えてSiNを使用する点である。   Using the CVD apparatus 1 shown in FIG. 1, a SiN film 11a having a refractive index of 2.0 was formed on the counter electrode 5B by a standard recipe in the same manner as in Comparative Example 1 (FIG. 7B). At this time, a SiN film 11a having a refractive index of 2.0 is also formed on the surface of the high-frequency electrode 5A. Thus, the state of the parallel plate electrode 5 after repeatedly performing the film-forming process was simulated. In this state, maintenance was performed as follows using the maintenance function of the CVD apparatus 1 of FIG. The difference from Example 1 is that SiN is used instead of a-si as the conductive thin film.

対向電極5B上に基板を載置しない状態で、プラズマCVD装置1の真空チャンバ3内にシランおよび窒素を一定流量で供給し、真空チャンバ3内の圧力を一定に保った状態で、平行平板電極5に定電流制御された交流電源PSから高周波電圧を印加し、絶縁膜11aの付着した平行平板電極に屈折率2.3のSiN膜(n=2.3 SiN)15bを成膜した。屈折率2.3のSiN膜は屈折率2.0のSiN膜(n=2.0 SiN)11aより導電性が高く、平行平板電極5A,5Bの絶縁膜を屈折率2.3のSiNで覆うことによって、図7(e)のa−Si膜15と同様に平行平板電極が一様に導電化された状態とした。絶縁堆積物11は屈折率2.3のSiN膜15bで覆われ、導電性となった。この状態で対向電極5B上に基板を載置し、基板表面に絶縁膜(屈折率2.0のSiN膜)を成膜すると、電荷が局所に集中することがなく、プラズマの生成が均一になり、その結果、得られるSiN膜の膜厚が均一になる。   In a state where the substrate is not placed on the counter electrode 5B, silane and nitrogen are supplied at a constant flow rate into the vacuum chamber 3 of the plasma CVD apparatus 1 and the pressure in the vacuum chamber 3 is kept constant. A high frequency voltage was applied from the AC power source PS controlled at a constant current to 5 to form a SiN film (n = 2.3 SiN) 15b having a refractive index of 2.3 on the parallel plate electrode to which the insulating film 11a was adhered. The SiN film with a refractive index of 2.3 has higher conductivity than the SiN film with a refractive index of 2.0 (n = 2.0 SiN) 11a, and the insulating films of the parallel plate electrodes 5A and 5B are made of SiN with a refractive index of 2.3. By covering, the parallel plate electrode was made to be uniformly conductive like the a-Si film 15 in FIG. The insulating deposit 11 was covered with the SiN film 15b having a refractive index of 2.3 and became conductive. In this state, when the substrate is placed on the counter electrode 5B and an insulating film (SiN film having a refractive index of 2.0) is formed on the substrate surface, charges are not concentrated locally, and plasma generation is uniform. As a result, the thickness of the obtained SiN film becomes uniform.

実際、図7(e)の屈折率2.3のSiN膜の成膜後に、基板Sを対向電極5B上に載せ(図7(f))、再び標準成膜レシピに従ってSiN膜(屈折率2.0)を成膜したところ(図7(g))、基板の膜厚分布は実施例1のа−Siを用いた場合とほぼ同じとなり、平行平板電極内の基板に形成されたSiN膜の膜厚が場所によらず均一化された。   Actually, after the formation of the SiN film having a refractive index of 2.3 in FIG. 7E, the substrate S is placed on the counter electrode 5B (FIG. 7F), and again according to the standard film formation recipe (refractive index of 2). 0.0) (FIG. 7 (g)), the film thickness distribution of the substrate is almost the same as in the case of using a-Si in Example 1, and the SiN film formed on the substrate in the parallel plate electrode The film thickness was made uniform regardless of the location.

[比較例2]
図1に示すCVD装置1を用いて、比較例と同様にして標準レシピで対向電極5B上に屈折率2.0のSiN膜11aを成膜した(図7(b))。このとき、高周波電極5Aの表面にも屈折率2.0のSiN膜11aが成膜される。このようにして、成膜工程を繰返し実施した後の平行平板電極5の状態を模擬的に再現した。電極表面がほぼ完全に絶縁膜11で覆われる状態になったため、SiN膜の成膜を続行した場合に、高周波電極5Aの端部付近に周囲より高密度のプラズマ放電が目視で観察された(図12参照)。また、放電中は高周波電極5Aの負の直流電位Vdcが一定でなく変動し、高周波電極5Aに蓄積する電荷量が不安定であった(図9参照)。
[Comparative Example 2]
Using the CVD apparatus 1 shown in FIG. 1, a SiN film 11a having a refractive index of 2.0 was formed on the counter electrode 5B by a standard recipe in the same manner as in the comparative example (FIG. 7B). At this time, a SiN film 11a having a refractive index of 2.0 is also formed on the surface of the high-frequency electrode 5A. Thus, the state of the parallel plate electrode 5 after repeatedly performing the film-forming process was simulated. Since the surface of the electrode is almost completely covered with the insulating film 11, when the deposition of the SiN film is continued, a high-density plasma discharge is visually observed near the end of the high-frequency electrode 5A ( (See FIG. 12). Further, during the discharge, the negative DC potential Vdc of the high frequency electrode 5A fluctuated and was not constant, and the amount of charge accumulated in the high frequency electrode 5A was unstable (see FIG. 9).

図1に示すCVD装置1を用いて、比較例2と同様にして標準レシピで対向電極5B上に屈折率2.0のSiN膜11aを成膜した(図7(b))。このとき、高周波電極5Aの表面にも屈折率2.0のSiN膜11aが成膜される。このようにして、絶縁膜の成膜工程を繰返し実施した後の平行平板電極5の状態を模擬的に再現した。この状態で図1のCVD装置1のメンテナンス機能を用いて成膜を続けたところ、放電が検知され(図2、ステップS6参照)、SiN膜の成膜(生産)が中止され、次のようにメンテナンスが行われた。   Using the CVD apparatus 1 shown in FIG. 1, a SiN film 11a having a refractive index of 2.0 was formed on the counter electrode 5B by a standard recipe in the same manner as in Comparative Example 2 (FIG. 7B). At this time, a SiN film 11a having a refractive index of 2.0 is also formed on the surface of the high-frequency electrode 5A. Thus, the state of the parallel plate electrode 5 after repeatedly performing the process of forming the insulating film was simulated. In this state, when the film formation is continued using the maintenance function of the CVD apparatus 1 in FIG. 1, discharge is detected (see FIG. 2, step S6), and the film formation (production) of the SiN film is stopped. Maintenance was performed.

プラズマCVD装置1の真空チャンバ3内に屈折率2.3のSiNが得られるように調整された原料ガスをガス供給機構7より導入し、真空チャンバ内3の圧力を一定に保った状態で、平行平板電極5に高周波電圧を印加し、平行平板電極5に屈折率2.3のSiN膜を成膜した。平行平板電極5の堆積絶縁物11をSiN(屈折率2.3)で覆うことによって、平行平板電極5は導電化され、プラズマ発生時に平行平板電極5に蓄積する電荷量が一様に分布する状態となった。   In the state where the raw material gas adjusted so that SiN having a refractive index of 2.3 is obtained in the vacuum chamber 3 of the plasma CVD apparatus 1 is introduced from the gas supply mechanism 7 and the pressure in the vacuum chamber 3 is kept constant. A high frequency voltage was applied to the parallel plate electrode 5, and a SiN film having a refractive index of 2.3 was formed on the parallel plate electrode 5. By covering the deposited insulator 11 of the parallel plate electrode 5 with SiN (refractive index 2.3), the parallel plate electrode 5 is made conductive, and the amount of charge accumulated in the parallel plate electrode 5 is uniformly distributed when plasma is generated. It became a state.

平行平板電極5の表面をSiN(屈折率2.3)膜で一様に覆った後に、再び標準成膜レシピでSiN(屈折率2.0)膜を成膜した。これにより、局所的な高密度プラズマ放電(異常放電)ADの発生が検知されなかった。成膜中のVdcは一定値であり、高周波電極に蓄積する電荷量が安定しており、局所的に過剰電流が流れることがなかった。SiN(屈折率2.3)膜の成膜後における成膜中の直流電圧Vdcの変動は、実施例2の図9とほぼ同様であった。   After the surface of the parallel plate electrode 5 was uniformly covered with an SiN (refractive index 2.3) film, an SiN (refractive index 2.0) film was formed again by a standard film formation recipe. Thereby, generation | occurrence | production of local high-density plasma discharge (abnormal discharge) AD was not detected. Vdc during film formation was a constant value, the amount of charge accumulated in the high-frequency electrode was stable, and no excessive current flowed locally. The fluctuation of the DC voltage Vdc during the film formation after the SiN (refractive index 2.3) film was formed was almost the same as that in FIG.

[変形例2]
実施例3において、a−Si成膜および屈折率2.3以上の窒化シリコン(SiN)膜の成膜を、シランの他に、窒素および水素、アンモニアを含むガス組成を用いて行った。実施例3とほぼ同様の結果が得られた。
[Modification 2]
In Example 3, an a-Si film and a silicon nitride (SiN) film having a refractive index of 2.3 or more were formed using a gas composition containing nitrogen, hydrogen, and ammonia in addition to silane. Almost the same result as in Example 3 was obtained.

実施例1〜3では、基板を載置することなく平行平板電極表面に意図的に絶縁膜を堆積して、堆積絶縁物11の存在するプラズマCVD装置の平行平板電極の状態を模擬的に再現したが、本実施例では、実際に、図1のCVD装置1を用いて、メンテナンス機能をオンにした状態で絶縁膜の成膜(生産)を行った。   In Examples 1 to 3, an insulating film is intentionally deposited on the surface of the parallel plate electrode without placing a substrate, and the state of the parallel plate electrode of the plasma CVD apparatus in which the deposited insulator 11 exists is simulated. However, in this example, the insulating film was actually formed (produced) with the maintenance function turned on using the CVD apparatus 1 of FIG.

スイッチ14により装置を起動させ、制御装置10のROM18に格納されている成膜処理プログラムにより成膜を行う。図示しない入力手段により標準レシピでSiN膜(屈折率2.0)を成膜する成膜条件を記憶装置(不図示)に設定する。制御装置10のCPU16は設定された条件のデータを参照して、ガス供給機構7とガス排気機構9等を制御し、これにより制御装置10の制御に基づいて成膜準備が行われる(図2、ステップS2)。成膜を繰り返して行っている際、異常放電が検知器12により検知されると、検知器12から検知信号が制御装置10に送信される。制御装置10のCPUは検知器12からの信号を受信するとガス供給機構7とガス排気機構9等に成膜中止指令を送信し、絶縁膜の成膜(生産)が中止される。生産が中止されると、制御装置10はガス供給機構7とガス排気機構9等に導電膜の成膜の開始指令を発し、メンテナンスが開始される。基板Sを基板ホルダ上に載置せずに、a−Si膜を平行平板電極5の電極面に成膜する。このメンテナンスが終了すると、プログラムに従い、制御装置10は、先に設定された絶縁膜の成膜条件に従って基板の表面に成膜を行う準備を行い、基板表面に対して絶縁膜の成膜(生産)が再開される。   The apparatus is activated by the switch 14 and film formation is performed by a film formation processing program stored in the ROM 18 of the control apparatus 10. A film forming condition for forming a SiN film (refractive index 2.0) by a standard recipe is set in a storage device (not shown) by an input means (not shown). The CPU 16 of the control device 10 refers to the data of the set conditions to control the gas supply mechanism 7 and the gas exhaust mechanism 9 and the like, thereby preparing for film formation based on the control of the control device 10 (FIG. 2). Step S2). When an abnormal discharge is detected by the detector 12 during repeated film formation, a detection signal is transmitted from the detector 12 to the control device 10. When the CPU of the control device 10 receives a signal from the detector 12, it sends a film formation stop command to the gas supply mechanism 7, the gas exhaust mechanism 9, etc., and the film formation (production) of the insulating film is stopped. When the production is stopped, the control device 10 issues a command to start forming a conductive film to the gas supply mechanism 7 and the gas exhaust mechanism 9 and the maintenance is started. An a-Si film is formed on the electrode surface of the parallel plate electrode 5 without placing the substrate S on the substrate holder. When this maintenance is completed, according to the program, the control device 10 prepares to form a film on the surface of the substrate in accordance with the previously set insulating film forming conditions, and forms an insulating film on the substrate surface (production ) Is resumed.

上記の場合は、装置起動後、絶縁膜の成膜処理の回数(C)が所定の限界成膜回数(Rc)より小さい(C<Rc)段階で検知器12により異常放電が検知された場合である。C<Rcの段階で異常放電が検知されなかった場合は、成膜処理の回数がC=Rcとなった段階で、制御装置10により生産中止指令が送信され、生産が中止される。生産が中止されると、上述のメンテナンスが行われ、メンテナンスが終了すると、設定された成膜条件に従って成膜準備がなされ、絶縁膜の成膜が再開される。このようにして、適宜メンテナンスを行いつつ、基板表面への絶縁膜の成膜が繰り返される。これにより均一な膜厚の絶縁膜を有する製品が得られた。   In the above case, when the abnormal discharge is detected by the detector 12 at the stage where the number of film formation processes (C) of the insulating film is smaller than the predetermined limit film formation number (Rc) (C <Rc) after starting the apparatus. It is. When abnormal discharge is not detected at the stage of C <Rc, the production stop command is transmitted by the control device 10 at the stage when the number of film forming processes becomes C = Rc, and the production is stopped. When production is stopped, the above-described maintenance is performed. When the maintenance is completed, film formation is prepared according to the set film formation conditions, and the film formation of the insulating film is resumed. In this manner, the insulating film is repeatedly formed on the substrate surface while performing appropriate maintenance. As a result, a product having an insulating film having a uniform thickness was obtained.

実施例4において導電膜としてa−Si膜の替わりに実施例2と同様に屈折率2.3のSiN膜を成膜したところ、同様に均一な膜厚の絶縁膜が得られた。   When a SiN film having a refractive index of 2.3 was formed as a conductive film in Example 4 instead of the a-Si film in the same manner as in Example 2, an insulating film having a uniform film thickness was obtained in the same manner.

準備段階として、絶縁膜の成膜を繰り返して、初めて製品に膜厚が不均一であることが観察された成膜回数を記録しておく。この記録された回数に基づき安全を見込んだ若干内輪の回数、例えば8回を限界成膜回数として設定し、絶縁膜の成膜処理の回数がこの限界成膜回数の値に達した段階で製品の製造をいったん中止し、実施例1と同様に基板ホルダ5に基板Sの無い状態で導電膜の成膜を行う。このメンテナンスを行った後、再び実施例1と同様に基板に絶縁膜の成膜を繰り返す。目標成膜回数になった時点で成膜処理を終了する。目標成膜回数になる前に限界成膜回数に達した場合は、製品の製造をいったん中止し、メンテナンスを行った後、製品の製造を行う。このサイクルを目標成膜回数に達するまで繰り返す。   As a preparatory stage, the number of film formations in which it was observed that the film thickness was not uniform for the first time was recorded after the insulating film was formed repeatedly. Based on the recorded number of times, the number of inner rings, for which safety is anticipated, for example, 8 is set as the limit film formation number, and the product is formed when the number of insulating film formation processes reaches the limit film formation value. As in Example 1, the conductive film is formed on the substrate holder 5 without the substrate S. After performing this maintenance, an insulating film is repeatedly formed on the substrate in the same manner as in the first embodiment. When the target number of film formation is reached, the film formation process is terminated. If the limit number of film formation is reached before reaching the target number of film formation, the production of the product is temporarily stopped, maintenance is performed, and then the product is produced. This cycle is repeated until the target number of film formation is reached.

実施例6では、メンテナンスを行うか否かを上述の限界成膜回数を設定して成膜回数がその限界成膜回数に達したか否かにより判断しているが、本実施例では、製品の製造を繰り返して、最初に異常放電が観察または検知された段階でいったん製品の製造を中止し、他の実施例と同様のメンテナンスを行う。   In the sixth embodiment, whether or not to perform maintenance is determined by setting the above-mentioned limit film formation frequency and determining whether or not the film formation frequency has reached the limit film formation frequency. The manufacturing of the product is repeated, and when the abnormal discharge is first observed or detected, the manufacturing of the product is once stopped, and the maintenance similar to the other embodiments is performed.

[変形例3]
実施例7において、限界成膜回数はさらに異常放電の発生がはじめて観察または検知される成膜回数も考慮して設定してもよい。
[Modification 3]
In Example 7, the limit number of film formations may be set in consideration of the number of film formations at which abnormal discharge is observed or detected for the first time.

限界成膜回数を設定する方式による場合は、異常放電の発生を指標にする場合に比べて製品の歩留まりがさらに向上する利点がある。   The method of setting the limit number of film formation has an advantage that the yield of the product is further improved as compared with the case where the occurrence of abnormal discharge is used as an index.

[変形例4]
実施例1〜4および変形例1〜3において、異常放電の検知は検知器12により検知したが、目視により異常放電の発生を検知してもよい。また、プログラムに従い自動的に成膜処理工程が進行するように構成したが、各工程への移行はマニュアル操作によってもよい。
[Modification 4]
In Examples 1 to 4 and Modifications 1 to 3, the detection of abnormal discharge was detected by the detector 12, but the occurrence of abnormal discharge may be detected visually. In addition, the film forming process is automatically advanced according to the program, but the transition to each process may be performed manually.

実施例6では、限界成膜回数を設定して成膜回数がその限界成膜回数に達したか否かにより、また変形例3では異常放電の発生がはじめて観察または検知されたことにより、メンテナンスを行うか否かを判断している。本実施例では、成膜(生産)中に平行平板電極の電極面に堆積した絶縁物の膜厚を、図示しない光学式膜厚測定装置によりリアルタイムに測定し、膜厚が所定の膜厚に到達した段階でいったん製品の製造を中止し、他の実施例と同様のメンテナンスを行う。メンテナンス終了後、成膜準備を行い、成膜(生産)を再開する。   In Example 6, the limit number of film formation is set, and whether or not the number of film formation reaches the limit number of film formation, and in Modification 3, the occurrence of abnormal discharge is observed or detected for the first time. It is determined whether or not to perform. In this example, the film thickness of the insulator deposited on the electrode surface of the parallel plate electrode during film formation (production) is measured in real time by an optical film thickness measuring device (not shown), and the film thickness is adjusted to a predetermined film thickness. When it reaches, the production of the product is temporarily stopped, and maintenance similar to the other embodiments is performed. After maintenance is completed, film formation preparation is performed, and film formation (production) is resumed.

以上の説明はあくまで一例であり、本発明の特徴を損なわない限り、本発明は上述した実施の形態および変形例に限定されるものではない。また、実施の形態と変形例の一つとを組み合わせること、もしくは、実施の形態と変形例の複数とを組み合わせることも可能である。さらに、変形例同士をどのように組み合わせることも可能である。あるいは、実施の形態または実施例、変形例中の一部の工程を他の実施の形態または実施例、変形例において用いること、または置きかえることも可能である。さらにまた、本発明の技術的思想の範囲内で考えられる他の形態についても、本発明の範囲内に含まれる。   The above description is merely an example, and the present invention is not limited to the above-described embodiments and modifications unless the features of the present invention are impaired. Further, it is possible to combine the embodiment and one of the modified examples, or to combine the embodiment and a plurality of modified examples. Furthermore, it is possible to combine the modified examples in any way. Alternatively, part of the steps in the embodiment, the example, or the modification can be used in or replaced with another embodiment, the example, or the modification. Furthermore, other forms conceivable within the scope of the technical idea of the present invention are also included in the scope of the present invention.

本発明は従来のプラズマCVD装置に装置または部品を追加することなく、均一な膜厚分布の薄膜を形成することができ、特に太陽電池用絶縁薄膜の製造に好適に利用することができる。   The present invention can form a thin film having a uniform film thickness distribution without adding an apparatus or parts to a conventional plasma CVD apparatus, and can be suitably used particularly for the production of an insulating thin film for solar cells.

1 プラズマCVD装置
3 真空チャンバ
5 平行平板電極
5A 高周波電極
5B 対向電極(基板ホルダ)
7 ガス供給機構
9 ガス排気機構
11 絶縁物
11a SiN膜(屈折率2.0)
12 検知器
13 アースシールド
14 スイッチ
15 導電膜
15a a−Si膜
15b SiN膜(屈折率2.3)
16 CPU
18 ROM
105C 端部
111A 絶縁物のコーナー部
MB マッチングボックス
AD 異常放電
D プラズマ放電(グロー放電)
PS 交流電源
S 基板
DESCRIPTION OF SYMBOLS 1 Plasma CVD apparatus 3 Vacuum chamber 5 Parallel plate electrode 5A High frequency electrode 5B Counter electrode (substrate holder)
7 Gas supply mechanism 9 Gas exhaust mechanism 11 Insulator 11a SiN film (refractive index 2.0)
12 detector 13 earth shield 14 switch 15 conductive film 15a a-Si film 15b SiN film (refractive index 2.3)
16 CPU
18 ROM
105C End 111A Insulator corner MB Matching box AD Abnormal discharge D Plasma discharge (Glow discharge)
PS AC power supply S Substrate

Claims (10)

電極を用いた容量結合型プラズマCVDによって基板の表面に薄膜を形成するプラズマCVD成膜方法において、
前記基板の表面へ薄膜を形成する薄膜形成工程と、
前記薄膜形成工程で前記基板の表面に薄膜を形成した後、前記基板が無い状態で前記薄膜と比較して導電性の高い薄膜を前記電極の表面に生成する導電性薄膜形成工程とを有することを特徴とするプラズマCVD成膜方法。
In a plasma CVD film forming method of forming a thin film on the surface of a substrate by capacitively coupled plasma CVD using an electrode,
Forming a thin film on the surface of the substrate; and
After forming a thin film on the surface of the substrate in the thin film forming step, a conductive thin film forming step of generating a thin film on the surface of the electrode having a higher conductivity than the thin film without the substrate. The plasma CVD film-forming method characterized by these.
電極を用いた容量結合型プラズマCVDによって基板の表面に薄膜を形成するプラズマCVD装置において、
前記基板の表面へ薄膜を形成する薄膜形成手段と、
前記薄膜形成手段による一定量の薄膜を前記基板の表面に形成した後、前記基板が無い状態で前記薄膜と比較して導電性の高い薄膜を前記電極の表面に生成する導電性薄膜生成手段とを備えたことを特徴とするプラズマCVD装置。
In a plasma CVD apparatus for forming a thin film on the surface of a substrate by capacitively coupled plasma CVD using an electrode,
A thin film forming means for forming a thin film on the surface of the substrate;
A conductive thin film generating means for forming a thin film having a higher conductivity on the surface of the electrode in the absence of the substrate after forming a certain amount of thin film on the surface of the substrate by the thin film forming means; A plasma CVD apparatus comprising:
平行平板電極にて放電を行い、基板の表面に窒化シリコン薄膜を成膜するプラズマCVD成膜方法において、
前記基板の表面へ屈折率2.3未満の窒化シリコン薄膜を形成する薄膜形成工程と、
前記基板の表面へ一定量の窒化シリコン薄膜を形成した後に、基板が無い状態で、アモルファスシリコン(以下、a−Si)または屈折率2.3以上の窒化シリコン膜を前記平行平板電極の表面に生成する窒化シリコン薄膜形成工程とを有することを特徴とするプラズマCVD成膜方法。
In a plasma CVD film forming method in which discharge is performed with parallel plate electrodes and a silicon nitride thin film is formed on the surface of the substrate,
A thin film forming step of forming a silicon nitride thin film having a refractive index of less than 2.3 on the surface of the substrate;
After a certain amount of silicon nitride thin film is formed on the surface of the substrate, amorphous silicon (hereinafter a-Si) or a silicon nitride film having a refractive index of 2.3 or more is formed on the surface of the parallel plate electrode without the substrate. A plasma CVD film forming method comprising: forming a silicon nitride thin film forming step.
平行平板電極にて放電を行い、基板の表面に窒化シリコン薄膜を成膜するプラズマCVD装置において、
前記基板表面へ屈折率2.3未満の窒化シリコン薄膜を形成する薄膜形成手段と、
前記基板表面へ一定量の窒化シリコン薄膜を形成した後に、前記基板が無い状態で、アモルファスシリコン(a−Si)または屈折率2.3以上の窒化シリコン膜を前記平行平板電極の表面に生成する窒化シリコン薄膜形成手段とを備えたことを特徴とするプラズマCVD装置。
In a plasma CVD apparatus that discharges with parallel plate electrodes and forms a silicon nitride thin film on the surface of the substrate,
Thin film forming means for forming a silicon nitride thin film having a refractive index of less than 2.3 on the substrate surface;
After a certain amount of silicon nitride thin film is formed on the surface of the substrate, amorphous silicon (a-Si) or a silicon nitride film having a refractive index of 2.3 or more is formed on the surface of the parallel plate electrode without the substrate. A plasma CVD apparatus comprising: a silicon nitride thin film forming unit.
平行平板電極にて放電を行い、基板に絶縁性薄膜を成膜するプラズマCVD装置を用いる絶縁性薄膜の成膜方法であって、
前記基板に絶縁膜を成膜する絶縁膜成膜工程と、
前記平行平板電極の表面のメンテナンスが必要であるか否かを判断する判断工程と、
前記判断工程において前記メンテナンスが必要であると判断された場合に、前記基板が無い状態で前記平行平板電極の表面に導電膜を成膜する導電膜成膜工程とを備える絶縁性薄膜成膜方法。
A method of forming an insulating thin film using a plasma CVD apparatus that discharges with parallel plate electrodes and forms an insulating thin film on a substrate,
An insulating film forming step of forming an insulating film on the substrate;
A determination step of determining whether maintenance of the surface of the parallel plate electrode is necessary;
An insulating thin film forming method comprising: a conductive film forming step of forming a conductive film on a surface of the parallel plate electrode without the substrate when it is determined that the maintenance is necessary in the determining step .
請求項5に記載の絶縁性薄膜成膜方法において、
さらに、異常放電の発生を検出する異常放電発生検出工程を備え、
前記判断工程における前記メンテナンスが必要であるか否かの判断を、前記異常放電の発生の有無に基づいて行うことを特徴とする絶縁性薄膜成膜方法。
In the insulating thin film formation method according to claim 5,
Furthermore, an abnormal discharge occurrence detection process for detecting the occurrence of abnormal discharge is provided,
A method for forming an insulating thin film, comprising: determining whether or not the maintenance is necessary in the determining step based on whether or not the abnormal discharge has occurred.
請求項5に記載の絶縁性薄膜成膜方法において、
さらに、あらかじめ連続して行われる成膜処理の回数を設定する限界成膜回数設定工程を備え、
前記判断工程における前記メンテナンスが必要であるか否かの判断を、前記限界成膜回数設定工程において設定された限界成膜回数の到達により行うことを特徴とする絶縁性薄膜成膜方法。
In the insulating thin film formation method according to claim 5,
Furthermore, a limit film formation number setting step for setting the number of film formation processes performed continuously in advance is provided,
An insulating thin film forming method, wherein the determination in the determining step whether or not the maintenance is necessary is performed by reaching a limit film forming number set in the limit film forming number setting step.
請求項5に記載の絶縁性薄膜成膜方法において、
さらに、絶縁膜の膜厚検査工程を備え、
前記判断工程における前記メンテナンスが必要であるか否かの判断を、前記膜厚検査工程において設定された膜厚の到達により行うことを特徴とする絶縁性薄膜成膜方法。
In the insulating thin film formation method according to claim 5,
In addition, the film thickness inspection process of the insulating film,
A method for forming an insulating thin film, comprising: determining whether the maintenance in the determining step is necessary or not by reaching a film thickness set in the film thickness inspection step.
請求項6に記載の絶縁性薄膜成膜方法において、
前記絶縁膜成膜工程と、前記異常放電発生検出工程と、前記導電膜成膜工程とを繰り返すことを特徴とする絶縁性薄膜成膜方法。
The insulating thin film formation method according to claim 6,
An insulating thin film forming method comprising repeating the insulating film forming step, the abnormal discharge occurrence detecting step, and the conductive film forming step.
請求項5〜9のいずれか一項に記載の絶縁性薄膜成膜方法において、
前記絶縁性薄膜は屈折率2.3未満のSiN膜であり、前記導電膜はa−Si膜または屈折率2.3以上のSiN膜であることを特徴とする絶縁性薄膜成膜方法。
In the insulating thin film formation method according to any one of claims 5 to 9,
The insulating thin film forming method, wherein the insulating thin film is a SiN film having a refractive index of less than 2.3, and the conductive film is an a-Si film or a SiN film having a refractive index of 2.3 or more.
JP2009285599A 2009-12-16 2009-12-16 Plasma cvd device Pending JP2011127168A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2009285599A JP2011127168A (en) 2009-12-16 2009-12-16 Plasma cvd device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2009285599A JP2011127168A (en) 2009-12-16 2009-12-16 Plasma cvd device

Publications (1)

Publication Number Publication Date
JP2011127168A true JP2011127168A (en) 2011-06-30

Family

ID=44290072

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2009285599A Pending JP2011127168A (en) 2009-12-16 2009-12-16 Plasma cvd device

Country Status (1)

Country Link
JP (1) JP2011127168A (en)

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0750413A (en) * 1993-03-31 1995-02-21 Siliconix Inc High-voltage semiconductor structure and preparation thereof
JPH0982647A (en) * 1995-09-20 1997-03-28 Sanyo Electric Co Ltd Tray for semiconductor thin-film manufacturing device
JP2001102196A (en) * 1999-09-29 2001-04-13 Hitachi Kokusai Electric Inc Plasma treatment apparatus
JP2004266147A (en) * 2003-03-03 2004-09-24 Kawasaki Microelectronics Kk Method for cleaning plasma processing apparatus and susceptor for plasma processing apparatus
JP2005276060A (en) * 2004-03-26 2005-10-06 Matsushita Electric Ind Co Ltd Management device and method for semiconductor manufacturing equipment
JP2007262480A (en) * 2006-03-28 2007-10-11 Shin Meiwa Ind Co Ltd Vacuum film deposition apparatus and film deposition method
JP2009135253A (en) * 2007-11-30 2009-06-18 Panasonic Corp Plasma treating device, and plasma treating method

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0750413A (en) * 1993-03-31 1995-02-21 Siliconix Inc High-voltage semiconductor structure and preparation thereof
JPH0982647A (en) * 1995-09-20 1997-03-28 Sanyo Electric Co Ltd Tray for semiconductor thin-film manufacturing device
JP2001102196A (en) * 1999-09-29 2001-04-13 Hitachi Kokusai Electric Inc Plasma treatment apparatus
JP2004266147A (en) * 2003-03-03 2004-09-24 Kawasaki Microelectronics Kk Method for cleaning plasma processing apparatus and susceptor for plasma processing apparatus
JP2005276060A (en) * 2004-03-26 2005-10-06 Matsushita Electric Ind Co Ltd Management device and method for semiconductor manufacturing equipment
JP2007262480A (en) * 2006-03-28 2007-10-11 Shin Meiwa Ind Co Ltd Vacuum film deposition apparatus and film deposition method
JP2009135253A (en) * 2007-11-30 2009-06-18 Panasonic Corp Plasma treating device, and plasma treating method

Similar Documents

Publication Publication Date Title
JP6386519B2 (en) CVD apparatus and method of manufacturing CVD film
JP4121269B2 (en) Plasma CVD apparatus and method for performing self-cleaning
US10679831B2 (en) Substrate processing apparatus, method of manufacturing semiconductor device and non-transitory computer-readable recording medium
US7588036B2 (en) Chamber clean method using remote and in situ plasma cleaning systems
US9765430B2 (en) Plasma processing apparatus and film formation method
JP4714166B2 (en) Substrate plasma processing apparatus and plasma processing method
WO1999019537A9 (en) Dual frequency excitation of plasma for film deposition
JP2011508434A (en) Silicon nitride film with low wet etching rate
US20120180810A1 (en) Cleaning of a process chamber
TWI429782B (en) Plasma film-forming method and plasma cvd device
JP7419343B2 (en) Method and apparatus for low particle plasma etching
JP2020129696A (en) Substrate processing apparatus, plasma flicker determination method, plasma abnormality determination method, semiconductor device manufacturing method, and program
US20200058539A1 (en) Coating material for processing chambers
TW307027B (en) Process for reducing circuit damage during pecvd in single wafer pecvd system
JP2008205279A (en) Method and device for depositing silicon-based thin film
TW201933496A (en) Oxidation resistant protective layer in chamber conditioning
TW201308431A (en) Integrated process modulation for PSG gapfill
KR100755116B1 (en) Method for fabricating pecvd silicon nitride
US11699577B2 (en) Treatment for high-temperature cleans
JP2011127168A (en) Plasma cvd device
US20220270858A1 (en) Methods of tuning to improve plasma stability
JP2003059840A (en) Apparatus and method for plasma treatment
US20220020589A1 (en) Dielectric coating for deposition chamber
US11145504B2 (en) Method of forming film stacks with reduced defects
JP2008244389A (en) Vacuum treatment apparatus, vacuum treatment method, and plasma cvd method

Legal Events

Date Code Title Description
A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20120222

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20130627

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20130702

A02 Decision of refusal

Free format text: JAPANESE INTERMEDIATE CODE: A02

Effective date: 20131029