JP2011124838A - Semiconductor storage device and delay time control method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To perform delay time control at high speed, and to improve performance. <P>SOLUTION: A temperature sensor S1 detects a temperature to be outputted as temperature information. A TAP holding circuit S2 locks a DLL circuit S4 within a use temperature range at a preliminarily used frequency and a voltage state, and holds the lock state of the DLL circuit S4 as initial delay time information by being associated with an occasional temperature detected by the temperature sensor S1, When actually used, the DLL circuit S4 reads the initial delay time information to the temperature generated by the temperature sensor S1 when delay time control is started from the TAP holding circuit S2, and starts the delay time on the basis of its lock information. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a semiconductor memory device and a delay time control method using a DLL (Delay Locked Loop).

  In a semiconductor memory device such as an SDRAM having a DLL, the DLL limits the delay time of an internal clock used inside the semiconductor memory device with respect to a reference clock (CLK) supplied from the outside to be within a predetermined range. In order to change the delay time from a state outside the predetermined range (unlocked state) to a locked state within the predetermined range, the lock-in time (synchronous) corresponding to several hundreds of clock cycles is usually used. Pull-in time) is required (see, for example, Patent Document 1).

This DLL locking operation is often stipulated to be performed every time after entering the self-refresh operation state.
This is because during the self-refresh operation period, it is necessary to reduce the power consumption, and generally the operation of the DLL is also stopped. For this reason, the semiconductor memory device is reduced in power consumption, so that heat generation due to internal loss is reduced and temperature is lowered. Thus, when the amount of change in temperature is large across the self-refresh operation period, the dynamic characteristics of the active elements constituting the circuit change. This is because the delay time of the signal changes due to the temperature change, so that the lock state held in the DLL is different from the value suitable for the actual operation.

JP-A-8-226957

  However, in the semiconductor memory device having a DLL according to the prior art, as described above, the DLL holds the delay time of the internal clock within a predetermined range with respect to the reference CLK supplied from the outside. Usually, a lock-in time corresponding to several hundreds of clock cycles is required. Until the lock-in time elapses, it is not compensated whether the delay time of the internal clock is included in the predetermined range. Therefore, the delay time of the reference clock and the internal clock supplied from the outside is included in the predetermined range. As a result, it is impossible to perform a read function which requires that synchronization be ensured, and there is a problem that performance is deteriorated.

  In order to solve the above-described problem, the present invention provides a DLL unit that controls a delay time of an internal clock signal synchronized with an external clock signal supplied from the outside, and stores initial delay time information corresponding to a use temperature. The delay time control is started on the basis of the initial delay time information corresponding to the temperature at the start of the delay time control operation.

  According to the present invention, the initial delay time information corresponding to the use temperature is held, and when the delay time control is started by the DLL unit, the initial delay time held corresponding to the temperature at the start of the delay time control. Since the delay time control by the DLL unit is started based on the information, the lock operation can be performed at a high speed and the system performance can be improved.

1 is a block diagram showing a configuration of an SDRAM in which a DLL according to an embodiment of the present invention is used. It is a circuit diagram which shows the structure of the DLL lock information acquisition and selection function by a temperature sensor by this embodiment. It is a circuit diagram which shows the structural example of temperature sensor circuit S1 by this embodiment. FIG. 4 is a circuit diagram showing a configuration example of a TAP holding circuit S2 according to the present embodiment. It is a circuit diagram which shows the structural example of TAP transfer circuit S3 by this embodiment. It is a circuit diagram showing an example of composition of DLL circuit S4 by this embodiment. FIG. 5 is a circuit diagram illustrating a configuration example of a TAP holding circuit Dk (k = 1 to m) in FIG. 4. FIG. 8 is a circuit diagram showing a configuration example of a TAP storage control circuit F2 in the TAP holding circuit Dk of FIG. FIG. 9 is a circuit diagram showing a configuration example of level shifters H4 and H10 in the TAP storage control circuit F2 of FIG. 4 is a timing diagram for explaining the operation of the DLL in the semiconductor memory device according to the present embodiment. 5 is a timing diagram for explaining the operation of the DLL according to the present embodiment.

Hereinafter, an embodiment of the present invention will be described with reference to the drawings.
In a system using a semiconductor memory device having a DLL, the frequency and power supply voltage of the clock used can be handled as manageable information. Therefore, the factor that cannot be managed among the conditions affecting the lock information (TAP) that determines the lock state of the DLL due to other factors is the temperature.
If the TAP information that changes in accordance with the temperature is obtained in advance by some means, the DLL locks the DLL based on the information obtained by the above means by using the temperature lock information (TAP) at the time of the DLL reset. By starting the operation, the lock-in time can be shortened and the lock can be performed at a very high speed. This shortening of the lock-in time reduces the time for limiting the function operation and can improve the performance.

Therefore, the operating temperature is detected by providing a temperature sensor with a temperature detection range of α ° C. step inside the semiconductor memory device. Further, in order to determine the initial state, the DLL is locked at a predetermined use temperature within the use temperature range under the condition of the frequency and the power supply voltage used in advance in the system. Also, the operating temperature is changed within the operating temperature range, and the DLL lock state when the temperature sensor detects a transition of α ° C. is held in the register as initial delay time control information. Then, after the DLL lock information (TAP) in the temperature detection accuracy in the α ° C. step is held in the operating temperature range, the information is stored by an electric fuse or the like.
In actual use in the system, the DLL operation is performed based on the stored lock information (initial delay time control information) of the DLL. That is, the DLL lock information (TAP) corresponding to the temperature at the start of the lock is read from the data stored in the electric fuse or the like according to the temperature detected by the temperature sensor, and the DLL lock is performed based on the lock information. Start operation. By doing so, the locking operation can be made very fast. Therefore, it is possible to reduce the performance degradation, which is a conventional problem.

  FIG. 1 is a block diagram showing a configuration of an SDRAM in which a DLL according to an embodiment of the present invention is used. In FIG. 1, reference numeral 2 is a clock generator, 3 is a command decoder, 4 is a mode register, and 5 is a control circuit. 6 is a row address buffer & refresh counter, and 7 is a column address counter & burst counter. 8 is a row decoder, 9 is a column decoder, 10 is a memory cell array, and 11 is a sense amplifier. 12 is a data control circuit, 13 is a latch circuit, 14 is an input / output buffer, and 15 is a DLL (Delay Locked Loop).

Next, RI is an internal Read command obtained by decoding external commands, / CS, / RAS, / CAS, / WE. The PCLK signal and the ICLK signal are clock signals having a certain delay time with respect to the external clock CK. The command RI is read into the control circuit 5 by the internal clock PCLK and supplied as the RP signal to the data control circuit 12 and the latch circuit 13, and the TAPTR signal, the TSTORE signal, the DLLRST signal, and the DLLEN signal are supplied to the DLL 15.
The DLL 15 generates an LCLK signal that is a clock signal in which a delay time with respect to the ICLK signal is controlled according to the TAPTR signal, the TSTORE signal, the DLLRST signal, and the DLLEN signal that are control signals for controlling the DLL 15, and the latch circuit 13 Output to the input / output buffer 14.

FIG. 2 is a circuit diagram showing the configuration of the DLL lock information acquisition and selection function by the temperature sensor according to the present embodiment.
The temperature sensor S1 shown in this figure detects the temperature of the device based on the detection accuracy of the α ° C. step in the actual use temperature range. The temperature information of the detected device is generated as an m-bit TEMP <m: 1> signal. The TEMP <m: 1> signal is supplied to the TAP holding circuit S2.
The TAP holding circuit S2 holds and outputs DLL lock information (TAP) corresponding to the temperature information of the TEMP <m: 1> signal output from the temperature sensor S1. The lock information (TAP) is supplied to the TAP transfer circuit S3 as a TAPL <n: 1> signal. There are n TAP transfer circuits S3, and DLL lock information (TAP) is transferred between the TAP holding circuit S2 and the DLL circuit S4 connected thereto. The lock information (TAP) is exchanged between the TAP transfer circuit S3 and the DLL circuit S4 as a TAPDLL <n: 1> signal.

  Here, the TAPDL <n: 1> signal is a signal held as a signal of a latch part such as a flip-flop in the DLL in the locked state, and is output to the outside as lock information. The data is rewritten according to (drive), and the lock information in the DLL is also rewritten. Therefore, the TAPDL <n: 1> signal that is the DLL lock information signal of the DLL circuit S4 is also an input signal to the TAP transfer circuit S3.

  The TAPTR signal is a signal set by an external command such as MRS (mode register set). Whether the lock information (TAP) held in the DLL circuit S4 is transferred to the TAP holding circuit S2 side or the lock information (TAP) held in the TAP information holding circuit S2 is transferred to the DLL circuit S4 side by this signal Select. The TAPTR signal is input to the TAP holding circuit S2 and the TAP transfer circuit S3, and transferred by controlling the TAP transfer circuit S3 that mediates transfer between the DLL circuit S4 and the TAP holding circuit S2.

The TSTORE signal is set by an external command such as MRS and is supplied as a signal for causing the TAP holding circuit S2 to hold TAP information.
The DLLRST signal is a signal set by an external command such as MRS, and is a signal for resetting the DLL circuit S4 and is supplied to the TAP transfer circuit S3 and the DLL circuit S4.
The DLLEN signal is set by an external command such as MRS, and is a signal for enabling the DLL circuit S4, and is supplied to the TAP holding circuit S2 and the DLL circuit S4.
The ICLK signal is a reference clock supplied to the DLL circuit S4, and is supplied as a target for delay adjustment.
When the DLLRST signal is asserted after the DLLEN signal is asserted and the DLL circuit S4 is enabled, the LCLK signal starts the locking operation of the DLL circuit S4 and then the clock signal of the DLL circuit S4. Is output as

  FIG. 3 is a circuit diagram showing a configuration example of the temperature sensor circuit S1 according to the present embodiment. In FIG. 3, the series resistance unit T <b> 1 includes k resistors connected in series between the power supply VINT that is a constant voltage and the GND level.

  The temperature-dependent level generation unit T2 includes a constant current source L1 that uses the power source VIND as a current source, and a diode L2 that is connected between the constant current source L1 and GND. The temperature dependence level generation unit T2 is set so as to exhibit a linear negative voltage dependence with respect to the temperature, and the output level of the VREFT signal changes according to the detected temperature change.

  The differential amplifier circuit group T3 differentially amplifies the output level of the VREFT signal as a reference potential (reference) with respect to the level of the VIN <t> signal (t = 1 to m) output from the series resistance unit T1, It consists of m differential amplifier circuits that output as TEMPC <t> signals (t = 1 to m).

The temperature range pulse generator T4 is supplied with the TEMPC <t + 1> signal from the differential amplifier circuit group T3, outputs the TPB <t> signal, the inverter At (t = 1 to m), and the TEMPC <t> signal. A TPB <t> signal is supplied and a two-input AND circuit Bt (t = 1 to m) that outputs a TEMP <t> signal. However, the input of the inverter Am is connected to the GND potential.
An output signal as a temperature sensor circuit in the temperature range pulse generation unit T4 is a TEMP <m: 1> signal.

FIG. 4 is a circuit diagram showing a configuration example of the TAP holding circuit S2 according to the present embodiment.
The TAP holding circuit S2 shown in this figure includes a TAP holding circuit group E1, and the TAP holding circuit group E1 has a plurality of TAP holding circuits Dk (k = 1 to m). The TAP holding circuit Dk controls the input / output of the DLL lock information TAPL <n: 1> signal according to the temperature state detected with the detection accuracy of the α ° C. step. It is provided according to the number of divisions indicating the divided temperature state. This figure shows a case where the operating temperature range is divided into m. For example, when -5 ° C to 90 ° C is used, and the lock information (TAP) of DLL is held according to the temperature state divided by the step width of 5 ° C, 20 TAPs are held. A circuit Dm (m = 20) is required.

  Each TAP holding circuit Dk has commands such as a TEMP <m: 1> signal (ie, TEMP <k> (k = 1 to m)), a DLLEN signal, an external MRS, and the like output from the temperature sensor circuit S1 of FIG. In order to fix the data by the TAPTR signal, which is a signal for selecting whether to capture the TAPL <n: 1> signal, which is the lock information from the DLL circuit S4, or to output to the DLL side, and the electric fuse, etc. The TSTORE signal is input as an input signal.

  FIG. 5 is a circuit diagram showing a configuration example of the TAP transfer circuit S3 according to the present embodiment. In FIG. 5, an inverter E1 receives a TAPL <s> signal and outputs a TAPTB signal. The inverter E2 receives the TAPTB signal and outputs a TAPL <s> signal. When the TAPTB signal is input and the DLLRSTB signal is asserted, the clocked inverter E3 sets the output to an enable state, and when the DLLRST signal is asserted, the clocked inverter E3 outputs the TAPDLL <s> signal.

  The inverter E4 receives the DLLRST signal and outputs a DLLRSTB signal. The inverter E5 receives the TAPDLL <s> signal and outputs a TAPDB signal. The inverter E6 receives the TAPDB signal and outputs a TAPDL <s> signal. When the TAPDB signal is input and the TAPTRB signal is asserted, the clocked inverter E7 sets the output to an enable state, and when the TAPTR signal is asserted, the clocked inverter E7 outputs a TAPL <s> signal. The inverter E8 receives the TAPTR signal and outputs a TAPTRB signal.

  FIG. 6 is a circuit diagram showing a configuration example of the DLL circuit S4 according to the present embodiment. In FIG. 6, the delay adjustment circuit G1 inputs and outputs a TAPDLL <n: 1> signal that is lock information (TAP), an ICLK signal that is a lock delay operation adjustment target signal, and a DLLEN signal that is a DLL enable signal. , A DLLRST signal as a reset signal for initializing the DLL and a PCCTRL signal as a phase comparison result are input. Then, the delay adjustment circuit G1 outputs the DCLK signal whose delay time is adjusted with respect to the ICLK signal and the LCLK signal adjusted so as to be output earlier than the DCLK signal by a fixed time. The phase comparison circuit G2 compares the phases of the ICLK signal and the DCLK signal output from the delay adjustment circuit G1, and outputs the comparison result as a PCCTRL signal.

FIG. 7 is a circuit diagram showing a configuration example of the TAP holding circuit Dk (k = 1 to m) of FIG.
The TAP holding circuit Dk shown in this figure includes a set of a plurality of flip-flops F1 and a TAP storage control circuit F2 provided correspondingly.
The flip-flop F1 includes n flip-flops, and is supplied with the TEMP signal as a clock (CK) and each of the TAPL <n: 1> signals as data (D). The flip-flop F1 outputs the data (D) captured during the period when the clock CK is at the “L” level as the output signal (Q) during the period when the clock (CK) is at the “H” level. The output signals Q are output as LTAP <n: 1> signals, respectively.

  The TAP storage control circuit F2 includes n TAP storage control circuits, and is supplied with a DLLEN signal, which is a DLL enable signal, the TAPTR signal, the TEMPT signal, and the TSTORE signal. The TAP storage control circuit F2 receives the LTAP <n: 1> signal from the flip-flop F1 as an LTAP <s> signal, and uses the TAPL <s> signal as a TAPL <n: 1> signal according to conditions. Output.

  FIG. 8 is a circuit diagram showing a configuration example of the TAP storage control circuit F2 in the TAP holding circuit Dk of FIG. The inverter H1 is supplied with the TSTORE signal and outputs the TSTRB signal. The 2-input NOR circuit H2 is supplied with the TSTRB signal and the LTAP <s> signal, and outputs an inverted output of these logical sums as the EFENPB signal. The 2-input NAND circuit H3 is supplied with the LTAP <s> signal and the TSTORE signal, and outputs an inverted output of these logical products as a TAPSTB signal.

  The level shifter H4 is supplied with the TAPSTB signal and outputs a TAPSTSV signal obtained by converting the signal potential. The buffer H5 is supplied with the EFENPB signal and outputs the EFENB signal. In the PMOS transistor H6, the TAPSTSV signal is supplied to the gate, and the VSVT power supply is applied to the source. In the NMOS transistor H7, the EFENB signal is supplied to the gate, the GND potential is applied to the source, the drain is connected to the drain of the PMOS transistor H6, and the drain output is output as the EFTAP signal. In the breakdown insulating film H8, one electrode is applied with the GND potential, and the other electrode is connected to the transmission path of the EFTAP signal.

  The buffer H9 is supplied with the TSTORE signal and outputs a TSTBF signal. The level shifter H10 is supplied with the TSTBF signal and outputs a TSTTRB signal obtained by converting the signal potential. The inverter H11 is supplied with the TSTTRB signal, inverts it, and outputs it as the TSTTR signal. The transfer gate H12 is supplied with the EFTAP signal, the gate of the PMOS is supplied with the TSTTRB signal, the gate of the NMOS is supplied with the TSTTR signal, and the TSTTRB signal is also enabled in response to the assertion and outputs the TAPLB signal.

The delay element H13 is supplied with the DLLEN signal, delays the DLLEN signal, and outputs it as a DENDL signal. The inverter H14 is supplied with the DENDL signal, inverts it, and outputs it as the DENDLB signal. The 2-input NAND circuit H15 is supplied with the DENDLB signal and the DLLEN signal, and outputs an inverted output of the logical product of them as an EFPREB signal. In the PMOS transistor H16, an EFPREB signal is supplied to the gate, a VDD power supply voltage is applied to the source, and a drain is connected to the transmission path of the TAPLB signal.
The inverter H17 is supplied with the TAPLB signal, inverts it, and outputs it as a TAPLL signal. The inverter H18 is supplied with the TAPLL signal, inverts it, and outputs it as a TAPLB signal.

The inverter H19 is supplied with the TAPTR signal, inverts it, and outputs it as a TAPBTR signal. The 2-input AND circuit H20 is supplied with the TAPBTR signal and the TEMPT signal, takes a logical product of them, and outputs it as a TAPSEL signal.
The inverter H21 is supplied with the TAPSEL signal, inverts it, and outputs it as a TAPSELB signal. In the PMOS transistor H22, the TAPSELB signal is supplied to the gate, and the VDD power supply voltage is applied to the source. The PMOS transistor H23 has a gate supplied with a TAPLB signal and a source connected to the drain of the PMOS transistor H22.

In the NMOS transistor H25, a TAPSEL signal is supplied to the gate, the GND potential is applied to the source, and the drain is connected to the source of the NMOS transistor H24.
The NMOS transistor H24 has a gate supplied with a TAPLB signal, a source connected to the drain of the NMOS transistor H25, a drain connected to the drain of the PMOS transistor H23, and outputs a TAPL <s> signal.

FIG. 9 is a circuit diagram showing a configuration example of the level shifters H4 and H10 in the TAP storage control circuit F2 of FIG.
In the PMOS transistors P3 and P5 shown in this figure, the VSVT power supply voltage is applied to the respective sources, and the gates are connected to the respective drains. That is, the PMOS transistors P3 and P5 form a holding circuit that stores a pair of complementary states.
The inverter P1 is supplied with the IN signal, inverts it, and outputs it as the INB signal.
In the NMOS transistor P2, the IN signal is supplied to the gate, the GND potential is applied to the source, and the drain is connected to the drain of the PMOS transistor P3.
In the NMOS transistor P4, the INB signal is supplied to the gate, the GND potential is applied to the source, and the drain is connected to the drain of the PMOS transistor P5. Then, an OUT signal is output from the drain of the NMOS transistor P4 in accordance with the supplied IN signal.

Next, the operation of this embodiment will be described.
FIG. 10 is a timing diagram for explaining the operation of the DLL in the semiconductor memory device according to the present embodiment.
In this figure, as a timing diagram for retaining and fixing DLL lock information in the α ° C temperature step, the DLL 15 is locked at the operating frequency and power supply voltage in the actual use system, and the actual use temperature range 3 shows an operation in accordance with a series of processes in which the lock information (TAP) of the DLL 15 acquired at the α ° C. step is fixed by the electric fuse while the temperature is increased from a low temperature.

  In this step, after the DLL 15 is operated by the MRS and the DLL 15 signal by the DLL RST signal, the TAPTR signal is set to the “H” level by a command such as an external MRS. Thereafter, the temperature is increased from the low temperature side of the actual use temperature range to the high temperature side of the actual use temperature range. First, in the temperature dependence level generation unit T2 that performs detection using the temperature dependence of the diode L2 (FIG. 3), the current Id flowing through the diode L2 is constant current controlled by the constant current source L1 and becomes a constant value. When the voltage level of the anode contact VREFT of the diode L2 is Vd0 when the temperature is T0K (Kelvin), the current Id is generally expressed by Expression (1).

  Id = A × e ((q × Vd0−Eg) / k × T0) (1)

  In equation (1), A is a proportional constant indicating a constant value, q is an elementary charge amount, k is a Boltzmann constant, Eg is band gap energy, and e (x) is a function indicating the power of the base e of the natural logarithm. It is. Here, when the amount of change of the anode contact VREFT when the temperature changes by ΔT ° C. is ΔVd, it is expressed by Expression (2).

  Id = A × e ((q × (Vd0 + ΔVd) −Eg) / k × (T0 + ΔT)) (2)

  Since the current Id is constant current controlled without being dependent on the temperature change and is constant, the exponents of the equations (1) and (2) are equal, and therefore, expressed as the equation (3).

  (Q × Vd0−Eg) / k × T0 = (q × (Vd0 + ΔVd) −Eg) / k × (T0 + ΔT) (3)

  When formula (3) is arranged with respect to ΔVd, formula (4) is obtained.

  ΔVd = −ΔT × (Eg / q−Vd0) / T0 (4)

  Note that (Eg / q) indicates a band gap voltage, which is about 1.2 V when silicon is used as a material.

  When silicon is used, it can be seen that the voltage change amount ΔVd with respect to the temperature change of ΔT ° C. has a negative proportional relationship with the temperature change amount ΔT if Vd0 is 1.2 V or less. From this relationship, the output level of the VIN <t> (t = 1 to m) signal output from the series resistance unit T1 (FIG. 3) and the signal VREFT that is the output of the temperature dependent level generation unit T2 by the diode L2. The resistance value of the series resistor T1 is adjusted so that the level of the α ° C. step in the operating temperature range matches.

  As a result, the level of the signal VREFT output from the temperature dependent level generation unit T2 decreases as the temperature rises, so VIN <t> (t = 1 to m) output from the series resistance groups R1 to Rk. On the other hand, when the level of the signal VREFT is determined by the differential amplifier circuit group T3, the TEMPC <m> signal transitions to the “H” level when a predetermined temperature is reached in response to the temperature rise.

  Therefore, the TEMPC <t> (t = 1 to m) signal group corresponds to the temperature rise as shown in FIG. 10, and is in the “H” level state in the order from the TEMPC <1> signal to the TEMPC <m> signal. The number of signals indicating the “H” level state increases. Due to this transition, the output TEMP <t> signal of the two-input AND circuits B1 to Bm of the temperature range pulse generation unit T4 transitions from the “L” level to the “H” level, and the next TEMPC < Since the t + 1> signal is still in the “L” level, the TPB <t> signal changes to the “H” level. When the next TEMPC <t + 1> signal changes from “L” level to “H” level, the TPB <t> signal changes from “H” level to “L” level (when t = m, TEMP The <t> signal only transitions to the “H” level because the TEMPC <t + 1> signal is applied with the GND potential).

  Thereby, the TEMP <t> signal can indicate the detected temperature state according to the detection accuracy of the α ° C. step. Here, the TAPDL <s> signal as the lock information (TAP) output from the DLL circuit S4 in FIG. 5 indicates the lock state in the DLL circuit S4, and values corresponding to the state are latched by the inverters E5 and E6. ing. In this latched TAPDB data, since the TAPTR signal is at the “H” level, the TAPTRB signal is at the “L” level, the output of the clocked inverter E7 is in the enable state, the TAPDB signal is inverted, and TAPL <s > Output as a signal.

  This TAPL <s> signal is latched by inverters E1 and E2. At this time, since the DLLRST signal is at the “L” level, the DLLRSTB signal is at “H”, and the clocked inverter E3 is in the disabled state, so that the exchange from the TAPL <s> side to the TAPDLL <s> side is performed. There is no. Therefore, according to the configuration example of the TAP transfer circuit S3 in FIG. 5, the TAPDLL <n: 1> signal, which is n-bit DLL lock information (TAP), is output as a TAPL <n: 1> signal.

  The TAPDLL <n: 1> signal, which is the lock information (TAP) of the DLL, changes according to the change in the delay time of the transistor depending on the temperature change. In FIGS. 10 and 11, the value of the changing TAPDLL <n: 1> signal is shown in lower case alphabets. At the transition from the “L” level to the “H” level of the TEMP signal, the n flip-flops F1 in FIG. 7 have TAPDLL <n: 1 which is lock information (TAP) from the DLL circuit S4 in FIG. > Latches the data held as the TAPL <n: 1> signal and holds it as the LTAP <n: 1> signal.

  The LTAP <n: 1> signal is supplied to the TAP holding circuits D1 to Dm in the TAP holding circuit group E1 in the configuration example of the TAP holding circuit S2 in FIG. ), The information of the TAPL <n: 1> signal at the time of the transition is latched by the respective TAP holding circuits D1 to Dm, and LTAP <n: 1. > Hold as a signal.

  10, the LTAP <n: 1> signal in the TAP holding circuit D1 in FIG. 4 holds the TAPL <n: 1> = b state, and the LTAP <n: 1> signal in the TAP holding circuit D2 in FIG. 4 holds the TAPL <n: 1> = e state, and the LTAP <n: 1> signal in the TAP holding circuit D3 of FIG. 4 holds the TAPL <n: 1> = h state. The TAPL <n: 1> = s state is held in the LTAP <n: 1> signal in the TAP holding circuit Dm-2, and the LTAP <n: 1> signal in the TAP holding circuit Dm-1 in FIG. The TAPL <n: 1> = v state is held, and the LTAP <n: 1> signal in the TAP holding circuit Dm in FIG. 4 shows the case where the TAPL <n: 1> = y state is held. .

  The DLL lock information (TAP) obtained for each α ° C. step is completed in response to the temperature rise within the actual use temperature range. After the acquisition of the lock information (TAP) is completed, a TSSTORE, which is a control signal generated by a command such as an external MRS for leaving the acquired lock information as fixed data in the electric fuse (breaking insulating film), is set to “ Set to “H” level.

As a result, in the TAP storage control circuit F2 of FIG. 7, the “H” level is supplied to the LTAP <n: 1> signal. Therefore, in the configuration example of the TAP storage control circuit F2 in FIG. 8, since the LTAP <s> signal is at the “H” level, the output of the 2-input NAND circuit H3 becomes the “L” level, and the level shifter H4 causes the TAPTSSV The signal becomes “L” level.
This is because, in the configuration example of the level shifter circuits H4 and H10 in FIG. 9, since the IN signal becomes “L” level, the INB signal becomes “H” level by the inverter P1, and the output OUT by the NMOS transistor P4 becomes OUT. Is caused to become “L” level.

  Next, since the TSTORE signal is at “H” level, the TSTRB signal is at “L” level, and the EFENPB signal that is the output of the 2-input NOR circuit H2 is “H” level because LTAP <s> is at “H” level. The EFENB signal inputted to the gate of the NMOS transistor H7 becomes “L” level. Therefore, the PMOS transistor H6 is turned on, the NMOS transistor H7 is turned off, and the VSTAP level to which the breakdown insulating film H8 is connected is applied with the VSVT level.

  Here, the breakdown insulating film H8 is not broken by applying a normal VDD level, but is broken by applying a level higher than the VDD level. Therefore, the VSVT level for destroying the breakdown insulating film H8 is set to a level higher than the VDD level necessary for destroying the breakdown insulating film H8 within a range not destroying the transistor. By applying the VSVT level to the EFTAP signal, the breakdown insulating film H8 is destroyed, and before the destruction, the insulating state with respect to the GND potential is changed to the conductive state, and the EFTAP signal is lowered to the GND potential. Connected with a resistor.

  At this time, the TSTBF signal becomes the “H” level, the TSTTRB signal becomes the “H” level of the VSVT level converted by the level shifter H10 (FIG. 8), and the TSTTR signal becomes the “L” level by the inverter H11. This is because, if the TSTTRB signal is set to the “H” level of the VSVT level in the configuration example of the level shifter circuit in FIG. 9, the IN signal is set to the “H” level. The NMOS transistor P4 is turned off, the NMOS transistor P2 is turned on, the INSVB signal is turned to "L" level, the PMOS transistor P5 is turned on, and the output OUT becomes "H" level of the VSVT level. by.

As a result, the transfer gate H12 shown in FIG. 8 enters the OFF state, blocks the applied VSVT level, and protects it from being applied to other elements outside the range where the application of the VSVT level is required.
On the other hand, a signal of “L” level is input to the LTAP <n: 1> signal. In the configuration example of the TAP storage control circuit F2 in FIG. 8, since the LTAP <s> signal is at the “L” level, the output of the 2-input NAND circuit H3 is at the “H” level. As in the case of the signal, the TAPSTSV signal becomes the “H” level of the VSVT level.

  Next, since the TSTORE signal is at “H” level, the TSTRB signal is at “L” level, and the EFENPB signal which is the output of the 2-input NOR circuit H2 is “L” because LTAP <s> is at “L” level. The EFENB signal input to the gate of the NMOS transistor H7 is set to the “H” level. Therefore, the PMOS transistor H6 is turned off, the NMOS transistor H7 is turned on, and the GND level is applied to the EFENB signal to which the breakdown insulating film H8 is connected. In this state, the breakdown insulating film H8 is not applied with a potential sufficient to destroy the insulating film and is not destroyed.

  Through the above steps, the DLL lock information (TAP) for each temperature detection range in the α ° C. step in the actual use temperature range is held depending on whether or not the breakdown insulating film H8 is broken. FIG. 10 shows a case where LTAP <s> corresponds to the TAP holding circuit D2 in FIG.

Next, FIG. 11 shows a timing diagram from the DLL reset to the locked state in actual use.
First, a DLLEN signal is generated by an external MRS (mode register set) command for enabling the DLL, and a DLLRST signal of 1 is output by an external MRS command for resetting the next input DLL. A shot signal is generated. In response to the DLLRST signal, the DLL is reset and the lock operation starts.

Upon receiving this DLLRST signal, only the TEMP <k> signal corresponding to the temperature state at that time becomes “H” level, and other than TEMP <k> has an exclusive relationship and becomes “L” level.
In the configuration example of the DLL TAP holding circuit S2 of FIG. 4, the TAP holding circuit Dk to which TEMP <k> is supplied as the “H” level is shown. The TEMP signal of the TAP holding circuit Dk (FIG. 8) corresponding to this case becomes “H” level.

  Here, since the TSTORE signal is at the “L” level, the TSTBF signal supplied to the level shifter H10 (FIG. 8) becomes the “L” level, the TSTRB signal output from the level shifter H10 becomes the “L” level, and the inverter H11 The TSTTR signal output from the “H” level becomes “H” level. Therefore, the transfer gate H12 is turned on. Further, the TSTRB signal becomes “H” level by the inverter H1, and since the TSTRB signal is “H” level in the 2-input NOR circuit H2, the EFENPB signal is output as “L” level, and the buffer H5 of this EFENPB signal is output. The EFENB signal through the signal also becomes “L” level.

  Since the TSTORE signal is also at the “L” level in the 2-input NAND circuit H3, the TAPSTB signal is output as the “H” level, and the output of the level shifter H4 becomes the “H” level of the VSVT level. Therefore, the PMOS transistor H6 and the NMOS transistor H7 are in an OFF state and do not enter an EFTAP signal. Since the TAPTR signal is also at the “L” level, the TAPBTR signal is at the “H” level and the TEMP signal is at the “H” level. Therefore, the TAPSEL signal that is the output of the 2-input AND circuit H20 is at the “H” level. Thus, the TAPSELB signal becomes “L” level by the inverter H21. Therefore, the TAPLB signal is output to the TAPL <s> signal as inverted logic.

  Here, the TAPLB signal is in the same state as the EFTAP signal because the transfer gate H12 is in the ON state. In this state, during the period in which the DLLEN signal is at the “L” level, the DENDL signal that is the output of the delay element H13 is at the “L” level, the DENDLB signal is at the “H” level, and the two inputs to which the DLLEN signal is input. The EFPREB signal, which is the output of the NAND circuit H15, becomes “H” level, and the PMOS transistor H16 for precharging the TAPLB signal is turned off.

  After that, when an external MRS (mode register set) command for enabling the DLL is supplied and the DLLEN signal becomes “H” level, the change of the DLLEN signal to the “H” level is transmitted to the DENDLB signal. Meanwhile, the EFPREB signal becomes “L” level, and the TAPLB signal can be precharged to “H” level. .

  At this time, when the breakdown insulating film H8 is destroyed, the EFTAP signal is in a state in which the GND potential is applied via a low resistance, so that the TAPLB portion via the transfer gate is also affected by the GND potential. As a result, the precharge by the PMOS transistor H16 does not become effective, the TAPLB signal becomes “L” level, the “L” level state is latched by the inverters H17 and H18, and the TAPL <s> signal has the “H” level. Is output.

  On the contrary, when the breakdown insulating film H8 is not destroyed, the EFTAP signal is in a state insulated from the GND potential, and the precharge by the PMOS transistor H16 becomes effective without being affected by the GND potential. The TAPLB signal becomes “H” level, the “H” level state is latched by the inverters H17 and H18, and the “L” level is output to the TAPL <s> signal.

  Here, in the TAP holding circuit to which the “L” level is supplied as the TEMP signal, the TAPSEL signal that is the output of the 2-input AND circuit H20 becomes the “L” level and the TAPSELB signal becomes the “H” level. The transistor H22 and the NMOS transistor H25 are turned off, and the output to the TAPL <s> signal is cut off.

  As the TAPL <s> signal, the signal from the TAP storage control circuit F2 that receives the “H” level supply as the TEMP <k> signal is supplied, so that it does not enter the floating state. In this way, the TAPL <n: 1> of the TAP holding circuit in which TEMP <k> is input at the “H” level is obtained from the TAPL <n: 1> signal.

  FIG. 11 shows a case where the TAPL <n: 1> = o state is obtained. Thereafter, a DLLRST signal is generated as a one-pulse signal by an external MRS command for resetting the DLL. Then, the DLLRSTB signal in FIG. 5 is set to “H” level by the inverter E4, and the output of the clocked inverter E3 is enabled. The TAPPTB signal outputs inverted data of the TAPL <s> signal by the inverter E1, and further outputs the same data as the TAPL <s> signal as the TAPDLL <s> signal by the clocked inverter E3.

  Here, since the TAPTR signal is at the “L” level, the TAPTRB signal is at the “H” level, and the output of the clocked inverter E7 is in an inactive disabled state (Disable), from the TAPDLL <s> side. Data exchange to the TAPL <s> side is not performed. In other words, the TAPL <s> signal is latched by the inverters E1 and E2, and the TAPDLL <s> signal is also latched by the inverters E5 and E6, and data is held.

  Here, as described above, the TAPDLL <s> signal is held by a latch portion such as a flip-flop in the DLL circuit S4 when the DLL is in a locked state. Further, the clocked inverter E3 periodically operates to change the state of a data latch contact such as a flip-flop holding the lock information (TAP) in the DLL circuit S4, and the held information is rewritten. Therefore, the data supplied as the TAPL <n: 1> signal is supplied as the TAPDL <n: 1> signal and taken in as lock information (TAP) in the DLL circuit S4.

  The DLL circuit S4 starts a locking operation based on the information of the captured TAPDLL <n: 1> signal. Here, since the TAPDLL <n: 1> signal which is the lock information (TAP) is the lock information (TAP) of the DLL circuit S4 acquired at the start of the lock operation and at a temperature within α ° C, The lock information (TAP) is very close to the lock information (TAP). Therefore, the locking operation can be completed very quickly.

FIG. 11 shows a process from the reset state of the DLL to the locked state by performing delay adjustment for every three cycles of the ICLK signal.
In the DLL delay adjustment shown in this figure, the lock information fetched as an initial state is TAPDLL <n: 1> = o.
Further, the result of comparison in the phase comparison circuit G2 between the DCLK signal output from the delay adjustment circuit G1 and the delay adjustment target signal ICLK in the configuration example of the DLL circuit S4 in FIG. 6 is the delay adjustment as the PCCTRL signal. Input to the circuit G1.
In the DLL circuit S4, if the PCCTRL signal is at “H” level, the delay amount is increased. If the PCCTRL signal is at “L” level, adjustment is performed according to the determination result of the DLL lock state so as to decrease the delay amount. .
In the determination of the DLL lock state, the state in which the PCCTRL signal changes from the “H” level to the “L” level or from the “L” level to the “H” level at the timing when the ICLK signal changes is determined as the DLL lock state. That is, a state where the timings at which both signals change coincide with each other is defined as a DLL lock state. As a result of the determination, the state that has reached the locked state with TAPDL <n: 1> = r is shown as lock information (TAP).

  In the conventional DLL lock operation, it is common to start the coarse adjustment from the initial state that is uniformly set inside, and then to perform the fine adjustment process, so several hundred cycles are required until the lock operation. However, according to the present embodiment, it is possible to perform a locking operation from an initial value in the vicinity of the locking state determined by the initial state set according to the temperature, and it is possible to complete the locking operation at high speed.

  According to the embodiment described above, in a semiconductor memory device having a DLL, when the frequency and voltage used in advance are known, the temperature information from the temperature sensor can be obtained, for example, in an α ° C. step. In this case, the lock information (TAP) of the locked state of the DLL in the unit of α ° C. is held and fixed, so that the lock information (TAP) of the DLL corresponding to the temperature during use is held in actual use. By reading from the data side and performing a locking operation from the TAP, a DLL locking operation is performed at high speed. As a result, the DLL can be locked at high speed, and the performance of the system can be increased accordingly.

15 DLL
S1 Temperature sensor S2 TAP holding circuit S3 TAP transfer circuit S4 DLL circuit T1 Series resistance unit T2 Temperature dependent level generation unit T3 Differential amplifier circuit T4 Temperature range pulse generation unit E1 Inverter D1 to Dm TAP holding circuit E1, E2, E4, E5 , E6 Inverter E3, E7 Clocked inverter G1 Delay adjustment circuit G2 Phase comparison circuit F1 Flip-flop F2 TAP memory control circuit H1, H11, H14, H17, H18, H19, H21 Inverter H2 NOR circuit H3 NAND circuit H4, H10 Level shifter H5 , H9 buffer H6 PMOS transistor H7 NMOS transistor H8 insulating film for breakdown H12 transfer gate H13 delay element H15 NAND circuit H16 transistor H20 AND circuits H22, H23 PMOS transistor H24, H25 NMOS transistor

Claims (8)

The DLL unit for controlling the delay time of the internal clock signal synchronized with the external clock signal supplied from the outside holds initial delay time information corresponding to the use temperature and corresponds to the temperature at the start of the delay time control operation. A semiconductor memory device, wherein delay time control is started based on the initial delay time information. The DLL unit is
A temperature detector that detects the operating temperature and generates temperature information;
A delay time information holding unit for holding the initial delay time information in a use temperature range corresponding to the fluctuation range of the use temperature;
A DLL circuit that starts delay time control based on the held initial delay time information corresponding to the temperature information generated by the temperature detection unit at the start of the delay time control. The semiconductor memory device according to claim 1. The DLL unit is
When not in use, when changing the temperature in a predetermined step from the low temperature side to the high temperature side of the operating temperature range, the delay time control information in the locked state in the DLL circuit obtained for each predetermined step, While transferring to the delay time information holding unit, the initial delay time held in the delay time information holding unit corresponding to the temperature information generated by the temperature detection unit at the start of the delay time control during actual use A transfer circuit for transferring information to the DLL circuit;
The delay time information holding unit
When not in use, the delay time information obtained by each of the predetermined steps transferred by the transfer circuit is held in correspondence with temperature information indicating the temperature of each step, and in the actual use, by the temperature detection unit. Supplying the initial delay time information according to the generated temperature information to the transfer circuit;
The semiconductor memory device according to claim 2. The temperature detector
A reference voltage generator for generating a reference voltage;
A temperature dependent voltage generator for generating a temperature dependent voltage;
A temperature information generating unit that outputs temperature information corresponding to the temperature of the memory element based on a difference between the reference voltage generated by the reference voltage generating unit and the temperature dependent voltage generated by the temperature dependent level generating unit; The semiconductor memory device according to claim 3, comprising: The DLL unit for controlling the delay time of the internal clock signal synchronized with the external clock signal input from the outside holds the initial delay time information corresponding to the use temperature, and corresponds to the temperature at the start of the delay time control. A delay time control method characterized by starting delay time control based on initial delay time information. Detecting the use temperature and generating temperature information;
Holding the initial delay time information in the use temperature range corresponding to the fluctuation range of the use temperature in association with temperature information indicating the temperature at that time;
The method further comprises the step of starting delay time control based on the stored initial delay time information corresponding to temperature information indicating a temperature at the start of delay time control by the DLL unit. 6. The delay time control method according to 5. The delay time in the locked state of the delay time control performed by the DLL unit, which is obtained for each predetermined step when the temperature is changed in a predetermined step from the low temperature side to the high temperature side of the use temperature range when not in use. Holding information as the initial delay time information in association with temperature information indicating the current temperature;
Selecting the initial delay time information according to the generated temperature information during actual use;
The DLL unit starts delay time control based on the transferred initial delay time information;
The delay time control method according to claim 6, further comprising: Generating a reference voltage;
Generating a temperature dependent voltage;
The delay time control method according to claim 7, further comprising: outputting temperature information indicating a temperature of the memory element based on a difference between the reference voltage and the temperature dependent voltage.

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