JP2011123088A - Liquid crystal display device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To secure a charging time for an auxiliary capacitor signal even when the number of scanning lines changes, and to restrain disturbance of an image to the utmost by satisfying requirements of polarity inversion of the auxiliary capacitor signal in continuous two frames in a multi-pixel type liquid crystal panel. <P>SOLUTION: Voltage is changed over in a voltage change-over pattern substantially balancing in holding period of two kinds of voltage levels in a video corresponding period W1 and a V-blank corresponding period W2, and auxiliary capacitor signals CS1-CS12 different in voltage level from that in the preceding frame are generated. The voltages of the auxiliary capacitor signals CS1-CS12 generated in a predetermined charging period immediately before the generation of a vertical synchronizing signal GSP of the next frame in the V-blank corresponding period W2 are fixed. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a liquid crystal display device including a liquid crystal panel in which two sets of liquid crystal electrodes capable of changing a potential after a pixel gradation signal is supplied as needed are provided for each pixel of an image.

In a liquid crystal display device, the viewing angle characteristic of a liquid crystal panel is an important quality item.
For example, Patent Document 1 discloses a liquid crystal panel (hereinafter, referred to as a multi-picture element type liquid crystal panel) in which two subpixels each having a different liquid crystal capacity are provided for each pixel of an image.
FIG. 2 is an equivalent circuit of one pixel portion g0 in the multi-picture element type liquid crystal panel disclosed in Patent Document 1.
In the multi-picture element type liquid crystal panel, a pixel display unit g0 provided for each pixel of an image has a first subpixel unit a0 and a second subpixel unit b0.
In addition, the two sub-pixel portions a0 and b0 in the pixel display portion g0 are portions where liquid crystal electrode pairs a1 and b1, auxiliary capacitors a2 and b2, and transistors a3 and b3 are individually provided.
The two pairs of liquid crystal electrodes a1 and b1 are electrode pairs (counter electrodes) that face each other with the liquid crystal layers a1 ′ and b1 ′ interposed therebetween. A liquid crystal capacitor is constituted by the liquid crystal electrode pairs a1 and b1 and the liquid crystal layers a1 ′ and b1 ′.
The two transistors a3 and b3 are connected to the grayscale signal of the pixel for each of the two pairs of liquid crystal electrodes a1 and b1 depending on whether or not a horizontal synchronization signal (gate clock signal GCK described later) is input for the effective scanning line. It is a switch part which switches supply presence or absence. The horizontal synchronizing signal is supplied to both transistors a3 and b3 through a scanning signal line HL provided for each effective scanning line. The gradation signal is supplied to both transistors a3 and b3 through a gradation signal line VL provided for each pixel group in one column in the vertical direction of the video.
In addition, the pair of auxiliary capacitors a2 and b2 has two sets of the liquid crystal electrode pairs a1 and b1 after the grayscale signal is supplied according to the voltage level of the auxiliary capacitor signal supplied through the bus signal line CSBL. It is a capacitor for changing each electric potential.
In the multi-picture element type liquid crystal panel, a pair of auxiliary capacitance signals having different voltage levels are periodically supplied to the pair of auxiliary capacitances a2 and b2 provided for each pixel. Supplied while changing. Accordingly, the potentials of the two pairs of liquid crystal electrodes a1 and b1 (the potentials of the respective liquid crystal capacitors) after the gradation signal (the signal of the voltage level corresponding to the gradation level of each pixel) is supplied are periodically generated. To change. As described above, the multi-picture element type liquid crystal panel divides one video pixel into two sub-pixels, and actively changes the luminance (potential of two liquid crystal capacitors) of the two sub-pixels. It realizes video output with excellent viewing angle characteristics.

By the way, in the multi-picture element type liquid crystal panel, one auxiliary capacitance signal is collectively supplied to one auxiliary capacitance a2 in each pixel on the scanning line for one line, and to the other auxiliary capacitance b2. The other one auxiliary capacity signal is supplied all at once.
FIG. 3 is a connection diagram of the main signal line CSL and the bus signal line CSBL, which are signal lines for transmitting auxiliary capacitance signals to the auxiliary capacitors a2 and b2.
The backbone signal line CSL is a set of signal lines including a plurality of pairs of signal lines to which a pair of auxiliary capacitance signals having different voltage levels are input. FIG. 3 shows an example of the multi-picture element type liquid crystal panel provided with twelve core signal lines CSL1 to CSL12. The main signal lines CSL1 and CSL2, CSL3 and CSL4, CSL5 and CSL6,. Each of these 6 pairs is a pair. Therefore, for example, when a high-level auxiliary capacitance signal is supplied to the first basic signal line CSL1 among the auxiliary capacitance signals of two types of high and low voltages, the second basic signal line CSL2 has a low level. An auxiliary capacitance signal is supplied. When a low level auxiliary capacitance signal is supplied to the first main signal line CSL1, a high level auxiliary capacitance signal is supplied to the second main signal line CSL2.

Further, the multi-picture element type liquid crystal panel is provided with a plurality of bus signal lines CSBL along each effective scanning line.
Then, for each pair of auxiliary capacitors a2 and b2 for one line on the effective scanning line, one of the pair of auxiliary capacitors a2 and b2 and one of the main signal lines CSL and the bus signal line CSBL Are electrically connected.

FIG. 10 is a time chart showing an example of a signal pattern of the conventional auxiliary capacitance signal supplied to the multi-picture element type liquid crystal panel shown in FIGS.
FIG. 10 shows a gate start pulse signal GSP that is a vertical synchronization signal, a gate clock signal GCK that is a horizontal synchronization signal, and auxiliary capacitance signals CS1 to CS12 supplied to each of the 12 core signal lines CSL1 to CSL12. A time chart is shown. Hereinafter, the period of the gate clock signal GCK (horizontal synchronization signal) is a unit of time, and the time of one period is expressed as 1H. The start pulse signal GSP and the gate clock signal GCK both detect a signal input (signal ON) when falling from a high level state to a low level state.
The example shown in FIG. 10 is a time chart of each signal in a time zone when the V blank period (non-video period) of a certain frame is switched to the video period of the next frame. The example shown in FIG. 10 is an example in which the number of effective scanning lines is 1080 and the total number of scanning lines is 1130 (that is, the number of ineffective scanning lines is 50).
As described above, the pair of auxiliary capacitance signals (CS1 and CS2, CS3 and CS4,..., CS11 and CS12) are signals having different voltage levels, and the voltage levels are periodically switched. ing. Hereinafter, regarding the auxiliary capacitance signals CS1 to CS12, the same voltage level is referred to as the same polarity, and the different voltage levels are referred to as different polarities.

In FIG. 10, the portion indicated by the elliptical broken line is the gate clock signal GCK (horizontal synchronization signal) in the scanning line where the auxiliary capacitors a2 and b2 to which the auxiliary capacitor signals CS1 to CS12 are supplied. ) Is turned on (a falling edge is detected). That is, at the time indicated by the elliptical broken line, the gradation signal is supplied to the liquid crystal electrode pair a1 and b1 on the scanning line where the supply destination (auxiliary points a2 and b2) of the auxiliary capacitance signal exists. . Hereinafter, the time when the elliptical broken line in each of the auxiliary capacitance signals CS1 to CS12 is marked is referred to as the liquid crystal operation start time.
For example, as shown in FIG. 3, the auxiliary capacitors a2 and b2 on the first to third (first to third lines) scanning lines are connected to the first and second core signal lines CSL1 and CSL2. Yes. Therefore, in the first and second auxiliary capacitance signals CS1 and CS2, the generation point of the first to third gate clock signals GCK after the generation of the gate start pulse signal GSP is the liquid crystal operation start point. Yes. In FIG. 10, t00 represents the generation time of the gate start pulse signal GSP, and t0 represents the generation time of the gate clock signal GCK for the first scanning line.

The auxiliary capacitors a2 and b2 require a certain charging time from when the auxiliary capacitor signals CS1 to CS12 are supplied until reaching the rated potential state. For example, when the frequency of the gate clock signal GCK is 120 Hz, the auxiliary capacitors a2 and b2 have a charging time of about 8H or more (the auxiliary capacitor signal until the potential state becomes 97% of the rated (full charge state). Supply duration).
Further, when the auxiliary capacitors a2 and b2, which are the supply destinations, are insufficiently charged at the liquid crystal operation start time in each of the auxiliary capacitance signals CS1 to CS12, the potentials of the liquid crystal electrode pairs a1 and b1 corresponding thereto. However, a potential failure state deviates from the assumed (design) potential. Then, the image is disturbed on the scanning line where the liquid crystal electrode pair a1 and b1 in the potential defect state exists.
Therefore, the auxiliary capacity signals CS1 to CS12 that complete the 97% charge in the time of 8H ideally have a period of 8H or more until the liquid crystal operation start point (the elliptical broken line portion), or at least It is desirable that the same polarity (voltage level is constant) is maintained for a period of 5H or more. Hereinafter, for each of the auxiliary capacity signals CS1 to CS12, the time during which the same polarity (voltage level is constant) until the liquid crystal operation start point (the elliptical broken line part) is reached is referred to as auxiliary capacity charging time. In the example shown in FIG. 10, the auxiliary capacity charging time of the auxiliary capacity signals CS1 and CS2 is 9H or more, the auxiliary capacity charging time of the auxiliary capacity signals CS3 to CS10 is 8H or more, and the auxiliary capacity signals CS11 and CS12 This is an example in which the auxiliary capacity charging time is secured for 20H or more.

In addition, in the same scanning line in two or more consecutive frames, when the polarity of the auxiliary capacitance signal at the time of starting the liquid crystal operation becomes the same polarity, the gradation between the scanning line and another scanning line is used. A difference in the light transmittance of the liquid crystal layer occurs more than the difference in signal level, which causes unevenness in image luminance.
Also, when the difference between the holding times of the two types of voltage levels in the auxiliary capacitance signals CS1 to CS12 is too large, that is, when the bias of the holding time in one of the two polarities is large, the auxiliary capacitance signal Disturbances in the image occur on the scanning lines to which CS1 to CS12 are supplied. Furthermore, if the time for maintaining the auxiliary capacitance signals CS1 to CS12 at one of the two polarities is too long, the liquid crystal layer may be damaged and lead to breakage.
As described above, the auxiliary capacity signals CS1 to CS12 are set so as to satisfy as much as possible the three requirements of balancing the holding time of two polarities, ensuring sufficient auxiliary capacity charging time, and polarity inversion in two consecutive frames. It is desirable.
The balancing of the holding times of the two polarities is a condition that the holding times of the two kinds of voltage levels (two polarities) are balanced.
The polarity inversion in the two consecutive frames is a condition that the polarities of the auxiliary capacitance signals CS1 to CS12 are not the same in the same scanning line in the two consecutive frames.

In the video signal, every time the gate start pulse GSP (vertical synchronization signal) is generated, the total number of scanning lines in one frame is determined. Here, since the number of effective scanning lines is fixed (for example, 1080), each time the gate start pulse GSP (vertical synchronization signal) is generated, the number of ineffective inspection lines in one frame may be determined. .
In the conventional liquid crystal display device having the multi-picture element type liquid crystal panel, every time a video signal of a new frame is input and the gate start pulse GSP is generated, the number of scanning lines of the current frame is 1 Under the assumption that the number of scanning lines in the previous frame is the same, the signal patterns (two polarity change patterns) of the auxiliary capacitance signals CS1 to CS12 are set so as to satisfy the three requirements as much as possible. It was.

That is, in the conventional liquid crystal display device, every time the gate start pulse signal GSP (vertical synchronization signal) is generated, the same number of the gate clock signals as the total number of effective scanning lines and ineffective scanning lines of the previous frame. The voltage switching patterns of the auxiliary capacitance signals CS1 to CS12 are set based on a period in which GCK (horizontal synchronization signal) is generated (hereinafter referred to as an all scanning line corresponding period).
The voltage switching pattern is a signal pattern in which holding periods of two types of voltage levels (two polarities) are balanced for each pair of the auxiliary capacitance signals in the scanning line corresponding period.
Here, from the predetermined starting point after the generation of the gate start pulse signal GSP (vertical synchronization signal), the same number of the gate clock signals GCK (horizontal synchronization signal) as the number of effective scanning lines of the previous frame is generated. The period is referred to as a video corresponding period W1.
Further, from the end of the video corresponding period W1, a period in which the same number of the gate clock signals GCK (horizontal synchronization signals) as the number of ineffective scanning lines of the previous frame is generated is a V blank corresponding period W2. Called.
Note that the starting point of the video corresponding period W1 is determined in advance for each pair of auxiliary capacitance signals (or for each pair of core signal lines).
In the example shown in FIG. 10, the video corresponding period W1 is a period of 1080H, and the V blank corresponding period W2 is 50H (= total number of scanning lines−number of effective scanning lines = 1130-1080) following the video corresponding period W1. Is the period.
Further, the starting point of the video corresponding period W1 in each of the pair of auxiliary capacitance signals (CS11 and CS12, CS1 and CS2, CS3 and CS4,..., CS9 and CS10) is the gate start pulse signal GSP (vertical synchronization signal). 1H elapsed time, 5H elapsed time, 9H elapsed time,..., 21H elapsed time from occurrence.

In the example shown in FIG. 10, the pair of auxiliary capacitance signals CS11 and CS12 has a period of 1080H from the generation time t0 of the gate clock signal GCK for the first scanning line after the generation of the gate start pulse signal GSP. In the video corresponding period W1, the polarity is set to sequentially reverse every 24H.
Further, the pair of auxiliary capacitance signals CS1 and CS2 is 24H in the video corresponding period W1 (1080H) starting from the time when 4H has elapsed (shifted) from the starting point t0 of the voltage switching pattern of the pair of auxiliary capacitance signals CS11 and CS12. The polarity is set so that the polarity is sequentially reversed.
Similarly, for the pair of auxiliary capacitance signals (CS3 and CS4, CS5 and CS6,..., CS9 and CS10), the starting point is sequentially shifted by 4H, and the polarity is changed every 24H in the video corresponding period W1 (1080H). It is set to invert sequentially.
Further, each of the auxiliary capacitance signals CS1 to CS12 has a difference in time length between the divided periods of 1 V or less in the V blank corresponding period W2 (50H) following the video corresponding period W1. In addition, it is divided into an even number of periods so that each divided period is 24H or less (in the example of FIG. 10, four divisions of 12H × 2 period and 13H × 2 period), and the polarity is sequentially inverted for each divided period. Is set as follows.
Thereby, balancing of the holding times of the two polarities is realized.
Further, if the V blank corresponding period W2 is 24H or more and the number of scanning lines does not change between consecutive frames, the auxiliary capacitor charging time of 7H or more is secured in any of the auxiliary capacitance signals CS1 to CS12. Is done.
Further, according to the conventional setting method of the auxiliary capacitance signals CS1 to CS12 described above, each of the auxiliary capacitance signals CS1 to CS12 at the time of starting the liquid crystal operation if the number of scanning lines does not change between consecutive frames. Are sequentially reversed to the opposite polarity every frame. Thereby, polarity inversion in two consecutive frames is also realized.

JP 2005-189804 A

However, when the number of scanning lines changes between consecutive frames, that is, when the number of ineffective scanning lines (the length of the V blank period) changes between consecutive frames, the conventional liquid crystal display device is sufficient. The two requirements of securing the auxiliary capacity charging time and polarity inversion in two consecutive frames are not satisfied, and there is a problem in that the image is disturbed.
FIG. 11 is a time chart showing an example of the conventional signal patterns of the auxiliary capacitance signals CS1 to CS12 when the number of scanning lines decreases (1130 → 1120).
In the conventional example shown in FIG. 11, the liquid crystal operation start time corresponding to the first, fifth, ninth,..., And seventeenth scanning lines (first line) of the auxiliary capacitance signals CS1 to CS10. Is opposite to the polarity at the same point shown in FIG. This represents that the polarity of the auxiliary capacitance signals CS1 to CS10 in the same scanning line in the previous frame is the same.
Further, in the conventional example shown in FIG. 11, the auxiliary capacity charging is performed at the liquid crystal operation start time corresponding to the second to fourth, sixth to eighth,..., 18th to 20th scanning lines. The time is in the range of 0H to 2H, and sufficient auxiliary capacity charging time (for example, 5H or more) is not ensured.

FIG. 12 is a time chart showing an example of a signal pattern of the conventional auxiliary capacitance signals CS1 to CS12 when the number of scanning lines increases (1130 → 1148). In the example of FIG. 12, since the V blank corresponding period W2 extends beyond the initially assumed length, the polarity maintaining time in the V blank corresponding period W2 is extended to the upper limit of the period of 24H.
Also in the conventional example shown in FIG. 12, similarly to the example of FIG. 11, there arises a problem that a sufficient auxiliary capacity charging time is not secured and a problem that polarity inversion in two consecutive frames is not realized. ing.
In the example shown in FIGS. 11 and 12, when the number of scanning lines increases or decreases between two consecutive frames, image distortion may occur in the first to twentieth scanning lines.
Accordingly, the present invention has been made in view of the above circumstances, and an object of the present invention is to provide the auxiliary capacitor even when the number of scanning lines is changed in a liquid crystal display device having the multi-picture element type liquid crystal panel. The three requirements of balancing the holding time of the two polarities in the signal, ensuring sufficient auxiliary capacity charging time, and polarity reversal in two consecutive frames can be satisfied as much as possible, and as a result, the number of scanning lines changes An object of the present invention is to provide a liquid crystal display device capable of minimizing image disturbance caused by the above.

In order to achieve the above object, a liquid crystal display device according to the present invention includes two sets of liquid crystal electrode pairs facing each other with a liquid crystal layer interposed therebetween, and the two sets of liquid crystals depending on whether or not a horizontal synchronization signal is input for an effective scanning line. Switch means for switching whether or not to supply a pixel gradation signal to each of the electrode pairs, and potentials of the two liquid crystal electrode pairs after the pixel gradation signals are supplied in accordance with the voltage level of the supplied auxiliary capacitance signal A pixel display unit including a pair of auxiliary capacitances for changing the video signal, and a basic signal including a plurality of pairs of basic signal lines to which a pair of auxiliary capacitance signals having different voltage levels are input. A line group and a pair of auxiliary capacitors for one line on a scanning line are electrically connected to one of the pair of auxiliary capacitors and one of the main signal lines in the main signal line group. The present invention is applied to a liquid crystal display device including a liquid crystal panel provided with a bus signal line, and includes the following elements (1) to (5). Is.
(1) Synchronization signal generation means for generating a vertical synchronization signal corresponding to at least two consecutive frames of video based on a predetermined reference clock signal and an input video signal.
(2) In the effective scanning period in which the same number of horizontal synchronization signals as the number of predetermined effective scanning lines is generated, the voltage is switched in a voltage switching pattern in which the holding periods of the two types of voltage levels are substantially balanced, and the voltage switching pattern is First auxiliary capacitance signal generating means for generating the pair of auxiliary capacitance signals that are opposite to those of the previous frame by shifting each pair of basic signal lines by a predetermined period.
(3) Each time the vertical synchronizing signal is generated, the voltage level is held at each of the two types of voltage levels, and the pair of auxiliary capacitance signals whose voltage levels are different from those in the previous frame are Second auxiliary capacitance signal generating means for generating a pair of basic signal lines.
(4) The number of ineffective scanning lines of one frame is specified based on the vertical synchronization signal corresponding to at least two consecutive frames generated by the synchronization signal generating means, and the specified number of ineffective scanning lines In the non-effective scanning period in which the same number of horizontal synchronization signals are generated, the voltage is switched in a voltage switching pattern in which the holding periods of the two types of voltage levels are substantially balanced, and the voltage switching pattern is opposite to that in the previous frame. Third auxiliary capacitance signal generating means for generating the pair of auxiliary capacitance signals. Here, the third auxiliary capacitance signal generating means generates the pair of auxiliary capacitance signals generated during a predetermined charging period immediately before the generation of the vertical synchronization signal of the next frame in the ineffective scanning period. The voltage is fixed. Further, the charging period is, for example, a period of a predetermined range that is greater than or equal to a predetermined lower limit value and less than or equal to a predetermined upper limit value.
(5) For each of the pair of basic signal lines, an interrupt period after the generation of the vertical synchronization signal predetermined for each pair of basic signal lines is a signal generated by the second auxiliary capacitance signal generating means And the generation signal by the first auxiliary capacitance signal generation means is supplied during the period excluding the interrupt period within the effective scanning period, and the third auxiliary capacitance signal generation means is supplied during the non-effective scanning period. Supply signal switching means for supplying a generation signal.
Note that two or more pairs of the liquid crystal electrode pairs may be provided for each pixel display unit (each pixel). Similarly, it is sufficient that two or more auxiliary capacitors are provided for each pixel display unit (for each pixel).
In the liquid crystal display device according to the present invention configured as described above, even when the number of scanning lines changes between consecutive frames, the holding time of the two polarities in the auxiliary capacitance signal is balanced, and sufficient auxiliary capacitance charging is performed. The three requirements of securing time and polarity reversal in two consecutive frames can be satisfied as much as possible, and image disturbance due to changes in the number of scanning lines can be suppressed as much as possible. In particular, by appropriately setting the charging time, the auxiliary capacity charging time that is longer than the charging time can be ensured, which is suitable for preventing image disturbance due to a change in the number of scanning lines. is there.

  More specifically, the third auxiliary capacitance signal generating means may be configured such that the ineffective scanning period has a length equivalent to that of the charging period immediately before the generation of the vertical synchronization signal corresponding to the next frame. The voltage is switched in a voltage switching pattern in which the holding period of each of the two voltage levels is substantially balanced between the even number of first divided periods and the first divided period within the ineffective scanning period. It is considered that the voltage of the pair of auxiliary capacitance signals generated in the charging period immediately before the generation of the vertical synchronization signal corresponding to the next frame is fixed by dividing into two divided periods. It is done.

  According to the present invention, even when the number of scanning lines changes between successive frames, the holding time of the two polarities in the auxiliary capacity signal is balanced, sufficient auxiliary capacity charging time is ensured, and two consecutive frames are obtained. 3 can be satisfied as much as possible, and the image disturbance caused by the change in the number of scanning lines can be suppressed as much as possible. In particular, by appropriately setting the charging time, the auxiliary capacity charging time that is longer than the charging time can be ensured, which is suitable for preventing image disturbance due to a change in the number of scanning lines. is there.

The block diagram of the principal part of the liquid crystal display device X which concerns on embodiment of this invention. An equivalent circuit of a pixel display portion in a multi-picture element type liquid crystal panel. FIG. 6 is a connection diagram (partially omitted) of the basic signal line CSL and the bus signal line CSBL in the multi-picture element type liquid crystal panel. 4 is a time chart of a part (starting portion) of a first auxiliary capacitance signal pattern in a video corresponding period in the liquid crystal display device X. 4 is a time chart of a part (end part) of the first auxiliary capacitance signal pattern in the video corresponding period in the liquid crystal display device X. 4 is a time chart of a first auxiliary capacitance signal pattern in a V blank corresponding period in the liquid crystal display device X. FIG. 6 is a time chart of a part (starting portion) of a second auxiliary capacitance signal pattern in a video corresponding period in the liquid crystal display device X. 4 is a time chart of a part (end part) of a second auxiliary capacitance signal pattern in a video corresponding period in the liquid crystal display device X. The time chart of the 2nd auxiliary capacity signal pattern of the V blank corresponding period in liquid crystal display X. 10 is a time chart of an auxiliary capacitance signal pattern when there is no change in the number of scanning lines in a conventional liquid crystal display device. 6 is a time chart of an auxiliary capacitance signal pattern when the number of scanning lines in a conventional liquid crystal display device is reduced. 6 is a time chart of an auxiliary capacitance signal pattern when the number of scanning lines in a conventional liquid crystal display device increases. 6 is a time chart of a pattern of auxiliary capacitance signal fixation after a vertical synchronization signal is input in the liquid crystal display device X. 4 is a time chart of an auxiliary capacitance signal pattern when the number of scanning lines in the liquid crystal display device X decreases. 6 is a time chart of an auxiliary capacitance signal pattern when the number of scanning lines in the liquid crystal display device X increases. 4 is a time chart of an auxiliary capacitance signal pattern when there is no change in the number of scanning lines in the liquid crystal display device X. 12 is a time chart showing another example of the first auxiliary capacitance signal pattern in the V blank corresponding period in the liquid crystal display device X.

Embodiments of the present invention will be described below with reference to the accompanying drawings for understanding of the present invention. In addition, the following embodiment is an example which actualized this invention, Comprising: It is not the thing of the character which limits the technical scope of this invention.
First, the configuration of a liquid crystal display device X according to an embodiment of the present invention will be described with reference to FIG.
As shown in FIG. 1, the liquid crystal display device X is, for example, a liquid crystal television receiver or the like, and includes a liquid crystal panel 1 that is the multi-picture element type liquid crystal panel, and a liquid crystal driving circuit Z that drives the liquid crystal panel 1. And.
As already described with reference to FIG. 2, the liquid crystal panel 1 is a switch unit that switches between two pairs of the liquid crystal electrodes a <b> 1 and b <b> 1 and whether or not to supply a pixel gradation signal for each pixel of an image. The pixel display part g0 including the two transistors a3 and b3 and a pair of the auxiliary capacitors a2 and b2 is provided for each pixel of the image.

The liquid crystal panel 1 is provided with twelve core signal lines CSL (core signal line group) composed of a pair (two) × 6 sets of signal lines, and for each pair of the main signal lines CSL, A pair of auxiliary capacitance signals having different polarities (different voltage levels) are input.
Further, the liquid crystal panel 1 includes one of the pair of auxiliary capacitors (a2 or b2) and one of the main signal lines CSL1 to CSL12 for each of the pair of auxiliary capacitors a2 and b2 for one line on the scanning line. 1081 bus signal lines CSBL that electrically connect one are also provided. The connection pattern of these signal lines is shown in FIG. 3, and the details thereof are as described above.
The gate clock signal GCK, which is a horizontal synchronizing signal, is supplied to the transistors a3 and b3 through the scanning line signal HL provided along the video scanning line.
Further, the gradation signal representing the luminance level of the pixel (light transmission level of the liquid crystal) is supplied to the transistors a3 and b3 through the gradation signal line VL provided for each pixel group in one column in the vertical direction of the video. The

Further, as shown in FIG. 1, the liquid crystal driving circuit Z includes a video decoder 11, a synchronization signal generating circuit 12, a gradation signal generating circuit 2, a scanning signal generating circuit 3, a video corresponding period CS signal generating circuit 4, V A blank corresponding period CS signal generation circuit 5, an interrupt CS signal generation circuit 6, and a CS signal switching circuit 7 are provided.
The liquid crystal driving circuit Z receives a predetermined reference clock signal used in the liquid crystal display device X and a video signal (for example, a composite video signal) sent from the outside.
The video decoder 11 outputs a horizontal synchronization signal HSYNC, a vertical synchronization signal VSYNC, a data enable signal DE, video data, and the like according to the predetermined reference clock signal and the video signal input to the liquid crystal driving circuit Z. .

The synchronization signal generation circuit 12 includes a gate start pulse signal GSP representing a vertical synchronization signal and a gate clock signal representing a horizontal synchronization signal in accordance with the horizontal synchronization signal HSYNC, the vertical synchronization signal VSYNC, the predetermined reference clock signal, and the like. GCK is generated and output. The gate start pulse signal GSP and the gate clock signal GCK output from the synchronization signal generation circuit 12 are the gradation signal generation circuit 2, the scanning signal generation circuit 3, the video corresponding period CS signal generation circuit 4, and the like. V blank corresponding period CS signal generation circuit 5, interrupt CS signal generation circuit 6, CS signal switching circuit 7 and the like are input.
Here, the synchronization signal generation circuit 12 generates the gate start pulse signal GSP and the gate clock signal GCK corresponding to at least two consecutive frames after the frame currently displayed on the liquid crystal panel 1. To do. For example, the liquid crystal driving circuit Z is provided with a memory (not shown) that stores the video signal corresponding to at least two consecutive frames, and the synchronization signal generation circuit 12 is configured to output the video of the two frames or more. Based on the signal, the gate start pulse signal GSP and the gate clock signal GCK are generated and stored. Therefore, the synchronization signal generation circuit 12 can know in advance the generation timing of the gate start pulse signal GSP corresponding to at least two consecutive frames and the number of gate clock signals GCK (the number of scanning lines). . Here, based on the predetermined reference clock signal and the video signal, the video decoder 11 when generating a gate start pulse signal GSP (vertical synchronization signal) corresponding to at least two consecutive frames of video and the video signal The synchronization signal generation circuit 12 corresponds to synchronization signal generation means.
The synchronization signal generation circuit 12 generates the gate start pulse signal GSP corresponding to two consecutive frames and the number of the gate clock signals GCK in one frame (the total number of effective scanning lines and ineffective scanning lines). Information) is transmitted to the V blank corresponding period CS signal generation circuit 5, the CS signal switching circuit 7, and the like.

The gradation signal generation circuit 2 generates the gradation signal for each video of one horizontal line (one scanning line) based on the video data (video signal) input from the video decoder 11. Circuit for outputting to the gradation signal line VL. The gradation signal is generated and output for each pixel group on each of the first to 1080th scanning lines in synchronization with the gate clock signal GCK after the generation of the gate start pulse signal GSP.
The scanning signal generation circuit 3 is a circuit that sequentially outputs the gate clock signal GCK to each of the first to 1080 scanning line signal lines HL after the generation of the gate start pulse signal GSP.

The video corresponding period CS signal generation circuit 4 (an example of the first auxiliary capacitance signal generating means) generates the video corresponding period W1 (here, 1080H) every time the gate start pulse signal GSP (vertical synchronization signal) is generated. For generating the auxiliary capacitance signals CS1 to CS12 in the period of The auxiliary capacitance signals CS1 to CS12 are signals to be output to the main signal lines CSL1 to CSL12, respectively.
4 and 5 are time charts showing a first signal pattern of the auxiliary capacitance signals CS1 to CS12 generated by the video corresponding period CS signal generation circuit 4. FIG. 4 and 5 show time charts of the start portion and the end portion of the first signal pattern, respectively. In addition, the elliptical broken line shown in each time chart of FIGS. 4 to 17 is a mark indicating the liquid crystal operation start time.
4 and 5, the video corresponding period CS signal generation circuit 4 starts from the generation time t0 of the gate clock signal GCK for the first scanning line after the generation of the gate start pulse signal GSP. In the video corresponding period W1, which is a period of 1080H, a pair of auxiliary capacitance signals CS11 and CS12 whose polarity is sequentially inverted every 24H are generated.

The video corresponding period CS signal generation circuit 4 starts from the time point when 4H has elapsed (shifted) from the starting point t0 of the voltage switching pattern of the pair of auxiliary capacitance signals CS11 and CS12, and the video corresponding period W1 (period of 1080H). ), A pair of auxiliary capacitance signals CS1 and CS2 whose polarity is sequentially inverted every 24H are generated.
Further, the video corresponding period CS signal generation circuit 4 also shifts the starting point for each of the other pair of auxiliary capacitance signals (CS3 and CS4, CS5 and CS6,. In the period W1 (1080H period), a signal whose polarity is sequentially inverted every 24H is generated.

7 and 8 are time charts showing second signal patterns of the auxiliary capacitance signals CS1 to CS12 generated by the video corresponding period CS signal generation circuit 4. FIG. 7 and 8 show time charts of the start portion and the end portion of the second signal pattern, respectively.
The second signal pattern shown in FIGS. 7 and 8 is obtained by inverting the polarities of the auxiliary capacitance signals CS1 to CS12 with respect to the first signal pattern shown in FIGS.
Each time the video start period CS signal generation circuit 4 generates the gate start pulse signal GSP, the auxiliary capacitance signals CS1 to CS12 according to the first signal pattern (FIGS. 4 and 5), and the first The auxiliary capacitance signals CS1 to CS12 according to the second signal pattern (FIGS. 7 and 8) are sequentially switched and generated.

The V blank corresponding period CS signal generation circuit 5 (an example of the third auxiliary capacitance signal generating means) is configured such that the auxiliary capacitance signals CS1 to CS12 in the V blank corresponding period W2 following the video corresponding period W1 (the period of 1080H). Is a circuit that generates As described above, the starting point of the V blank corresponding period W2 is the end point of the video corresponding period W1.
Here, the length of the V blank corresponding period W2 is determined from the number of scanning lines between two consecutive gate start pulse signals GSP generated by the synchronization signal generation circuit 12, and the number of effective scanning lines determined in advance. This is the length of the period (the so-called V blank period) in which the gate clock signals GCK are generated for the number of ineffective scanning lines minus (the period of 1080H here).

Specifically, the V blank corresponding period CS signal generation circuit 5 is based on the generation timing of the gate start pulse signal GSP corresponding to at least two consecutive frames generated by the synchronization signal generation circuit 12. The number of ineffective scanning lines of the frame (the total number of scanning lines between two gate start pulse signals GSP−1080H) is specified. The V blank corresponding period CS signal generation circuit 5 has substantially the holding periods of the two types of voltage levels in the V blank corresponding period W2 in which the same number of horizontal synchronizing signals as the number of ineffective scanning lines specified are generated. The auxiliary capacitance signals CS1 to CS12 are generated in which the voltage is switched in a balanced voltage switching pattern and the voltage switching pattern is opposite to that in the previous frame.
Further, in the liquid crystal display device X, the V blank corresponding period CS signal generation circuit 5 performs a predetermined charge immediately before the generation of the gate start pulse signal GSP of the next frame in the V blank corresponding period W2. The voltage level of the pair of auxiliary capacitance signals (CS1 and CS2, CS3 and CS4,..., CS11 and CS12) generated during the period is fixed. The pair of auxiliary capacitance signals (CS1 and CS2, CS3 and CS4,..., CS11 and CS12) correspond to the pair of core signal lines (CSL1 and CSL2, CSL3 and CSL4,..., CSL11 and CSL12), respectively. It is a signal for supplying.
In the present embodiment, the V blank corresponding period CS signal generation circuit 5 falls within a predetermined range of 8H to 16H immediately before the generation of the gate start pulse signal GSP corresponding to the next frame in the V blank corresponding period W2. A period is set as a charging period, and in this charging period, a pair of auxiliary capacitance signals (CS1 and CS2, CS3 and CS4,..., CS11 are held at a voltage level opposite to that in the previous frame. And CS12). The charging period is not less than a predetermined lower limit (here, 8H) that is a time from when the auxiliary capacitors a2 and b2 start to supply the auxiliary capacitor signals CS1 to CS12 to a rated potential state, Further, it may be determined in advance for a period of time equal to or less than a predetermined upper limit value (here, 16H). Of course, it is conceivable that the charging period is set to a predetermined constant value without giving a predetermined range.

FIG. 6 is a time chart showing a first signal pattern of the auxiliary capacitance signals CS1 to CS12 generated by the V blank corresponding period CS signal generation circuit 5. The example shown in FIG. 6 is an example in which the length of the V blank corresponding period W2 is 50H, that is, the total number of scanning lines in one frame is 1130.
The V blank corresponding period CS signal generation circuit 5 divides the V blank corresponding period W2 into an even number of divided periods, and generates the auxiliary capacitance signals CS1 to CS12 whose polarities are sequentially inverted for each divided period. At that time, the divided period is set so that the difference in time length between them is 1H or less. That is, in the V blank corresponding period W2, the auxiliary capacitance signals CS1 to CS12 are switched in voltage by a voltage switching pattern in which the holding periods of the two types of voltage levels are substantially balanced. One division period is set to be 24H or less.
Here, the V blank corresponding period CS signal generation circuit 5 sets the V blank corresponding period W2 to the same length as the charging period immediately before the generation of the gate start pulse signal GSP corresponding to the next frame. Of the even number of first divided periods and the voltage switching pattern in which the holding periods of the two types of voltage levels are substantially balanced, excluding the first divided period in the V blank corresponding period W2. By dividing into the second divided period to be switched, the voltages of the auxiliary capacitance signals CS1 to CS12 generated in the charging period immediately before the generation of the gate start pulse signal GSP corresponding to the next frame are fixed.
In the example shown in FIG. 6, the blank corresponding period W2 of 50H between 1081H to 1130H is 8H × 4 period (an example of the second divided period) and 9H × 2 period (of the first divided period) from the beginning. For example). As shown in FIG. 6, the first signal pattern in the video corresponding period W1 shown in FIGS. 4 and 5 and the first signal pattern in the blank corresponding period W2 shown in FIG. One set.

FIG. 9 is a time chart showing a first signal pattern of the auxiliary capacitance signals CS1 to CS12 generated by the V blank corresponding period CS signal generation circuit 5. In the example of FIG. 9 as well, the length of the V blank corresponding period W2 is 50H. The second signal pattern shown in FIG. 9 is obtained by inverting the polarities of the auxiliary capacitance signals CS1 to CS12 with respect to the first signal pattern shown in FIG. Therefore, the second signal pattern in the video corresponding period W1 shown in FIGS. 7 and 8 and the second signal pattern in the V blank corresponding period W2 shown in FIG. 9 are one set.
That is, when the auxiliary capacitance signals CS1 to CS12 having the first signal pattern shown in FIGS. 4 and 5 are generated by the video corresponding period CS signal generation circuit 4, the V blank corresponding period CS signal generation is subsequently performed. The auxiliary capacitance signals CS1 to CS12 having the first signal pattern shown in FIG.
Further, when the auxiliary capacity signals CS1 to CS12 having the second signal pattern shown in FIGS. 7 and 8 are generated by the video corresponding period CS signal generation circuit 4, the V blank corresponding period CS signal generation is subsequently performed. The auxiliary capacitance signals CS1 to CS12 having the second signal pattern shown in FIG.
The auxiliary capacitance signals CS1 to CS12 generated by the video corresponding period CS signal generation circuit 4 and the V blank corresponding period CS signal generation circuit 5 are transmitted to the CS signal switching circuit 7.

As described above, each of the video corresponding period CS signal generation circuit 4 and the V blank corresponding period CS signal generation circuit 5 has the same number of horizontal synchronization signals as the total number of effective scanning lines and ineffective scanning lines of one frame. The auxiliary capacitance signals CS1 to CS12 that are generated each time the gate start pulse signal GSP (vertical synchronization signal) is generated during the period in which the voltage generation occurs is a voltage switching pattern in which the holding periods of the two voltage levels are balanced. Are switched (ie, the polarity is switched).
Here, the video corresponding period CS signal generation circuit 4 has a pair of auxiliary capacitance signals (CS11 and CS12, CS1 and CS2, CS3 and CS4,..., Opposite to those in the previous frame of the voltage switching pattern. CS9 and CS10) are generated by shifting each of the pair of basic signal lines (CSL11 and CSL12, CSL1 and CSL2, CSL3 and CSL4,..., CSL9 and CSL10) by a period of 4H.
Further, the V blank corresponding period CS signal generation circuit 5 generates a pair of auxiliary capacitance signals CS1 to CS12 which are opposite to the voltage switching pattern in the previous frame. Further, the V blank corresponding period CS signal generation circuit 5 is based on the gate start pulse signal GSP (vertical synchronization signal) corresponding to at least two consecutive frames generated by the synchronization signal generation circuit 12. The predetermined charging period immediately before the generation of the gate start pulse signal GSP (vertical synchronizing signal) corresponding to the next frame in the V blank corresponding period W2 is opposite to that in the previous frame. The pair of auxiliary capacitance signals CS1 to CS12 fixed at the voltage level are generated.

  On the other hand, the interrupt CS signal generation circuit 6 (an example of the second auxiliary capacitance signal generation means) has a voltage level of the two kinds of voltage levels every time the gate start pulse signal GSP (vertical synchronization signal) is generated. A pair of auxiliary capacitance signals (CS1 and CS2, CS3 and CS4,..., CS11 and CS12) held in (two polarities) are generated. The pair of auxiliary capacitance signals (CS1 and CS2, CS3 and CS4,..., CS11 and CS12) are supplied to the pair of core signal lines (CSL1 and CSL2, CSL3 and CSL4,..., CSL11 and CSL12), respectively. It is a signal for. At that time, the interrupt CS signal generation circuit 6 sets the polarity (voltage level) of each of the auxiliary capacitance signals CS1 to CS12 to a different polarity from that of the previous frame.

FIG. 13 is a time chart of the auxiliary capacitance signals CS1 to CS12 generated by the interrupt CS signal generation circuit 6.
As indicated by a thick line in FIG. 13, the auxiliary capacitance signals CS1 to CS12 generated by the interrupt CS signal generation circuit 6 are signals whose polarities are held constant (fixed). However, the auxiliary capacitance signals CS1 to CS12 shown in FIG. 13 are generated by the video corresponding period CS signal generation circuit 4 in the previous frame in the first signal pattern shown in FIGS. This is a signal when CS1 to CS12 are generated.
On the other hand, when the auxiliary capacity signals CS1 to CS12 of the second signal pattern shown in FIGS. 7 and 8 are generated by the video corresponding period CS signal generation circuit 4 in the previous frame, the interrupt is generated. The CS signal generation circuit 6 generates the auxiliary capacitance signals CS1 to CS12 in which the polarity is inverted with respect to the signal shown in FIG.
The auxiliary capacitance signals CS1 to CS12 generated by the interrupt CS signal generation circuit 6 are also transmitted to the CS signal switching circuit 7.
As will be described later, since the generation signal of the interrupt CS signal generation circuit 6 is used only in the following interrupt periods, the interrupt CS signal generation circuit 6 performs each signal only in the interrupt period. Can also be generated.
The interruption period of the auxiliary capacitance signals CS1 and CS2 is a period of 5H from the time when the gate start pulse signal GSP is generated.
The interruption period of the auxiliary capacitance signals CS3 and CS4 is a period of 9H from the time when the gate start pulse signal GSP is generated.
The interruption period of the auxiliary capacitance signals CS5 and CS6 is a period of 13H from the time when the gate start pulse signal GSP is generated.
The interruption period of the auxiliary capacitance signals CS5 and CS6 is a period of 16H from the time when 1H has elapsed from the time when the gate start pulse signal GSP is generated.
The interruption period of the auxiliary capacitance signals CS7 and CS8 is a period of 20H from the time when 1H has elapsed from the time of generation of the gate start pulse signal GSP.
The interruption period of the auxiliary capacitance signals CS11 and CS12 is a period of 1H from the time when the gate start pulse signal GSP is generated.

The CS signal switching circuit 7 includes the auxiliary capacitance signals CS1 to CS12 (hereinafter referred to as standard auxiliary capacitance signals CS1a to CS12a) generated by the video corresponding period CS signal generation circuit 4 and the interrupt CS signal. The auxiliary capacitance signals CS1 to CS12 (hereinafter referred to as interrupt auxiliary capacitance signals CS1b to CS12b) generated by the generation circuit 6 and the auxiliary capacitance signals CS1 to CS1 generated by the V blank corresponding period CS signal generation circuit 5 This is a circuit for switching which of CS12 (hereinafter referred to as standard auxiliary capacitance signals CS1c to CS12c) is supplied to the basic signal lines CSL1 to CSL12.
More specifically, the CS signal switching circuit 7 (an example of a supply signal switching unit) supplies the standard auxiliary capacitance signals CS1a to CS12a to the main signal lines CSL1 to CSL12 in the video corresponding period W1, The interrupt auxiliary capacitance signals CS1b to CS12b are supplied in a predetermined interrupt period after the generation of the gate start pulse signal GSP (vertical synchronization signal), and the fixed auxiliary capacitor is supplied in the V blank corresponding period W2. Signals CS1c to CS12c are supplied.
The interrupt period is a period predetermined for each of the pair of core signal lines (CSL1 and CSL2, CSL3 and CSL4,..., CSL11 and CSL12), and is the period described above.
Therefore, in the liquid crystal display device X, as shown in FIGS. 6 and 9, the auxiliary capacitances in which the polarities of the auxiliary capacitance signals CS1 to CS12 are supplied to the same scanning line at the same point in the previous frame. The polarity is different from that of the signals CS1 to CS12.
Further, in the liquid crystal display device X, as shown in FIGS. 6 and 9, since the voltage is fixed during the charging period immediately before the generation of the gate start pulse signal GSP (vertical synchronization signal), the first to At the time of starting the liquid crystal operation corresponding to the 20th scanning line, at least the auxiliary capacity charging time is secured for 8H or more. Therefore, in the liquid crystal display device X, image disturbance due to the change in the number of scanning lines is suppressed as much as possible.

FIG. 14 is a time chart showing an example of a signal pattern of the auxiliary capacitance signals CS1 to CS12 in the liquid crystal display device X when the number of scanning lines decreases (1130 → 1120). The example of FIG. 14 is an example to be compared with the time chart for the conventional liquid crystal display device shown in FIG.
In the example shown in FIG. 14, unlike the example shown in FIG. 11, the polarity of the auxiliary capacitance signals CS1 to CS10 corresponds to any of the first to twentieth scanning lines (first to twentieth lines). Even at the start of operation, the polarity is the same as the polarity at the same point shown in FIG. This indicates that the polarity of the auxiliary capacitance signals CS1 to CS10 in the same scanning line in the previous frame is different from the polarity.
Also, in the example shown in FIG. 14, unlike the example shown in FIG. 11, the voltage is fixed during the charging period immediately before the generation of the gate start pulse signal GSP (vertical synchronization signal). At the time of starting the liquid crystal operation corresponding to each fourth scanning line, the auxiliary capacity charging time is secured at least 8H from the time before the generation of the gate start pulse signal GSP. Further, at the liquid crystal operation start time corresponding to each of the fifth to twelfth scanning lines, the auxiliary capacity charging time is secured at least 12H from the time before the generation of the gate start pulse signal GSP. . Further, even at the liquid crystal operation start time corresponding to the 13th to 20th scanning lines, the auxiliary capacity charging time of at least 12H or more is secured before the liquid crystal operation start time.

FIG. 15 is a time chart showing an example of the signal patterns of the auxiliary capacitance signals CS1 to CS12 in the liquid crystal display device X when the number of scanning lines increases (1130 → 1148). The example of FIG. 15 is an example to be compared with the time chart of the conventional liquid crystal display device shown in FIG.
Also in the example illustrated in FIG. 15, unlike the example illustrated in FIG. 12, the polarity of the auxiliary capacitance signals CS <b> 1 to CS <b> 10 corresponds to any of the first to twentieth scanning lines (first to twentieth lines). Also at the time of starting the liquid crystal operation, the polarity is the same as the polarity at the same point shown in FIG. This indicates that the polarity of the auxiliary capacitance signals CS1 to CS10 in the same scanning line in the previous frame is different from the polarity.
Also, in the example shown in FIG. 15, unlike the example shown in FIG. 12, the voltage is fixed during the charging period immediately before the generation of the gate start pulse signal GSP (vertical synchronization signal). At the time of starting the liquid crystal operation corresponding to each of the fourth to fourth scanning lines, the auxiliary capacity charging time is secured at least 8H from the time before the generation of the gate start pulse signal GSP. Further, at the liquid crystal operation start time corresponding to each of the fifth to twelfth scanning lines, the auxiliary capacity charging time is secured at least 12H from the time before the generation of the gate start pulse signal GSP. . Further, even at the liquid crystal operation start time corresponding to the 13th to 20th scanning lines, the auxiliary capacity charging time of at least 12H or more is secured before the liquid crystal operation start time.

From the examples shown in FIGS. 14 and 15, even if the number of scanning lines increases or decreases between two consecutive frames, at least 8H or more before the generation time of the gate start pulse signal GSP for all the scanning lines. Since the auxiliary capacity charging time is ensured, video disturbance can be prevented.
FIG. 16 is a time chart showing an example of the signal patterns of the auxiliary capacitance signals CS1 to CS12 in the liquid crystal display device X when the number of scanning lines is not changed (1130 → 1130). The example of FIG. 16 is an example to be compared with the time chart of the conventional liquid crystal display device shown in FIG.
Also in the example shown in FIG. 16, the polarities of the auxiliary capacitance signals CS1 to CS12 are different from the polarities of the auxiliary capacitance signals CS1 to CS12 in the same scanning line in the previous frame.
Also in the example shown in FIG. 16, at least 8H or more of the auxiliary dose charging time is secured at the liquid crystal operation start time corresponding to the first to twentieth scanning lines.
As described above, in the liquid crystal display device X, even when the number of scanning lines changes, the problem of securing the auxiliary capacity charging time is greatly improved as compared with the conventional case.
Further, in the liquid crystal display device X, the remaining two requirements of the above-described polarity inversion in two consecutive frames and balancing of the holding times of the two polarities in the auxiliary capacitance signal are satisfied. Therefore, in the liquid crystal display device X, image disturbance due to the change in the number of scanning lines is suppressed as much as possible.

By the way, in the liquid crystal display device X, when the number of scanning lines is remarkably small, if the processing of interrupting the supply of the interrupt auxiliary capacitance signals CS1b to CS12b is performed after the generation of the gate start pulse signal GSP, the bipolar display The condition for balancing the holding time (balance between holding times of both polarities) is broken, and image unevenness (band unevenness) is likely to occur.
Therefore, the interruption is performed only when the CS signal switching circuit 7 has a total number of effective scanning lines and ineffective scanning lines of the previous frame equal to or greater than a predetermined lower limit number (for example, 1104). The interrupt auxiliary capacitance signals CS1b to CS12b are supplied to the main signal line CSL during the period, and in other cases, the standard auxiliary capacitance signals CS1a to CS12a are supplied to the main signal line CSL even during the interrupt period. It is possible.
Thereby, it is possible to prevent the occurrence of image unevenness (band unevenness).

In the embodiment, the length of the charging period provided immediately before the end of the V blank period W2 (the liquid crystal operation start time) is adjusted in the range of 8H to 16H, but is not limited thereto.
For example, as shown in FIG. 17, the length of the charging period immediately before the end of the V blank period W2 (the liquid crystal operation start time) is fixed to 8H, and the last two including the charging period in the V blank period W2 It is also conceivable to adjust the fraction of the number of scanning lines in the V blank period W2 in other divided periods other than the one divided period.
Specifically, in the example shown in FIG. 17, the blank corresponding period W2 of 108H between 1081H and 1130H is divided into six divided periods in the order of 9H × 2 period and 8H × 4 period from the top.
Even in such a configuration, since the voltage is fixed during the charging period immediately before the generation of the gate start pulse signal GSP (vertical synchronization signal), the first to fourth scanning lines correspond to the first scanning line. At the time of starting the liquid crystal operation, the auxiliary capacity charging time is secured at least 8H from the time before the generation of the gate start pulse signal GSP. Further, at the liquid crystal operation start time corresponding to the fifth to twelfth scanning lines, the auxiliary capacity charging time is secured at least 12H from the time before the generation of the gate start pulse signal GSP. Also, at the liquid crystal operation start time corresponding to each of the 13th to 20th scanning lines, the auxiliary capacity charging time of at least 12H or more is secured before the liquid crystal operation start time.

  The present invention is applicable to a liquid crystal display device.

X: liquid crystal display device 1: liquid crystal panel 2: gradation signal generation circuit 3: scanning signal generation circuit 4: video corresponding period CS signal generation circuit 5: V blank corresponding period CS signal generation circuit 6: interrupt CS signal generation circuit 7 : CS signal switching circuit W1: Video corresponding period W2: V blank corresponding period

Claims (3)

Two sets of liquid crystal electrode pairs facing each other across the liquid crystal layer, and switch means for switching whether or not to supply a pixel gradation signal to each of the two sets of liquid crystal electrode pairs according to the presence or absence of the input of a horizontal synchronization signal for the effective scanning line A pixel display unit including a pair of auxiliary capacitors that change the potential of each of the two pairs of liquid crystal electrodes after the pixel gradation signal is supplied according to the voltage level of the supplied auxiliary capacitor signal. A basic signal line group including a plurality of pairs of basic signal lines that are provided for each pixel and to which a pair of auxiliary capacitance signals having different voltage levels are input, and the pair of auxiliary capacitors for one line on the scanning line And a liquid crystal panel provided with a plurality of bus signal lines for electrically connecting one of the pair of auxiliary capacitors to any one of the basic signal lines in the basic signal line group. A crystal display device,
Synchronization signal generating means for generating a vertical synchronization signal corresponding to at least two consecutive frames of video based on a predetermined reference clock signal and an input video signal;
In the effective scanning period in which the same number of horizontal synchronizing signals as the number of predetermined effective scanning lines are generated, the voltage is switched in a voltage switching pattern in which the holding periods of the two types of voltage levels are substantially balanced, and the voltage switching pattern is one before. First auxiliary capacitance signal generating means for generating the pair of auxiliary capacitance signals, which are opposite to those in the case of the first frame, by shifting each pair of basic signal lines by a predetermined period;
Each time the vertical synchronization signal is generated, a voltage level is held at each of the two types of voltage levels, and the pair of auxiliary capacitance signals whose voltage levels are different from those in the previous frame are transferred to the pair of cores. Second auxiliary capacitance signal generation means for generating each signal line;
Based on the vertical synchronization signal corresponding to at least two consecutive frames generated by the synchronization signal generation means, the number of ineffective scanning lines of one frame is specified, and the same number as the specified number of ineffective scanning lines. In the ineffective scanning period in which the horizontal synchronizing signal is generated, the voltage is switched in a voltage switching pattern in which the holding periods of the two types of voltage levels are substantially balanced, and the voltage switching pattern is opposite to that in the previous frame. Third auxiliary capacitance signal generating means for generating a pair of auxiliary capacitance signals;
For each of the pair of core signal lines, a generation signal from the second auxiliary capacitance signal generation means is supplied during an interrupt period after the generation of the vertical synchronization signal predetermined for each of the pair of core signal lines. The generation signal by the first auxiliary capacitance signal generation means is supplied during the period excluding the interruption period within the effective scanning period, and the generation signal by the third auxiliary capacitance signal generation means is supplied during the non-effective scanning period. Supply signal switching means to supply;
Comprising
The third auxiliary capacitance signal generating means fixes the voltage of the pair of auxiliary capacitance signals generated during a predetermined charging period immediately before the vertical synchronization signal of the next frame is generated in the ineffective scanning period. A liquid crystal display device characterized by that.   The liquid crystal display device according to claim 1, wherein the charging period is a period of a predetermined range that is greater than or equal to a predetermined lower limit value and less than or equal to a predetermined upper limit value. The third auxiliary capacitance signal generating means comprises:
The ineffective scanning period is an even number of first divided periods having a length equivalent to the charging period immediately before the generation of the vertical synchronization signal corresponding to the next frame, and within the ineffective scanning period. Divided into a second divided period in which the voltage is switched in a voltage switching pattern in which the holding periods of the two types of voltage levels are substantially balanced, excluding the first divided period. 3. The liquid crystal display device according to claim 1, wherein a voltage of the pair of auxiliary capacitance signals generated during the charging period immediately before the corresponding vertical synchronization signal is generated is fixed.

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