JP2011119760A - Method of manufacturing semiconductor element - Google Patents

Method of manufacturing semiconductor element Download PDF

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JP2011119760A
JP2011119760A JP2011035074A JP2011035074A JP2011119760A JP 2011119760 A JP2011119760 A JP 2011119760A JP 2011035074 A JP2011035074 A JP 2011035074A JP 2011035074 A JP2011035074 A JP 2011035074A JP 2011119760 A JP2011119760 A JP 2011119760A
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substrate
semiconductor
electrode
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main surface
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JP5201229B2 (en
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Giichi Marutsuki
義一 丸月
Takao Misaki
貴生 三崎
Takaya Yuasa
貴哉 湯浅
Masayoshi Takahashi
正良 高橋
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Nichia Corp
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Nichia Corp
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Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor light-emitting element and a semiconductor light-emitting device that are improved in luminous efficiency and light extraction efficiency, and to manufacture the semiconductor light-emitting element in good yield by a method of manufacturing the same by suppressing chipping. <P>SOLUTION: The method of manufacturing the semiconductor element includes: a semiconductor forming step of forming a semiconductor on a principal surface of a substrate; and a groove portion-forming step of forming a groove portion on a first principal surface side of the substrate; and a substrate separating step of removing a part of the substrate to open the groove portion on a second principal surface side, and separating the substrate. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

本発明は、半導体発光素子に関し、特に窒化物系半導体発光素子とその製造方法及び半導体発光装置に関する。   The present invention relates to a semiconductor light emitting device, and more particularly to a nitride semiconductor light emitting device, a method for manufacturing the same, and a semiconductor light emitting device.

従来、窒化物半導体発光素子においては、基板にサファイアを用いることが多い。しかし、サファイアは絶縁体であるため、これを基板として用いる場合には、基板の上にある半導体の一部を露出させて、ここに電極を形成しなければならない(このようにすると、素子1個あたりの使用面積が大きくなって、コストの削減が困難となる)。そこで、素子の小型化のため、Si基板の上に窒化物半導体を形成し、基板の裏面に電極を設けた窒化物半導体発光素子が提案されている。特許文献1では、Si基板上にSi基板側から順にp型窒化物半導体層、発光層、n型窒化物半導体層を積層し、Si基板はp型窒化物半導体層を露出するように除去されており、この露出領域上にp型電極が形成されている。   Conventionally, in a nitride semiconductor light emitting device, sapphire is often used for a substrate. However, since sapphire is an insulator, when it is used as a substrate, a part of the semiconductor on the substrate must be exposed and an electrode must be formed thereon (in this case, the element 1 The use area per piece becomes large and it becomes difficult to reduce the cost). In order to reduce the size of the device, a nitride semiconductor light emitting device in which a nitride semiconductor is formed on a Si substrate and an electrode is provided on the back surface of the substrate has been proposed. In Patent Document 1, a p-type nitride semiconductor layer, a light emitting layer, and an n-type nitride semiconductor layer are sequentially stacked on a Si substrate from the Si substrate side, and the Si substrate is removed so as to expose the p-type nitride semiconductor layer. A p-type electrode is formed on the exposed region.

また、窒化物半導体発光素子の製造においては、基板に窒化物半導体を形成して電極を設け、素子化するという方法が用いられている。特許文献2には、素子化の方法として、半導体層及び基板に分離溝を設け、溝に沿って荷重を加えるという方法が開示されている。
さらに、特許文献3及び4には、基板上の半導体層を素子の大きさに分離して半導体層側に別の基板を接合し、元の基板と半導体層とを分離した後、素子形状に分割するという方法が開示されている。
特開2003−86839号公報 特開平11−126923号公報 特開2004−47918号公報 特開2004−363532号公報
In manufacturing a nitride semiconductor light emitting device, a method is used in which a nitride semiconductor is formed on a substrate, an electrode is provided, and the device is formed. Patent Document 2 discloses a method of providing a separation groove in a semiconductor layer and a substrate and applying a load along the groove as a method for forming an element.
Further, in Patent Documents 3 and 4, the semiconductor layer on the substrate is separated into element sizes, another substrate is bonded to the semiconductor layer side, the original substrate and the semiconductor layer are separated, and then the element shape is obtained. A method of dividing is disclosed.
JP 2003-86839 A JP-A-11-126923 Japanese Patent Laid-Open No. 2004-47918 JP 2004-363532 A

半導体と異種材料の基板の裏面に電極を形成し、電流を注入すると、基板と半導体の間(界面)には高い電気障壁が存在するため、Si基板を用いた窒化物系半導体発光素子には、順方向電圧(Vf)が非常に高く、発光効率が悪くなるという問題があった。しかし、引用文献1のように基板を部分的に除去すると、基板が除去された領域上部の半導体層に流れる電流量が基板が除去されていない領域上部の半導体層に流れる電流量よりも多くなり、領域によって流れる電流量に偏りが生じるため、発光層の全面において均一な発光を得ることが難しくなる。   When an electrode is formed on the back surface of a substrate made of a material different from that of a semiconductor and a current is injected, a high electrical barrier exists between the substrate and the semiconductor (interface). There is a problem that the forward voltage (Vf) is very high and the luminous efficiency is deteriorated. However, when the substrate is partially removed as in the cited document 1, the amount of current flowing through the semiconductor layer above the region where the substrate is removed becomes larger than the amount of current flowing through the semiconductor layer above the region where the substrate is not removed. Since the amount of current flowing depending on the region is biased, it is difficult to obtain uniform light emission over the entire surface of the light emitting layer.

また、Si基板上に積層された窒化物半導体を外力により素子化するとチッピングを生じやすく、得られたチップ切断面の品質が十分でないため歩留まりが低下するという問題がある。素子化の方法としては、特許文献2のように半導体層に溝部を設け、基板を外力によって分割するという方法もあるが、この方法でも基板のチッピングが問題となっている。チッピングが生じると、Si基板と半導体の界面において段差が生じ、半導体の端面から出た光が、突出している基板に吸収されてしまう。   In addition, when the nitride semiconductor laminated on the Si substrate is made into an element by an external force, chipping is likely to occur, and there is a problem that the yield is lowered because the quality of the obtained chip cut surface is not sufficient. As a method for forming an element, there is a method in which a groove is provided in a semiconductor layer as in Patent Document 2 and the substrate is divided by an external force. Even in this method, chipping of the substrate is a problem. When chipping occurs, a step occurs at the interface between the Si substrate and the semiconductor, and light emitted from the end face of the semiconductor is absorbed by the protruding substrate.

また特許文献3及び4では、半導体層の途中若しくは基板が露出するまでエッチングして半導体層を素子の大きさに分離し、別の基板を半導体層側に貼り合わせて成長基板を除去している。基板貼り合わせ、基板除去の工程が増えることによって精度のばらつきによる生産性及び歩留まりの低下という問題が起こる。また、基板除去時に、半導体層に損傷が多くなり、素子特性が悪化するという問題もある。   In Patent Documents 3 and 4, etching is performed in the middle of the semiconductor layer or until the substrate is exposed to separate the semiconductor layer into element sizes, and another substrate is bonded to the semiconductor layer side to remove the growth substrate. . Increasing the number of steps for bonding and removing the substrates causes problems of productivity and yield reduction due to variations in accuracy. In addition, there is a problem in that when the substrate is removed, damage to the semiconductor layer increases and the device characteristics deteriorate.

さらに引用文献1のように、基板の裏面に電極を設けた後に素子化するという従来の方法では、電極は基板裏面の面積と同じ若しくはそれよりも小さい面積で形成することになり、電流の注入効率が低下し、電流拡散性が悪くなるという問題があった。さらに、Si基板は非透光性であり光を吸収するので、半導体の側面から出た光が基板に吸収され、光の取り出し効率が低下するという問題もある。   Further, in the conventional method of forming an element after providing an electrode on the back surface of the substrate as in the cited document 1, the electrode is formed with an area equal to or smaller than the area of the back surface of the substrate. There was a problem that efficiency decreased and current diffusibility deteriorated. Furthermore, since the Si substrate is non-translucent and absorbs light, there is also a problem that light emitted from the side surface of the semiconductor is absorbed by the substrate and the light extraction efficiency decreases.

そこで本発明は、上記課題を解決する半導体発光素子とその製造方法及び半導体発光装置を提供することを目的とする。   Therefore, an object of the present invention is to provide a semiconductor light-emitting element, a method for manufacturing the same, and a semiconductor light-emitting device that solve the above-described problems.

本発明の半導体発光素子は、第1の主面と第2の主面とを有する導電性の基板の第1の主面上に半導体を有し、第2の主面上に第1電極を有する半導体発光素子において、基板の側面と半導体の側面が連続した状態、若しくは基板の幅と半導体の幅が略同一であり、第1電極は第2の主面の全面と基板の側面に連続して設けられていることを特徴とする。   The semiconductor light emitting device of the present invention has a semiconductor on a first main surface of a conductive substrate having a first main surface and a second main surface, and has a first electrode on the second main surface. In the semiconductor light emitting device having the semiconductor device, the side surface of the substrate and the side surface of the semiconductor are continuous, or the width of the substrate and the width of the semiconductor are substantially the same, and the first electrode is continuous with the entire surface of the second main surface and the side surface of the substrate. It is characterized by being provided.

本発明の半導体発光素子においては、基板の第2の主面側の幅が、半導体の幅より小さいものが好ましく、基板はSi基板からなり、半導体は窒化物からなるものが好ましい。また、半導体は、基板側から順に少なくとも第1導電型の半導体と第2導電型の半導体とからなり、第2導電型の半導体上に第2電極が形成されていると好ましい。さらに、半導体と第2電極の界面において、半導体と第2電極の幅が略同一であることが好ましい。   In the semiconductor light emitting device of the present invention, the width on the second main surface side of the substrate is preferably smaller than the width of the semiconductor, the substrate is preferably a Si substrate, and the semiconductor is preferably a nitride. The semiconductor is preferably composed of at least a first conductivity type semiconductor and a second conductivity type semiconductor in order from the substrate side, and the second electrode is formed on the second conductivity type semiconductor. Furthermore, it is preferable that the widths of the semiconductor and the second electrode are substantially the same at the interface between the semiconductor and the second electrode.

本発明の半導体発光装置においては、本発明の半導体発光素子が実装されてなる半導体発光装置であって、第1電極側が実装され、第2電極側から光が取り出されることを特徴とする。   The semiconductor light emitting device of the present invention is a semiconductor light emitting device in which the semiconductor light emitting element of the present invention is mounted, wherein the first electrode side is mounted and light is extracted from the second electrode side.

本発明の半導体発光素子の製造方法は、基板の第1の主面上に半導体を形成する半導体形成工程と、基板の第1の主面側に溝部を形成する溝部形成工程と、を具備し、基板を一部除去し、第2の主面側で溝部を開口させて基板を分離する基板分離工程を具備することを特徴とする。   A method for manufacturing a semiconductor light emitting device according to the present invention includes a semiconductor forming step of forming a semiconductor on a first main surface of a substrate, and a groove forming step of forming a groove on the first main surface side of the substrate. A substrate separation step is provided in which a part of the substrate is removed and a groove is opened on the second main surface side to separate the substrate.

本発明の半導体発光素子の製造方法においては、溝部は、基板分離工程において半導体発光素子形状になるように素子を囲んで形成され、各素子の基板と半導体の界面において基板の幅と半導体の幅が略同一になるように形成されること、若しくは各素子の基板の第2の主面側の幅が半導体の幅より小さくなるように形成されることが好ましい。また、溝部は、エッチングにより形成されることが好ましい。   In the method for manufacturing a semiconductor light emitting device of the present invention, the groove portion is formed so as to surround the device so as to be in the shape of the semiconductor light emitting device in the substrate separation step, and the width of the substrate and the width of the semiconductor at the interface between the substrate of each device and the semiconductor Are preferably formed to be substantially the same, or formed so that the width of the second main surface side of the substrate of each element is smaller than the width of the semiconductor. Further, the groove is preferably formed by etching.

さらには、開口溝部を有する基板の第2の主面上に第1電極が形成されることを特徴とする。また、第1電極は溝部で深さ方向に延在し、電極は基板の厚さよりも浅く形成されること、若しくは電極基板及び該基板と接する同一導電型の半導体の厚さよりも浅く形成されることが好ましい。また、半導体形成工程において、基板側から順に少なくとも第1導電型の半導体と第2導電型の半導体とが形成され、前記第2導電型の半導体上には第2電極が形成されることが好ましい。また、溝部形成工程は、半導体形成工程の後に具備し、溝部を形成する領域の第2電極、第2電極の積層方向の半導体及び基板をエッチングする工程であることを特徴とする。   Furthermore, the first electrode is formed on the second main surface of the substrate having the opening groove. The first electrode extends in the depth direction at the groove, and the electrode is formed shallower than the thickness of the substrate, or is formed shallower than the thickness of the electrode substrate and the semiconductor of the same conductivity type in contact with the substrate. It is preferable. In the semiconductor formation step, it is preferable that at least a first conductivity type semiconductor and a second conductivity type semiconductor are formed in order from the substrate side, and a second electrode is formed on the second conductivity type semiconductor. . The groove forming step is a step of etching the second electrode in the region where the groove is to be formed, the semiconductor in the stacking direction of the second electrode, and the substrate after the semiconductor forming step.

また、本発明の半導体発光素子の製造方法においては、基板はSi基板であり、前記半導体は窒化物からなることが好ましい。   In the method for manufacturing a semiconductor light emitting device of the present invention, the substrate is preferably a Si substrate, and the semiconductor is preferably made of a nitride.

本発明によれば、発光効率及び光の取り出し効率を向上させた半導体発光素子及び半導体発光装置を提供することができる。また、その製造方法により、チッピングの発生を抑制し、歩留まり良く半導体素子を製造することができる。   ADVANTAGE OF THE INVENTION According to this invention, the semiconductor light-emitting device and semiconductor light-emitting device which improved the light emission efficiency and the light extraction efficiency can be provided. In addition, the manufacturing method can suppress the occurrence of chipping and manufacture a semiconductor element with a high yield.

本発明の実施の形態に係る半導体発光素子の断面図Sectional drawing of the semiconductor light-emitting device which concerns on embodiment of this invention 本発明の実施の形態に係る半導体発光素子の製造方法Manufacturing method of semiconductor light emitting device according to embodiments of the present invention 本発明の一実施の形態に係る半導体発光素子の製造方法Manufacturing method of semiconductor light emitting device according to one embodiment of the present invention 本発明の一実施の形態に係る半導体発光素子の製造方法Manufacturing method of semiconductor light emitting device according to one embodiment of the present invention 本発明の一実施の形態に係る半導体発光素子の断面図Sectional drawing of the semiconductor light-emitting device which concerns on one embodiment of this invention 本発明の一実施の形態に係る半導体発光素子の断面図Sectional drawing of the semiconductor light-emitting device which concerns on one embodiment of this invention 本発明の一実施の形態に係る半導体発光素子の製造方法Manufacturing method of semiconductor light emitting device according to one embodiment of the present invention 本発明の一実施の形態に係る半導体発光素子の断面図Sectional drawing of the semiconductor light-emitting device which concerns on one embodiment of this invention

以下、本発明について説明するが、本発明の半導体発光素子は、実施の形態に示された構造に限定されるものではない。
図1及び2は本発明の実施の形態に係る半導体発光素子及びその製造方法を現すものである。
図1は、本発明の実施の形態に係る半導体発光素子の構成をあらわすものであって、基板10の第1の主面上に半導体20を有し、基板の第2の主面上に第1電極30、半導体上に第2電極40を有し、第1電極は第2の主面の全面と基板の側面に連続して設けられている半導体発光素子である。図1に示す各構成について説明する。
Hereinafter, although this invention is demonstrated, the semiconductor light-emitting device of this invention is not limited to the structure shown by embodiment.
1 and 2 show a semiconductor light emitting device and a method for manufacturing the same according to an embodiment of the present invention.
FIG. 1 shows a configuration of a semiconductor light emitting device according to an embodiment of the present invention. The semiconductor light emitting device includes a semiconductor 20 on a first main surface of a substrate 10 and a second main surface of the substrate. One electrode 30 and a second electrode 40 on a semiconductor are provided, and the first electrode is a semiconductor light emitting element provided continuously on the entire surface of the second main surface and the side surface of the substrate. Each configuration shown in FIG. 1 will be described.

〔基板10〕
基板は、Siなどの導電性基板が好ましい。本発明は、基板の導電型を限定しないため、基板は、n型、p型のいずれともすることもできる。
〔半導体20〕
半導体は、窒化物などの基板と異種材料のものからなる。半導体は、少なくとも発光構造を有し、好ましくはn型半導体若しくはp型半導体が含まれているものであり、さらに好ましくはp−n接合を有するものである。さらには、n型半導体及びp型半導体を有することもできるし、n型半導体とp型半導体の間に活性層を有する構造にすることもできる。本発明においては、半導体が活性層を有さない構造でもよく、この場合は、n型半導体とp型半導体との界面において、発光し、発光領域となる。
〔電極30,40〕
電極材料としては、半導体の材料に合わせて少なくとも1種類以上の金属を適宜選択し、その合金、積層構造、それらの化合物などを用いることができる。半導体にIII−V族の材料を用いた場合は、正電極としてはNi/Au、ITO(酸化インジウムスズ)など、負電極としてはW/Al、Ti/Alなどを用いることが好ましい。また、本発明においては、正電極を第1電極、負電極を第2電極としてもよいし、負電極を第1電極、正電極を第2電極とすることもできる。
[Substrate 10]
The substrate is preferably a conductive substrate such as Si. Since the present invention does not limit the conductivity type of the substrate, the substrate can be either n-type or p-type.
[Semiconductor 20]
The semiconductor is made of a material different from the substrate such as nitride. The semiconductor has at least a light emitting structure, preferably includes an n-type semiconductor or a p-type semiconductor, and more preferably has a pn junction. Furthermore, an n-type semiconductor and a p-type semiconductor can be included, and a structure having an active layer between the n-type semiconductor and the p-type semiconductor can be employed. In the present invention, the semiconductor may have a structure without an active layer. In this case, light is emitted at the interface between the n-type semiconductor and the p-type semiconductor to form a light emitting region.
[Electrodes 30, 40]
As the electrode material, at least one or more kinds of metals can be appropriately selected in accordance with the semiconductor material, and an alloy, a laminated structure, a compound thereof, or the like can be used. When a III-V group material is used for the semiconductor, it is preferable to use Ni / Au, ITO (indium tin oxide) or the like as the positive electrode and W / Al, Ti / Al, or the like as the negative electrode. In the present invention, the positive electrode may be the first electrode, the negative electrode may be the second electrode, the negative electrode may be the first electrode, and the positive electrode may be the second electrode.

図2は、本発明の実施の形態1に係る半導体発光素子の製造方法を示すものであって、半導体形成工程(図2(a))と、溝部形成工程(図2(b))と、基板分離工程(図2(c))とを具備する。以下に各工程について説明する。   FIG. 2 shows a method for manufacturing the semiconductor light emitting device according to the first embodiment of the present invention, in which a semiconductor forming step (FIG. 2A), a groove forming step (FIG. 2B), And a substrate separation step (FIG. 2C). Each step will be described below.

(半導体形成工程)
基板10の第1の主面上に、半導体20を形成する(図2(a))。少なくとも導電性の基板と基板とは異なる導電型の半導体とで構成される。具体的には、n型の基板の上にp型の半導体を形成する、若しくはp型の基板の上にn型の半導体を形成するものである。半導体は、好ましくはn型半導体及びp型半導体からなるものである。半導体がn型半導体及びp型半導体からなるとき、基板は導電性、非導電性を問わないが、導電性基板を用いるものが好ましく、その場合、基板の導電型は任意に選ぶことができ、その上に積層する半導体の導電型も同様である。基板と基板に接する半導体の導電型を同じにしてもよいし、異なる導電型としても良い。すなわち、n型の基板の上に第1導電型の半導体としてn型半導体を形成し第2導電型の半導体としてp型半導体を形成する、n型の基板の上に第1導電型の半導体としてp型半導体を形成し第2導電型の半導体としてn型半導体を形成する、などが考えられる。基板がp型の場合も同様であり、それぞれの形態において、第1導電型の半導体と第2導電型の半導体との間に活性層を形成することもできる。また、基板と半導体の間にバッファー層などを適宜設けることもできる。バッファー層を設けることにより、結晶性良く半導体を形成し電気的特性の良い素子を得ることができる。
(Semiconductor formation process)
A semiconductor 20 is formed on the first main surface of the substrate 10 (FIG. 2A). At least the conductive substrate and the substrate are composed of different conductive semiconductors. Specifically, a p-type semiconductor is formed on an n-type substrate, or an n-type semiconductor is formed on a p-type substrate. The semiconductor is preferably composed of an n-type semiconductor and a p-type semiconductor. When the semiconductor is composed of an n-type semiconductor and a p-type semiconductor, the substrate may be conductive or non-conductive, but preferably uses a conductive substrate, in which case the conductivity type of the substrate can be arbitrarily selected, The same applies to the conductivity type of the semiconductor layer stacked thereon. The conductivity type of the substrate and the semiconductor in contact with the substrate may be the same or different conductivity types. That is, an n-type semiconductor is formed as a first conductivity type semiconductor on an n-type substrate and a p-type semiconductor is formed as a second conductivity type semiconductor. As a first conductivity-type semiconductor on an n-type substrate. It is conceivable to form a p-type semiconductor and form an n-type semiconductor as the second conductivity type semiconductor. The same applies to the case where the substrate is p-type. In each embodiment, an active layer can be formed between the first conductivity type semiconductor and the second conductivity type semiconductor. In addition, a buffer layer or the like can be provided as appropriate between the substrate and the semiconductor. By providing the buffer layer, a semiconductor can be formed with good crystallinity and an element with good electrical characteristics can be obtained.

(溝部形成工程)
基板の第1の主面側に溝部50を形成する(図2(b))。基板に半導体20を形成した後で基板分離工程を行う前に、基板の第1の主面側に溝部を形成する。このとき、基板を所望の形状に区画分離するために溝部を自由に形成することができ、基板10がバー形状になるようにストライプ状の溝部を形成したり、任意の区画を形成するように溝部を形成したり、所望の素子形状になるように溝部を形成したりできる。
このとき、半導体側から基板の第2の主面60の深さにある電極の形成予定位置よりも深く溝部を形成する。溝部の深さとしては、基板の第2の主面に形成する電極の形成予定面よりも深ければよく、好ましくは基板と半導体の界面から50μm以上、さらに好ましくは80μm以上のものである。これにより、ウエハ面内で基板の一部が分離されないという問題を防ぎ、歩留まり良く基板を分離することができる。その深さは一定でも良いし、一定でなくてもよい。
(Groove formation process)
The groove part 50 is formed in the 1st main surface side of a board | substrate (FIG.2 (b)). Before the substrate separation step is performed after the semiconductor 20 is formed on the substrate, a groove is formed on the first main surface side of the substrate. At this time, a groove portion can be freely formed to partition and separate the substrate into a desired shape, and a striped groove portion is formed so that the substrate 10 has a bar shape, or an arbitrary partition is formed. A groove part can be formed, or a groove part can be formed so that it may become a desired element shape.
At this time, the groove is formed deeper than the electrode formation planned position at the depth of the second main surface 60 of the substrate from the semiconductor side. The depth of the groove may be deeper than the surface on which the electrode to be formed on the second main surface of the substrate is formed, preferably 50 μm or more, more preferably 80 μm or more from the interface between the substrate and the semiconductor. As a result, the problem that a part of the substrate is not separated in the wafer surface can be prevented, and the substrate can be separated with a high yield. The depth may be constant or may not be constant.

前記溝部50の形成方法としては、エッチング(ドライエッチング、ウェットエッチング)、スクライブ(カッタースクライブ、レーザスクライブなど)又はダイシング等を用いる)方法がある。スクライバーを用いて形成すると、半導体と基板で硬さが違うので、同一面では割れず、基板が突出した形状となる。エッチングを用いて形成すると、溝部の幅を5μm程度の幅まで制御することができるので、溝部の幅を細くすることによって、除去される面積が小さくなり、一枚のウエハからの素子の採れ数を多くすることができる。その中でも、マスクを用いたRIE(反応性イオンエッチング)が好ましく、その理由としては、マスクのパターンによって自由に素子形状を決めることができるので、複雑な形にしたり、実装部の形状に合わせた素子形状としたりすることもでき、好ましい。本発明においては、素子形状については特に限定しないので、上面視したときの素子形状が矩形、円形、三角形、六角形、平行四辺形、菱形などにすることができる。また、上面視したときの素子形状が六角形や円形の場合、電流が素子全体に均一に流れる傾向にあり好ましい。また、上面視したときの素子の形状を円形とした場合は、側面から均一に光を取り出すことができ好ましい。上面視したときの素子形状を矩形、三角形、六角形、平行四辺形、菱形とした場合は、発光面積を大きくすることができ好ましい。上面視したときの素子の形状を六角形とした場合、素子全体に電流を均一流すことができ、発光面積も大きくすることができるため最も好ましい。また、図4のように一枚のウエハに密に素子を配置することができる。このときのA−A´断面図が図2(b)となる。さらに、配光特性の良い素子が得られるという利点もある。   Examples of the method for forming the groove 50 include etching (dry etching, wet etching), scribe (cutter scribe, laser scribe, etc.) or dicing. When formed using a scriber, the semiconductor and the substrate are different in hardness, so that the substrate does not break and the substrate protrudes. When formed using etching, the width of the groove can be controlled to about 5 μm. Therefore, by reducing the width of the groove, the area to be removed is reduced, and the number of elements taken from a single wafer is reduced. Can be more. Among them, RIE (reactive ion etching) using a mask is preferable. The reason is that the element shape can be freely determined by the mask pattern, so that the shape is complicated or matched to the shape of the mounting part. An element shape can also be used, which is preferable. In the present invention, since the element shape is not particularly limited, the element shape when viewed from above can be a rectangle, a circle, a triangle, a hexagon, a parallelogram, a rhombus, or the like. Further, it is preferable that the element shape when viewed from above is a hexagonal shape or a circular shape because current tends to flow uniformly over the entire element. In addition, when the shape of the element when viewed from above is circular, it is preferable because light can be extracted uniformly from the side surface. When the element shape when viewed from above is a rectangle, triangle, hexagon, parallelogram, or rhombus, the light emitting area can be increased, which is preferable. When the shape of the element when viewed from the top is a hexagon, it is most preferable because a current can flow uniformly through the entire element and a light emitting area can be increased. Further, the elements can be densely arranged on one wafer as shown in FIG. FIG. 2B is a cross-sectional view taken along the line AA ′ at this time. Furthermore, there is an advantage that an element having a good light distribution characteristic can be obtained.

また、溝部50を形成する場合のエッチング条件を選択することで、溝部の側面を基板の主面に対して垂直な面(垂直面)や基板の主面に対して傾斜した面(傾斜面)にすることができ、溝部の側面、すなわち半導体発光素子の端面を任意に形成することができる。これにより、半導体及び基板の幅を制御することができ、素子の端面形状を任意に変えることが可能である。エッチング条件としては、エッチングガスのガス材料、ガスの流量、混合ガスの場合はそれぞれのガスの混合比、雰囲気圧力、マスクの形状及びプラズマ条件などであり、これらを組み合わせて所望の半導体発光素子の端面を得るためのエッチング条件とすることができる。また、エッチング条件によっては、基板や半導体のエッチング面が角のない丸みを帯びた形状とすることができ、これによって基板を分離するときのチッピングや素子の割れを防止できる。また、エッチングによって平滑な面が得られ、第2の主面側を実装基板や回路基板に実装したときに強固に実装することができる。   Further, by selecting the etching conditions for forming the groove 50, the side surface of the groove is perpendicular to the main surface of the substrate (vertical surface) or the surface is inclined with respect to the main surface of the substrate (inclined surface). The side surface of the groove, that is, the end surface of the semiconductor light emitting element can be arbitrarily formed. Thereby, the width of the semiconductor and the substrate can be controlled, and the end face shape of the element can be arbitrarily changed. Etching conditions include the gas material of the etching gas, the gas flow rate, and in the case of a mixed gas, the mixing ratio of each gas, the atmospheric pressure, the mask shape, and the plasma conditions. Etching conditions for obtaining the end face can be set. In addition, depending on the etching conditions, the etched surface of the substrate or semiconductor can have a rounded shape with no corners, thereby preventing chipping and element cracking when separating the substrate. Further, a smooth surface can be obtained by etching, and the second main surface side can be firmly mounted when mounted on a mounting substrate or a circuit substrate.

例えば、溝部50の幅を一定に、すなわち溝部の側面を垂直面にすることで、素子の端面において基板と半導体が連続した面で形成され、基板と半導体に界面において基板の幅と半導体の幅が略同一になるように形成することができる。これにより、図1のように基板と半導体が連続した端面を持つ素子を形成することができ、従来は基板と半導体の界面において基板が突出する段差が生じ、その基板突出部で光吸収が起こっていたが、それを防ぐことができる。さらに、素子が安定した形となっているので実装時にも安定し好ましい。引用文献1では基板が除去されているため半導体と基板が接する面積が小さいが、図1のように形成すると、基板と半導体の接する面積が大きくなるので電流注入効率が良いという効果もある。   For example, by making the width of the groove portion 50 constant, that is, by making the side surface of the groove portion a vertical surface, the end surface of the element is formed as a continuous surface of the substrate and the semiconductor. Can be formed to be substantially the same. As a result, an element having an end face where the substrate and the semiconductor are continuous as shown in FIG. 1 can be formed. Conventionally, there is a step where the substrate protrudes at the interface between the substrate and the semiconductor, and light absorption occurs at the protruding portion of the substrate. I was able to prevent it. Furthermore, since the element has a stable shape, it is stable and preferable at the time of mounting. In Cited Document 1, since the substrate is removed, the area where the semiconductor and the substrate are in contact with each other is small. However, when the substrate is formed as shown in FIG. 1, the area where the substrate and the semiconductor are in contact with each other is increased.

さらには、溝部50の幅を半導体側からエッチングするときに最初は小さく、基板において形成するときは大きく、すなわち、基板の幅が半導体の幅よりも小さくなるようにして形成し、各素子の基板の第2の主面側の幅が半導体の幅より小さくなるように形成することもできる。この場合、混合ガスを用いた異方性の弱いエッチングでガスの流量を変えることにより2段階エッチングを行う。このとき、半導体を好ましいエッチング条件とすることで半導体の溝部の幅を細くすることができ、半導体の除去される面積を小さくすることができ、発光面積を大きくすることができる。これにより、図5及び図6のように基板の側面と前記半導体の側面が連続してなり基板の第2の主面側の幅が半導体の幅より小さい素子を得ることができ、図1のように基板と半導体が連続した端面を持つ素子と比較して、発光部の大きさは同じままでさらに基板による光吸収を抑制することができる。   Further, the width of the groove 50 is initially small when etching from the semiconductor side and large when formed on the substrate, that is, the substrate is formed so that the width of the substrate is smaller than the width of the semiconductor. It is also possible to form such that the width on the second main surface side is smaller than the width of the semiconductor. In this case, two-stage etching is performed by changing the gas flow rate by etching with weak anisotropy using a mixed gas. At this time, by setting the semiconductor to preferable etching conditions, the width of the groove portion of the semiconductor can be reduced, the area where the semiconductor is removed can be reduced, and the light emitting area can be increased. Thus, as shown in FIGS. 5 and 6, the side surface of the substrate and the side surface of the semiconductor are continuous, and an element in which the width of the second main surface side of the substrate is smaller than the width of the semiconductor can be obtained. Thus, as compared with an element having an end face where a substrate and a semiconductor are continuous, the size of the light emitting portion remains the same, and light absorption by the substrate can be further suppressed.

この場合、図5及び図6のように基板と半導体の界面付近を境に基板の幅が狭くなっていくような形とすると、他の形態と比較して基板の第2の主面の面積が小さいため、第2の主面側を実装する際に素子の実装に要する面積を小さくすることができ、精密な実装をすることができ好ましい。基板と半導体の界面付近においては基板と半導体の幅を略同一とし、基板の第2の主面側においては基板の幅が狭くなるような形態とすることで、図5の場合と比較して、基板から半導体への電流注入を均一に行うことができ、電流拡散性の良い素子を得ることができるので好ましい。また、図5では、第2の主面と連続する基板の側面は第2の主面と略垂直な面であるが、図6のように第2の主面と連続する基板の側面が第2の主面側に傾斜した面であっても良く、このような形態とすると電極を均一な厚さで形成することができ好ましい。   In this case, the area of the second main surface of the substrate is smaller than that of the other embodiments when the width of the substrate is narrowed near the interface between the substrate and the semiconductor as shown in FIGS. Therefore, when mounting the second main surface side, the area required for mounting the element can be reduced, and precise mounting is preferable. Compared to the case of FIG. 5, the width of the substrate and the semiconductor is substantially the same in the vicinity of the interface between the substrate and the semiconductor, and the width of the substrate is narrowed on the second main surface side of the substrate. This is preferable because current can be uniformly injected from the substrate to the semiconductor, and an element having good current diffusivity can be obtained. In FIG. 5, the side surface of the substrate continuous with the second main surface is a surface substantially perpendicular to the second main surface, but the side surface of the substrate continuous with the second main surface is the first side as shown in FIG. 2 may be a surface inclined toward the main surface side, and such a configuration is preferable because the electrode can be formed with a uniform thickness.

(基板分離工程)
基板を一部除去して基板の第2の主面側で溝部を開口させて基板を分離する(図2(c))。具体的には、基板の第1の主面側から第2の主面より深い溝部を形成した後で、半導体側を粘着シート70等の保持部材で保持した状態で基板10の厚さを薄くして第1の主面に対向する第2の主面60を露出させ、溝部50を基板の第2の主面側で開口させることによって基板を分離する。これにより、局所的に外力をかけずに基板を分離することができる。さらには、基板を薄くすることによって、放熱性のよい素子が得られる。また、素子の重心が安定し、実装しやすく好ましい。また他の方法として、基板の第2の主面側にマスクを設け、溝部に達するまで基板をエッチングして溝部を開口させて基板を分離することもできる。
(Substrate separation process)
A part of the substrate is removed and a groove is opened on the second main surface side of the substrate to separate the substrate (FIG. 2C). Specifically, after forming a groove deeper than the second main surface from the first main surface side of the substrate, the thickness of the substrate 10 is reduced with the semiconductor side held by a holding member such as an adhesive sheet 70. Then, the second main surface 60 facing the first main surface is exposed, and the substrate is separated by opening the groove 50 on the second main surface side of the substrate. Thereby, a board | substrate can be isolate | separated, without applying external force locally. Furthermore, by reducing the thickness of the substrate, an element with good heat dissipation can be obtained. In addition, the center of gravity of the element is stable, which is preferable for easy mounting. As another method, a mask may be provided on the second main surface side of the substrate, and the substrate may be separated by etching the substrate until the groove is reached to open the groove.

基板の第2の主面を露出させる方法としては、研磨、エッチングなどの方法を用いることができ、一つの方法を選択して行うことで工程にかかる時間を短く、工程を簡略化することができる。また、研磨した後にRIE(反応性イオンエッチング)を行うと、この後の基板の第2の主面上に設ける電極の形成に適した平滑な面を形成することができ好ましい。さらに、素子の第2の主面側を実装基板や回路基板に実装する場合に強固に実装され、チップの割れ、欠けなどを防止することができる。また、エッチングを用いた場合は、基板の第2の主面側の幅が半導体の幅より小さく、基板の第2の主面側から見たときに半導体が露出した形状とすることもできる。このような素子では光の取り出し効率を高めることができ好ましい。さらに、エッチング条件を選択することにより、Si基板が角のない丸みを帯びた形状とすることができ、第2の主面側を実装基板や回路基板に実装した場合に強固に実装することができ好ましい。   As a method for exposing the second main surface of the substrate, methods such as polishing and etching can be used. By selecting one method, the time required for the process can be shortened and the process can be simplified. it can. In addition, it is preferable to perform RIE (reactive ion etching) after polishing because a smooth surface suitable for forming an electrode provided on the second main surface of the substrate can be formed. Furthermore, when the second main surface side of the element is mounted on a mounting board or a circuit board, the element is firmly mounted, and chip breakage, chipping, and the like can be prevented. When etching is used, the width of the second main surface side of the substrate is smaller than the width of the semiconductor, and the semiconductor can be exposed when viewed from the second main surface side of the substrate. Such an element is preferable because the light extraction efficiency can be increased. Furthermore, by selecting the etching conditions, the Si substrate can be formed into a rounded shape with no corners, and when the second main surface side is mounted on a mounting substrate or a circuit board, it can be firmly mounted. This is preferable.

また、図5及び図6のように基板の第2の主面側の幅が半導体の幅より小さい素子においては、基板における溝部の幅が半導体における溝部の幅より大きく形成されているので、研磨時に発生し溝部に堆積する不純物等を除去しやすく、またこの後の電極形成工程においても容易に電極を形成することができ好ましい。   Further, in the element in which the width of the second main surface side of the substrate is smaller than the width of the semiconductor as shown in FIGS. 5 and 6, the width of the groove portion in the substrate is formed larger than the width of the groove portion in the semiconductor. Impurities that are sometimes generated and deposited in the trenches can be easily removed, and the electrodes can be easily formed in the subsequent electrode formation step.

また、このとき、基板を分離することによって必ずしも素子化されるわけではなく、基板分離工程において前述のようにバー形状にしたり、任意の区画を形成したりして、基板を分離し、この後に素子化する工程を別に設けても良い。例えば、第2の主面を露出させることによって基板をバー状に分離し、さらにスクライバーなどにより素子化しても良い。   At this time, the substrate is not necessarily separated into elements, but in the substrate separation step, the substrate is separated by forming a bar shape or forming an arbitrary section as described above. A step of forming an element may be provided separately. For example, the substrate may be separated into bars by exposing the second main surface, and further formed into an element by a scriber or the like.

(電極形成工程)
基板分離工程後、半導体側を保持した状態で基板10の第2の主面上に第1電極30を形成することができる(図7)。また、第1電極は溝部の第2の主面側の開口状態を保持して溝部で深さ方向に延在する。このとき、電極を形成する領域については特に限定はなく、任意に形成することができるが、電極は第2の主面の全面に形成するとともに溝部で深さ方向に延在することが好ましい。これによって、電流注入効率が向上し、電流拡散性が良くなり、Vfを低下させることができる。また、基板分離工程後に電極を形成するので、溝部に電極を形成することができ、第2の主面及び第2の主面と連続する素子の側面に連続して電極を形成することができる。このとき、基板分離工程において素子形状に分離された基板の厚さよりも浅く電極を形成する。若しくは素子形状に分離された基板及び該基板と接する同一導電型の半導体の厚さよりも浅く電極を形成する。電極が異なる導電型の半導体に接触しないように溝部を狭く形成して電極を形成することにより、第1電極が異なる導電型の半導体に接触してショートするのを防ぐことができる。また、基板に接する電極の面積を大きくすることによって、電流注入効率を向上させることができる。さらに、電極が側面に形成された場合には、半導体の側面からの出射光が、パッケージなどの外的要因によって反射した光が側面の電極によって反射されるので基板に吸収されることなく、光取り出しを向上させた素子を得ることができる。また、この方法で電極を形成すると、半導体が分離された後に電極を形成するので、素子の形状に関わらず基板の第2の主面全面に電極を形成することが容易にでき好ましい。
(Electrode formation process)
After the substrate separation step, the first electrode 30 can be formed on the second main surface of the substrate 10 while holding the semiconductor side (FIG. 7). The first electrode extends in the depth direction at the groove portion while maintaining the opening state of the groove portion on the second main surface side. At this time, the region for forming the electrode is not particularly limited and can be arbitrarily formed. However, the electrode is preferably formed on the entire surface of the second main surface and extends in the depth direction at the groove. Thereby, current injection efficiency is improved, current diffusibility is improved, and Vf can be lowered. In addition, since the electrode is formed after the substrate separation step, the electrode can be formed in the groove, and the electrode can be continuously formed on the second main surface and the side surface of the element continuous with the second main surface. . At this time, the electrode is formed shallower than the thickness of the substrate separated into the element shape in the substrate separation step. Alternatively, the electrode is formed shallower than the thickness of the substrate separated into the element shape and the semiconductor of the same conductivity type in contact with the substrate. Forming the electrode by forming the groove narrowly so that the electrode does not contact different conductivity type semiconductors can prevent the first electrode from contacting and shorting to the different conductivity type semiconductor. Further, the current injection efficiency can be improved by increasing the area of the electrode in contact with the substrate. Furthermore, when the electrode is formed on the side surface, the light emitted from the side surface of the semiconductor is reflected by the electrode on the side surface because the light reflected by the external factors such as the package is reflected, so that the light is not absorbed by the substrate. An element with improved extraction can be obtained. In addition, it is preferable to form the electrode by this method because the electrode is formed after the semiconductor is separated, so that the electrode can be easily formed on the entire second main surface of the substrate regardless of the shape of the element.

また、第1電極は必ずしも基板が分離される前に形成する必要はなく、基板に第1電極を設けた後で電極を介して基板の第2の主面側にマスクを設け、溝部に達するまで電極及び基板をエッチングして溝部を開口(基板を分離)させることもできる。若しくは、開口部を有する形状の第1電極を形成し、開口部の基板をエッチングして溝部を開口(基板を分離)させることもできる。   In addition, the first electrode is not necessarily formed before the substrate is separated. After the first electrode is provided on the substrate, a mask is provided on the second main surface side of the substrate via the electrode to reach the groove. It is also possible to etch the electrodes and the substrate until the grooves are opened (separate the substrate). Alternatively, the first electrode having a shape having an opening can be formed, and the substrate in the opening can be etched to open the groove (separate the substrate).

また、基板上に半導体20を形成した後に半導体上に第2電極40を形成できる。このとき、電極を形成する領域については特に限定はなく、任意に形成することができるが、電流拡散性の点から、半導体上の全面に形成することが好ましい。また、半導体及び基板に溝部を形成する場合、第2電極を設ける前に溝部を形成してもよいし、第2電極を形成した後に溝部を形成してもよい。第2電極を導電性酸化物膜により形成すると、その後にRIEにより溝部を形成する際に第2電極も半導体及び基板と同時に加工することができ、図8のように半導体と第2電極の幅を略同一になる。これにより、工程を簡略化でき、図1と比較して電極面積の大きい素子が得られ、好ましい。また、少なくとも基板を分離する前に第2電極を設けることにより、半導体上に容易に電極を設けることができ好ましい。また、前述の基板分離工程において半導体側を粘着シート等の保持部材で保持する際に剥がれることなく保持でき、歩留まり良く製造できる。   In addition, the second electrode 40 can be formed on the semiconductor after the semiconductor 20 is formed on the substrate. At this time, the region for forming the electrode is not particularly limited and can be arbitrarily formed. However, it is preferably formed over the entire surface of the semiconductor from the viewpoint of current diffusion. Moreover, when forming a groove part in a semiconductor and a board | substrate, a groove part may be formed before providing a 2nd electrode, and a groove part may be formed after forming a 2nd electrode. When the second electrode is formed of a conductive oxide film, the second electrode can be processed simultaneously with the semiconductor and the substrate when the groove is formed by RIE, and the width of the semiconductor and the second electrode as shown in FIG. Are substantially the same. Thereby, the process can be simplified, and an element having a larger electrode area than that of FIG. 1 can be obtained, which is preferable. In addition, it is preferable that the second electrode is provided at least before separating the substrate so that the electrode can be easily provided on the semiconductor. Moreover, when the semiconductor side is held by a holding member such as an adhesive sheet in the above-described substrate separation step, it can be held without being peeled off, and can be manufactured with high yield.

また、以上により得られた半導体発光素子の第1電極側を実装し、第2電極側から光が取り出される半導体発光装置を得ると、第1電極の面積が大きいため、素子を実装する際に用いる接着剤などの接合部材と接する面積が大きくなり、素子と実装基板や回路基板との密着性が向上し好ましい。   Further, when the semiconductor light emitting device obtained by mounting the first electrode side of the semiconductor light emitting element obtained as described above and extracting light from the second electrode side is large, the area of the first electrode is large. The area in contact with the joining member such as the adhesive to be used is increased, and the adhesion between the element and the mounting board or circuit board is preferably improved.

以下に、本発明の窒化物半導体発光素子の具体的実施例を示す。しかし本発明はこれに限定されない。
(実施例1)
図1に示された半導体発光素子を作製する場合、まず、MOCVD(有機金属化学気相成長)反応装置内にSi基板10をセットし、n型半導体、活性層、p型半導体からなる半導体20を順次積層する。続いて、最上層にあるp型半導体のほぼ全面に透光性電極として、膜厚300nmのNi/Auの正電極40と、その正電極の上の一部にボンディング用のAuよりなるパッド電極(図示せず)を0.5μmの膜厚で形成する。次に、ウエハの表面全面にSiNよりなる保護膜を形成して、次に、フォトリソグラフィー技術を用いて、素子の大きさが150μm角になるように幅20μmの開口部を設けてレジストパターンを形成する。前記開口部の領域の保護膜をRIEを用いCHF3ガスによりエッチングする。次に、剥離液でレジストパターンを除去する。次に、ITO電極及び窒化物半導体はSiCl4ガスを用いて、Si基板はSF6ガスを用いてをRIEを行い、基板の裏面に形成する負電極の形成位置よりも深い半導体と基板の界面から100μmのところまでエッチングして溝部50を形成する。その後、フッ酸で保護膜を除去する。次に、半導体側を粘着シート70により一時的に固定し、Si基板を研磨することにより負電極の形成位置である第2の主面60を露出する。これにより、溝部が基板の第2の主面側で開口され、ウエハの半導体側が固定された状態で基板が素子状に分離される。さらに、基板の第2の主面にRIEを行うことにより電極形成面を平滑に整える。次に、TiとAlを含む負電極30を基板の第2の主面に形成及び溝部に形成し、Si基板の第2の主面の全面及び側面に連続して形成する。
Specific examples of the nitride semiconductor light emitting device of the present invention are shown below. However, the present invention is not limited to this.
Example 1
When the semiconductor light emitting device shown in FIG. 1 is manufactured, first, a Si substrate 10 is set in a MOCVD (metal organic chemical vapor deposition) reactor, and a semiconductor 20 made of an n-type semiconductor, an active layer, and a p-type semiconductor. Are sequentially stacked. Subsequently, a Ni / Au positive electrode 40 with a film thickness of 300 nm is formed on almost the entire surface of the p-type semiconductor in the uppermost layer, and a pad electrode made of Au for bonding is formed on a part of the positive electrode. (Not shown) is formed with a film thickness of 0.5 μm. Next, a protective film made of SiN is formed on the entire surface of the wafer. Next, using a photolithography technique, an opening having a width of 20 μm is provided so that the element size becomes 150 μm square, and a resist pattern is formed. Form. The protective film in the region of the opening is etched with CHF3 gas using RIE. Next, the resist pattern is removed with a stripping solution. Next, RIE is performed using SiCl4 gas for the ITO electrode and the nitride semiconductor, and SF6 gas for the Si substrate, and 100 μm from the interface between the semiconductor and the substrate deeper than the formation position of the negative electrode formed on the back surface of the substrate. Etching is performed up to this point to form the groove 50. Thereafter, the protective film is removed with hydrofluoric acid. Next, the semiconductor side is temporarily fixed by the pressure-sensitive adhesive sheet 70, and the second main surface 60 as the negative electrode forming position is exposed by polishing the Si substrate. As a result, the groove is opened on the second main surface side of the substrate, and the substrate is separated into elements in a state where the semiconductor side of the wafer is fixed. Further, the electrode formation surface is smoothed by performing RIE on the second main surface of the substrate. Next, the negative electrode 30 containing Ti and Al is formed on the second main surface of the substrate and in the groove, and is continuously formed on the entire surface and side surfaces of the second main surface of the Si substrate.

(実施例2)
実施例1において、第2の主面を露出する際にSi基板を研磨する代わりに、SF6ガスを用いてエッチングによりSi基板を除去する。それ以外は実施例1と同様にして形成する。実施例2の半導体発光素子においては、実施例1と比較して工程にかかる時間を短くし、生産性を向上することができた。
実施例2の変形例として、基板の幅よりも半導体の幅のほうが大きく、基板の第2の主面側から見たときに半導体が露出した形状とした。このとき、溝部の幅を半導体側20μm、基板側40μmとして形成した。この場合、光の取り出し効率を高めた素子を得ることができた。また、Si基板が角のない丸みを帯びた形状となり、特にSi基板の第2の主面側が丸みを帯びた形状となることで、第2の主面側を実装基板や回路基板に実装したときに強固に実装された。
(Example 2)
In Example 1, instead of polishing the Si substrate when exposing the second main surface, the Si substrate is removed by etching using SF 6 gas. Otherwise, it is formed in the same manner as in Example 1. In the semiconductor light emitting device of Example 2, the time required for the process was shortened compared with Example 1, and the productivity could be improved.
As a modification of Example 2, the width of the semiconductor is larger than the width of the substrate, and the semiconductor is exposed when viewed from the second main surface side of the substrate. At this time, the width of the groove was formed so that the semiconductor side was 20 μm and the substrate side was 40 μm. In this case, an element having improved light extraction efficiency could be obtained. In addition, the Si substrate has a rounded shape with no corners. In particular, the second main surface side of the Si substrate has a rounded shape, so that the second main surface side is mounted on a mounting board or a circuit board. When implemented firmly.

(実施例3)
図4に示された半導体発光素子を作成する場合、溝部50を形成するときに一辺75μmの六角形になるようにレジストパターンを形成する。それ以外は実施例1と同様にして形成する。実施例3の半導体発光素子においては、実施例1と比較して配光特性の良い素子が得られた。
(Example 3)
When the semiconductor light emitting device shown in FIG. 4 is formed, a resist pattern is formed so as to form a hexagonal shape with a side of 75 μm when the groove portion 50 is formed. Otherwise, it is formed in the same manner as in Example 1. In the semiconductor light emitting device of Example 3, an element having better light distribution characteristics than that of Example 1 was obtained.

本発明は、すべての半導体素子に適用できるが、特に、窒化物系の半導体素子に適している。   The present invention can be applied to all semiconductor elements, but is particularly suitable for nitride-based semiconductor elements.

10.基板
20.半導体
30.第1電極
40.第2電極
50.溝部
60.第2の主面
70.粘着シート
10. Substrate 20. Semiconductor 30. First electrode 40. Second electrode 50. Groove 60. Second main surface 70. Adhesive sheet

Claims (10)

基板の第1の主面上に半導体を形成する半導体形成工程と、
前記基板の第1の主面側に溝部を形成する溝部形成工程と、を具備し、
前記基板を一部除去し、第2の主面側で前記溝部を開口させて基板を分離する基板分離工程を具備することを特徴とする半導体素子の製造方法。
A semiconductor forming step of forming a semiconductor on the first main surface of the substrate;
A groove forming step of forming a groove on the first main surface side of the substrate,
A method of manufacturing a semiconductor device, comprising: a substrate separation step of removing a part of the substrate and separating the substrate by opening the groove on the second main surface side.
前記溝部は、前記基板分離工程において前記半導体発光素子形状になるように素子を囲んで形成され、各素子の基板と半導体の界面において前記基板の幅と前記半導体の幅が略同一になるように形成されることを特徴とする請求項1に記載の半導体素子の製造方法。 The groove is formed so as to surround the element so as to be in the shape of the semiconductor light emitting element in the substrate separation step, and the width of the substrate and the width of the semiconductor are substantially the same at the interface between the substrate and the semiconductor of each element. The method of manufacturing a semiconductor device according to claim 1, wherein the semiconductor device is formed. 前記溝部は、前記基板分離工程において前記半導体発光素子形状になるように素子を囲んで形成され、各素子の基板の第2の主面側の幅が半導体の幅より小さくなるように形成されることを特徴とする請求項1又は2に記載の半導体素子の製造方法。 The groove is formed so as to surround the element so as to be in the shape of the semiconductor light emitting element in the substrate separation step, and is formed so that the width of the second main surface side of the substrate of each element is smaller than the width of the semiconductor. The method for manufacturing a semiconductor device according to claim 1, wherein: 前記溝部は、エッチングにより形成されることを特徴とする請求項1乃至3のいずれか1項に記載の半導体素子の製造方法。 The method for manufacturing a semiconductor device according to claim 1, wherein the groove is formed by etching. 前記開口溝部を有する基板の第2の主面上に第1電極が形成されることを特徴とする請求項1乃至4のいずれか1項に記載の半導体素子の製造方法。 5. The method of manufacturing a semiconductor device according to claim 1, wherein the first electrode is formed on a second main surface of the substrate having the opening groove. 6. 前記第1電極は前記溝部で深さ方向に延在し、該電極は前記基板の厚さよりも浅く形成されることを特徴とする請求項5に記載の半導体素子の製造方法。 6. The method of manufacturing a semiconductor device according to claim 5, wherein the first electrode extends in the depth direction at the groove, and the electrode is formed to be shallower than the thickness of the substrate. 前記第1電極は前記溝部で深さ方向に延在し、該電極は前記基板及び該基板と接する同一導電型の半導体の厚さよりも浅く形成されることを特徴とする請求項5に記載の半導体素子の製造方法。 The said 1st electrode is extended in the depth direction in the said groove part, This electrode is formed shallower than the thickness of the semiconductor of the same conductivity type which contact | connects the said board | substrate and this board | substrate. A method for manufacturing a semiconductor device. 前記半導体形成工程において、前記基板側から順に少なくとも第1導電型の半導体と第2導電型の半導体とが形成され、前記第2導電型の半導体上には第2電極が形成されることを特徴とする請求項1乃至7のいずれか1項に記載の半導体素子の製造方法。 In the semiconductor forming step, at least a first conductivity type semiconductor and a second conductivity type semiconductor are formed in order from the substrate side, and a second electrode is formed on the second conductivity type semiconductor. A method for manufacturing a semiconductor device according to any one of claims 1 to 7. 前記溝部形成工程は、半導体形成工程の後に具備し、前記溝部を形成する領域の第2電極、該第2電極の積層方向の半導体及び基板をエッチングする工程であることを特徴とする請求項8に記載の半導体素子の製造方法。 9. The groove forming step is a step of etching the second electrode in a region where the groove is to be formed, the semiconductor in the stacking direction of the second electrode, and the substrate after the semiconductor forming step. The manufacturing method of the semiconductor element of description. 前記基板はSi基板であり、前記半導体は窒化物からなることを特徴とする請求項1乃至9のいずれか1項に記載の半導体素子の製造方法。 The method for manufacturing a semiconductor device according to claim 1, wherein the substrate is a Si substrate, and the semiconductor is made of nitride.
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