JP2011114440A - Differential signal generation circuit and frequency conversion circuit - Google Patents

Differential signal generation circuit and frequency conversion circuit Download PDF

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JP2011114440A
JP2011114440A JP2009267183A JP2009267183A JP2011114440A JP 2011114440 A JP2011114440 A JP 2011114440A JP 2009267183 A JP2009267183 A JP 2009267183A JP 2009267183 A JP2009267183 A JP 2009267183A JP 2011114440 A JP2011114440 A JP 2011114440A
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drain
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Toshio Orii
俊雄 折井
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Seiko Epson Corp
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Seiko Epson Corp
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<P>PROBLEM TO BE SOLVED: To improve an S/N ratio in a differential signal generation circuit. <P>SOLUTION: The differential signal generation circuit 31 includes: a source grounding circuit 311 for amplifying an inputted RF signal; a drain grounding circuit 312 for generating differential signals RF<SB>+</SB>and RF<SB>-</SB>of the amplified RF signal; and a capacity part 313 for adjusting a phase difference between the generated differential signals RF<SB>+</SB>and RF<SB>-</SB>. A first resistor R1 and a second resistor R2 in the drain grounding circuit 312 equalize the amplitude of the differential signals RF<SB>+</SB>and RF<SB>-</SB>, and the capacitor part 313 adjusts the phase difference between the differential signals RF<SB>+</SB>and RF<SB>-</SB>to be almost 180 degrees. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

本発明は、差動信号生成回路及びこの差動信号生成回路を備えた周波数変換回路に関する。   The present invention relates to a differential signal generation circuit and a frequency conversion circuit including the differential signal generation circuit.

スーパーへテロダイン方式の無線通信装置では、受信信号に、装置内部で生成した局部発振信号(ローカル信号)を乗算(合成)して中間周波数の信号(IF信号)に変換するミキサーが用いられる。このとき、変換効率を上げるため、入力信号として差動信号を入力するミキサー(例えば、ギルバート・セル・ミキサーなど)が用いられ、ミキサーの前段には、受信信号を増幅するとともに差動信号に変換する差動増幅回路が設けられる。この差動増幅回路としては、例えば、特許文献1に開示されているように、特性が同じ二つのトランジスタを対称的に接続した差動トランジスタ対を用いた構成が一般的である。   A superheterodyne wireless communication apparatus uses a mixer that multiplies (synthesizes) a received signal by a local oscillation signal (local signal) generated inside the apparatus and converts the received signal into an intermediate frequency signal (IF signal). At this time, in order to increase the conversion efficiency, a mixer (for example, a Gilbert cell mixer) that inputs a differential signal as an input signal is used, and the received signal is amplified and converted into a differential signal at the front stage of the mixer. A differential amplifier circuit is provided. As this differential amplifier circuit, for example, as disclosed in Patent Document 1, a configuration using a differential transistor pair in which two transistors having the same characteristics are symmetrically connected is generally used.

特開2007−208612号公報JP 2007-208612 A

ところで、GPS信号などの1GHz以上の高周波信号を受信する場合、差動増幅回路の構成素子(増幅用素子や負荷素子など)が発生する雑音によるS/N比の低下が問題となる。また、増幅度を上げるために差動増幅回路を複数段縦続接続すると、回路素子の数が多くなるほど、S/N比の低下の程度が大きくなる。本発明は、上記事情に鑑みてなされたものであり、差動信号生成回路におけるS/N比の改善を図ることを目的としている。   By the way, when receiving a high-frequency signal of 1 GHz or higher such as a GPS signal, there is a problem of a decrease in S / N ratio due to noise generated by constituent elements (amplifying elements, load elements, etc.) of the differential amplifier circuit. Further, when a plurality of stages of differential amplifier circuits are connected in order to increase the degree of amplification, the degree of reduction in the S / N ratio increases as the number of circuit elements increases. The present invention has been made in view of the above circumstances, and an object thereof is to improve the S / N ratio in a differential signal generation circuit.

上記課題を解決するための第1の形態は、1GHz以上の規定高周波信号がゲートに入力されるソース接地回路と、前記ソース接地回路の出力段に設けられ、第1の抵抗を介してドレインが電源ラインに接続され、第2の抵抗を介してソースが接地されて、ドレイン及びソースから前記規定高周波信号の差動信号を出力するドレイン接地回路とを備え、前記第1の抵抗と前記第2の抵抗とは、前記ドレイン接地回路のドレイン及びソースそれぞれからの出力信号の振幅を同等に調整するための抵抗値でなる差動信号生成回路である。   A first form for solving the above problem is provided in a grounded source circuit to which a specified high-frequency signal of 1 GHz or more is input to a gate, and an output stage of the grounded source circuit, and a drain is provided via a first resistor. A power source line, a source grounded through a second resistor, a drain and a drain ground circuit that outputs a differential signal of the specified high-frequency signal from the source, and the first resistor and the second resistor The resistor is a differential signal generation circuit having a resistance value for equally adjusting the amplitudes of the output signals from the drain and the source of the grounded drain circuit.

この第1の形態によれば、規定高周波信号が入力されるソース接地回路と、このソース接地回路の出力段に設けられて規定高周波信号の差動信号を出力するドレイン接地回路とを備える差動信号生成回路が構成される。つまり、ソース接地回路によって、入力された規定高周波信号が増幅され、ドレイン接地回路によって、増幅された規定高周波信号の差動信号が生成される。これにより、増幅用素子としてはソース接地回路の1つのトランジスタで済むため、差動トランジスタ対を用いた従来の差動増幅回路と比較して、増幅用素子の数を減らすことができ、S/N比の低下を防止した差動信号生成回路を実現できる。   According to the first aspect, a differential including a source grounded circuit to which a specified high-frequency signal is input, and a drain grounded circuit that is provided at an output stage of the source grounded circuit and outputs a differential signal of the specified high-frequency signal. A signal generation circuit is configured. That is, the input specified high-frequency signal is amplified by the source ground circuit, and the differential signal of the amplified specified high-frequency signal is generated by the drain ground circuit. As a result, since only one transistor of the common source circuit is required as an amplifying element, the number of amplifying elements can be reduced as compared with a conventional differential amplifying circuit using a differential transistor pair. A differential signal generation circuit that prevents a decrease in the N ratio can be realized.

また、ドレイン接地回路における第1の抵抗及び第2の抵抗によって、ドレイン及びソースそれぞれからの出力信号の振幅が同等に調整される。これにより、振幅がほぼ一致した差動信号が生成される。   Further, the amplitudes of the output signals from the drain and the source are adjusted equally by the first resistor and the second resistor in the common drain circuit. Thereby, a differential signal having substantially the same amplitude is generated.

第2の形態として、第1の形態の差動信号生成回路であって、前記ドレイン接地回路のソースと前記差動信号の出力端との間に、ドレイン及びソースそれぞれからの出力信号の位相差を180度に調整するための容量が設けられてなる差動信号生成回路を構成しても良い。   A second form is a differential signal generation circuit according to the first form, wherein the phase difference of the output signals from the drain and the source is between the source of the grounded drain circuit and the output terminal of the differential signal. A differential signal generation circuit provided with a capacitor for adjusting the angle to 180 degrees may be configured.

この第2の形態によれば、ドレイン接地回路のソースと差動信号の出力端との間に設けられた容量によって、ドレイン及びソースからの出力信号の位相差が180度に調整される。これにより、位相差がほぼ180度に調整された差動信号が生成される。   According to the second embodiment, the phase difference between the output signals from the drain and the source is adjusted to 180 degrees by the capacitance provided between the source of the common drain circuit and the output terminal of the differential signal. As a result, a differential signal whose phase difference is adjusted to approximately 180 degrees is generated.

また、第3の形態として、1GHz以上の規定高周波信号の受信信号に局部発振信号を乗算して当該局部発振信号の高調波と前記規定高周波信号の周波数との差周波数の信号を取り出す周波数変換回路であって、前記受信信号を入力する第1又は第2の形態の差動信号生成回路と、前記差動信号生成回路から出力される差動信号それぞれに前記局部発振信号を乗算するミキサー部と、前記ミキサー部の出力信号から前記差周波数の信号成分を抽出するフィルター部とを備えた周波数変換回路を構成しても良い。   Further, as a third mode, a frequency conversion circuit that multiplies a received signal of a specified high-frequency signal of 1 GHz or more by a local oscillation signal and extracts a signal having a difference frequency between the harmonic of the local oscillation signal and the frequency of the specified high-frequency signal. A differential signal generation circuit of the first or second form for inputting the reception signal, and a mixer unit for multiplying each of the differential signals output from the differential signal generation circuit by the local oscillation signal; A frequency conversion circuit including a filter unit that extracts the signal component of the difference frequency from the output signal of the mixer unit may be configured.

GPS受信装置のブロック構成図。The block block diagram of a GPS receiver. 周波数変換部のブロック構成図。The block block diagram of a frequency conversion part. 差動信号生成回路の回路構成図。The circuit block diagram of a differential signal generation circuit.

以下、図面を参照して、本発明の実施形態を説明する。なお、以下では、本発明を、測位用衛星の一種であるGPS(Global Positioning System)衛星から発信されているGPS信号を受信するGPS受信装置に適用した場合を説明するが、本発明の適用可能な実施形態がこれに限定されるものではない。   Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the following, the case where the present invention is applied to a GPS receiver that receives a GPS signal transmitted from a GPS (Global Positioning System) satellite, which is a kind of positioning satellite, will be described. However, the embodiment is not limited to this.

[構成]
図1は、本実施形態におけるGPS受信装置1のブロック構成図である。図1に示すように、GPS受信装置1は、GPSアンテナ10と、RF(Radio Frequency)受信回路部20と、ベースバンド部40とを備えて構成される。
[Constitution]
FIG. 1 is a block configuration diagram of a GPS receiver 1 according to the present embodiment. As shown in FIG. 1, the GPS receiver 1 includes a GPS antenna 10, an RF (Radio Frequency) receiving circuit unit 20, and a baseband unit 40.

GPSアンテナ10は、測位用衛星の一種であるGPS衛星から発信されているGPS衛星信号を含むRF信号を受信する。なお、GPS衛星信号は、GPS衛星毎に異なる拡散符号の一種であるPRN(Pseudo Random Noise)コードで直接スペクトラム拡散方式により変調された1.57542[GHz]の通信信号である。PRNコードは、コード長1023チップを1フレームとする繰返し周期1msの擬似ランダム雑音符号である。   The GPS antenna 10 receives an RF signal including a GPS satellite signal transmitted from a GPS satellite that is a kind of positioning satellite. The GPS satellite signal is a 1.57542 [GHz] communication signal directly modulated by a spread spectrum system with a PRN (Pseudo Random Noise) code, which is a kind of spreading code different for each GPS satellite. The PRN code is a pseudo random noise code having a repetition period of 1 ms with a code length of 1023 chips as one frame.

RF受信回路部20は、SAW(Surface Acoustic Wave)フィルター21と、LNA(Low Noise Amplifier)22と、周波数変換部30と、増幅部23と、ADC(Analog to Digital Converter)24とを有する。   The RF receiving circuit unit 20 includes a SAW (Surface Acoustic Wave) filter 21, an LNA (Low Noise Amplifier) 22, a frequency conversion unit 30, an amplification unit 23, and an ADC (Analog to Digital Converter) 24.

SAWフィルター21は、バンドパスフィルターであり、GPSアンテナ10で受信されたRF信号に対して、所定帯域の信号を通過させ帯域外の周波数成分を遮断する。LNA22は、低雑音アンプであり、SAWフィルター21から出力されたRF信号を増幅する。   The SAW filter 21 is a band-pass filter, and allows a signal in a predetermined band to pass through the RF signal received by the GPS antenna 10 and blocks out-of-band frequency components. The LNA 22 is a low noise amplifier and amplifies the RF signal output from the SAW filter 21.

周波数変換部30は、LNA22から出力されたRF信号に所定の局部発振信号Loを乗算して、該RF信号を中間周波数信号(IF信号)に変換する。増幅部23は、周波数変換部30から出力されたIF信号を増幅する。ADC24は、増幅部23から出力されたアナログ信号であるIF信号を、デジタル信号に変換する。   The frequency conversion unit 30 multiplies the RF signal output from the LNA 22 by a predetermined local oscillation signal Lo, and converts the RF signal into an intermediate frequency signal (IF signal). The amplification unit 23 amplifies the IF signal output from the frequency conversion unit 30. The ADC 24 converts the IF signal that is an analog signal output from the amplifying unit 23 into a digital signal.

ベースバンド部40は、RF受信回路部20から出力されたIF信号に対する相関処理を行ってGPS衛星信号を捕捉・抽出し、データを復号して航法メッセージや時刻情報を取り出し、疑似距離の算出演算や測位演算を行う。   The baseband unit 40 performs correlation processing on the IF signal output from the RF receiving circuit unit 20 to capture and extract GPS satellite signals, decodes the data to extract navigation messages and time information, and calculates pseudo distances. And positioning calculation.

図2は、周波数変換部30のブロック構成図である。図2に示すように、周波数変換部30は、差動信号生成回路31と、局部発振信号生成部32と、差動変換回路33と、ミキサー34と、LPF35とを有して構成される。   FIG. 2 is a block configuration diagram of the frequency conversion unit 30. As shown in FIG. 2, the frequency conversion unit 30 includes a differential signal generation circuit 31, a local oscillation signal generation unit 32, a differential conversion circuit 33, a mixer 34, and an LPF 35.

差動信号生成回路31は、LNA22から入力されたRF信号を増幅し、差動形式の信号RF,RFに変換する。 The differential signal generation circuit 31 amplifies the RF signal input from the LNA 22 and converts it into differential signals RF + and RF .

局部発振信号生成部32は、VCO(Voltage Controlled Oscillator)等の発振器を有し、周波数FLoの局部発振信号(ローカル信号)Loを生成する。差動変換回路33は、局部発振信号生成部32からの局部発振信号Loを、差動形式の信号Lo,Loに変換する。 The local oscillation signal generation unit 32 includes an oscillator such as a VCO (Voltage Controlled Oscillator) and generates a local oscillation signal (local signal) Lo having a frequency F Lo . The differential conversion circuit 33 converts the local oscillation signal Lo from the local oscillation signal generation unit 32 into differential signals Lo + and Lo .

ミキサー34は、複数のMOSトランジスタで構成されるギルバート・セル・ミキサーで実現される。このミキサー34には、差動信号生成回路31からRF信号が差動形式の信号RF,RFとして入力され、差動変換回路33から局部発振信号Loが差動形式の信号Lo,Loとして入力され、RF信号と局部発振信号Loとを乗算した信号MIXを、差動形式の信号MIX,MIXとして出力する。 The mixer 34 is realized by a Gilbert cell mixer composed of a plurality of MOS transistors. An RF signal is input from the differential signal generation circuit 31 to the mixer 34 as differential signals RF + and RF , and a local oscillation signal Lo is input from the differential conversion circuit 33 to the differential signals Lo + and Lo. - is input as the signal MIX obtained by multiplying the RF signal and the local oscillation signal Lo, the signal of the differential type MIX +, MIX - output as.

LPF35は、ミキサー34から出力される信号に対して、RF信号と局部発振信号Loとの差周波数を含む低帯域の信号を通過させ、帯域外の周波数成分を遮断する。このLPF35により、ミキサー34の出力信号から希望のIF信号IF,IFが抽出される。なお、差動形式の信号IF,IFであるため、後段の回路ではどちらか一方の信号をIF信号として利用することとしても良いし、或いは、差動信号IF,IFの差電圧をIF信号として利用することとしても良い。 The LPF 35 passes a low-band signal including a difference frequency between the RF signal and the local oscillation signal Lo with respect to the signal output from the mixer 34, and blocks out-of-band frequency components. The LPF 35 extracts desired IF signals IF + and IF from the output signal of the mixer 34. Since the differential signals IF + and IF are used, either one of the signals may be used as an IF signal in the subsequent circuit, or the differential voltage between the differential signals IF + and IF may be used. May be used as an IF signal.

図3は、差動信号生成回路31の回路構成図である。図3に示すように、差動信号生成回路31は、ソース接地回路311と、ドレイン接地回路312と、容量部313とを有して構成される。   FIG. 3 is a circuit configuration diagram of the differential signal generation circuit 31. As shown in FIG. 3, the differential signal generation circuit 31 includes a source ground circuit 311, a drain ground circuit 312, and a capacitor unit 313.

ソース接地回路311は、MOSトランジスタTR1をソース接地した回路であり、入力されたRF信号を増幅する。MOSトランジスタTR1のゲート端子Gには、直流成分遮断用のコンデンサC1を介してLNA22からのRF信号が印加され、ソース端子Sは接地され、ドレイン端子Dは負荷抵抗Rを介して電源ラインVddに接続されている。そして、MOSトランジスタTr1のドレイン端子Dからの出力Vd1が、ソース接地回路311の出力信号となる。 The source ground circuit 311 is a circuit in which the MOS transistor TR1 is grounded, and amplifies the input RF signal. The RF signal from the LNA 22 is applied to the gate terminal G of the MOS transistor TR1 via the capacitor C1 for cutting off the DC component, the source terminal S is grounded, and the drain terminal D is connected to the power supply line Vdd via the load resistor RL. It is connected to the. The output Vd1 from the drain terminal D of the MOS transistor Tr1 becomes the output signal of the source ground circuit 311.

ドレイン接地回路312は、MOSトランジスタTR2をドレイン接地した回路(ソースフォロワ)であり、ソース接地回路311の出力段に設けられ、このソース接地回路311により増幅されたRF信号の差動信号RF,RFを生成する。 The drain ground circuit 312 is a circuit (source follower) in which the MOS transistor TR2 is grounded to the drain, and is provided at the output stage of the source ground circuit 311. The differential signal RF + , the RF signal amplified by the source ground circuit 311 is provided. RF is generated.

MOSトランジスタTR2のゲート端子Gには、直流成分遮断用のコンデンサC2を介して前段のソース設置回路311の出力信号が印加され、ドレイン端子Dは、第1の抵抗R1を介して電源ラインVddに接続され、ソース端子Sは、第2の抵抗R2を介して接地(GND)されている。そして、MOSトランジスタTR2のドレイン端子D及びソース端子Sそれぞれからの出力Vd2,Vsが、ソース接地回路311の出力信号となり、ドレイン端子Dが差動出力端子RFに接続され、ソース端子Sが容量部313を介して差動出力端子RFに接続されている。 The output signal of the previous source installation circuit 311 is applied to the gate terminal G of the MOS transistor TR2 via the DC component blocking capacitor C2, and the drain terminal D is connected to the power supply line Vdd via the first resistor R1. The source terminal S is connected and grounded (GND) via the second resistor R2. The outputs from the drain terminal D and source terminal S of the MOS transistor TR2 Vd2, Vs becomes the output signal of the common source circuit 311, the drain terminal D is the differential output terminal RF - is connected to the source terminal S is capacity It is connected to the differential output terminal RF + via the part 313.

ここで、ドレイン接地回路312における第1の抵抗R1及び第2の抵抗R2は、差動信号RF,RFの振幅の大きさが一致するよう、その抵抗値が定められている。 Here, the resistance values of the first resistor R1 and the second resistor R2 in the common drain circuit 312 are determined so that the amplitudes of the differential signals RF + and RF are equal.

容量部313は、MOSトランジスタTR2のソース端子Sと差動出力端子RFとの間に設けられており、MOSトランジスタTR2のソース端子Sからの出力信号Vsの位相を調整するための容量素子でなる。すなわち、MOSトランジスタTR2のドレイン端子Dからの出力Vd2とソース端子Sからの出力Vsとは位相がほぼ180度ずれた信号となっているが、MOSトランジスタTr2の寄生抵抗や寄生容量の影響により完全に180度になってはおらず僅かな誤差がある。容量部313は、この出力Vd2,Vsの位相差の誤差を調整し、差動信号RF,RFの位相差が完全に180度となるよう、その容量値Cが定められている。 The capacitor unit 313 is provided between the source terminal S of the MOS transistor TR2 and the differential output terminal RF +, and is a capacitor element for adjusting the phase of the output signal Vs from the source terminal S of the MOS transistor TR2. Become. That is, the output Vd2 from the drain terminal D of the MOS transistor TR2 and the output Vs from the source terminal S are signals that are almost 180 degrees out of phase, but are completely affected by the parasitic resistance and parasitic capacitance of the MOS transistor Tr2. However, there is a slight error. The capacitance unit 313 adjusts the error of the phase difference between the outputs Vd2 and Vs, and the capacitance value C is determined so that the phase difference between the differential signals RF + and RF is completely 180 degrees.

なお、容量部313は、ディスクリート素子で構成することも可能ではあるが、1GHz以上の高周波信号の位相を調整するための容量であるため、微小な容量で足りる。そこで、本実施形態では、一例として、ウェル抵抗でなる抵抗素子を短絡することで、接合容量或いは基板寄生容量を容量素子として利用する。   Note that the capacitor 313 can be composed of discrete elements, but it is a capacitor for adjusting the phase of a high-frequency signal of 1 GHz or more, and thus a minute capacitor is sufficient. Therefore, in the present embodiment, as an example, a junction capacitor or a substrate parasitic capacitance is used as a capacitor element by short-circuiting a resistor element formed of a well resistor.

[作用・効果]
このように、本実施形態におけるGPS受信装置1では、差動信号生成回路31は、入力されたRF信号を増幅するソース接地回路311と、増幅されたRF信号の差動信号RF,RFを生成するドレイン接地回路312と、生成された差動信号RF,RFの位相差を調整する容量部313とを備えて構成される。つまり、増幅用素子としてソース接地回路311のMOSトランジスタTR1のみで済むため、差動トランジスタ対を利用した従来の差動増幅回路に比較して、増幅用素子の数を減らし、S/N比の改善を図った差動信号生成回路31となる。また、ドレイン接地回路312における第1の抵抗R1及び第2の抵抗R2によって、差動信号RF,RFの振幅が同じとなるとともに、容量部313によって、差動信号RF,RFの位相差がほぼ180度となるように調整される。
[Action / Effect]
As described above, in the GPS receiver 1 according to the present embodiment, the differential signal generation circuit 31 includes the source grounding circuit 311 that amplifies the input RF signal, and the differential signals RF + and RF − of the amplified RF signal. The drain grounding circuit 312 for generating the signal and the capacitor unit 313 for adjusting the phase difference between the generated differential signals RF + and RF are configured. That is, since only the MOS transistor TR1 of the source grounded circuit 311 is required as an amplifying element, the number of amplifying elements is reduced and the S / N ratio is reduced as compared with a conventional differential amplifying circuit using a differential transistor pair. The differential signal generation circuit 31 is improved. The first and second resistors R1 and R2 in the grounded drain circuit 312 have the same amplitude of the differential signals RF + and RF , and the capacitance unit 313 allows the differential signals RF + and RF to be The phase difference is adjusted to be approximately 180 degrees.

[変形例]
なお、本発明の適用可能な実施形態は、上述の実施形態に限定されることなく、本発明の趣旨を逸脱しない範囲で適宜変更可能なのは勿論である。
[Modification]
It should be noted that embodiments to which the present invention can be applied are not limited to the above-described embodiments, and can be appropriately changed without departing from the spirit of the present invention.

(A)容量部313
例えば、容量部313は、ドレイン接地回路312のMOSトランジスタTR2のソース端子S側ではなく、ドレイン端子D側に設けても良いし、或いは、ソース端子S及びドレイン端子Dの両方側に設けても良い。
(A) Capacitor 313
For example, the capacitor 313 may be provided on the drain terminal D side instead of the source terminal S side of the MOS transistor TR2 of the drain ground circuit 312 or may be provided on both the source terminal S and the drain terminal D side. good.

(B)ミキサー34
また、上述の実施形態では、ミキサー34はギルバード・セル・ミキサーとしたが、例えばダブル・バランス型のミキサーなど、入力信号が差動形式で入力されるミキサーであれば、何れでも良い。
(B) Mixer 34
In the above-described embodiment, the mixer 34 is a Gilbird cell mixer. However, any mixer may be used as long as an input signal is input in a differential format, such as a double balance type mixer.

(C)受信装置
また、上述の実施形態では、GPS信号を受信するGPS受信装置1としたが、例えばGLONASS(GLObal Navigation Satellite System)といった他の衛星測位システムにおける衛星信号を受信する受信装置にも同様に適用可能である。
(C) Receiving Device In the above-described embodiment, the GPS receiving device 1 that receives GPS signals is used. However, the receiving device that receives satellite signals in other satellite positioning systems such as GLONASS (GLObal Navigation Satellite System) is also used. The same applies.

1 GPS受信装置、10 GPSアンテナ、20 RF受信回路部、21 SAWフィルター、22 LNA、23 増幅部、24 ADC、30 周波数変換部、31 差動信号生成回路、32 局部発振信号生成部、33 差動変換回路、34 ミキサー、35 LPF、40 ベースバンド部、311 ソース接地回路、312 ドレイン接地回路、313 容量部、TR1 MOSトランジスタ、Tr2 MOSトランジスタ DESCRIPTION OF SYMBOLS 1 GPS receiver, 10 GPS antenna, 20 RF receiving circuit part, 21 SAW filter, 22 LNA, 23 Amplifying part, 24 ADC, 30 Frequency conversion part, 31 Differential signal generation circuit, 32 Local oscillation signal generation part, 33 Difference Dynamic conversion circuit, 34 mixer, 35 LPF, 40 baseband section, 311 source ground circuit, 312 drain ground circuit, 313 capacitance section, TR1 MOS transistor, Tr2 MOS transistor

Claims (3)

1GHz以上の規定高周波信号がゲートに入力されるソース接地回路と、
前記ソース接地回路の出力段に設けられ、第1の抵抗を介してドレインが電源ラインに接続され、第2の抵抗を介してソースが接地されて、ドレイン及びソースから前記規定高周波信号の差動信号を出力するドレイン接地回路と、
を備え、
前記第1の抵抗と前記第2の抵抗とは、前記ドレイン接地回路のドレイン及びソースそれぞれからの出力信号の振幅を同等に調整するための抵抗値でなる、
差動信号生成回路。
A grounded source circuit in which a specified high-frequency signal of 1 GHz or more is input to the gate;
Provided at the output stage of the grounded source circuit, the drain is connected to the power supply line through the first resistor, the source is grounded through the second resistor, and the differential of the specified high-frequency signal from the drain and the source A grounded drain circuit for outputting a signal;
With
The first resistor and the second resistor are resistance values for adjusting the amplitude of the output signal from each of the drain and the source of the common drain circuit,
Differential signal generation circuit.
前記ドレイン接地回路のソースと前記差動信号の出力端との間に、ドレイン及びソースそれぞれからの出力信号の位相差を180度に調整するための容量が設けられてなる、
請求項1に記載の差動信号生成回路。
A capacitor for adjusting the phase difference of the output signals from the drain and the source to 180 degrees is provided between the source of the grounded drain circuit and the output terminal of the differential signal.
The differential signal generation circuit according to claim 1.
1GHz以上の規定高周波信号の受信信号に局部発振信号を乗算して当該局部発振信号の高調波と前記規定高周波信号の周波数との差周波数の信号を取り出す周波数変換回路であって、
前記受信信号を入力する請求項1又は2に記載の差動信号生成回路と、
前記差動信号生成回路から出力される差動信号それぞれに前記局部発振信号を乗算するミキサー部と、
前記ミキサー部の出力信号から前記差周波数の信号成分を抽出するフィルター部と、
を備えた周波数変換回路。
A frequency conversion circuit for multiplying a reception signal of a specified high frequency signal of 1 GHz or more by a local oscillation signal and extracting a signal having a difference frequency between a harmonic of the local oscillation signal and the frequency of the specified high frequency signal,
The differential signal generation circuit according to claim 1 or 2, wherein the reception signal is input;
A mixer unit that multiplies each of the differential signals output from the differential signal generation circuit by the local oscillation signal;
A filter unit for extracting the signal component of the difference frequency from the output signal of the mixer unit;
A frequency conversion circuit comprising:
JP2009267183A 2009-11-25 2009-11-25 Differential signal generation circuit and frequency conversion circuit Withdrawn JP2011114440A (en)

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Country Link
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Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH11298295A (en) * 1998-04-10 1999-10-29 Mitsubishi Electric Corp Unbalance-balance converter and balanced mixer
JP2009206554A (en) * 2008-02-26 2009-09-10 Nsc Co Ltd Am broadcasting reception circuit

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH11298295A (en) * 1998-04-10 1999-10-29 Mitsubishi Electric Corp Unbalance-balance converter and balanced mixer
JP2009206554A (en) * 2008-02-26 2009-09-10 Nsc Co Ltd Am broadcasting reception circuit

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