JP2011113504A - Touch panel input device, device for driving touch panel, method for driving touch panel, and system display - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To increase sensitivity in detecting a touch in a capacitive coupling type touch panel. <P>SOLUTION: A touch panel input device 6 is provided with: a plurality of first electrodes Y<SB>1</SB>to Y<SB>n</SB>arranged along a first direction in a touch region 61a to be touched by a contact body; a plurality of second electrodes X<SB>1</SB>to X<SB>m</SB>arranged so as to cross the plurality of first electrodes along a second direction which is orthogonal to the first direction in the touch region; selection circuits 7 and 8 for selecting one of the plurality of first electrodes and one of the plurality of second electrodes, and for electrically floating at least one of the non-selected first electrodes and the non-selected second electrodes; and a capacitance detection circuit 9 for detecting a characteristic value based on the capacitance of a capacitor connected to the first electrode and the second electrode selected by the selection circuit. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a touch panel input device using a capacitive coupling method, a touch panel drive device, a touch panel drive method, and a system display including the touch panel input device.

  In a conventional capacitively coupled touch panel, a plurality of electrodes are sequentially selected and charged by a scanning circuit, and the unselected electrodes are connected to a power source set to a predetermined potential. Specifically, a plurality of X coordinate electrodes (X1 to X4) are provided on the surface of the substrate of the touch panel. A plurality of Y coordinate electrodes (Y1 to Y4) are provided so as to be orthogonal to the X coordinate electrodes via an insulating film. One end of each Y coordinate electrode is connected to the Y drive circuit (30), and each X coordinate electrode is connected to the X detection circuit (40). The Y drive circuit sequentially selects a plurality of Y coordinate electrodes and connects them to a reference potential power supply (VL), and a plurality of unselected Y coordinate electrodes have a high potential power supply (VH) having a voltage higher than the reference potential. To connect to. The X detection circuit sequentially selects a plurality of X coordinate electrodes and connects them to the integration circuit. Then, a current flows to a capacitor formed at the intersection of the Y coordinate electrode connected to the high potential power source and the X coordinate electrode connected to the integrating circuit. The integration circuit integrates this current value and outputs the integration value to the coordinate detection circuit (50).

  When the touch panel is driven, if a touch area is touched with a finger, a new capacitor is generated between the X coordinate electrode and the Y coordinate electrode and the finger. For this reason, more charges are accumulated in the X coordinate electrode and the Y coordinate electrode passing under the finger than when the touch is not performed. And the integral value by the integrating circuit connected to the X coordinate electrode increases. The presence or absence of touch and the touch position are determined by detecting the increased integrated value (see Patent Document 1).

JP 2009-015489 A

However, since a reference voltage or a high voltage is applied to all the Y coordinate electrodes, when a certain Y coordinate electrode is selected and the voltage rises, a capacitor formed between adjacent Y coordinate electrodes is also charged. . As a result, the electric charge flowing into the selected Y coordinate electrode increases as compared with the case where no other Y coordinate electrode is adjacent. Since the capacitor formed by touching the touch panel is very small, it is difficult to accurately detect whether or not the charge flowing into the Y coordinate electrode is larger than when the touch is not touched. That is, it has been difficult to increase the detection sensitivity for detecting whether or not the touch panel has been touched.
Therefore, the problem to be solved by the present invention is to increase the detection sensitivity for detecting the presence or absence of touch in a capacitively coupled touch panel.

In order to solve the above problems, according to one aspect of the present invention,
A plurality of first electrodes arranged along a first direction in a touch area touched by the contact body;
A plurality of second electrodes arranged crossing the plurality of first electrodes along a second direction orthogonal to the first direction in the touch region;
One of the plurality of first electrodes and one of the plurality of second electrodes are selected, and at least one of the non-selected first electrodes and the non-selected second electrodes is electrically connected A selection circuit for floating,
A capacitance detection circuit that detects a characteristic value based on a capacitance of a capacitor formed by being connected to the first electrode and the second electrode selected by the selection circuit;
A touch panel input device is provided.

Preferably, the capacitance detection circuit includes a charging circuit for charging the capacitor, and a charging time from when charging by the charging circuit is started until a charging voltage of the capacitor reaches a predetermined threshold value as the characteristic value. A charging time measuring circuit for measuring; a discharging circuit for discharging the capacitor after the charging voltage reaches the predetermined threshold; and a voltage of the second electrode after the discharging by the discharging circuit is started. A discharge time measuring circuit that measures a discharge time until the lower threshold value is reached as the characteristic value.
Preferably, there is provided a control circuit for obtaining a charge / discharge time ratio comprising a ratio of the charge time to the discharge time for the capacitor and determining whether or not the value of the charge / discharge time ratio falls within a predetermined range.
Preferably, the control circuit is configured such that when the total time of the charging time and the discharging time is greater than a predetermined reference value and the charge / discharge time ratio is included in the predetermined range, the capacitor of the touch area A detection signal for detecting that the contact body has been touched on the formation area is output, and in other cases, the detection signal is not output.
Preferably, the selection circuit electrically floats the non-selected first electrodes and the non-selected second electrodes.

According to another aspect of the invention,
A plurality of first electrodes arranged along a first direction in a touch area touched by a contact body; and the first electrode along a second direction orthogonal to the first direction in the touch area; A touch panel drive device for driving a touch panel having a plurality of second electrodes arranged in an intersecting manner,
One of the plurality of first electrodes and one of the plurality of second electrodes are selected, and at least one of the non-selected first electrodes and the non-selected second electrodes is electrically connected A selection circuit for floating,
A capacitance detection circuit that detects a characteristic value based on a capacitance of a capacitor formed by being connected to the first electrode and the second electrode selected by the selection circuit;
There is provided a touch panel drive device comprising:

Preferably, the capacitance detection circuit includes a charging circuit for charging the capacitor, and a charging time from when charging by the charging circuit is started until a charging voltage of the capacitor reaches a predetermined threshold value as the characteristic value. A charging time measuring circuit for measuring; a discharging circuit for discharging the capacitor after the charging voltage reaches the predetermined threshold; and a voltage of the second electrode after the discharging by the discharging circuit is started. A discharge time measuring circuit that measures a discharge time until the lower threshold value is reached as the characteristic value.
Preferably, there is provided a control circuit for obtaining a charge / discharge time ratio comprising a ratio of the charge time to the discharge time for the capacitor and determining whether or not the value of the charge / discharge time ratio falls within a predetermined range.
Preferably, the control circuit is configured such that when the total time of the charging time and the discharging time is greater than a predetermined reference value and the charge / discharge time ratio is included in the predetermined range, the capacitor of the touch area A detection signal for detecting that the contact body has been touched on the formation area is output, and in other cases, the detection signal is not output.
Preferably, the selection circuit causes the non-selected first electrodes and the non-selected second electrodes to be in an electrically floating state. The touch panel drive device according to item.

According to another aspect of the invention,
A plurality of first electrodes arranged along a first direction in a touch area touched by a contact body; and the first electrode along a second direction orthogonal to the first direction in the touch area; A touch panel driving method for driving a touch panel having a plurality of second electrodes arranged in an intersecting manner,
Sequentially selecting each of the first electrodes;
Sequentially selecting each of the second electrodes,
At least one of each of the first electrodes not selected and each of the second electrodes not selected is set in an electrically floating state;
A touch panel driving method is provided that detects a characteristic value based on a capacitance of a capacitor formed by being connected to the selected first electrode and the second electrode.

Preferably, a charging time from when the capacitor is charged and the charging is started until a charging voltage of the capacitor reaches a predetermined upper threshold is measured as the characteristic value, and the charging voltage is the predetermined upper threshold. Then, discharging of the capacitor is started, and a discharge time from when the discharging of the capacitor is started until the charging voltage becomes a lower threshold lower than the upper threshold is measured as the characteristic value.
Preferably, a charge / discharge time ratio comprising a ratio between the charge time and the discharge time is obtained, a total time of the charge time and the discharge time is greater than a predetermined reference value, and the charge / discharge time ratio is within the predetermined range. If it is included in the touch area, it is determined that the contact body is touched on the capacitor formation area of the touch area, and otherwise, it is not determined that the contact body is touched.

According to another aspect of the invention,
A display panel;
A plurality of first electrodes arranged along a first direction in a touch area touched by a contact body, and the plurality of first electrodes along a second direction orthogonal to the first direction in the touch area. A plurality of second electrodes arranged crossing the electrodes, and a touch panel provided on the display surface side of the display;
A drive device for driving the touch panel,
The drive device
One of the plurality of first electrodes and one of the plurality of second electrodes are selected, and at least one of the non-selected first electrodes and the non-selected second electrodes is electrically connected A selection circuit for floating,
A capacitance detection circuit that detects a characteristic value based on a capacitance of a capacitor formed by being connected to the first electrode and the second electrode selected by the selection circuit;
A system display is provided.

Preferably, the capacitance detection circuit includes a charging circuit for charging the capacitor, and a charging time from when charging by the charging circuit is started until a charging voltage of the capacitor reaches a predetermined threshold value as the characteristic value. A charging time measuring circuit for measuring; a discharging circuit for discharging the capacitor after the charging voltage reaches the predetermined threshold; and a voltage of the second electrode after the discharging by the discharging circuit is started. A discharge time measuring circuit that measures a discharge time until the lower threshold value is reached as the characteristic value.
Preferably, there is provided a control circuit for obtaining a charge / discharge time ratio comprising a ratio of the charge time to the discharge time for the capacitor and determining whether or not the value of the charge / discharge time ratio falls within a predetermined range.
Preferably, the control circuit is configured such that when the total time of the charging time and the discharging time is greater than a predetermined reference value and the charge / discharge time ratio is included in the predetermined range, the capacitor of the touch area A detection signal for detecting that the contact body has been touched on the formation region is output, and in other cases, the detection signal is not output.
Preferably, the selection circuit electrically floats the non-selected first electrodes and the non-selected second electrodes.

  ADVANTAGE OF THE INVENTION According to this invention, the detection sensitivity which detects the presence or absence of a touch can be raised in a capacitive coupling type touch panel.

It is the disassembled perspective view which showed the system display in 1st Embodiment of this invention. It is the schematic block diagram which showed the touchscreen input device in the same embodiment. It is the front view which showed the touchscreen input device in the same embodiment. It is IV-IV sectional drawing of FIG. FIG. 4 is a circuit diagram illustrating a first scanning circuit in the same embodiment. FIG. 6 is a circuit diagram showing a second scanning circuit in the same embodiment. It is the circuit diagram which showed the electrostatic capacitance detection circuit in the same embodiment. It is a timing chart of the touch panel input device in the embodiment. It is a timing chart of the touch panel input device in the embodiment. It is the circuit diagram which showed the electrostatic capacitance detection circuit in 2nd Embodiment of this invention. It is a timing chart of the touch panel input device in the embodiment. It is a timing chart of the touch panel input device in the embodiment. It is a graph which shows the voltage of the wiring of the 2nd scanning circuit in the embodiment.

  Hereinafter, preferred embodiments for carrying out the present invention will be described with reference to the drawings. However, although various technically preferable limitations for implementing the present invention are given to the embodiments described below, the scope of the invention is not limited to the following embodiments and illustrated examples.

(First embodiment)
First, the configuration of the system display 1 according to the first embodiment of the present invention will be described.
FIG. 1 is an exploded perspective view of an example of a system display 1. As shown in FIG. 1, the system display 1 includes an upper case 2, a lower case 3, a liquid crystal display panel 4, a backlight 5, a touch panel input device 6, and the like. Hereinafter, the configuration in a state where the system display 1 is assembled will be specifically described.

  The lower case 3 is assembled in a nested manner with respect to the upper case 2. A rectangular display window 22 is opened in the top plate 21 of the upper case 2. A rectangular window 32 is opened in the bottom plate 31 of the lower case 3.

  A liquid crystal display panel 4 and a touch panel input device 6 are provided inside the upper case 2 and the lower case 3. The liquid crystal display panel 4 is mounted on the bottom plate 31 of the lower case 3. The liquid crystal display panel 4 is configured as follows.

  The liquid crystal display panel 4 is of an active matrix drive system, for example. In the liquid crystal display panel 4, the upper substrate 42 faces the lower substrate 41. A sealing material is provided in a frame shape along the edge portion of the upper substrate 42, the sealing material is sandwiched between the upper substrate 42 and the lower substrate 41, and the upper substrate 42 and the lower substrate 41 are bonded by the sealing material. ing. Liquid crystal is sealed between the lower substrate 41 and the upper substrate 42 and inside the sealing material. Since the size of the lower substrate 41 is larger than the size of the upper substrate 42, a part of the lower substrate 41 protrudes from the edge of the upper substrate 42. A portion where the lower substrate 41 and the upper substrate 42 overlap is a display area. On the upper surface in the display area of the lower substrate 41, a plurality of scanning lines are provided so as to extend in the horizontal direction in parallel with each other, and a plurality of signal lines extend in the vertical direction in parallel with each other. Is provided. A thin film transistor is formed at each intersection of the scanning line and the signal line. The gate electrode of the thin film transistor is connected to the scanning line, one of the source electrode and the drain electrode of the thin film transistor is connected to the signal line, and the other is connected to the transparent pixel electrode. A plurality of pixel electrodes are arranged in a matrix on the surface of the lower substrate 41. On the other hand, a transparent common electrode is formed on the surface of the upper substrate 42 facing the lower substrate 41. Alignment films are formed on the surfaces of the pixel electrode and the common electrode, respectively. Further, a color filter is formed on the upper substrate 42. A polarizing plate 43 is stuck on the upper substrate 42.

  One end portion of the FPC 44 is joined to the non-display area 41 a that protrudes from the edge of the upper substrate 42 in the lower substrate 41. An IC chip 45 is surface-mounted on the non-display area 41a. The IC chip 45 includes a driver that drives the liquid crystal display panel 4. A plurality of output terminals of the IC chip 45 are connected to scanning lines and signal lines extending from the display area. The plurality of input terminals of the IC chip 45 are connected to a plurality of lead wirings formed on the non-display area 41a, and these lead wirings are formed from one end portion to the other end portion of the FPC 44. Each is connected to the wiring. A terminal formed at the other end of the FPC 44 is inserted into an electronic board (not shown).

  The backlight 5 is disposed on the lower side of the lower case 3 so as to face the lower surface of the liquid crystal display panel 4 through the window 32. Specifically, the backlight 5 faces the lower substrate 41 of the liquid crystal display panel 4. The backlight 5 is a surface light emitting device and emits light toward the liquid crystal display panel 4. The backlight 5 is, for example, an array of point light emitting elements such as LEDs arranged in a matrix, a combination of point light emitting elements such as LEDs arranged and a light guide plate, a linear light emitting element such as a cold cathode tube, and a light guide plate. Or a surface light emitting element such as an electroluminescence element. An FPC 51 is connected to the backlight 5. The FPC 51 is connected to an electric board (not shown).

  The touch panel input device 6 includes a touch panel 6a, a flexible circuit sheet (hereinafter referred to as FPC) 65, and an IC chip 66. The IC chip 66 is surface-mounted on the touch panel 6a by a COG (Chip On Glass) method. The FPC 65 is bonded to the touch panel 6a. A touch panel 6 a is accommodated inside the upper case 2 and the lower case 3. The touch panel 6 a is overlaid on the display surface of the liquid crystal display panel 4. That is, the touch panel 6 a has a touch area 61 a and is overlaid on the polarizing plate 43 of the liquid crystal display panel 4. The upper case 2 is put on the touch panel 6a. The touch panel 6a faces the display window 22 of the upper case 2, and the display window 22 is blocked by the touch panel 6a.

  In the above description, the touch panel 6a is attached to the display surface of the liquid crystal display panel 4, but may be attached to the display surface of a display other than the liquid crystal display panel 4. For example, the touch panel 6a may be attached to the display surface of an organic electroluminescence display, a plasma display, an inorganic electroluminescence display, a light emitting diode display, a field emission display, a vacuum fluorescent display, a cathode ray tube, or electronic paper. The display may be a dot matrix display type display or a segment display. The display may be a self-luminous display, a transmissive display, or a reflective display. When the display is a self-luminous or reflective display, the backlight 5 may not be provided.

  Hereinafter, the touch panel input device 6 will be described in detail. 2 is a schematic configuration diagram of the touch panel input device 6, FIG. 3 is a front view of the touch panel input device 6, and FIG. 4 is a sectional view taken along the line IV-IV in FIG.

  The touch panel 6a is of a capacitive coupling type. In the touch panel 6a, the rectangular upper substrate 62 faces the rectangular lower substrate 61 as shown in FIG. The length of the lower substrate 61 in the short direction is equal to the length of the upper substrate 62 in the short direction, and the length of the lower substrate 61 in the longitudinal direction is longer than that of the upper substrate 62. Therefore, in a state where one short side of the lower substrate 61 and one short side of the upper substrate 62 are aligned and overlapped, a part of the lower substrate 61 protrudes from the edge of the upper substrate 62. A portion where the lower substrate 61 and the upper substrate 62 overlap is a touch region 61a.

As shown in FIG. 3, a plurality of Y electrodes Y _{1 to} Y _{n that} are _first electrodes are provided on the upper surface of the touch region 61 a of the lower substrate 61. Specifically, n (n− = 2 or more natural numbers) Y electrodes Y _{1 to} Y _n are formed to be parallel to each other and extend along the short direction of the touch region 61a. Further, the upper surface of the touch area 61a, a plurality of X electrodes _X 1 to X _m is provided as a second electrode. Specifically, m (m− = 2 or more natural number) X electrodes X _{1 to} X _m are provided so as to extend in a direction perpendicular to the Y electrodes Y _{1 to} Y _n .

Each of the Y electrodes Y _{1 to} Y _n has a plurality of electrode patterns Y ₁ a to Y _n a and a plurality of connecting portions Y ₁ b to Y _n b. The electrode patterns _Y 1 to Y _n a and the coupling portion _Y 1 _{b~Y n} b is formed of a transparent conductive material such as indium tin oxide (ITO). Specifically, the electrode patterns Y ₁ to Y n _a having a substantially square shape is formed in a matrix in the touch area 61a a on the lower substrate 61. Between the electrode patterns _{Y 1} a and _Y 1 a to both electrode patterns adjacent in the lateral direction of the touch area 61a _{Y n} a and _{Y n} a, coupling portion _Y 1 _{b~Y n} b is the electrode pattern _Y 1 a to It is formed integrally with Y _na . Then, the electrode pattern _{Y 1} a and _Y 1 a to the electrode pattern _{Y n} a and _{Y n} a is conductive, respectively.

X electrodes _X 1 to X _m has a plurality of electrode patterns _X 1 A to X _m a and a plurality of bridges _X 1 _{b~X m} b. Specifically, electrode patterns X ₁ a to X _m a having a substantially square shape are arranged in a matrix. The electrode patterns _X 1 _{a~X m} a is formed of a transparent conductive material such as ITO similarly to the Y electrodes _Y 1 to Y _n. The electrode patterns _X 1 _{a~X m} a is formed on the same plane and the Y electrode _Y 1 to Y _n. Further, the electrode patterns _X 1 _{a~X m} a, the connecting portions adjacent in the longitudinal direction of the touch area 61a _{Y 1} b and _Y 2 B to connecting portion _{Y (n-1)} b and _{Y n} b respectively between the positioned. A pair of corners X ₁ c of each electrode pattern X ₁ a to X _m a is directed to both short sides of the lower substrate 61. Then, the electrode pattern _{X 1} a and _X 1 a to the electrode pattern _{X m} and _{X m} adjacent in the longitudinal direction of the touch area 61a is spaced so as not to touch the connecting portion _Y 1 _{b~Y n} b, together and facing the corner _{X 1} c and _X 1 _{c~X m} c and _{X m} c. Further, another pair of corner _X 1 _{d~X m} d of each electrode pattern _X 1 _{a~X m} a is oriented in a direction in both long sides of the lower substrate 61, respectively. Then, the electrode patterns X ₁ a and X ₂ a to X _(m−1) a and X _m a that are adjacent to each other in the short direction of the touch area 61 a are slightly spaced from each other at their angles X ₁ d and X _2. d~ angle _{X (m-1)} are facing the d and _{X m} d.

On the Y electrodes _Y 1 to Y _n and the electrode pattern _X 1 A to X _m a is the insulating film 63 as shown in FIG. 4 is deposited on Betaichimen, Y electrodes _Y 1 to Y _n and the electrode pattern X _{1 a to} X _m a are covered with an insulating film 63. Metal bridge _X 1 _{b~X m} b is provided from the upper surface of the insulating film 63 over the electrode pattern _X 1 _{a~X m} a. Specifically, one end of the bridge _X 1 _{b~X m} b formed in a U-shape, as well as through the insulating film 63, the electrode pattern _{X 1} adjacent in the longitudinal direction of the touch area 61a a and _X 1 a We are in contact with - the electrode pattern _{X m} a and _{X m} one at the corner of a _X 1 c~X _m c. The other end of the bridge _X 1 _{b~X m} b makes contact with the adjacent electrode patterns _{X 1} a and _X 1 a to the electrode pattern _{X m} a and _{X m} a while the corners _X 1 _{c~X m} c of ing. Then, the electrode pattern _{X 1} a and _X 1 a to the electrode pattern _{X m} a and _{X m} a is conductive, respectively. The X electrodes _X 1 to X _m are provided in this way.

Each bridge X ₁ b of the X electrode X ₁ crosses over the connecting portions Y ₁ b to Y _n b and intersects with the Y electrodes Y _{1 to} Y _n , respectively. Also, another bridge _X 2 _{b~X m} b, straddle over the connecting portion _Y 1 _{b~Y n} b, intersect respectively and the Y electrode _Y 1 to Y _n. Then, the insulating film 64 so as to cover the bridge _X 1 _{b~X m} b is deposited Betaichimen. An adhesive is applied on the insulating film 64, and the upper substrate 62 is bonded. In this way, the touch panel 6a is configured. In touch area 61a of the touch panel 6a, since a plurality of electrode patterns _X 1 _{a~X m} a and a plurality of electrode patterns _Y 1 to Y _n a is provided adjacent to each other, the capacitive component between the electrodes Is formed. The capacitive component becomes a form which is connected to the respective electrode patterns _Y 1 to Y _n a and the electrode patterns _X 1 _{a~X m} a, when it was used as a capacitor _C 11 _{-C mn,} FIG as an equivalent circuit It becomes the form shown in 2.

Capacitor C _b shown in FIG. 2, of the X electrodes X ₁ to X _m, a capacitance component is formed between the adjacent. Here, when a contact body such as a finger contacts the upper substrate 62, a capacitor C _f is formed between the electrode pattern X _i a and the electrode pattern Y _j a in the vicinity of the contact portion. For example, as shown in FIG. 2, between the contact body comes into contact with the upper substrate 62 in the top of the near intersections between the X electrode X ₂ and the Y electrodes Y _2, an electrode pattern X ₂ a and the electrode pattern Y ₂ a , i.e. the capacitor _{C f} is formed between the X electrode _{X 2} and the Y electrodes _{Y 2.}

  As shown in FIGS. 1 and 3, the FPC 65 is connected to the touch panel 6a. Specifically, one end portion of the FPC 65 is bonded to the non-touch area 61 b that protrudes from the edge of the upper substrate 62 in the lower substrate 61. The FPC 65 extends from the inside of the upper case 2 and the lower case 3 to the outside of the upper case 2 and the lower case 3. Wiring for supplying power to the IC chip 66 and transmitting signals is formed from one end portion of the FPC 65 to the other end portion. A terminal is formed at the tip of the FPC 65.

An IC chip 66 is surface-mounted on the touch panel 6a. Specifically, the IC chip 66 is surface-mounted on the non-touch area 61 b that protrudes from the edge of the upper substrate 62 in the lower substrate 61. The plurality of output terminals of the IC chip 66, X electrodes ₁ to X exiting extending from the touch area 61a _m and Y electrodes _Y 1 to Y _n are connected. The plurality of input terminals of the IC chip 66 are connected to a plurality of routing wirings formed on the non-touch area 61b, and these routing wirings are a plurality of wirings of the FPC 65 bonded on the non-touch area 61b. Are connected to each. The terminals of the FPC 65 are inserted into an electronic board (not shown).

  The IC chip 66 includes a drive device 6b. As shown in FIG. 2, the driving device 6b includes a first scanning circuit 7, a second scanning circuit 8, a capacitance detection circuit 9, a control circuit 10, and the like.

The control circuit 10 operates the first scanning circuit 7, the second scanning circuit 8, and the capacitance detection circuit 9.
The first scanning circuit 7 is a selection circuit for sequentially selecting the Y electrodes _Y 1 to Y _n. A selected _{one of the} Y electrodes Y _{1 to} Y _n is grounded (becomes a reference potential), and an unselected one is electrically floated.
The second scanning circuit 8 is a selection circuit that sequentially selects the X electrodes X _{1 to} X _m when the Y electrodes Y _{1 to} Y _n are selected by the first scanning circuit 7. Of the X electrodes X _{1 to} X _m , those not selected become electrically floating.
The capacitance detection circuit 9 includes a selection of the Y electrodes Y _{1 to} Y _n by the first scanning circuit 7 and a selection of the X electrodes X _{1 to} X _m by the second scanning circuit 8. The capacitance of the capacitor formed between them is detected. The capacitance detection circuit 9 outputs a signal representing the detected capacitance.
Control circuit 10 determines the selected ones of the Y electrodes Y ₁ to Y _n, the presence or absence of the intersection touch in the vicinity of the selected ones of the X electrodes X ₁ to X _m. That is, the control circuit 10 determines the presence / absence of a touch based on the signal input from the capacitance detection circuit 9 and outputs a signal representing the determination result. For example, if the signal output from the control circuit 10 is 1 bit, the signal output from the control circuit 10 is “1” when there is a touch, and the control circuit 10 when there is no touch. The signal output from is “0”. Here, when the Y electrode Y ₁ and the X electrode X ₁ are selected by the first scanning circuit 7 and the second scanning circuit 8, the Y electrode Y _n and the X electrode are selected by the first scanning circuit 7 and the second scanning circuit 8. The signal output from the control circuit 10 until the time _Xm is selected represents the coordinates of the touch position.

As shown in FIG. 5, the first scanning circuit 7 includes a shift register 71, switches SW_Y1 to SW_Yn, and the like.
The Y electrodes Y _{1 to} Y _n are connected to the wiring (reference potential line) set to the reference potential (ground) via the switches SW_Y _{1 to} SW_Yn, respectively. Switch SW_Y1~SW_Yn, respectively, to open and close between the Y electrodes _Y 1 to Y _n and the reference potential line (on-off). For example, the switch SW_Y1 is in a closed state (on state) when the signal input from the shift register 71 is at a high level, and is in an open state (off state) when the signal is at a low level. The same applies to the switches SW_Y2 to SW_Yn.
The shift register 71 has n output terminals. Switches SW_Y1 to SW_Yn are connected to the respective output terminals. The shift register 71 in synchronization with the input of the set signal ST _2, to select a switch SW_Y1～SW_Yn. For example, every time the set signal ST ₂ of a high level is input to the shift register 71, by the output terminal for outputting a high level signal is gradually shifted to sequentially neighboring switch SW_Y1~SW_Yn are sequentially selected .
The shift register 71, until the next set signal ST ₂ is input from the input of the set signal ST _2, and holds the selected state.
Which selected ones of the switches SW_Y1~SW_Yn is selected among the closed state (ON state), Y electrodes _Y 1 to Y _n is the reference potential. Meanwhile, those that are not selected among the switches SW_Y1~SW_Yn is opened (OFF state), those that are not selected among the Y electrodes Y ₁ to Y _n is electrically floating.
Set signal ST ₂ is output by the control circuit 10. Further, the control circuit 10 outputs the clock signal CK ₁ to the shift register 71, and the shift register 71 operates based on the clock signal CK ₁ .

As shown in FIG. 6, the second scanning circuit 8 includes a shift register 81, switches SW_X1 to SW_Xm, and the like.
The X electrodes X _{1 to} X _m are connected to the wiring 84 via switches SW_X 1 to SW_Xm, respectively. Switch SW_X1~SW_Xm, respectively, to open and close between the X electrodes _X 1 to X _m and the wiring 84. For example, the switch SW_X1 is in a closed state (on state) when the signal input from the shift register 81 is at a high level, and is in an open state (off) state when the signal is at a low level. The same applies to the switches SW_X2 to SW_Xm.
The shift register 81 has m output terminals. The switches SW_X1 to SW_Xm are connected to the output terminals, respectively. The shift register 81 in synchronization with the input of the set signal ST _3, selects the switch SW_X1～SW_Xm. For example, every time the set signal ST ₃ of a high level is input, by an output terminal a high level signal is output shifts to sequentially neighboring switch SW_X1~SW_Xm are sequentially selected.
The shift register 81, until the next set signal ST ₃ from the input of the set signal ST ₃ is input, it retains its selected state.
The selected one of the switches SW_X1 to SW_Xm closes the wiring 84. As a result, a selected _one of the X electrodes X _{1 to} X _m conducts to the wiring 84. On the other hand, an unselected switch among the switches SW_X1 to SW_Xm opens between the wiring 84. As a result, the X electrodes X _{1 to} X _m that are not selected are disconnected from the wiring 84 and become electrically floating.
Set signal ST ₃ is output by the control circuit 10. Further, the control circuit 10 outputs the clock signal CK ₂ to the shift register 81.

As shown in FIG. 7, the capacitance detection circuit 9 includes a charging circuit 91, a charging time measuring circuit 92, a determination circuit 93, a discharging circuit 94, and the like.
Charging circuit 91, the charging time measuring circuit 92 and discharge circuit 94, the set signal ST ₁ which is output by the control circuit 10 is input.
The charging circuit 91 inputs the set signal ST _1, begins to charge through the wiring 84. Specifically, the charging circuit 91 charges a capacitor formed between a selected _one of the Y electrodes Y _{1 to} Y _{n and} a selected one of the X electrodes X _{1 to} X _m .
Judging circuit 93, when the charging by the charging circuit 91, the voltage of the wiring 84 (the voltage of the wiring 84 corresponds to a voltage of a selected one of the X electrodes X ₁ to X _m. The same applies hereinafter.) The upper threshold When V _th H is reached, the reset signal R ₁ is output. Charging circuit 91, by the reset signal R ₁ is input, it terminates the charging.
Charging time measuring circuit 92 starts counting by the set signal ST ₁ is input, terminates the time counting by the reset signal R ₁ is input. Charging time measuring circuit 92 measures the time from the input a set signal ST ₁ until a reset signal is input R _1. The charging time measuring circuit 92 outputs a signal representing the measured time to the control circuit 10. The time measured by the charging time measuring circuit 92 is the static capacitance of the capacitor formed between the selected _one of the Y electrodes Y _{1 to} Y _{n and} the selected one of the X electrodes X _{1 to} X _m. It corresponds to the capacitance value.
Discharge circuit 94, the reset signal R ₁ is input as a set signal, begins to discharge through the line 84. Specifically, the discharge circuit 94 discharges a capacitor formed between a selected _one of the Y electrodes Y _{1 to} Y _{n and} a selected one of the X electrodes X _{1 to} X _m . Discharge circuit 94, by the set signal ST ₁ is input, it terminates the discharge.

The charging circuit 91 includes a constant voltage source 91a, a flip-flop 91b, a switch 91c, a resistor 91e, and the like.
The constant voltage source 91a generates a constant voltage. The constant voltage source 91a is connected to the capacitor 91d and the wiring 84 through a resistor 91e and a switch 91c. The switch 91c opens and closes the wiring 84 and the capacitor 91d and the constant voltage source 91a. The switch 91c is connected to the output terminal of the flip-flop 91b that is the first holding circuit. Flip-flop 91b, when the set signal ST ₁ to the set terminal is input closes the switch 91c, maintaining thereafter the closed state of the switch 91c to the reset signal R ₁ to the reset terminal is input. Flip-flop 91b, when the reset signal R ₁ is input to the reset terminal is opened the switch 91c, remain open switch 91c to thereafter set signal ST ₁ to the set terminal is input. Specifically, the flip-flop 91b outputs a high-level signal to the switch 91c when a low-level signal is input to the reset terminal and a high-level signal is input to the set terminal. As a result, the switch 91c is closed. Thereafter, the flip-flop 91b continues to output a high level signal until a high level signal is input to the reset terminal. Thereby, the closed state of the switch 91c continues. The flip-flop 91b outputs a low-level signal when a high-level signal is input to the reset terminal while a low-level signal is input to the set terminal. Thereby, the switch 91c is opened. Thereafter, the flip-flop 91b continues to output a high level signal until a high level signal is input to the set terminal. Thereby, the open state of the switch 91c is continued.
When the switch 91c is in the closed state (ON state), a predetermined constant voltage to selected ones of the X electrodes X ₁ to X _m by the constant voltage source 91a is applied. Then, a charge is charged in the selected _{one of} the X electrodes X _{1 to} X _m , and the voltage rises. That is, the selected ones of the X electrodes X ₁ to X _m, a capacitor formed between the selected ones of the Y electrodes Y ₁ to Y _n are charged.
A constant current source may be used instead of the constant voltage source 91a.

The capacitor 91d has a larger capacitance C _sum than the capacitors C _{11 to} C _mn . The capacitor 91d is connected between the wiring 84 and the reference potential.

The charging time measuring circuit 92 includes an AND gate 92a and a counter 92b. The determination circuit 93 includes a comparator 93a and an inverter 93b.
The wiring 84 is connected to the inverting input (−) terminal of the comparator 93a. A voltage source whose voltage is set to the upper threshold V _th H is connected to the non-inverting input (+) terminal of the comparator 93a. The comparator 93a compares the voltage of the wiring 84 with the upper threshold value V _th H. The comparator 93a outputs the comparison result to the AND gate 92a. Specifically, when the voltage of the wiring 84 is lower than the upper threshold value V _th H, the comparator 93a outputs a high level, and when the voltage of the wiring 84 is equal to or higher than the upper threshold value V _th H, the comparator 93a The output of 93a is at a low level.
The output of the comparator 93a is input to the AND gate 92a. The clock signal CK ₃ output by a control circuit 10, is input to the AND gate 92a. AND gate 92a outputs the output and logical multiplication of the clock signal CK ₃ of the comparator 93a to the counter 92b. Therefore, when the output of the comparator 93a is at a high level, the output of the AND gate 92a becomes a clock signal.
Set signal ST ₁ of a high level output by the control circuit 10 is inputted to the start terminal and preset terminal of the counter 92b.
The inverter 93b inverts the output of the comparator 93a. The output of the comparator 93a through an inverter 93b is signal inverted is reset signal R _1. Reset signal R ₁ of the high level signal of a low level output by the comparator 93a is inverted by the inverter 93b is input to the stop terminal of the counter 92b.
Counter 92b, when the set signal ST ₁ is input as a set signal and the preset signal, the preset count value and starts counting of the clock signal input from the AND gate 92a. Counter 92b is a period from the set signal ST ₁ is inputted to the reset signal _{R 1} is input, it counts the clock output from the AND gate 92a. The counter 92b is reset signal R ₁ of a high level is input as a stop signal to stop the counting. Then, it outputs the count value N _1, the control circuit 10 as a characteristic value based on the electrostatic capacitance of the capacitor.

The discharge circuit 94 includes a flip-flop 94a, a switch 94b, and the like.
A switch 94b is connected in series between the wiring 84 and the reference potential. The switch 94b opens and closes between the wiring 84 and the reference potential. The switch 94b is connected to the output terminal of the flip-flop 94a that is the second holding circuit. Flip-flop 94a is reset signal R ₁ is input as a set signal to the set terminal closes the switch 94b, is maintained then a closed switch 94b until the set signal ST ₁ to the reset terminal is input. Flip-flop 94a, when the set signal ST ₁ to the reset terminal is input with opening the switch 94b, it is maintained thereafter set terminal of the opened switch 94b until the reset signal R ₁ is input as a set signal. Specifically, the flip-flop 94a outputs a high-level signal when a high-level signal is input to the set terminal while a low-level signal is input to the reset terminal. As a result, the switch 94b is closed. The flip-flop 94a continues to output a high level signal until a new high level signal is input to the reset terminal. As a result, the switch 94b is kept closed. The flip-flop 94a outputs a low-level signal when a high-level signal is input to the reset terminal while a low-level signal is input to the set terminal. This opens the switch 94b. The flip-flop 94a continues to output a low level signal until a new high level signal is input to the set terminal. As a result, the switch 94b is kept open.
When the switch 94b is in the closed state (ON state), charges in selected ones of the X electrodes X ₁ to X _m is discharged, its voltage decreases. That is, the capacitor formed between the selected _{one of} the X electrodes X _{1 to} X _{m and} the selected one of the Y electrodes Y _{1 to} Y _n is discharged.

As shown in FIG. 2, the control circuit 10 includes a relay circuit 10a, a first oscillation circuit 10b, a second oscillation circuit 10c, a third oscillation circuit 10d, and an arithmetic unit 10e.
First oscillation circuit 10b generates a clock signal CK _1. The first oscillation circuit 10 b outputs the clock signal CK ₁ to the shift register 71.
Second oscillation circuit 10c generates a clock signal CK _2. The second oscillation circuit 10 c outputs the clock signal CK ₂ to the shift register 81.
Third oscillator circuit 10d generates a clock signal CK _3. Third oscillator circuit 10d outputs a clock signal CK ₃ to the AND gate 92a and the 2AND gate 195a.
FIG. 8 is a timing chart showing input / output of the relay circuit 10a. 8, (a) is an output to the shift register 71, (b) is an output to the shift register 81, (c) is an output to the flip-flop 91b and the counter 92b, and (d) is an input to the relay circuit 10a. Each is shown. As shown in FIG. 8, the relay circuit 10 a outputs a set signal ST ₂ to the shift register 71 and outputs a set signal ST ₃ to the shift register 81. Then, the relay circuit 10a outputs a set signal ST ₁ to the flip-flop 91b and the counter 92b. Then, the relay circuit 10a outputs the set signal ST _3, and outputs a set signal ST ₁ at a time later. Relay circuit 10a is repeatedly outputs a set signal ST ₁ and the set signal ST ₃ at predetermined time intervals. A from the output of the set signal ST ₁ until the next set signal ST ₁ is output, the charging and discharging of the capacitor is set to that interval to end one cycle. Further, the relay circuit 10a, a set signal ST ₃ each time the output m (the number of X electrodes) times, and outputs a set signal ST _2.
The arithmetic device 10e has a comparison circuit. Then, compared with a predetermined reference value count N ₁ according to the comparison circuit. The arithmetic device 10e outputs this comparison result. Specifically, when the count value N ₁ is greater than the predetermined reference value, the output is high (true: "1"), and it is a detection signal. On the other hand, if the count value N ₁ is equal to or less than the predetermined reference value, the output is low (false: "0") becomes. The functions of the arithmetic device 10e as described above may be realized by a program.

Next, the operation of the touch panel input device 6 will be described with reference to FIGS. Here, FIG. 9 is a timing chart showing input / output and the like of the capacitance detection circuit 9. FIG. 9 shows a timing chart of a period from when any _{one of} the X electrodes X _{1 to} X _m is selected to when the next one of the X electrodes X _{1 to} X _m is selected.
In the touch panel input device 6, an oscillation circuit 10b, 10c, the 10d, the clock signal CK ₁ to the shift register 71, a clock signal CK ₂ to the shift register 81, the clock signal CK ₃ to the AND gate 92a and the 2AND gate 195a Each is output. On the other hand, as shown in FIG. 8, the relay circuit 10a is a set signal ST ₂ at a high level to the shift register 71, and outputs each of the high level set signal ST ₃ to the shift register 81. Accordingly, the shift register 71 outputs a high level signal to the switch SW_Y1, and the shift register 81 outputs a high level signal to the switch SW_X1. Thus the switch SW_Y1 is turned ON, Y electrodes _{Y 1} is connected to a reference potential line. Further, the switch SW_X1, X electrodes _{X 1} is electrically connected to the wiring 84. On the other hand, the switch SW_Y2~SW_Yn is turned OFF, Y electrodes _Y 2 to Y _n becomes electrically floating state. Further, the switch SW_X2～SW_Xm, X electrodes _X 2 to X _m also becomes electrically floating state. Thereafter, the shift register 71, until the next set signal ST ₂ is input, to hold the switch SW_Y1 the ON state. Shift register 81, until the next set signal ST ₃ is input, it retains the state of the switch SW_X1.

Subsequently, as shown in FIG. 9, the control circuit 10 outputs a set signal ST ₁ at a high level to the stop pin, the preset terminal of the set terminal and the counter 92b of the flip-flop 91b. Then, the counter 92b is preset and starts counting. On the other hand, the output of the flip-flop 91b becomes high level, and the switch 91c is switched on. Then, X electrodes _{X 1} and the capacitor 91d is connected to the constant voltage source 91a. Thereby, the capacitor 91d is charged. The charge to the X electrodes _{X 1} is charged, the capacitor _{C 11} formed between the X electrodes _{X 1} and Y electrodes _{Y 1} is charged. Furthermore, if the contact is the contact body near the intersection between the X electrodes X ₁ and Y electrodes Y _1, capacitor C _f is charged. When the capacitor 91d and the capacitors C ₁₁ and C _f are charged, the voltage of the X electrode X ₁ and the wiring 84 increases.

Here, since the capacitances of the capacitors C ₁₁ and C _f are small, there is a possibility that the rate of increase in the voltage of the X electrode X ₁ and the wiring 84 is increased. However, since the large capacitor 91d of capacity than the capacitor _C 11, _{C f} is connected in parallel with the capacitor _C 11, _{C f,} it is possible to suppress the rate of rise of the voltage of the X electrode _{X 1} and the wiring 84.
Further, when the capacitor C _f is formed and when the capacitor C _f is not formed, the rising speed of the voltage of the X electrode X ₁ and the wiring 84 is different.

While the voltage of the X electrodes _{X 1} is raised, since the voltage of the X electrode _{X 1} and the wiring 84 is less than the upper threshold value _{V th} H, the output of the comparator 93a is at a high level. At this time, the control circuit 10 is outputting a clock signal CK ₃ to the AND gate 92a. Therefore, the output of AND gate 92a is a clock synchronized with the clock signal CK _3. The counter 92b counts the clock input from the AND gate 92a.

Thereafter, when the voltage of the X electrode _{X 1} and the wiring 84 reaches the upper threshold value _{V th} H, the output of the comparator 93a becomes low level. Therefore, the output of the AND gate 92a becomes a low level, and the clock of the output of the AND gate 92a is stopped.

On the other hand, the reset signal R ₁ of the high-level low-level signal outputted from the comparator 93a is inverted by the inverter 93b is inputted to the counter 92b and the flip-flop 94a. Counter 92b, by the reset signal R ₁ is input to the stop terminal, to stop the counting. Furthermore, the counter 92b outputs a count value N ₁ counted during a period from the set signal ST ₁ is inputted to the reset signal R ₁ of a high level is input to the arithmetic unit 10e of the control circuit 10. The count value N ₁ represents the time from when the set signal ST ₁ is input until the voltage of the X electrode X ₁ and the wiring 84 reaches the upper threshold V _th H.
Further, by the reset signal R ₁ of a high level is input to the reset terminal of the flip-flop 91b, the output of the flip-flop 91b becomes low level, the switch 91c is switched to OFF. Therefore, a state where the wiring 84, X electrodes _{X 1} and the capacitor 91d is cut off from the constant voltage source 91a is held.

On the other hand, when the reset signal R ₁ of a high level is input to the set terminal of the flip-flop 94a as a set signal, the output of the flip-flop 94a goes high, the switch 94b is switched to ON. Then, X electrodes _{X 1} and the capacitor 91d is connected to the reference potential. Thus, the charge stored in the X electrodes _{X 1} is discharged, the capacitor 91d and a capacitor _C 11, _{C b} is discharged. Furthermore, if the contact body near the intersection between the X electrodes X ₁ and Y electrodes Y ₁ are in contact, the capacitor C _f is discharged. Accordingly, the voltage of the X electrode _{X 1} and the wiring 84 is reduced. And if the capacitor C _f is formed, in the case where the capacitor C _f is not formed, the rate of decrease in the voltage of the X electrode X ₁ and the wiring 84 are different.

When the voltage of the X electrode _{X 1} and the wiring 84 is below the upper threshold value _{V th} H, the output of the comparator 93a becomes a high level again.
While the voltage of the X electrode X ₁ and the wiring 84 is reduced also, the output of the comparator 93a is a high level.

Thereafter, the voltage of the X electrode X ₁ is reduced to approximately the reference potential. Then, the relay circuit 10a is the output respectively set signal ST ₁ at a high level to the flip-flop 94a and the counter 92b. Then, the switch 94b is turned off. Therefore, a state where the wiring 84, X electrodes X ₁ and the capacitor 91d is cut off from the reference potential is held.

Further, outputs a set signal ST ₃ at a high level to the shift register 81 relay circuit 10a again outputs a set signal ST ₁ at a high level to the set terminal of the flip-flop 91b. Accordingly, the selected switch SW_X2 and the X electrode _{X 2} is, the X electrode _{X 2} is connected to the wiring 84, the switch 91c is opened again. Thus, even with respect to the X electrodes X _2, as in the case of X electrodes X _1, charging and discharging are performed.

Accordingly, as shown in FIG. 8, each of the shift register 81 is set signal ST ₃ is input, the X electrode _X 2 to X _m are sequentially selected sequentially line charging and discharging the X electrodes _X 2 to X _m Is called. Then, the relay circuit 10a, a set signal ST ₁ each time the output m times, it outputs a high level set signal ST ₂ of the shift register 71 again. Therefore, it switches SW_Y2~SW_Yn and Y electrodes _Y 2 to Y _n are sequentially selected. The selection of the switches SW_Yn and Y electrodes _{Y n} are made, switches SW_X1~SW_Xm and X electrodes _X 1 to X _m are sequentially selected, after the end of discharge in the X electrode _{X m,} the relay circuit 10a is a shift register 71 The high level set signal ST ₂ is output to the shift register 81, and the high level set signal ST ₃ is output to the shift register 81. Therefore, the switch SW_Y1 and Y electrodes _{Y 1} is selected, switches SW_X1 and X electrodes _{X 1} is selected. Thus, a series of operations are repeated.

Arithmetic unit 10e of the control circuit 10, each time the count value N ₁ is input, the following processing is performed. That is, the arithmetic unit 10e compares the count value N ₁ input from the counter 92b with a predetermined reference value. Count N ₁ is greater than a predetermined reference value, the output of the arithmetic unit 10e becomes a high level. On the other hand, if the count value N ₁ is equal to or less than the predetermined reference value, the output of the arithmetic unit 10e becomes a low level.

According to the present embodiment, only the capacitor formed between the X electrode and the Y electrode selected by the second scanning circuit is charged, and the selected X electrode and another X located in the vicinity of the X electrode are charged. The capacitor formed between the electrodes is not charged. Therefore, compared with the conventional configuration in which a predetermined voltage is applied to the X electrode that has not been selected, there is an effect that it is possible to more sensitively detect the presence or absence of a charge increase due to touch.
Further, the plurality of Y electrodes that are not selected by the first scanning circuit are electrically floated, thereby crossing the Y electrodes selected by the first scanning circuit and the X electrodes selected by the second scanning circuit. Since only the capacitor formed in the part is charged, compared to the conventional configuration in which a predetermined voltage is applied to the unselected Y electrode, it is possible to more sensitively detect the presence or absence of a charge increase due to touch. Play.

(Second Embodiment)
Next, the configuration of the touch panel input device 106 according to the second embodiment of the present invention will be described. The difference between the present embodiment and the first embodiment is the configuration of the capacitance detection circuit 109 and the control circuit 110. These will be specifically described below. In the figure, the same components as those in the first embodiment are denoted by the same reference numerals.

As shown in FIG. 10, the electrostatic capacitance detection circuit 109 includes a charging circuit 191, a discharging circuit 194, a discharging time measuring circuit 195, and a second determining circuit 196 in addition to the charging time measuring circuit 92 and the determining circuit 93. Since the configuration of the charging time measuring circuit 92 and the determination circuit 93 is the same as that of the first embodiment, the description thereof is omitted.
Discharge time measuring circuit 195, starts counting by the reset signal R ₁ is input, terminates the time counting by the reset signal R ₂ is input. Discharge time measuring circuit 195 measures the time from the input of the reset signal R ₁ until the reset signal R ₂ is input. The discharge time measuring circuit 195 outputs a signal representing the measured time to the control circuit 110. The time measured by the discharge time measuring circuit 195 is the static capacitance of the capacitor formed between the selected _one of the Y electrodes Y _{1 to} Y _{n and} the selected one of the X electrodes X _{1 to} X _m. Represents electric capacity.
The second decision circuit 196, when the discharge by the discharge circuit 194, the voltage of the wiring 84 When turned under the threshold _{V th} L, and outputs a reset signal _{R 2.}
Discharge circuit 194, the reset signal R ₁ is input as a set signal, begins to discharge through the line 84. The discharge circuit 194, by the reset signal R ₂ is input to end the discharge. Specifically, the discharge circuit 194 discharges a capacitor formed between a selected _one of the Y electrodes Y _{1 to} Y _{n and} a selected one of the X electrodes X _{1 to} X _m .
Control circuit 110, each time the reset signal _{R 2} is input, and outputs a set signal ST _1. Timing reset signal R ₂ is output to the front and rear by the presence or absence of the touch on the touch panel 106a. Thus, spacing the set signal ST ₁ is outputted is not necessarily constant different from the first embodiment.

The charging circuit 191 includes a constant current source 191a in addition to the flip-flop 91b and the switch 91c. In addition, no resistor is provided between the constant current source 191a and the switch 91c.
The constant current source 191a generates a constant current. The constant current source 191a is connected to the capacitor 91d and the wiring 84 through the switch 91c.

The second determination circuit 196 includes a second comparator 196a and a second inverter 196b. The discharge time measuring circuit 195 includes a second AND gate 195a, a second counter 195b, and the like.
The wiring 84 is connected to the non-inverting input (+) terminal of the second comparator 196a. A voltage source whose voltage is the lower threshold V _th L is connected to the inverting input (−) terminal of the second comparator 196a. The lower threshold value V _th L is lower than the upper threshold value V _th H. The second comparator 196a compares the voltage of the wiring 84 with the lower threshold value V _th L. The second comparator 196a outputs the comparison result to the second AND gate 195a. Specifically, when the voltage of the wiring 84 is higher than the lower threshold value V _th L, the output of the second comparator 196a is at a high level, and when the voltage of the non-inverting input terminal is lower than the lower threshold value V _th L, 2 The output of the comparator 196a is at a low level.
The output of the second comparator 196a is input to the second AND gate 195a. The clock signal CK ₃ output by the control circuit 110, is input to the 2AND gate 195a. The 2AND gate 195a outputs an output and logical multiplication of the clock signal CK ₃ of the comparator 196a to the second counter 195b. Therefore, when the output of the second comparator 196a is at a high level, the output of the second AND gate 195a becomes a clock signal.
The inverter 196b inverts the output of the second comparator 196a. Signal output is inverted in the second comparator 196a is reset signal _{R 2} via the inverter 196b. Low-level signal outputted by the second comparator 196a is reset signal R ₂ of high level which is inverted by the second inverter 196b is inputted to the stop terminal of the second counter 195b. Further, the reset signal R ₁ of high level signal of a low level output by the comparator 93a is inverted by the inverter 93b is input to the start terminal and preset terminal of the second counter 195b.
The second counter 195b is reset signal _{R 1} of a high level is input as a set signal and the preset signal, starts counting the clock input from the 2AND gate 195a. The second counter 195b is between from the input of the reset signal _{R 1} until a reset signal is input _{R 2,} counts the clock of the output of the 2AND gate 195a. The second counter 195b is reset signal _{R 2} is input to stop the counting. Then, it outputs the count value N _2, the control circuit 110 as a characteristic value based on the electrostatic capacitance of the capacitor.

The discharge circuit 194 includes a flip-flop 94a, a switch 94b, a resistor 194c, and the like.
A switch 94b and a resistor 194c are connected in series between the wiring 84 and the reference potential.
Here, the reference potential is equal to the lower threshold value V _{th L,} or is set to a slightly lower potential than the lower threshold value V _{th L.}

As shown in FIG. 2, the control circuit 110 includes a relay circuit 110a, a first oscillation circuit 10b, a second oscillation circuit 10c, a third oscillation circuit 110d, and an arithmetic unit 110e.
Description of the first oscillation circuit 10b and the second oscillation circuit 10c is omitted.
The third oscillation circuit 110d generates a clock signal CK _3. The third oscillation circuit 110d outputs a clock signal CK ₃ to the AND gate 92a and the 2AND gate 195a.
FIG. 11 is a timing chart showing input / output of the relay circuit 110a. 11, (a) is an output to the shift register 71, (b) is an output to the shift register 81, (c) is an output to the flip-flop 91b and the counter 92b, and (d) is an input to the relay circuit 110a. Each is shown. As shown in FIG. 11, the relay circuit 110 a outputs a set signal ST ₂ to the shift register 71 and outputs a set signal ST ₃ to the shift register 81. Then, the relay circuit 110a outputs a set signal ST ₁ to the flip-flop 91b and the counter 92b. Then, the relay circuit 110a, every time the reset signal _{R 2} is input, and outputs a set signal ST _3, and outputs a set signal ST ₁ at a time later. Further, the relay circuit 10a each time the reset signal _{R 2} is input m (X number of electrode) times, and outputs a set signal ST _2.
The arithmetic device 110e includes a CPU, a RAM, a ROM, and the like, and performs various processes based on a program recorded in the ROM.
Arithmetic unit 110e compares the predetermined reference value stored count value _{N 1} input from the counter 92b in the ROM.
On the other hand, the arithmetic unit 110e calculates the ratio _N 1 / _{N 2} of the count value _{N 1} and the count value _{N 2.} The arithmetic device 110e determines whether or not the ratio N ₁ / N ₂ is within a predetermined range. Specifically, the arithmetic unit 110e compares the predetermined upper reference value and lower reference value stored in the ROM. The predetermined range is determined by the upper reference value and the lower reference value.
The arithmetic device 110e outputs the results of these comparisons. Specifically, the count value N ₁ is greater than a predetermined reference value, and, when the ratio N _{1 /} N ₂ is within a predetermined range, the output is high level computing unit 110e (true: "1") and , That is the detection signal. On the other hand, when the count value N ₁ is less than or equal to the predetermined reference value, or when the ratio N ₁ / N ₂ is outside the predetermined range, the output of the arithmetic unit 110e becomes a low level (false: “0”). .

Although the arithmetic device 110e functions as described above by executing a program, the function of the arithmetic device 110e as described above may be realized by a logic circuit. Specifically, the arithmetic unit 110e includes a comparison circuit, a division circuit, a determination circuit, an AND circuit, and the like. Comparison circuit compares the count value N ₁ with a predetermined reference value. Division circuit divides the count value _{N 1} and the count value _{N 2.} The determination circuit compares the output (ratio N ₁ / N ₂ ) of the division circuit with a predetermined upper reference value and a lower reference value. The AND circuit outputs a logical product of the output of the comparison circuit and the output of the division circuit.

Next, the operation of the touch panel input device 6 will be described with reference to FIGS. 11 and 12. Here, FIG. 12 is a timing chart showing input / output and the like of the capacitance detection circuit 9. FIG. 12 shows a timing chart of a period from when any _{one of} the X electrodes X _{1 to} X _m is selected to when the next one of the X electrodes X _{1 to} X _m is selected.
In the touch panel input device 6, an oscillation circuit 10b, 10c, the 110d, the clock signal CK ₁ to the shift register 71, a clock signal CK ₂ to the shift register 81, the clock signal CK ₃ to the AND gate 92a and the 2AND gate 195a Each is output. On the other hand, as shown in FIG. 11, a relay circuit 110a is a set signal ST ₂ at a high level to the shift register 71, and outputs each of the high level set signal ST ₃ to the shift register 81. Accordingly, the shift register 71 outputs a high level signal to the switch SW_Y1, and the shift register 81 outputs a high level signal to the changeover switch SW_X1. Thus the switch SW_Y1 is turned ON, Y electrodes _{Y 1} is connected to a reference potential line. Further, by switching the switch SW_X1, X electrodes _{X 1} is electrically connected to the wiring 84. On the other hand, the switch SW_Y2~SW_Yn is turned OFF, Y electrodes _Y 2 to Y _n is an electrically floating state. The selector switch SW_X2~SW_Xm, X electrodes _X 2 to X _m is an electrically floating state. Thereafter, the shift register 71, until entering the next set signal ST _2, to hold the switch SW_Y1 the ON state. Shift register 81, until entering the next set signal ST _3, holds the state of the changeover switch SW_X1.

Subsequently, as shown in FIG. 12, the control circuit 110 outputs a set signal ST ₁ at a high level to the stop pin, the preset terminal of the set terminal and the counter 92b of the flip-flop 91b. Then, the counter 92b is preset and starts counting. On the other hand, the output of the flip-flop 91b becomes high level, and the switch 91c is switched on. Then, X electrodes _{X 1} and the capacitor 91d is connected to the constant current source 191a. Thereby, the capacitor 91d is charged. The charge to the X electrodes _{X 1} is charged, the capacitor _{C 11} which is formed in between the X electrodes _{X 1} and Y electrodes _{Y 1} is charged. The capacitor C _b formed between the X electrode X ₂ adjacent thereto and the X electrodes X ₁ is charged. Furthermore, if the contact is the contact body near the intersection between the X electrodes X ₁ and Y electrodes Y _1, capacitor C _f is charged. By capacitor 91d and a capacitor _{C 11,} C b, are _{C f} is charged, the voltage of the X electrode _{X 1} and the wiring 84 is increased.

Here, since the capacitances of the capacitors C ₁₁ , C _b , and C _f are small, there is a risk that the voltage rising speed of the X electrode X ₁ and the wiring 84 is increased. However, the capacitor _{C 11,} C b, because a large capacitor 91d capacity than _{C f} is connected in parallel to the capacitor _{C 11, C b, C f} , suppress the rate of rise of the voltage of the X electrode _{X 1} and the wiring 84 be able to.
Further, when the capacitor C _f is formed and when the capacitor C _f is not formed, the rising speed of the voltage of the X electrode X ₁ and the wiring 84 is different.

While the voltage of the X electrodes _{X 1} is raised, since the voltage of the X electrode _{X 1} and the wiring 84 is less than the upper threshold value _{V th} H, the output of the comparator 93a is at a high level. At this time, the control circuit 110 outputs the clock signal CK ₃ to the AND gate 92a. Therefore, the output of AND gate 92a is a clock synchronized with the clock signal CK _3. The counter 92b counts the clock input from the AND gate 92a. Note, while a voltage of the X electrodes X ₁ is rising, output of the second comparator 196a is at a high level.

Thereafter, when the voltage of the X electrode _{X 1} and the wiring 84 reaches the upper threshold value _{V th} H, the output of the comparator 93a becomes low level. Therefore, the output of the AND gate 92a becomes a low level, and the clock composed of the output of the AND gate 92a is stopped.

On the other hand, the low level of the signal output from the comparator 93a is reset signal _{R 1} of the high level is inverted by the inverter 93b is, counter 92b, the second counter 195b and a flip-flop 94a, is input to 94b. Counter 92b, by the reset signal R ₁ is input to the stop terminal, to stop the counting. Furthermore, the counter 92b outputs a count value N ₁ counted during a period from the set signal ST ₁ is inputted to the reset signal R ₁ of a high level is input to the arithmetic unit 110e of the control circuit 110. The count value N ₁ represents the time from when the set signal ST ₁ is input until the voltage of the X electrode X ₁ and the wiring 84 reaches the upper threshold V _th H.
Further, by the reset signal R ₁ of a high level is input to the reset terminal of the flip-flop 91b, the output of the flip-flop 91b becomes low level, the switch 91c is switched to OFF. Therefore, a state where the wiring 84, X electrodes _{X 1} and the capacitor 91d is blocked from the constant current source 191a is held.

Further, when the reset signal R ₁ of a high level is input to the start terminal preset terminal of the second counter 195b, together with the second counter 195b is preset, it begins counting.
On the other hand, when the reset signal R ₁ of a high level is input to the set terminal of the flip-flop 94a as a set signal, the output of the flip-flop 94a goes high, the switch 94b is switched to ON. Then, X electrodes _{X 1} and the capacitor 91d is connected to the reference potential. Thus, the charge stored in the X electrodes _{X 1} is discharged, the capacitor 91d and a capacitor _C 11, _{C b} is discharged. Furthermore, if the contact body near the intersection between the X electrodes X ₁ and Y electrodes Y ₁ are in contact, the capacitor C _f is discharged. Accordingly, the voltage of the X electrode _{X 1} and the wiring 84 is reduced. And if the capacitor C _f is formed, in the case where the capacitor C _f is not formed, the rate of decrease in the voltage of the X electrode X ₁ and the wiring 84 are different.
When the voltage of the X electrode _{X 1} and the wiring 84 is below the upper threshold value _{V th} H, the output of the comparator 93a becomes a high level again.

While the voltage of the X electrodes _{X 1} is lowered, since the voltage of the X electrode _{X 1} and the wiring 84 is below the threshold value _{V th} L or more, the output of the second comparator 196a is at a high level. At this time, the control circuit 110 outputs a clock signal CK ₃ to the 2AND gate 195a. Therefore, the output of the 2AND gate 195a is a clock synchronized with the clock signal CK _3. The second counter 195b counts the clock output from the second AND gate. Incidentally, while the voltage of the X electrode X ₁ and the wiring 84 is decreased, the output of the comparator 93a is a high level.

Thereafter, when the voltage of the X electrodes _{X 1} is reduced to below the threshold _{V th} L, the output of the second comparator 196a becomes low. Therefore, the output of the second AND gate 195a becomes a low level, and the clock of the output of the second AND gate 195a is stopped.

On the other hand, the low level signal outputted from the second comparator 196a is reset signal _{R 2} of high level which is inverted by the second inverter 196b is inputted second counter 195b, a second flip-flop 94a and relay circuit 110a . When the reset signal _{R 2} of a high level is input to the stop terminal of the second counter 195b, a second counter 195b stops counting. Furthermore, the second counter 195b is a count value N ₂ counted during the period from the reset signal R ₁ of the high level from the inverter 93b is inputted to the reset signal R ₂ of a high level is input to the arithmetic unit 10e Output. The count value N ₂ represents the time from when the reset signal R ₁ is input until the voltage of the X electrode X ₁ and the wiring 84 reaches the lower threshold value V _th L.
Further, when the reset signal R ₂ of a high level is input to the reset terminal of the flip-flop 94a, the output of the flip-flop 94a goes low, switch 94b is switched to OFF. Therefore, a state where the wiring 84, X electrodes X ₁ and the capacitor 91d is cut off from the reference potential is held.

When the reset signal R ₂ is input to the relay circuit 10a of the control circuit 110 outputs a set signal ST ₃ at a high level to the shift register 81 relay circuit 110a is again set at a high level to the set terminal of the flip-flop 91b and outputs a signal ST _1. Thus, the changeover switch SW_X2 and the X electrode _{X 2} is selected, the X electrode _{X 2} is connected to the wiring 84, the switch 91c is opened again. Thus, even with respect to the X electrodes X _2, as in the case of X electrodes X _1, charging and discharging are performed.

Therefore, as shown in FIG. 11, every time the reset signal R ₂ is input to the relay circuit 110 a of the control circuit 110, the X electrodes X _{2 to} X _m are sequentially selected, and charging / recharging for the X electrodes X _{2 to} X _{m is performed.} Discharging is performed sequentially. Then, the relay circuit 110a, a reset signal _{R 2} to each input of m times, and outputs a set signal ST ₂ at a high level to the shift register 71 again. Therefore, it switches SW_Y2~SW_Yn and Y electrodes _Y 2 to Y _n are sequentially selected. The selection switch SW_Yn and Y electrodes _{Y n} are made, the changeover switch SW_X1~SW_Xm and X electrodes _X 1 to X _m are sequentially selected, ends the discharge in the X electrode _{X m,} the relay circuit 110a reset signal R ₂ is input. Then, the relay circuit 110a is a set signal ST ₂ at a high level to the shift register 71, and outputs each of the high level set signal ST ₃ to the shift register 81. Therefore, the switch SW_Y1 and Y electrodes _{Y 1} is selected, the changeover switch SW_X1 and X electrodes _{X 1} is selected. Thus, a series of operations are repeated.

Arithmetic unit 110e of the control circuit 110, each time the reset signal R ₂ is input, the following processing is performed. That is, the arithmetic unit 110e compares the count value _{N 1} input from the counter 92b with a predetermined reference value. On the other hand, the arithmetic unit 110e is the ratio _N 1 / _{N 2} of the count value _{N 1} and the count value _{N 2} was calculated, the ratio _N 1 / _{N 2} is determined whether or not within a predetermined range. Then, the arithmetic device 110e outputs these comparison results. Specifically, the count value N ₁ is greater than a predetermined reference value, and, when the ratio N _{1 /} N ₂ is within a predetermined range, the output of the arithmetic unit 110e becomes a high level. On the other hand, if the count value N ₁ is less than a predetermined reference value, or, when the ratio N _{1 /} N ₂ is outside of the predetermined range, the output of the arithmetic unit 110e goes low.

As described above, in the present embodiment, not only the count value N ₁ indicating the charging time but also the count value N ₂ indicating the discharging time is measured, so that it is possible to prevent erroneous detection of the touch of the contact body. This will be specifically described below.
FIG. 13 is a graph showing the relationship between the voltage V input to the inverting input terminal of the comparator 93a and the elapsed time t. FIG. 13A shows a case where the touch panel 6a is not touched with a finger or the like, and FIG. It shows when touching with a finger. Voltage input to the inverting input terminal of the comparator 93a indicates one of the voltage of the X electrode X ₁ to X _m, which is connected at that time. If the charging time (count value N ₁ ) of each of the capacitors C _{11 to} C _mn when the finger or the like is not touched on the touch panel 6a is t _c and the discharge time (count value N ₂ ) is t _d , the capacitors C ₁₁ to C ₁₁ The time from the start of charging at one of C _{mn to} the end of discharging (period T) is t _c + t _d , and the ratio of charging time to discharging time (charge / discharge time ratio) is t _c / t _d .

When touched with a finger, etc. (around the capacitor C ₂₂ in this case) some point on the upper substrate 62 of the touch panel 6a, the X electrode X ₂ passing under the finger or the like is connected to the constant current source 191a, the X electrode through the upper substrate 62 from the X ₂ charge of minute flows into the finger. Then, X electrode _{X 2} and the finger, a capacitor _{C f} between the Y electrode _{Y 2} and the finger or the like occurs. As a result, the capacitance of the X electrode _{X 2} is increased. If the capacity has increased α times, the charging time (count value N ₁ ) of each of the capacitors C _{11 to} C _mn when the finger or the like is touched on the touch panel 6a is αt _c . The discharge time (count value N ₂ ) also increases α times to αt _d . The time (cycle T) from the start of charging with one of the capacitors C _{11 to} C _{mn to} the end of discharging is α (t _c + t _d ). On the other hand, the ratio between the charging time and the discharging time is αt _c / αt _d = t _c / t _d , and the value does not change when the touch panel 6 a is touched with a finger or the like.

By the way, in this touch panel input device 106, static electricity may be charged in the touch area 61a, thereby generating electrical noise, or electrical noise from the liquid crystal display panel 4 may enter. Then, the electrical noise, touch panel 6a to may change the value of the count value N ₁ even without the touch with a finger or the like. For example, the potential of the X electrode that is in conduction with the constant current source 191a may rise (or fall), and the time from when charging starts until the upper threshold value V _th H is reached may be shortened (or lengthened). On the other hand, when discharging, since electrical noise flows to the power source side of the reference potential, the amount of charge discharged from the capacitors C _{11 to} C _mn is the same as when no electrical noise is generated. Therefore, the ratio N ₁ / N ₂ is different depending on whether or not electrical noise is generated.

According to this embodiment, in addition to the effects of the first embodiment, also the count value N ₂ showing discharge time not only count values N ₁ showing the charging time is measured. Since the ratio of the count value N ₁ and the count value N ₂ when the electrical noise is not generated becomes constant value, even an increase in the charging time by checking the ratio by those or electrical noise due to the touch Can be determined. Therefore, there is an effect that erroneous detection of touch can be prevented.

In the above-described embodiment, scanning is performed by the second scanning circuit 8, but such scanning may not be performed. Specifically, the electrostatic capacitance detection circuit 109 is provided for each X electrode _X 1 to X _m, between the X electrodes _X 1 to X _m is the switch 91c and the switch 94b of each of the electrostatic capacitance detection circuit 109 Each may be connected. In this case, after the relay circuit 110a of the control circuit 110 outputs a set signal ST ₃ to the first scanning circuit 7, one of the Y electrodes _Y 1 to Y _n is selected by the first scanning circuit 7, the relay circuit 110a Outputs the set signal ST ₁ to all the capacitance detection circuits 109. The relay circuit 110 a outputs the set signal ST ₃ to the first scanning circuit 7 every time the reset signal R ₂ is input from all the capacitance detection circuits 109. By doing so, scanning is performed by the first scanning circuit 7.

1 system display 6, 106 touch panel input device 6a touch panel _{Y 1} -Y _n Y electrodes (first electrode)
X ₁ -X _m X electrode (second electrode)
6b, 106b driving device 7 first scanning circuit (selection circuit)
71 Shift registers SW_Y1 to SW_Yn Switch 8 Second scanning circuit (selection circuit)
81 shift register 82 wiring SW_X1 to SW_Xm switches 9, 109 electrostatic capacity detection circuits 91, 191 charging circuit 92 charging time measuring circuit 93 determining circuits 94, 194 discharging circuits 95, 195 discharging time measuring circuits 96, 196 second determining circuit 10 110 control circuit

Claims (18)

A plurality of first electrodes arranged along a first direction in a touch area touched by the contact body;
A plurality of second electrodes arranged crossing the plurality of first electrodes along a second direction orthogonal to the first direction in the touch region;
One of the plurality of first electrodes and one of the plurality of second electrodes are selected, and at least one of the non-selected first electrodes and the non-selected second electrodes is electrically connected A selection circuit for floating,
A capacitance detection circuit that detects a characteristic value based on a capacitance of a capacitor formed by being connected to the first electrode and the second electrode selected by the selection circuit;
A touch panel input device comprising: The capacitance detection circuit is
A charging circuit for charging the capacitor;
A charging time measuring circuit for measuring a charging time from the start of charging by the charging circuit until the charging voltage of the capacitor reaches a predetermined threshold as the characteristic value;
A discharge circuit for discharging the capacitor after the charging voltage reaches the predetermined threshold;
A discharge time measuring circuit that measures a discharge time from when the discharge by the discharge circuit is started until the voltage of the second electrode becomes a lower threshold lower than the threshold;
The touch panel input device according to claim 1, further comprising:   A charge / discharge time ratio comprising a ratio between the charge time and the discharge time for the capacitor is obtained, and a control circuit is provided for determining whether the value of the charge / discharge time ratio is included in a predetermined range. The touch panel input device according to claim 2.   When the total time of the charging time and the discharging time is larger than a predetermined reference value and the charging / discharging time ratio is included in the predetermined range, the control circuit is provided on the capacitor formation region of the touch region. 4. The touch panel input device according to claim 3, wherein a detection signal for detecting that the contact body is touched is output, and in other cases, the detection signal is not output.   5. The selection circuit according to claim 1, wherein the non-selected first electrodes and the non-selected second electrodes are in an electrically floating state. 6. Touch panel input device. A plurality of first electrodes arranged along a first direction in a touch area touched by a contact body; and the first electrode along a second direction orthogonal to the first direction in the touch area; A touch panel drive device for driving a touch panel having a plurality of second electrodes arranged in an intersecting manner,
One of the plurality of first electrodes and one of the plurality of second electrodes are selected, and at least one of the non-selected first electrodes and the non-selected second electrodes is electrically connected A selection circuit for floating,
A capacitance detection circuit that detects a characteristic value based on a capacitance of a capacitor formed by being connected to the first electrode and the second electrode selected by the selection circuit;
A drive device for a touch panel, comprising: The capacitance detection circuit is
A charging circuit for charging the capacitor;
A charging time measuring circuit for measuring a charging time from the start of charging by the charging circuit until the charging voltage of the capacitor reaches a predetermined threshold as the characteristic value;
A discharge circuit for discharging the capacitor after the charging voltage reaches the predetermined threshold;
A discharge time measuring circuit that measures a discharge time from when the discharge by the discharge circuit is started until the voltage of the second electrode becomes a lower threshold lower than the threshold;
The touch panel drive device according to claim 6, further comprising:   A charge / discharge time ratio comprising a ratio between the charge time and the discharge time for the capacitor is obtained, and a control circuit is provided for determining whether the value of the charge / discharge time ratio is included in a predetermined range. The touch panel drive device according to claim 7.   When the total time of the charging time and the discharging time is larger than a predetermined reference value and the charging / discharging time ratio is included in the predetermined range, the control circuit is provided on the capacitor formation region of the touch region. 9. The touch panel drive device according to claim 8, wherein a detection signal for detecting that the contact body is touched is output, and in other cases, the detection signal is not output.   10. The selection circuit according to claim 6, wherein the selection circuit electrically floats the unselected first electrodes and the unselected second electrodes. 11. Touch panel drive device. A plurality of first electrodes arranged along a first direction in a touch area touched by a contact body; and the first electrode along a second direction orthogonal to the first direction in the touch area; A touch panel driving method for driving a touch panel having a plurality of second electrodes arranged in an intersecting manner,
Sequentially selecting each of the first electrodes;
Sequentially selecting each of the second electrodes,
At least one of each of the first electrodes not selected and each of the second electrodes not selected is set in an electrically floating state;
A method for driving a touch panel, comprising: detecting a characteristic value based on a capacitance of a capacitor formed by being connected to the selected first electrode and the second electrode. Charging the capacitor, measuring the charging time from the start of charging until the charging voltage of the capacitor reaches a predetermined upper threshold, as the characteristic value,
After the charging voltage reaches the predetermined upper threshold, discharging of the capacitor is started, and a discharging time from the start of discharging of the capacitor until the charging voltage becomes a lower threshold lower than the upper threshold is set. The touch panel driving method according to claim 11, wherein the characteristic value is measured.   A charge / discharge time ratio comprising a ratio between the charge time and the discharge time is obtained, a total time of the charge time and the discharge time is larger than a predetermined reference value, and the charge / discharge time ratio is included in the predetermined range. The contact body is determined to be touched on a region where the capacitor is formed in the touch region, and otherwise, the contact body is not determined to be touched. Drive method of the touch panel. A display panel;
A plurality of first electrodes arranged along a first direction in a touch area touched by a contact body, and the plurality of first electrodes along a second direction orthogonal to the first direction in the touch area. A plurality of second electrodes arranged crossing the electrodes, and a touch panel provided on the display surface side of the display;
A drive device for driving the touch panel,
The drive device
One of the plurality of first electrodes and one of the plurality of second electrodes are selected, and at least one of the non-selected first electrodes and the non-selected second electrodes is electrically connected A selection circuit for floating,
A capacitance detection circuit that detects a characteristic value based on a capacitance of a capacitor formed by being connected to the first electrode and the second electrode selected by the selection circuit;
A system display comprising: The capacitance detection circuit is
A charging circuit for charging the capacitor;
A charging time measuring circuit for measuring a charging time from the start of charging by the charging circuit until the charging voltage of the capacitor reaches a predetermined threshold as the characteristic value;
A discharge circuit for discharging the capacitor after the charging voltage reaches the predetermined threshold;
A discharge time measuring circuit that measures a discharge time from when the discharge by the discharge circuit is started until the voltage of the second electrode becomes a lower threshold lower than the threshold;
15. A system display according to claim 14, comprising:   A charge / discharge time ratio comprising a ratio between the charge time and the discharge time for the capacitor is obtained, and a control circuit is provided for determining whether the value of the charge / discharge time ratio is included in a predetermined range. The system display according to claim 15.   When the total time of the charging time and the discharging time is larger than a predetermined reference value and the charging / discharging time ratio is included in the predetermined range, the control circuit is provided on the capacitor formation region of the touch region. 17. The system display according to claim 16, wherein a detection signal for detecting that the contact body is touched is output, and the detection signal is not output in other cases.   18. The selection circuit according to claim 14, wherein the selection circuit electrically floats the unselected first electrodes and the unselected second electrodes. 18. System display.

Images