JP2011109641A - Variable gain amplification device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a variable gain amplification device which can suppress deterioration of a noise characteristic generated according to attenuation amount, by fixing the attenuation amount while changing a gain by the variable gain amplification section. <P>SOLUTION: The variable gain amplification device has a variable attenuator 20 which attenuates an input signal. The device also has a variable gain amplifier 30 which changes and amplifies a gain of the attenuated input signal output from the variable attenuator 20. The device further has a controller 10 which fixes an attenuation of the variable attenuator 20 while the gain is changed by the variable gain amplifier 30. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a variable gain amplifying device, and more particularly to a variable gain amplifying device accompanied by attenuation of an input signal.

  In a receiver such as a communication device or a TV, various received radio wave states are assumed. In such a system, a signal having a wide range of signal strengths is input. For this reason, signal processing such as demodulation is performed after adjustment to an optimum signal intensity using a variable gain amplifier. Thus, the variable gain amplifying device requires a wide range of variable gain. Moreover, the case where a weak desired radio wave exists in a strong jamming radio wave is also assumed. In order to ensure reception performance in this case, low noise and low distortion are also required.

  FIG. 16 shows a configuration of a commonly used amplifier. The input signal is input to the variable gain amplifier 102 and the variable gain amplifier 103 in which the fixed attenuator 104 is connected in cascade. Adder 105 adds the output currents output from variable gain amplifiers 102 and 103 and outputs the result to current-voltage conversion circuit 106. The current-voltage conversion circuit 106 generates and outputs an output signal (output voltage). FIG. 17 shows a configuration example of the variable gain amplifiers 102 and 103. The variable gain amplifiers 102 and 103 have transistors 107 and 108. The current of the current source connected to the transistors 107 and 108 is Ic_a or Ic_b. The variable gain amplifiers 102 and 103 can change the gain by controlling the current Ic_a or Ic_b of the differential pair. The maximum output current of the gain amplifier is proportional to Ic_a or Ic_b. This figure shows an example of a differential amplifier, but the same applies to a single amplifier.

  Next, control methods and characteristics of the variable gain amplifiers 102 and 103 will be described with reference to FIG. FIG. 18A shows a control method for the variable gain amplifiers 102 and 103. The control circuit 101 continuously switches the control currents Ic_a and Ic_b for the variable gain amplifiers 102 and 103 according to the control signal 100. When the control current Ic_a decreases according to the control signal, the gain of the variable gain amplifier 102 decreases. Further, when the control current Ic_b increases, the gain of the variable gain amplifier 103 increases. Since the fixed attenuator 104 is cascade-connected to the variable gain amplifier 103, the gain of the added output current is reduced by the amount attenuated in the fixed attenuator 104. The gain change with respect to the control signal is shown in FIG. The variable range of the gain is determined by the attenuation amount of the fixed attenuator 104.

  Next, the configuration of the variable gain amplifying apparatus disclosed in Patent Document 1 will be described with reference to FIG. The variable gain amplifying apparatus includes a variable attenuator 111 whose signal attenuation is controlled by an attenuator control signal and a variable gain amplifier 112 whose gain is controlled by an amplifier control signal, which are connected in cascade. The variable gain amplifying apparatus further includes a control circuit 110 that generates an attenuator control signal and an amplifier control signal in accordance with a control signal given from the outside. The control by the control circuit 110 is shown in FIG. 21A shows the gain change of the variable gain amplifier 112, and FIG. 21B shows the change of the attenuation amount of the variable attenuator 111. FIG. As shown in FIG. 21 (C), the gain of the variable attenuator 111 is changed at the same time as the gain of the variable gain amplifier 112 is changed in accordance with the control signal input to the control circuit 110. The gain of the variable gain amplifying device is changed in accordance with a control signal input to the circuit.

JP 2004-328425 A

  The amplifier described in FIG. 16 has a problem that distortion characteristics deteriorate as shown in FIG. 18C when control is performed by the control method of FIG. Specifically, there is a problem that the 1 dB compression point varies. Here, the fluctuation of the 1 dB compression point will be described with reference to FIG. FIG. 19A shows input / output characteristics in the maximum gain state and the minimum gain state. The input / output characteristics in the maximum gain state and the minimum gain state are characteristics that are translated by the attenuation amount of the fixed attenuator 104. As shown in FIG. 19A, the 1 dB compression point in the maximum gain state and the minimum gain state shows the same value (dBm). Next, as shown in FIG. 18C, the input / output characteristics in a state where the distortion characteristics deteriorate are shown in FIG. Here, for the sake of explanation, individual characteristics of the variable gain amplifiers 102 and 103 are also shown. The variable gain amplifier 102 has a small gain and a small control current Ic_a. Therefore, the output saturates at a lower output compared to the maximum gain state. On the other hand, in the variable gain amplifier 103, the control current Ic_b is larger than the control current Ic_a, and the gain of the variable gain amplifier 103 is also large. Therefore, it saturates at a higher output than the variable gain amplifier 102. If the outputs of these two amplifiers are added with the vertical axis being a logarithm, the characteristic shown in FIG. 21B is obtained. From this figure, it can be seen that an inflection point exists in the middle of the output characteristics in the intermediate gain state. When the 1 dB compression point is obtained from this output characteristic, the 1 dB compression point is lower in the intermediate gain state than in the maximum gain state. In order to obtain a wide gain variable range as a variable gain device, it is necessary to increase the amount of attenuation of the fixed attenuator. In general, the deterioration of the distortion characteristic is proportional to the amount of attenuation of the fixed attenuator. It is known that such a problem occurs in a system that uses a fixed attenuator and switches the control current of the gain amplifier. In such an amplifier, a wide gain range and low distortion characteristics must be compatible. I can't.

  In addition, when the variable gain amplifying apparatus shown in FIG. 20 is operated by the control method of FIG. 21, since the variable gain amplifier is not a method of switching by the control current, it is possible to suppress deterioration of distortion characteristics. However, in such a case, there is a problem that noise characteristics deteriorate. In general, when an attenuator is connected in front of an amplifier and the gain is reduced by changing the attenuation, the noise characteristics are also deteriorated in proportion to the attenuation. The amount of deterioration is larger than when the gain is changed in the circuit configuration inside the amplifier. In the amplifier of FIG. 16, in the region where the maximum gain state is obtained, gain is obtained only from the variable gain amplifier 102, so that noise characteristics are not deteriorated by connecting the fixed attenuator 104. However, in the variable gain amplifying device of FIG. 20, the input signal is input to the variable gain amplifier 112 via the variable attenuator 111 even in the region where the maximum gain state is obtained. Therefore, in the variable gain amplifying device of FIG. 20, the noise characteristics are greatly deteriorated in the region where the maximum gain state is obtained as compared with the amplifier of FIG.

  A variable gain amplifying apparatus according to a first aspect of the present invention includes a variable attenuator that attenuates an input signal, and a first variable that amplifies the input signal after changing the gain output from the variable attenuator. The gain amplifying unit and the first control region in which the gain is changed by the first variable gain amplifying unit include a control unit that controls the amount of attenuation of the variable attenuating unit to be fixed. .

  By using such a variable gain amplifying device, the variable attenuating unit and the variable gain amplifying unit can be controlled, and the gain of the entire variable gain amplifying device can be controlled.

  According to the present invention, it is possible to provide a variable gain amplifying device that suppresses deterioration of noise characteristics that occur according to the amount of attenuation by fixing the amount of attenuation while the gain is changed by the variable gain amplifying unit. .

1 is a configuration diagram of a variable gain amplifying device according to a first exemplary embodiment; FIG. 3 is a diagram illustrating control contents of a control circuit according to the first exemplary embodiment. 1 is a configuration diagram of a variable gain amplifying device according to a first exemplary embodiment; FIG. 3 is a diagram showing noise characteristics according to the first exemplary embodiment. FIG. 3 is a configuration diagram of a variable gain amplifying device according to a second exemplary embodiment. FIG. 3 is a configuration diagram of a variable gain amplifying device according to a second exemplary embodiment. FIG. 6 is a configuration diagram of a control circuit according to a third embodiment. FIG. 6 is a configuration diagram of a variable gain amplifying device according to a third exemplary embodiment. FIG. 10 is a diagram illustrating control contents of a control circuit according to a third embodiment. It is a block diagram of the variable attenuator concerning other embodiment. It is a block diagram of the variable attenuator concerning other embodiment. It is a block diagram of the variable attenuator concerning other embodiment. It is a block diagram of the variable gain amplifier concerning other embodiment. It is a block diagram of the variable gain amplifier concerning other embodiment. It is a block diagram of the variable gain amplifier concerning other embodiment. It is a block diagram of the amplifier used generally. It is a block diagram of the variable gain amplifier which the amplifier generally used has. It is the figure which showed the control operation of the amplifier generally used. It is the figure which showed the output characteristic of the amplifier used generally. 1 is a configuration diagram of a variable gain amplifying device according to Patent Document 1. FIG. 10 is a diagram illustrating a control operation of a variable gain amplifying device according to Patent Document 1. FIG. FIG. 6 is a configuration diagram of a control circuit according to a fourth embodiment. It is a graph which shows the relationship between the conductance concerning Embodiment 4, and a control voltage. In Embodiment 4, it is a graph which shows the relationship between conductance at the time of using the control circuit used for Embodiment 3, and a control voltage. FIG. 10 is a configuration diagram of a control circuit according to a fifth embodiment; It is a graph which shows the relationship between the conductance concerning Embodiment 5, and a control voltage.

(Embodiment 1)
Embodiments of the present invention will be described below with reference to the drawings. A configuration example of the variable gain amplifying apparatus according to the first embodiment of the present invention will be described with reference to FIG. The variable gain amplifying apparatus includes a control circuit 10, a variable attenuator 20, and a variable gain amplifier 30.

  The control circuit 10 receives the control signal 100 and generates a variable attenuator control signal output to the variable attenuator 20 based on the control signal 100 and a variable gain amplifier control signal output to the variable gain amplifier 30. The control signal may be a control voltage composed of a voltage, for example. The variable attenuator 20 receives an input signal and attenuates the input signal. An input signal is a signal for which gain and gain control are performed and gain is obtained. The variable attenuator 20 outputs the attenuated input signal to the variable gain amplifier 30 that is cascade-connected to the variable attenuator 20. The variable gain amplifier 30 amplifies the input signal received from the variable attenuator 20 based on the variable gain amplifier control signal, and generates an output signal.

  Subsequently, the control operation of the control circuit 10 according to the first exemplary embodiment of the present invention will be described with reference to FIG. In this figure, the horizontal axis represents the magnitude of the control signal 100, and the vertical axis using the logarithmic axis represents the gain. As the control signal 100 increases, the control circuit 10 controls the variable attenuator 20 and the variable gain amplifier 30 so as to obtain a large gain. Here, a region where the gain value is decreased by a certain value from the maximum gain state of the variable gain amplifying device is defined as a gain variable region 1. That is, the gain variable region 1 is a region where the gain of the variable gain amplifier is changed while the gain of the variable gain amplifier 30 is changed. For example, a region attenuated by a quarter from the maximum gain state is defined as a gain variable region 1. Further, a region where the gain value is increased by a certain value from the minimum gain state of the variable gain device is defined as a gain variable region 3. That is, the gain variable region 3 is a region in which the gain of the variable gain amplifier is changed while the gain of the variable gain amplifier 30 is fixed. For example, the gain variable region 3 is a region where the gain is increased by a quarter from the minimum gain state. A region between the gain variable region 1 and the gain variable region 3 is defined as a gain variable region 2. That is, the gain variable region 2 is a region where the gain of the variable gain amplifier 30 is transferred from the gain variable region 3 to the gain variable region 1.

  In the gain variable region 1, the control circuit 10 changes the gain of the variable gain amplifier 30 by changing the gain of the variable gain amplifier 30, and does not change the attenuation amount of the variable attenuator 20 as a minimum. In the gain variable region 3, the gain of the variable gain amplifying device is made variable by changing the attenuation amount of the variable attenuator 20, and the gain of the variable gain amplifier 30 is minimized and is not changed. In the gain variable region 2, variable gain amplification is performed by changing part of the gain in the variable gain range of the variable gain amplifier 30 and changing part of the attenuation in the variable amount of attenuation of the variable attenuator 20. Make the gain of the device variable.

  Next, configuration examples of the variable attenuator 20 and the variable gain amplifier 30 according to the first exemplary embodiment of the present invention will be described with reference to FIG. The variable attenuator 20 includes a resistor 21, a MOS transistor 22, and a capacitor 23. The resistor 21 is connected to the input terminal of the variable attenuator 20. In addition, either the source or the drain of the MOS transistor 22 is connected to the resistor 21 and the other is connected to the capacitor 23 to be grounded.

  The variable gain amplifier 30 includes a current-voltage conversion circuit 31, bipolar transistors 32 and 33, a resistor 34, and a MOS transistor 35. The base of the bipolar transistor 32 is connected to the MOS transistor 22 and the capacitor 23 of the variable attenuator 20. The base of the bipolar transistor 33 is connected to the resistor 21 and the MOS transistor 22 of the variable attenuator 20. The resistor 34 and the MOS transistor 35 are connected to the emitters of the bipolar transistors 32 and 33.

  Next, operations of the variable attenuator 20 and the variable gain amplifier 30 will be described. The control voltage 220 is input to the MOS transistor 22 of the variable attenuator 20. The control voltage 220 is the same as the variable attenuator control signal input from the control circuit 10. The MOS transistor 22 can change the attenuation by the resistor 21 and the MOS transistor 22 by changing the input control voltage 220. For example, when the control voltage 220 is increased, the resistance value of the resistance between the source and drain of the MOS transistor 22 is controlled to be decreased. Thus, since the signal output to the base of the bipolar transistor 33 of the variable gain amplifier 30 becomes small, the variable attenuator 20 realizes an operation for increasing the attenuation. The signal output to the base of the bipolar transistor 32 is set to a fixed value by the capacitor 23.

  The control voltage 350 is input to the MOS transistor 35 of the variable gain amplifier 30. The control voltage 350 is the same as the variable gain amplifier control signal input from the control circuit 10. The MOS transistor 35 can change the source / drain resistance of the MOS transistor 35 which is the emitter resistance of the bipolar transistor 32 and the bipolar transistor 33 by changing the input control voltage 350. For example, when the control voltage 350 is increased, the resistance value of the resistance between the source and drain of the MOS transistor 35 is controlled to be decreased. As a result, the signal output from the current-voltage conversion circuit 31 becomes large, and an operation of amplifying is realized. As a result, the collector currents of the bipolar transistor 32 and the bipolar transistor 33 are changed without changing the bias current Ic1, and the differential voltage is output via the current-voltage conversion circuit 31.

  As described above, the following effects can be obtained by using the variable gain amplifying apparatus according to the first embodiment of the present invention. In the variable gain region 1, the gain of the variable gain amplifier 30 is changed, and the attenuation amount of the variable attenuator 20 is fixed to the minimum. As a result, it is possible to suppress the deterioration of noise characteristics that occurs in response to an increase in the attenuation amount of the variable attenuator 20. FIG. 4 is a diagram showing a state in which the deterioration of noise characteristics in the variable gain region 1 is suppressed. The case where the attenuation of the variable attenuator 20 is changed is indicated by a dotted line, and the attenuation of the variable attenuator 20 is fixed. The case where it was made is shown by the solid line. As shown in this figure, the noise characteristics in the variable gain region 1 are improved by performing the above control.

  Further, by changing the attenuation amount of the variable attenuator 20 in the gain variable regions 2 and 3, the variable gain range of the variable gain amplifying device can be widened. Furthermore, if the gain variable range required for the variable amplifying device is constant, the gain variable range required for the variable gain amplifier 30 can be narrowed by the amount of attenuation of the variable attenuator 20.

  Further, in the variable gain device according to the first exemplary embodiment of the present invention, the control for changing the gain is not performed by switching the control currents of the plurality of gain amplifiers, and therefore there is no deterioration in distortion characteristics.

(Embodiment 2)
Next, a configuration example of the variable gain amplifying apparatus according to the second embodiment of the present invention will be described with reference to FIG. The variable gain amplifying apparatus according to the second exemplary embodiment of the present invention includes a variable gain amplifier 40 and an adding unit 50 in addition to the configuration of FIG.

  The variable gain amplifier 40 receives an input signal, is controlled by a second variable gain amplifier control signal acquired from the control circuit 10, and outputs the gain-controlled input signal to the adder 50.

  The adder 50 adds the output signals after gain amplification obtained from the variable gain amplifier 30 and the variable gain amplifier 40. Thereby, an output signal of the variable gain amplifying device is generated.

  Next, configuration examples of the variable attenuator 20 and the variable gain amplifiers 30 and 40 of the variable gain amplifying apparatus according to the second embodiment of the present invention will be described with reference to FIG. The variable gain amplifying apparatus in this figure further includes bipolar transistors 41 and 42 constituting a variable gain amplifier 40 and a resistor 43 in addition to the configuration of FIG. The current / voltage conversion circuit 31 corresponds to the adding unit 50.

  The bipolar transistor 42 inputs the input signal before being attenuated by the resistor 21 of the variable attenuator 20 based on the base. In addition, the bipolar transistor 41 receives a signal set to a fixed value by the capacitor 23. In such a configuration, the collector current of the bipolar transistors 41 and 42 is changed by changing the bias current Ic2 connected to the emitters of the bipolar transistors 41 and 42. The bias current Ic2 is controlled by a second variable gain amplifier control signal from the control circuit 10. Thereby, the variable gain amplifier 40 can change the gain.

  In this figure, the collector current of the bipolar transistors 41 and 42 and the collector current of the bipolar transistors 32 and 33 are added and input to the current-voltage conversion circuit. After the current is converted into a voltage, it may be added to the voltage output from the variable gain amplifier 30.

  Here, in addition to the control in the first embodiment, the control circuit 10 reduces the gain of the variable gain amplifier 30 and increases the gain of the variable gain amplifier 40 from the state where the gain of the variable gain amplifier 30 is maximized. Thus, control is performed so that the amplification operation is switched from the variable gain amplifier 30 to the variable gain amplifier 40. That is, the control voltage 220 and the control voltage 350 in FIG. 6 are set so that the gain of the variable gain amplifier 30 is maximized and the attenuation amount of the variable attenuator 20 is minimized, and the bias current Ic2 is increased. Then, control is performed so as to reduce the current of the bias current Ic1. The bias currents Ic1 and Ic2 may be controlled based on the first variable gain amplifier control signal and the second variable gain amplifier control signal output from the control circuit 10, or the bias currents Ic1 and Ic2 may be controlled. A control signal used only for controlling may be newly provided.

  In the configuration of FIG. 1, even in the maximum gain state, since the variable attenuator 20 is connected in front of the variable gain amplifier 30, it is impossible to avoid deterioration of noise characteristics due to the attenuation effect of the variable attenuator 20. . However, it is possible to further suppress the deterioration of noise characteristics by switching the operation to the variable gain amplifier 40 that has nothing connected to the previous stage in the maximum gain state. In addition, since the control circuit 10 switches and controls the variable gain amplifier 30 and the variable gain amplifier 40, there is a concern about deterioration of distortion characteristics. However, since the variable gain amplifiers 30 and 40 according to the second embodiment of the present invention are switched in the maximum gain state, the attenuation amount of the variable attenuator 20 is fixed to the minimum. For this reason, the deterioration of the distortion characteristic that occurs in proportion to the amount of attenuation is suppressed.

(Embodiment 3)
Next, a configuration example of the control circuit 10 according to the third exemplary embodiment of the present invention will be described with reference to FIG. The control circuit 10 includes a power supply unit 11, a current-voltage conversion circuit 12, an operational amplifier 13, a MOS transistor 14, a bias power supply 15, and a MOS transistor 16. The current-voltage conversion circuit 12, the MOS transistor 14, and the bias power supply 15 are connected in series between the power supply unit 11 and the GND power supply. The operational amplifier 13 receives the voltage at the contact between the MOS transistor 14 and the current-voltage conversion circuit 12 and the control voltage 130 that is variably controlled, and outputs a gate voltage to the MOS transistor 14 and the MOS transistor 16. In this configuration, the MOS transistor 16 is controlled, and the MOS transistor 14 operates as a replica of the MOS transistor 16. The MOS transistor 16 is used as the MOS transistor 22 of the variable attenuator 20 or the MOS transistor 35 of the variable gain amplifier 30. Hereinafter, the operation of the control circuit 10 will be described.

  The operational amplifier 13 inputs a variably controlled gate voltage to the MOS transistor 14 by inputting the variably controlled control voltage 130. The MOS transistor 14 receives a variably controlled gate voltage to generate a source-drain current whose size changes. The source-drain current is converted into a voltage by the current-voltage conversion circuit 12. The voltage converted by the current-voltage conversion circuit 12 is controlled to be equal to the control voltage 130 by feedback control of the operational amplifier 13. In this way, the output voltage generated by the change in the voltage input to the positive terminal and the negative terminal of the operational amplifier 13 is output to the gates of the MOS transistors 14 and 16, and the resistance between the source and drain of the MOS transistors 14 and 16 is variably controlled. Is done. Since the source-drain resistance of the MOS transistor 16 to be controlled is controlled using the replica MOS transistor 14 in this way, the resistance between the source and drain of the MOS transistor 16 is not affected by environmental variations or process variations. To be accurately controlled. Further, by connecting the bias power supply 15 that supplies the same value as the source voltage of the MOS transistor 16 to the MOS transistor 14, the control error of the MOS transistors 14 and 16 can be suppressed.

  Next, a configuration example of the variable gain amplifying apparatus when the control circuit of FIG. 7 is applied to the configuration of FIG. 3 will be described with reference to FIG. The configuration examples of the variable attenuator 20 and the variable gain amplifier 30 are the same as those in FIG. The control circuit 10_1 is connected to the gate of the MOS transistor 35 of the variable gain amplifier 30, and the control circuit 10_2 is connected to the gate of the MOS transistor 22 of the variable attenuator 20. Since the control circuit 10_1 and the control circuit 10_2 have the same configuration, a configuration example of the control circuit 10_1 will be described below.

  The control circuit 10_1 includes bias power supplies 62 and 68, resistors 63, 64, 66, and 67, and an operational amplifier 65 in addition to the configuration of FIG. The resistor 61 corresponds to the current / voltage conversion circuit 12. The signal output from the operational amplifier 65 is input to the negative terminal of the operational amplifier 13. The control circuit 10_1 acquires the control signal 100 and inputs a signal determined by the bias power source 62 and the resistors 63 and 66 to the plus terminal of the operational amplifier 65. The output voltage amplified by the resistors 64 and 67 connected to the negative terminal of the operational amplifier 65 is output to the negative terminal of the operational amplifier 13. Similar control is also performed in the control circuit 10_2. In the control circuit 10_2, the acquired control signal 100 is input to the negative terminal of the operational amplifier corresponding to the operational amplifier 65. Thereby, as the control signal 100 increases, the signal output from the operational amplifier corresponding to the operational amplifier 65 decreases.

  The attenuation amounts and gains of the variable attenuator 20 and the variable gain amplifier 30 are controlled by the control voltages 220 and 350 output from the operational amplifiers 13 and 10_2 (corresponding to the operational amplifier 13) of the control circuit 10_1. The gain change of the variable gain amplifying apparatus in this case will be described with reference to FIG.

  In the variable gain region 2, the control circuit 10 changes the gain of a quarter of the variable gain range on the logarithmic axis of the variable gain amplifier 30 and a quarter of the attenuation variable range on the logarithmic axis of the variable attenuator 20. Attenuation is changed simultaneously. The attenuation amount of the variable attenuator 20 changes based on the source-drain resistance of the MOS transistor 22, and the gain of the variable gain amplifier 30 changes based on the source-drain resistance of the MOS transistor 35. As described above, in the gain possible region 2, the variable attenuator 20 and the variable gain amplifier 30 complementarily control the attenuation amount and the gain, thereby improving the linearity of the gain change of the variable gain amplifying apparatus. .

(Embodiment 4)
A configuration example of the control circuit 501 according to the fourth embodiment of the present invention will be described with reference to FIG. The control circuit 501 includes a power supply (VCC) 510, a power supply (GND) 511, bias power supplies 512 and 513, a resistor 521, MOS transistors 531 and 532, an operational amplifier 541, an input terminal 551, and an output terminal 552. Node 561. The MOS transistor will be described as an NMOS transistor, for example.

  The resistor 521, the MOS transistor 531, and the MOS transistor 532 are connected in series between a power supply (VCC) 510 and a power supply (GND) 511, and the resistor 521 is connected to the power supply (VCC) 510. A bias power supply 513 is connected between the MOS transistor 532 and the power supply (GND) 511. Further, a MOS transistor 531 is connected between the resistor 521 and the MOS transistor 532.

  One of the output terminals 552 is connected to the operational amplifier 541 and the MOS transistor 532, and the other is connected to the gate of the MOS transistor 22 of the variable attenuator 20 or the MOS transistor 35 of the variable gain amplifier 30.

  The node 561 outputs the voltage at the node between the resistor 521 and the MOS transistor 531 to the plus terminal side of the operational amplifier 541. The operational amplifier 541 receives a control voltage from the input terminal 551 on the negative terminal side. The control voltage can be set variably. Further, the operational amplifier 541 outputs a voltage to the MOS transistor 532 based on the voltage input to the plus terminal and the minus terminal. Here, the operational amplifier 541 outputs a voltage to the MOS transistor 532 and also outputs the same voltage to the output terminal 552.

  The bias power supply 512 outputs a voltage to the gate of the MOS transistor 531 so that the MOS transistor 531 operates in the saturation region. As an example, the bias power supply 512 is connected to the MOS transistor 531 so that the source-drain voltage Vds, the gate-source voltage Vgs, and the threshold voltage Vth of the MOS transistor 531 satisfy the relationship Vds> 2 (Vgs−Vth). A voltage is output to the gate. When the MOS transistor 531 operates in the saturation region, the potential of the source of the MOS transistor 531, that is, the drain side of the MOS transistor 532 is substantially fixed.

  Further, the bias power supply 512 is connected to the source of the MOS transistor 532 so that the MOS transistor 532 operates in the linear region. As an example, a bias setting that satisfies the condition of Vds << 2 (Vgs−Vth) with a small Vds is used. Further, the bias power supply 513 is connected so that the source of the MOS transistor 532 and the source of the MOS transistor 22 of the variable attenuator 20 or the source of the MOS transistor 35 of the variable gain amplifier 30 have the same potential. The MOS transistor 533 operates as a replica of the MOS transistor 532 and is a target transistor whose resistance value is variably controlled. The MOS transistor 533 inputs the voltage output from the output terminal 552 to the gate.

  Next, the operation of the control circuit 501 will be described. The control circuit 501 controls the MOS transistor 532 using feedback from the operational amplifier 541. When the control voltage Vcnt input to the input terminal 551 is variable, the node 561 is feedback-controlled so that a voltage equal to the control voltage Vcnt is generated. Further, assuming that the resistance value of the resistor 521 is R521 and the current generated in the resistor 521 is Ic521, Ic521 can be obtained by the following Expression 1.

  Ic521 = (VCC−Vcnt) / R521 (Formula 1)

  Further, since the MOS transistor 531 operates in the saturation region, the source-drain voltage Vds of the MOS transistor 532 is constant even if the Ic 521 changes. Therefore, the source-drain conductance g of the MOS transistor 532 (the reciprocal of the resistance between the source and drain of the MOS transistor 532) can be obtained by the following equation 2.

  g = Ic521 / Vds (Formula 2)

  Since the source-drain voltage Vds of the MOS transistor 532 is constant, the source-drain conductance g of the MOS transistor 532 changes in proportion to Ic521. Further, from the equations 1 and 2, the source-drain conductance g of the MOS transistor 532 is expressed by the following equation 3.

  g = (VCC−Vcnt) / (R521 × Vds) (Equation 3)

  Thus, the source-drain conductance g of the MOS transistor 532 is variably controlled according to the value of the control voltage Vcnt input to the input terminal 551. Furthermore, the slope of the change in the conductance g between the source and drain of the MOS transistor 532 is fixed in proportion to 1 / R521. FIG. 23 shows the relationship between the source-drain conductance g of the MOS transistor 532 and the control voltage Vcnt. FIG. 23 shows a state in which the source-drain conductance g of the MOS transistor 532 changes linearly according to the control voltage Vcnt.

  As described above, by using the control circuit 501 according to the fourth embodiment of the present invention, the source-drain voltage of the MOS transistor 532 can be fixed to a substantially constant value. Therefore, the MOS transistor 532 can continue the operation in the linear region regardless of the change in the current Ic521 generated in the resistor 521. Therefore, the slope of change in the conductance between the source and drain of the MOS transistor 532 with respect to the control voltage Vcnt can be made constant. That is, the source-drain conductance of the MOS transistor 532 can be controlled linearly. Accordingly, the change in conductance between the source and drain of the MOS transistor 533 connected to the operational amplifier 541 can be similarly controlled linearly. On the other hand, when the control circuit 10 of FIG. 7 is used, when the source-drain resistance of the MOS transistor 14 is low, the source-drain voltage of the MOS transistor 14 is small, and the MOS transistor 14 operates in a linear region. . However, the source-drain voltage of the MOS transistor 14 fluctuates due to a change in current flowing into the MOS transistor 14. Therefore, the source-drain conductance of the MOS transistor 14 does not change with a constant slope with respect to the control voltage. Further, when the source-drain resistance of the MOS transistor 14 is high, the MOS transistor 14 operates in a saturation region. Therefore, the slope of the change in resistance between the source and drain of the MOS transistor 14 with respect to the control voltage changes greatly. Accordingly, the MOS transistor 16 connected to the operational amplifier 13 has the same characteristics. FIG. 24 shows the relationship between the source-drain conductance of the MOS transistor 104 and the control voltage. Thus, when the control circuit 501 is used, compared to the case where the control circuit 10 is used, the resistance value has a wide variable range, and the conductance changes linearly with respect to the control voltage, that is, high resistance value controllability. A variable resistor using a MOS transistor can be realized. Therefore, by using the control circuit 501, the variable gain and the variable attenuation can be widened.

  Further, as described above, the control circuit 501 may be used as a control circuit of the variable gain amplifying device, or may be used alone as a variable resistor. That is, the control circuit 501 may be used by being incorporated in a device other than the variable gain amplifying device.

(Embodiment 5)
Next, the control circuit 502 according to the second embodiment of the present invention will be described with reference to FIG. The control circuit 502 according to FIG. 25 includes a power supply (VCC) 514, resistors 522 to 527, a MOS transistor 534, an input terminal 553, and voltage buffers 571 and 572 in addition to the configuration of 22.

  The resistor 522, the resistor 523, and the MOS transistor 534 are connected in series between the power supply (VCC) 514 and the source of the MOS transistor 532. One of the resistors 522 is connected to the power supply (VCC) 514 and the other is connected to the MOS transistor 534. One of the resistors 523 is connected to the source of the MOS transistor 532 and the bias power supply 512, and the other is connected to the MOS transistor 534. The MOS transistor 534 is connected between the resistors 522 and 523.

  The node 562 outputs the voltage at the node between the resistor 522 and the MOS transistor 534 to the negative terminal side of the operational amplifier 541. The operational amplifier 541 inputs a voltage to the negative terminal of the operational amplifier 541 based on the output voltage from the node 562 and the control voltage Vcnt input to the input terminal 551. At this time, the voltage output from the node 562 is output to the node 563 through the voltage buffer 572 and the resistor 526. Further, the control voltage Vcnt input to the input terminal 551 is output to the node 563 via the resistor 527. The node 563 divides the voltage output from the node 562 and the voltage determined based on the control voltage Vcnt by the resistors 526 and 527, and outputs the divided voltage to the negative terminal of the operational amplifier 541.

  The node 561 outputs the voltage at the node between the resistor 521 and the MOS transistor 531 to the plus terminal side of the operational amplifier 541. The operational amplifier 541 inputs a voltage to the plus terminal of the operational amplifier 541 based on the output voltage from the node 561 and the control voltage Vcent input to the input terminal 553. At this time, the voltage output from the node 561 is output to the node 564 via the voltage buffer 571 and the resistor 524. Further, the control voltage Vcent input to the input terminal 553 is output to the node 564 via the resistor 525. The node 564 divides the voltage output from the node 561 and the voltage determined based on the control voltage Vcent by the resistors 524 and 525, and outputs the divided voltage to the plus terminal of the operational amplifier 541.

  The resistors 521 and 522, the resistors 524 and 526, and the resistors 525 and 527 are configured to have substantially the same resistance value. This is one example, and various resistance values can be set.

  Next, the operation of the control circuit 502 in FIG. 25 will be described. The slope of the change in the conductance between the source and drain of the MOS transistor 532 with respect to the control voltage Vcnt is determined by the feedback loop determined by the operational amplifier 541, the ratio of the resistance values of the resistors 524 and 525, and the ratio of the resistance values of the resistors 526 and 527. It is fixed in proportion to R525 / (R521 × R524). Here, R521 indicates the resistance value of the resistor 521, R524 indicates the resistance value of the resistor 524, and R525 indicates the resistance value of the resistor 525. Further, when the control voltage Vcnt = the control voltage Vcent is input to the input terminals 551 and 553, the current generated in the resistors 521 and 522 is operated to have the same value by feedback. The bias power supply 512 is connected to the gates of the MOS transistors 531 and 534 so as to operate in the saturation region. Therefore, the potentials of the sources of the MOS transistors 531 and 534 are set to a substantially constant value. Thus, the source-drain conductance of the MOS transistor 532 is set to a constant value by the resistance value R523 of the resistor 523. This can be said to be a circuit operation in which the current flowing through the resistor 523 determined by the resistor 523, the MOS transistor 534, and the bias voltage 512 is mirrored so as to also flow through the MOS transistor 532, and the resistance value of the MOS transistor 532 corresponding to the resistor 523 The conductance is set to a constant value by R523.

  As described above, by using the control circuit 502 according to the fifth embodiment of the present invention, the slope of the change in the conductance between the source and drain of the MOS transistor 532 with respect to the control voltage Vcnt is proportional to R525 / (R521 × R524). Therefore, as in the fourth embodiment, the source-drain conductance of the MOS transistor 532 can be controlled linearly. Further, the resistance between the source and drain of the MOS transistor 532 when the control voltage Vcnt = the control voltage Vcent can be determined by R523. As a result, as shown in graphs 1 and 2 shown in FIG. 26, the relationship between conductance and Vcnt that may be changed due to environmental fluctuations and process fluctuations is calculated when the control voltage Vcnt = the control voltage Vcent. It can be uniquely set in the graph 3 having 1 / R523. Accordingly, the change in conductance between the source and drain of the MOS transistor 533 connected to the operational amplifier 541 can be controlled linearly and uniquely.

(Other embodiments)
Next, a configuration example of the variable attenuator 20 will be described with reference to FIG. The variable attenuator 20 in this figure has a configuration in which the resistor 21 of the variable attenuator 20 in FIG. One of the source and drain of the MOS transistor 81 is connected to the input terminal, and the other is connected to one of the source and drain of the MOS transistor 22 and the output terminal to the variable gain amplifier 30. Thereby, for example, the source-drain resistance of the MOS transistor 22 is lowered by increasing the control voltage 220 of the MOS transistor 22, and at the same time, the resistance between the source and drain of the MOS transistor 81 is raised by lowering the control voltage 810 of the MOS transistor 81. As described above, the amount of attenuation can be changed by controlling the two control voltages in a complementary manner.

  Next, a configuration example when the variable attenuator 20 is a differential input will be described with reference to FIG. The variable attenuator 20 in this figure has a configuration in which a resistor 82 is added to the configuration of the variable attenuator 20 in FIG. The resistor 82 is connected to a different side from the resistor 21 connected to one of the source and drain of the MOS transistor 22. Since the operation is the same as that of the first embodiment, description thereof is omitted.

  Next, another configuration example when the variable attenuator 20 is a differential input will be described with reference to FIG. The variable attenuator 20 in this figure has a configuration in which the resistors 21 and 82 in FIG. 11 are replaced with MOS transistors 83 and 84. The MOS transistors 83 and 84 variably control the source-drain resistance by the control voltage 830. The operation is the same as that of the variable attenuator 20 of FIG.

  Next, a configuration example of the variable gain amplifier 30 will be described with reference to FIG. The variable gain amplifier 30 includes a current-voltage conversion circuit 90, a bipolar transistor 91, and a MOS transistor 92. A signal output from the variable attenuator 20 is connected to the base of the bipolar transistor 91. Further, the current-voltage conversion circuit 90 is connected to the collector of the bipolar transistor 91, and the drain of the MOS transistor 92 is connected to the emitter. The source of the MOS transistor 92 is grounded. The gain obtained by the variable gain amplifier 30 can be changed by changing the resistance between the source and drain of the MOS transistor 92, which is the emitter resistance of the bipolar transistor 91, by the control voltage 920. Further, if the bias current of the bipolar transistor 91 is made constant and the conversion gain of the current-voltage conversion circuit 90 is made constant, a constant 1 dB compression point characteristic can be obtained.

  Next, another configuration example of the variable gain amplifier 30 will be described with reference to FIG. The variable gain amplifier 30 in FIG. 14 has a configuration in which the bipolar transistor 91 in FIG. 13 is replaced with a MOS transistor 93. The operation is the same as that of the variable gain amplifier 30 of FIG.

  Next, another configuration example of the variable gain amplifier 30 will be described with reference to FIG. The variable gain amplifier 30 in FIG. 15 has a configuration in which the bipolar transistors 32 and 33 of the variable gain amplifier 30 in FIG. 3 are replaced with MOS transistors 94 and 95. The operation is the same as that of the variable gain amplifier 30 of FIG.

  As described above, the variable attenuator 20 and the variable gain amplifier 30 can be combined with various circuit configurations according to the target characteristics.

  Note that the present invention is not limited to the above-described embodiment, and can be changed as appropriate without departing from the spirit of the present invention.

DESCRIPTION OF SYMBOLS 10, 10_1, 10_2 Control circuit 11 Power supply part 12 Current voltage conversion circuit 13 Operational amplifier 14 MOS transistor 15 Bias power supply 16 MOS transistor 20 Variable attenuator 21 Resistance 22 MOS transistor 23 Capacitor 30 Variable gain amplifier 31 Current voltage conversion circuit 32, 33 Bipolar Transistor 34 Resistor 35 MOS transistor 40 Variable gain amplifier 41, 42 Bipolar transistor 43 Resistor 50 Adder 61 Resistor 62, 68 Bias power supply 63, 64, 66, 67 Resistor 65 Operational amplifier 81 MOS transistor 83, 84 MOS transistor 90 Current voltage converter circuit 91 Bipolar transistor 92, 93 MOS transistor 94, 95 MOS transistor 101 Control circuit 102, 103 Variable gain array Flop 104 fixed attenuator 105 addition unit 106 current-voltage conversion circuit 107 and the transistor 110 control circuit 111 variable attenuator 112 a variable gain amplifier

Claims (15)

A variable attenuation unit for attenuating the input signal;
A first variable gain amplifying unit for changing and amplifying the gain of the attenuated input signal output from the variable attenuating unit;
A variable gain amplifying apparatus comprising: a control unit configured to control a first control region in which a gain is changed by the first variable gain amplifying unit so as to fix an attenuation amount of the variable attenuating unit. The control unit further includes:
The second control region for fixing the gain by the first variable gain amplifying unit is controlled to change the attenuation amount of the variable attenuating unit,
The third control region that shifts the gain of the first variable gain unit from the second control region to the first control region is controlled so as to change the attenuation amount of the variable attenuation unit. The variable gain amplifying device described. The first control region is a period in which the gain of the output signal from the first variable gain unit is greater than a first threshold,
The second control region is a period in which a gain of an output signal from the first variable gain unit is smaller than a second threshold indicating a gain smaller than the first threshold,
3. The variable gain amplifying apparatus according to claim 2, wherein the third control region is a period in which a gain of an output signal from the first variable gain section is smaller than the first threshold and larger than the second threshold. . The variable attenuation unit and the first variable gain amplification unit include a MOS transistor,
The control unit outputs a control voltage to a MOS transistor included in the variable attenuation unit and the first variable gain amplification unit, so that the attenuation amount of the variable attenuation unit and the first variable gain amplification unit 4. The variable gain amplifying apparatus according to claim 3, wherein the amount of gain change is controlled. The controller is
In the case of the first control region, a variable control voltage is output to the first variable gain amplification unit, and a fixed control voltage is output to the variable attenuation unit.
In the case of the second control region, a fixed control voltage is output to the first variable gain amplification unit, and a variable control voltage is output to the first variable attenuation unit.
5. The variable gain amplifying apparatus according to claim 4, wherein in the third control region, a variable control voltage is output to the first variable gain amplifying unit and the variable attenuating unit. A second variable gain amplifying unit connected in parallel with the variable attenuating unit and amplifying the gain of the acquired input signal;
The variable gain according to claim 1, further comprising: an output signal generation unit configured to generate an output signal based on a signal after gain amplification output from the first variable gain amplification unit and the second variable gain amplification unit. Amplification equipment. The controller is
The variable gain amplifying apparatus according to claim 6, wherein, in the case of the first control region, the gain of the first variable gain amplifying unit is decreased and the gain of the second variable gain amplifying unit is amplified. The controller is
A first resistance unit provided between the first power source and a second power source having a lower potential than the first power source and connected to the first power source;
A first MOS transistor provided between the first power supply and the second power supply and connected in series with the first resistor;
A second MOS transistor provided between the first MOS transistor and the second power supply and connected in series with the first MOS transistor;
An operational amplifier that outputs a gate voltage to the second MOS transistor based on a voltage at a node between the first resistor section and the first MOS transistor and a first control voltage;
8. The variable gain amplifying apparatus according to claim 1, wherein the operational amplifier outputs the gate voltage to an external variable resistor whose resistance value is controlled based on the gate voltage.   9. The variable gain amplifying apparatus according to claim 8, wherein the first MOS transistor operates in a saturation region, and the second MOS transistor operates in a linear region.   First bias voltage is supplied to the first MOS transistor and the second MOS transistor so that the first MOS transistor operates in a saturation region and the second MOS transistor operates in a linear region. The variable gain amplifying apparatus according to claim 9, further comprising a bias power supply.   11. The operational amplifier according to claim 8, wherein the operational amplifier outputs the gate voltage to a variable resistor using an external third MOS transistor whose resistance value is controlled based on the gate voltage. Variable gain amplifier.   And a second bias power source connected to the second MOS transistor so that one of the second MOS transistor and the third MOS transistor has substantially the same potential. The variable gain amplifying device according to any one of 8 to 11. A second resistor provided between a third power source and the second power source and connected to the third power source;
A fourth MOS transistor provided between the third power source and the second power source and connected in series with the second resistance unit;
A third resistor connected in series with a node of the fourth MOS transistor, the second MOS transistor, and the second power supply;
The operational amplifier includes a first input voltage determined based on a voltage at a node of the second resistor unit and the fourth MOS transistor and the first control voltage, the first resistor unit, and the first resistor unit. 13. The variable gain amplifying device according to claim 8, wherein a voltage at a node of one MOS transistor and a second input voltage determined based on the second control voltage are input.   14. The variable gain amplifying apparatus according to claim 13, wherein when the first control voltage and the second control voltage are the same, a resistance value of the second MOS transistor is determined by a resistance value of the third resistance unit.   The first input voltage includes a fourth resistor unit connected in series between a node of the second resistor unit and the fourth MOS transistor and an input terminal for inputting the first control voltage, and The second input voltage is divided between a node of the first resistor and the first MOS transistor and an input terminal for inputting the second control voltage. 15. The variable gain amplifying device according to claim 13 or 14, wherein the voltage is divided based on a sixth resistor and a seventh resistor connected in series.

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