JP2011109584A - Solid-state image sensor and solid-state imaging device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a solid-state image sensor whose mounting area can be reduced. <P>SOLUTION: The solid-state image sensor includes: a plurality of photoelectric converters 11 disposed in a matrix form in a photo-detecting area 10a on a substrate irradiated with light; a plurality of vertical transfer units 12 provided in parallel with one another in a row direction for vertically transferring signal charges of the photoelectric converters 11 in the unit of a column and provided in parallel with one another in the row direction in an OB area 10b covered with a light shielding film on the substrate for synchronously vertically transferring reference charges corresponding to dark currents to vertical transfer units 12; and a horizontal transfer unit for horizontally transferring signal charges and the reference charges read from the vertical transfer units 12. In the overall OB area 10b or in a part of it, an interval between neighboring vertical transfer units 12 is narrower than an interval between neighboring vertical transfer units 12 in the photo-detecting area 10a. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a solid-state imaging device such as a CCD used in a still camera, a video camera, and the like, and more particularly to a technique for reducing the mounting area of the solid-state imaging device.

An imaging apparatus such as a digital camera has a configuration in which a signal level is output from an effective pixel and an optical black pixel, and a signal level of the optical black pixel is subtracted from the signal level of the effective pixel (see, for example, Patent Document 1).
Thereby, the dark current component can be removed from the signal level of the effective pixel.
FIG. 10 is a schematic plan view showing a schematic configuration of such a solid-state imaging device.

The solid-state imaging device includes a semiconductor substrate 50 provided with a light receiving region 50a that receives irradiated light.
The light receiving area 50a is provided with photoelectric conversion sections 51 in a matrix form, and a vertical transfer section having a CCD structure that vertically transfers charges (signal charges) stored in one column provided in the vertical direction. 52 are provided on the side of each column of the photoelectric conversion units 51 (on the left side in the figure).

Further, the semiconductor substrate 50 is provided with an optical black (hereinafter referred to as “OB region”) 50 b covered with a light shielding film 55 adjacent to the light receiving region 50 a.
The OB region 50b is provided with a plurality of columns of vertical transfer units 52 that do not have the photoelectric conversion unit 51, and accumulates a charge (reference charge) that becomes a dark current.
For convenience of explanation, it is assumed that there are m columns of vertical transfer units 52 without the photoelectric conversion unit 51 in the OB region 50b.

Here, the vertical transfer unit 52 of the OB region 50b has the same configuration as the vertical transfer unit 52 of the light receiving region 50a, and the pitch of the adjacent vertical transfer units 52 is also the same as that of the vertical transfer unit 52 of the light receiving region 50a. It is.
In the above configuration, the vertical transfer units 52 in the light receiving region 50a and the OB region 50b sequentially transfer the signal charges and the reference charges in sequence by the drive pulses φV1 to φV8 output from the timing control circuit 56, respectively.

The horizontal transfer unit 53 includes a plurality of signal charges (hereinafter referred to as “signal charge group”) transferred from the lowest stage of each vertical transfer unit 52 in the light receiving region 50a and the bottom of each vertical transfer unit 52 in the OB region 50b. A plurality of reference charges (hereinafter referred to as “reference charge group”) transferred from the lower stage are sequentially horizontally transferred by drive pulses φH1 and φH2 output from the timing control circuit 56.
Here, the reference charge group includes m columns of reference charges in the horizontal transfer unit 53, and is transferred horizontally following the horizontal transfer of the signal charge group.

The signal charge group and the reference charge group horizontally transferred by the horizontal transfer unit 53 are converted into voltage values corresponding to each signal charge and each reference charge by the output unit 54 and output to the A / D conversion unit 57. The
The A / D conversion unit 57 performs A / D conversion on the acquired voltage value and outputs it to the signal processing unit 58.

Then, a digital signal having a voltage corresponding to the reference charge is clamped by a clamp pulse output from the timing control circuit 56 at a predetermined timing, and is output as a black reference signal to the signal processing unit 58.
For example, the signal processing unit 58 averages the signal levels corresponding to m columns of reference charges in the horizontal transfer unit 53 included in the reference charge group, and calculates the average value from the signal levels corresponding to the signal charges. Correction for subtraction is executed to generate an image signal that does not include a dark current component.

By the way, in recent years, as the number of pixels in solid-state imaging devices increases and the degree of integration increases, the number of horizontal transfer stages increases, the interelectrode capacitance also increases, and power consumption tends to increase.
Therefore, a horizontal interlaced solid-state imaging device capable of transferring charges while suppressing interelectrode capacitance has appeared.
In this type of solid-state imaging device, the vertical transfer units 52 in both areas including the light receiving area 50a and the OB area 50b are grouped into adjacent n columns (n is an integer of 2 or more), and the first column of each group The charges in the second row,..., And the last row are sequentially transferred horizontally in n times.

JP 2006-310655 A

  However, when horizontal transfer is performed by dividing one line into three times, in order to stably clamp the black reference signal, the clamp is usually performed once in each horizontal transfer period and three times in one line output period. It is. Further, in a solid-state imaging device that does not perform horizontal interlacing, one reference charge group includes reference charges for m columns of the horizontal transfer unit 53, but the charge for one horizontal line is divided into three times. In the case of the horizontal interlacing method, only one reference charge for (m / 3) columns of the horizontal transfer unit 53 is included in one reference charge group.

Therefore, when the horizontal transfer frequency is the same, in the horizontal interlaced solid-state imaging device as described above in order to stably clamp the black reference signal, (3 × m) columns of vertical transfer units 52 in the OB region 50b. Therefore, there is a problem that the mounting area of the solid-state imaging device increases and the manufacturing cost increases.
Even when horizontal interlacing is not performed, the demand for high pixel and high frame rate is high in the market, and as a result, the horizontal transfer frequency is high. In this respect as well, it is necessary to increase the number of pixels in the optical black area. There is a problem of increasing the area of the optical black region.

  The present invention has been made in view of the above problems, and an object of the present invention is to provide a solid-state imaging device capable of reducing the mounting area of the solid-state imaging device.

  In order to achieve the above object, a solid-state imaging device according to the present invention is provided in parallel with a plurality of photoelectric conversion units arranged in a matrix in a light receiving region on a substrate irradiated with light, and A reference charge corresponding to a dark current, which is arranged in parallel in a row direction in a plurality of first vertical transfer units that vertically transfer signal charges of the conversion unit in units of columns and an optical black region covered with a light shielding film on the substrate. A plurality of second vertical transfer units that perform vertical transfer in synchronization with the first vertical transfer units, and a signal charge read from each first vertical transfer unit and a reference charge read from each second vertical transfer unit. A horizontal transfer section that is configured such that, in all or part of the optical black area, the interval between adjacent second vertical transfer sections is narrower than the interval between adjacent first vertical transfer sections.

With the above configuration, in all or part of the optical black region, the pitch of the adjacent second vertical transfer units is narrower than the pitch of the adjacent first vertical transfer units, so the mounting density in the optical black region is higher than that of the light receiving region. And the mounting area of the entire solid-state imaging device can be reduced accordingly.
The optical black region is further divided into a first optical black region and a second optical black region, and the first optical black region is provided with a photoelectric conversion portion shielded by the light shielding film. In the second optical black region, no photoelectric conversion unit is provided, and the interval between the adjacent second vertical transfer units is narrower than the interval between the adjacent first vertical transfer units.

  As a result, due to the presence of the partial area in which the photoelectric conversion unit is provided, the structure of the light receiving region and the optical black region becomes equivalent during long exposure, and the value of the dark current in the photoelectric conversion unit and the vertical transfer path In addition, the existence of the other regions without the photoelectric conversion part can reduce the mounting area and reduce the dark current values in the light receiving region and the optical black region during normal exposure. It can be a problem-free level.

Here, it is desirable that the width of the second vertical transfer unit in the row direction is equal to the width of the first vertical transfer unit in the row direction.
As a result, the values of the dark current generated in the first vertical transfer unit and the second vertical transfer unit become equal, so that even if the temperature changes, it is possible to suppress a deviation in the value of the black reference signal between the two. it can.

The light shielding film may be further covered with a light shielding film different from the light shielding film in the optical black region.
As a result, even when the intensity of the irradiated light is high, the light does not easily enter the optical black region, so that the dark current can be detected with higher accuracy.
Further, the second vertical transfer unit includes a vertical transfer path provided so as to extend in the column direction on the substrate and a plurality of vertical transfer electrodes arranged above the vertical transfer path, and is disposed in the same row. Vertical transfer electrodes corresponding to each of the plurality of vertical transfer paths adjacent in the row direction are integrally formed in the optical black region in which the electrodes are electrically connected and no photoelectric conversion unit is provided. It may be.

As a result, the pitch of the vertical transfer paths adjacent in the row direction can be further reduced.
In addition, horizontal interlace drive that divides and outputs a signal of one line in the horizontal direction twice or more may be applied.
As a result, an increase in the mounting area of the solid-state imaging device can be suppressed even when it is necessary to set a larger number of second vertical transfer units in the optical black region than when horizontal interlace is not performed.

  In addition, this invention is good also as a solid-state imaging device provided with the said solid-state image sensor.

It is a plane schematic diagram for demonstrating schematic structure of the solid-state imaging device which concerns on embodiment of this invention. It is sectional drawing of the solid-state imaging device which concerns on embodiment of this invention. It is a plane schematic diagram explaining the basic composition in the solid-state imaging device. It is a plane schematic diagram which simplifies and shows the basic composition in the solid-state imaging device. 6 is a timing chart for explaining the operation of the solid-state imaging device according to the embodiment. (A)-(d) is a schematic diagram for description of operation | movement of the solid-state imaging device, respectively. It is a figure which shows the modification (the 1) of embodiment of this invention. It is a figure which shows the modification (the 2) of embodiment of this invention. It is a figure which shows the modification (the 3) of embodiment of this invention. It is a plane schematic diagram which shows the schematic structure of the conventional solid-state imaging device.

Hereinafter, a solid-state imaging device according to an embodiment of the present invention will be described with reference to the drawings.
FIG. 1 is a schematic plan view for explaining the configuration of a solid-state imaging device 1 according to an embodiment of the present invention.
This solid-state image pickup device 1 is a horizontal interlace CCD solid-state image pickup device that outputs a signal of one horizontal line divided into two or more times. For example, the solid-state image pickup device 1 is used in a still camera, and each unit unit pixel The semiconductor substrate 10 on which a plurality of photoelectric conversion portions 11 are formed is provided.

The semiconductor substrate 10 includes a light receiving region 10a which is a region irradiated with light through a lens (not shown), and an optical black region (hereinafter referred to as “OB region”) covered with a light shielding film 7b so as not to be irradiated with light. 10b), and photoelectric conversion units 11 are arranged in a matrix in the light receiving region 10a.
In the light receiving region 10a as well, in order to suppress the occurrence of smear, the light receiving region 10a is also provided with a light shielding film 7a so that only the light receiving surface of each photoelectric conversion unit 11 is exposed.

Here, the light shielding films 7a and 7b are made of, for example, a tungsten film.
When the photoelectric conversion units 11 arranged along the row direction (horizontal direction) and the column direction (vertical direction) in the light receiving region 10a receive light on the respective light receiving surfaces not covered by the light shielding film 7a, A signal charge corresponding to the amount of received light is generated by the conversion.
In the light receiving region 10a, a vertical transfer unit 12 having a CCD structure is provided on the side of the plurality of photoelectric conversion units 11 constituting one column along the vertical direction (the left side in FIG. 1).

The vertical transfer units 12 in the light receiving region 10a are arranged at a pitch of length L1 in the horizontal direction, and are stored in each of the photoelectric conversion units 11 in the column adjacent to the right side of the vertical transfer unit 12 in the horizontal direction. The charged charges (signal charges) are read out and transferred in the vertical direction.
In the solid-state imaging device 1 of the present embodiment, the photoelectric conversion unit 11 is not provided between the vertical transfer units 12 in the OB region 10b covered with the light shielding film 7b, and adjacent vertical transfer units in the OB region 10b. 12 are arranged at a pitch of a length L2 shorter than the length L1 in the horizontal direction.

Thereby, the mounting area is smaller than that of the conventional solid-state imaging device in which the pitch in the horizontal direction of the adjacent vertical transfer units 12 is the same in the light receiving region 10a and the OB region 10b.
Here, for example, when L1 is 1.5 μm and L2 is 0.375 μm, in the solid-state imaging device 1 having 12 million effective pixels, 1.11% of the mounting area can be reduced.

The mounting area reduction effect is a value calculated by setting the number of columns of the vertical transfer unit 12 in the light receiving region 10a to 4000 and the number of columns of the vertical transfer unit 12 in the OB region 10b to 60.
Each of the vertical transfer units 12 provided in the OB region 10b is shielded by the light shielding film 7b, so that a charge that becomes a dark current (a charge that is thermally excited in a light shielding state: hereinafter referred to as a “reference charge”). ) Are accumulated and transferred in the vertical direction.

The light receiving surface of each photoelectric conversion unit 11 provided in the light receiving region 10a is covered with one color filter selected from an R (red) filter, a G (green) filter, and a B (green) filter.
More specifically, the R, G, and B color filters are arranged in a Bayer array, the rows in which the G filters and the B filters are alternately arranged in the horizontal direction, and the R filters and the G filters in the horizontal direction. Are alternately arranged in the vertical direction (column direction).

Note that the solid-state imaging device 1 according to the present embodiment shown in FIG. 1 has a configuration in which all stages are vertically transferred in eight phases, but is not limited to such a configuration.
FIG. 2 is a cross-sectional view of the solid-state imaging device according to the embodiment of the present invention, and FIG. 3 is a schematic plan view for explaining the basic configuration of the light-receiving region 10a in the solid-state imaging device. The photoelectric conversion part 11 provided in 10a is abbreviate | omitted and drawn.

The basic configuration of the OB region 10b is substantially the same as that of the light receiving region 10a except that the photoelectric conversion unit 11 is not provided and the entire region is covered with the light shielding film 7b.
As shown in FIGS. 2 and 3, in the vertical transfer unit 12, a plurality of vertical transfer electrodes 9 are arranged on a vertical transfer path 112 formed to extend in the vertical direction.
Since such vertical transfer units 12 are arranged in parallel in the horizontal direction, the vertical transfer electrodes 9 are also arranged in a matrix as shown in FIG.

The adjacent vertical transfer electrodes 9 arranged in the same row (horizontal direction) are connected by a conductive line 9a.
Here, the width of the vertical transfer unit 12, that is, the width of the vertical transfer path 112 in the horizontal direction is equal in both the light receiving region 10a and the OB region 10b.
As a result, the values of the dark currents generated in the vertical transfer unit 12 in both the light receiving region 10a and the OB region 10b can be made substantially equal, so that even when the temperature changes, between the regions. It is possible to suppress the deviation of the black reference signal value.

Further, in the light receiving region 10a, the vertical transfer portion 12 provided with the vertical transfer electrode 9 is covered with a light shielding film 7a, and in the OB region 10b, the vertical transfer portion 12 provided with the vertical transfer electrode 9 is shielded from light. It is covered with a film 7b (see FIG. 2).
Returning to FIG. 1, in each vertical transfer portion 12 of the light receiving region 10a and the OB region 10b, a plurality of electrodes (not shown) for transferring charges in the vertical direction are arranged along the vertical direction. The drive pulse output from the timing control circuit 31 is applied to each electrode at a predetermined timing, so that the signal charge read to each vertical transfer unit 12 is sequentially in the vertical direction (downward in the figure). Transferred.

In the semiconductor substrate 10, the signal charges and the reference charges transferred from all the vertical transfer sections 12 provided in the light receiving area 10a and the OB area 10b are divided into three times in the horizontal direction (left direction in the figure). The horizontal transfer section 17 having a CCD structure for transferring to () is disposed in a state along the horizontal direction over the light receiving area 10a and the OB area 10b.
Between the vertical transfer unit 12 and the horizontal transfer unit 17, a charge holding unit 13 and a charge transfer unit (VOG unit) 18 for accumulating and holding charges are provided.

The charge holding unit 13 includes a storage unit 15 and a hold unit 16. By providing the storage unit 15 and the hold unit 16, the transfer of signal charges from the vertical transfer unit 12 to the horizontal transfer unit 17 is controlled.
The charge holding unit 13 and the VOG unit 18 are provided in each vertical transfer unit 12 for each predetermined number (three in this embodiment) of vertical transfer units 12 (hereinafter referred to as vertical transfer groups 12G) adjacent to each other. The charges are sequentially transferred to the horizontal transfer unit 17.

The horizontal transfer unit 17 performs horizontal transfer (horizontal interlace transfer) of the transferred charge every time charge is transferred from one vertical transfer unit 12 in each vertical transfer group 12G.
The semiconductor substrate 10 is provided with an output unit 14 that outputs a voltage corresponding to the charge horizontally transferred by the horizontal transfer unit 17.
The voltage output from the output unit 14 is supplied to an A / D conversion unit (signal conversion unit) 32 provided in the image signal generation unit 34.

The A / D converter 32 digitally converts the voltage output from the output unit 14 and outputs it to the signal processor 33 provided in the image signal generator 34.
The A / D converter 32 clamps the digital value of the voltage corresponding to the reference charge transferred from the predetermined vertical transfer unit 12 provided in the OB area 10b by the clamp pulse output from the timing control circuit 31. The clamped digital signal is output to the signal processing unit 33 as a black reference signal.

The signal processing unit 33 performs signal processing on the digital signal output from the A / D conversion unit 32 based on the clamped black reference signal to generate an image signal.
That is, the signal processing unit 33 subtracts the signal level of the optical black pixel from the signal level of the effective pixel, and outputs a signal obtained by removing the dark current component from the signal level of the effective pixel as an image signal.

FIG. 4 is a schematic plan view showing FIG. 3 in a simplified manner.
4 omits the photoelectric conversion unit 11 provided in the light receiving region 10a, as in FIG.
Further, in FIG. 4, the signal lines are omitted, and the signal charges vertically transferred through the vertical transfer units 12 in the light receiving region 10 a are read out from the color filters provided in the read photoelectric conversion units 11. Colors (R, G, B) are shown.

In the horizontal transfer unit 17, a plurality of electrodes (not shown) are arranged side by side along the horizontal direction. In this embodiment, three electrodes adjacent to each other in the horizontal transfer unit 17 are transferred by one horizontal transfer. As the group 17G, three-phase drive pulses φH1, φH2, and φH3 output from the timing control circuit 31 are applied at a predetermined timing.
Each electrode forms a unit transfer bit for horizontally transferring charges transferred from each vertical transfer unit 12 in the horizontal transfer unit 17.

  One horizontal transfer group 17G in the horizontal transfer unit 17 is arranged in the central part in the transfer direction, and has a sub-unit transfer bit H1 to which the drive pulse φH1 is applied and a downstream side in the horizontal transfer direction with respect to the sub-unit transfer bit H1. And main unit transfer bits H2 and H3, which are arranged on the upstream side and to which drive pulses φH2 and φH3 are applied, respectively.

  In the solid-state imaging device of this embodiment, one horizontal transfer group 17G in the horizontal transfer unit 17 is associated with one vertical transfer group 12G, and the charge holding unit 13 and the VOG unit 18 are connected to each vertical transfer group 12G. The charges transferred to the respective end portions of the three vertical transfer units 12 constituting the are sequentially transferred to the main unit transfer bits H2 or H3 in the horizontal transfer unit 17.

FIG. 3 shows two vertical transfer groups 12G adjacent to each other. In the following description, as shown in FIG. 4, the left vertical transfer group 12G is replaced with the first vertical transfer group 12G-1. The right vertical transfer group 12G is defined as a second vertical transfer group 12G-2.
Further, the three vertical transfer units 12 in one vertical transfer group 12G are referred to as a first vertical transfer unit 12a, a second vertical transfer unit 12b, and a third vertical transfer unit 12c in order from the left side.

Further, as shown in FIG. 4, the horizontal transfer group 17G corresponding to the first vertical transfer group 12G-1 is defined as the first horizontal transfer group 17G-1, and the horizontal transfer group corresponding to the second vertical transfer group 12G-2. Let 17G be the second horizontal transfer group 17G-2.
The storage unit 15 of the charge holding unit 13 receives the charges transferred from the first vertical transfer unit 12a, the second vertical transfer unit 12b, and the third vertical transfer unit 12c in each of the vertical transfer groups 12G-1 and 12G-2. The storage unit 16 includes a first storage unit Sa, a second storage unit Sb, and a third storage unit Sc, and the charge storage unit 13 includes a first storage unit Sa, a second storage unit Sb, and a third storage unit Sc. The first hold unit Ha, the second hold unit Hb, and the third hold unit Hc that hold the electric charges accumulated in the first and second hold units, respectively.

  As shown in FIG. 3, each of the first storage unit Sa, the second storage unit Sb, and the third storage unit Sc includes drive pulses φVST-a, φVST-b, and φVST-c output from the timing control circuit 31. Is applied to each of the first hold unit Ha, the second hold unit Hb, and the third hold unit Hc. The drive pulses φVHLD-a, φVHLD-b output from the timing control circuit 31 φVHLD-c is applied.

  In this embodiment, the drive pulses φVST-a, φVST-b, and φVST-c are respectively applied to a middle level (a high level signal applied when reading charges and a barrier when transferring charges). Charge is accumulated in each of the first storage unit Sa, the second storage unit Sb, and the third storage unit Sc, and driving pulses φVHLD-a, φVHLD. Since −b and φVHLD-c are at the middle level, charges are accumulated in the first hold unit Ha, the second hold unit Hb, and the third hold unit Hc, respectively.

The VOG unit 18 converts the signal charges held in the first hold unit Ha, the second hold unit Hb, and the third hold unit Hc corresponding to each vertical transfer group 12G to the main unit transfer bit of each horizontal transfer group 17G. Transfer to H2 or H3.
The drive pulse φVOG output from the timing control circuit 31 is applied to the VOG unit 18, and when the drive pulse φVOG changes from the middle level to the low level, the main unit of the corresponding horizontal transfer group 17G. Charges are transferred to the transfer bits H2 and H3.

  Similar to the light receiving region 10a, the OB region 10b is provided with three vertical transfer units 12a, 12b, and 12c that constitute the vertical transfer group 12G. The charge holding unit 13 and the VOG unit 18 use the light receiving region 10a. The reference charges of the vertical transfer units 12a, 12b, and 12c in the OB region 10b are transferred horizontally at the timing when the signal charges of the vertical transfer units 12a, 12b, and 12c of the vertical transfer group 12G are transferred to the horizontal transfer unit 17, respectively. Is transferred to the unit 17.

The operation of the solid-state imaging device having such a configuration will be described based on the timing chart of FIG. 5 and schematic diagrams shown in FIGS. 4 and 6A to 6D.
As shown in the timing chart of FIG. 5, in the first horizontal blanking period, each of the first to third vertical transfer units 12a in each of the first vertical transfer group 12G-1 and the second vertical transfer group 12G-2. , 12b, and 12c, the signal charges read from the photoelectric conversion units 11 adjacent on the right side are changed from the middle level to the low level by the eight-phase drive pulses φV1 to φV8, respectively. Transfer to the end close to 13.

  In this case, in the first vertical transfer unit 12a and the third vertical transfer unit 12c in the first vertical transfer group 12G-1, signal charges (hereinafter referred to as the signal charges) read from the photoelectric conversion unit 11 provided with the “R” color filter are provided. , “R-signal charge”) and signal charges (hereinafter referred to as “G-signal charge”) read out from the photoelectric conversion unit 11 provided with the “G” color filter. In the second vertical transfer unit 12b, the G-signal charge and the signal charge read from the photoelectric conversion unit 11 provided with the "B" color filter (hereinafter referred to as "B-signal charge") are transferred. ")") And the vertical transfer.

In the first vertical transfer unit 12a and the third vertical transfer unit 12c in the second vertical transfer group 12G-2, the G-signal charge and the B-signal charge are vertically transferred in a state of being alternately arranged, and the second vertical transfer unit 12G-2 performs the second vertical transfer. In the transfer unit 12b, the R-signal charge and the G-signal charge are vertically transferred in a state where they are alternately arranged.
FIG. 4 shows a signal charge accumulation state of each of the vertical transfer units 12a, 12b, and 12c immediately before the timing t1 (see FIG. 5, the same applies hereinafter).

At this timing t1, the signal charges of the vertical transfer units 12a, 12b, and 12c are at the middle level of φVST-a, φVST-b, and φVST-c. Transfer is started to the storage unit Sb and the third storage unit Sc, respectively.
In FIG. 4, R-signal charges, G− are connected to lower end portions of the first vertical transfer unit 12 a, the second vertical transfer unit 12 b, and the third vertical transfer unit 12 c in the first vertical transfer group 12 G- 1. The signal charge and the R-signal charge are respectively accumulated, and the G-signal charge is provided at the lower end of each of the first vertical transfer unit 12a to the third vertical transfer unit 12c in the second vertical transfer group 12G-2. , R-signal charge and G-signal charge are accumulated.

  In this state, when the drive pulse φV8 applied to each of the vertical transfer units 12a, 12b, and 12c becomes low level at the timing t3, the first storage unit Sa, the second storage unit Sb, Since the drive pulses φVST-a, φVST-b, and φVST-c applied to the third storage unit Sc are at the middle level, the signals accumulated at the ends of the vertical transfer units 12a, 12b, and 12c. Charge (R-signal charge, G-signal charge, R-signal charge in the first vertical transfer group 12G-1, G-signal charge, R-signal charge, G in the second vertical transfer group 12G-2) -Signal charges) are transferred to the first storage unit Sa, the second storage unit Sb, and the third storage unit Sc, respectively.

In this case, since the drive pulses φVHLD-a and φVHLD-b are at a low level, the first storage unit Sa and the second storage unit Sb transfer to the first vertical transfer unit 12a and the second vertical transfer unit 12b. The signal charges thus stored are accumulated in the first storage unit Sa and the second storage unit Sb.
On the other hand, since the drive pulse φVHLD-c is at the middle level at the timing t2, the signal charge transferred to the third storage unit Sc is transferred to the third hold unit Hc. Then, when the drive pulse φVOG applied to the VOG unit 18 is at a low level, signal charges are accumulated in the third hold unit Hc.

After that, when the drive pulse φVST-c applied to the third storage unit Sc becomes low level at timing t4, the signal charge of the third storage unit Sc is transferred to the third hold unit Hc and accumulated. As a result, the state shown in FIG.
In this state, when a predetermined time elapses and timing t5 is reached, the drive pulse φVOG applied to the VOG unit 18 becomes a middle level, and the signal charge accumulated in the third hold unit Hc is transferred to the VOG unit 18. Start to be. When the drive pulse φVHLD-c applied to the third hold unit Hc becomes low level at timing t6 while the middle level state of the drive pulse φVOG continues, the signal charge of the third hold unit Hc is It is transferred to the VOG unit 18.

  Further, at the subsequent timing t7, when the drive pulse φVOG applied to the VOG unit 18 becomes a low level, the signal charge transferred to the VOG unit 18 (the R-signal charge, the first charge in the first vertical transfer group 12G-1) In the second vertical transfer group 12G-2, as shown in FIG. 6B, the G-signal charge) is the main unit transfer bit H2 of the first horizontal transfer group 17G-1 and the second horizontal transfer group 17G-2 or H3 (main unit transfer bit H3 in FIG. 6B) is stored respectively.

When a predetermined time elapses after the drive pulse φVOG becomes low level and timing t8 is reached, three-phase drive pulses φH1 and φH2 are applied to the three electrodes of each horizontal transfer group 17G in the horizontal transfer unit 17. , ΦH3 is applied, and horizontal transfer of the signal charge transferred to the main unit transfer bit H2 or H3 is started.
The first horizontal blanking period ends when the application of the three-phase drive pulses φH1, φH2, and φH3 is started.

  In the first horizontal blanking period, also in the OB region 10b, the drive pulses φV1 to φV8 are applied to the vertical transfer unit 12 at the same timing, so that charges in the dark are transferred. Also in the charge holding unit 13 and the VOG unit 18, the drive pulses φVST-a, φVST-b, φVST-c, φVHLD-a, φVHLD-b, φVHLD-c, and φVOG are applied at the same timing, thereby The data is transferred to the main unit transfer bit H2 or H3 of the horizontal transfer group 17G in the transfer unit 17.

When the first horizontal transfer period starts at timing t8, three-phase drive pulses φH1, φH2, and φH3 are applied to the three electrodes of each horizontal transfer group 17G, whereby the main unit of each horizontal transfer group 17G is applied. The charges transferred to the transfer bit H2 or H3 are horizontally transferred to the output unit 14 in order.
Accordingly, after the signal charge transferred from the third vertical transfer unit 12c of each vertical transfer group 12G in the light receiving region 10a is transferred to the output unit 14, the third charge of each vertical transfer group 12G in the OB region 10b is continuously transmitted. The reference charge transferred from the vertical transfer unit 12 c is transferred to the output unit 14.

The output unit 14 outputs a voltage corresponding to the transferred charge to the A / D conversion unit 32 of the image signal generation unit 34.
The A / D conversion unit 32 performs A / D conversion on the voltage corresponding to the signal charge transferred from the third vertical transfer unit 12c of each vertical transfer group 12G in the light receiving region 10a and outputs the voltage to the signal processing unit 33. A voltage corresponding to the reference charge generated in the OB region 10b is clamped and output.

In the first horizontal transfer period, the timing control circuit 31 outputs a clamp pulse for clamping a voltage corresponding to the reference charge read from the OB region 10b.
As a result, the digital value of the voltage corresponding to the reference charge is clamped in the A / D conversion unit 32, and this digital value is output to the signal processing unit 33 as a black reference signal.
The signal processing unit 33 performs signal processing on the digital value of the voltage corresponding to the signal charge with reference to the black reference signal clamped by the A / D conversion unit 32 to generate an image signal.

  At the timing t9 when the horizontal transfer of charges by the three-phase drive pulses φH1, φH2, and φH3 output from the timing control circuit 31 is completed, one line worth from the third vertical transfer unit 12c in each vertical transfer group 12G. The first horizontal transfer period for horizontally transferring the signal charges to the output unit 14 ends, and the second horizontal blanking period for transferring the signal charges of the first vertical transfer unit 12a in each vertical transfer group 12G to the horizontal transfer unit starts. To do.

  In the second horizontal blanking period, the drive pulse φVHLD-a applied to the first hold unit Ha changes from the low level to the middle level and accumulates in the first storage unit Sa at a timing t10 when a predetermined time has elapsed from the timing t9. The signal charges thus started are transferred to the first hold unit Ha. At this time, since the drive pulse φVOG applied to the VOG unit 18 is at a low level, signal charges are accumulated in the first hold unit Ha.

Thereafter, at timing t11 while the drive pulse φVHLD-a continues to be at the middle level, the drive pulse φVST-a applied to the first storage unit Sa of the charge holding unit 13 becomes low level, and the VOG unit 18 The drive pulse φVOG applied to is at the middle level, and the charge accumulated in the first storage unit Sa is transferred to the first hold unit Ha and the VOG unit 18 .

When the drive pulse φVHLD-a applied to the first hold unit Ha becomes low level at the timing t12 while the drive pulse φVOG continues to be at the middle level, the signal charge accumulated in the first hold unit Ha Is transferred to the VOG unit 18.
When the drive pulse φVOG applied to the VOG unit 18 becomes a low level at timing t13 thereafter, as shown in FIG. 6C, the signal charges (first vertical transfer group 12G-1) transferred to the VOG unit 18 are obtained. R-signal charge in the second vertical transfer group 12G-2 and G-signal charge in the second vertical transfer group 12G-2) to the main unit transfer bits H2 or H3 of the first horizontal transfer group 17G-1 and the second horizontal transfer group 17G-2. Each is forwarded.

After that, at timing t14 after a predetermined time has elapsed, application of three-phase drive pulses φH1, φH2, and φH3 to the horizontal transfer unit 17 is started.
As a result, the second horizontal blanking period ends and the second horizontal transfer period starts.
Even in the second horizontal blanking period, the reference charge transferred to the end of the first vertical transfer unit 12a of the vertical transfer group 12G in the OB region 10b is the main charge of each horizontal transfer group 17G in the horizontal transfer unit 17. Transferred to the unit transfer bit H2 or H3, respectively.

In the second horizontal transfer period, as described above, when the three-phase drive pulses φH1, φH2, and φH3 are applied to the horizontal transfer unit 17, the signal charges transferred to the main unit transfer bit H2 or H3 and the reference The charges are sequentially transferred horizontally to the output unit 14 and output from the output unit 14 to the A / D conversion unit 32.
Also in this case, a clamp pulse is output from the timing control circuit 31.

As a result, the digital value of the voltage corresponding to the reference charge is clamped in the A / D conversion unit 32, and this digital value is output to the signal processing unit 33 as a black reference signal.
At the timing t15 when the horizontal transfer of charges by the three-phase drive pulses φH1, φH2, and φH3 from the timing control circuit 31 is completed, the charge for one horizontal line from the first vertical transfer unit 12a in each vertical transfer group 12G. The second horizontal transfer period for horizontally transferring the signal to the output unit 14 ends, and the third horizontal blanking period for transferring the signal charge of the second vertical transfer unit 12a in each vertical transfer group 12G to the horizontal transfer unit 17 starts. .

In the third horizontal blanking period, at timing t16 when a predetermined time has elapsed from timing t15, the drive pulse φVHLD-b applied to the second hold unit Hb becomes the middle level, and the signal accumulated in the second storage unit Sb The charge starts to be transferred to the second hold unit Hb.
At this time, since the drive pulse φVOG applied to the VOG unit 18 is at a low level, signal charges are accumulated in the second hold unit Hb.

  Thereafter, at timing t17 while the drive pulse φVHLD-b continues to be at the middle level, the drive pulse φVST-b applied to the second storage unit Sb of the charge holding unit 13 becomes low level and the VOG unit 18 The drive pulse φVOG applied to is at the middle level, and the charge accumulated in the first storage unit Sa is transferred to the first hold unit Ha and the VOG unit 18.

When the drive pulse φVHLD-a applied to the second hold unit Hb becomes low level at timing t18 while the drive pulse φVOG continues to be at the middle level, the signal charge accumulated in the second hold unit Hb Is transferred to the VOG unit 18.
When the drive pulse φVOG applied to the VOG unit 18 becomes a low level at the subsequent timing t19, as shown in FIG. 6D, the signal charges (first vertical transfer group 12G-1) transferred to the VOG unit 18 are obtained. G-signal charge in the second vertical transfer group 12G-2 and R-signal charge in the second vertical transfer group 12G-2 are the main unit transfer bits H2 or H3 (first horizontal transfer group 17G-1 and second horizontal transfer group 17G-2). In FIG. 6D, the data is transferred to the main unit transfer bit H3).

Thereafter, at timing t20 after a predetermined time has elapsed, application of the three-phase drive pulses φH1, φH2, and φH3 to the horizontal transfer unit 17 is started.
As a result, the third horizontal blanking period ends and the third horizontal transfer period starts.
Even in the third horizontal blanking period, in the OB region 10b, the reference charge transferred to the end of the second vertical transfer unit 12b of the vertical transfer group 12G is transferred to each horizontal transfer group 17G in the horizontal transfer unit 17. Transferred to main unit transfer bit H2 or H3, respectively.

With the start of the third horizontal transfer period, as described above, the signal charge and the reference charge transferred to the main unit transfer bit H2 or H3 by the three-phase drive pulses φH1, φH2, and φH3 applied to the horizontal transfer unit 17 Are sequentially transferred to the output unit 14 and output from the output unit 14 to the A / D conversion unit 32.
Also in this case, a clamp pulse is output from the timing control circuit 31 at a predetermined timing t21.

As a result, the digital value of the voltage corresponding to the reference charge is clamped in the A / D conversion unit 32, and this digital value is output to the signal processing unit 33 as a black reference signal.
Thereafter, the same operations as those performed in the first horizontal blanking period, the first horizontal transfer period, the second horizontal blanking period, the second horizontal transfer period, the third horizontal blanking period, and the third horizontal transfer period described above. The operation is performed in order, and in each vertical transfer group 12G, the charges of the third vertical transfer unit 12c, the first vertical transfer unit 12a, and the second vertical transfer unit 12b are transferred to each horizontal transfer group in that order. Are transferred horizontally.

Here, when the data is not accumulated for a long time, the dark current generated in the vertical transfer unit 12 is dominant with respect to the photoelectric conversion unit 11, so the OB region 10b shown in FIG. 1 or the OB region 10d in FIG. Thus, since the dark currents of the vertical transfer units 12 coincide with each other, there is no practical problem even with the above structure.
<Modification>
The present invention is not limited to the above-described embodiment, and the following modifications can be implemented.

(1) In the above embodiment, the OB region 10b of the solid-state imaging device 1 is the photoelectric conversion unit 11 is not provided, is not limited to this configuration.
For example, the OB area is further divided into a first optical black area and a second optical black area, and the first optical black area is provided with a photoelectric conversion portion shielded by the light shielding film, In this optical black region, no photoelectric conversion unit may be provided.

FIG. 7 is a schematic plan view for explaining a schematic configuration of the solid-state imaging device having such a configuration.
As shown in the figure, the first OB region 10c in which the photoelectric conversion unit 11 shielded by the light shielding film 7b is provided between the adjacent vertical transfer units 12 in the vertical direction, and the adjacent vertical transfer unit. 12, there is a second OB region 10 d without the photoelectric conversion unit 11.

Here, the pitch L3 of the vertical transfer unit 12 in the first OB region 10c and the pitch L1 of the vertical transfer unit 12 in the light receiving region 10a are the same.
Here, when the imaging target of the solid-state imaging device is in a bright place and the exposure time required for imaging is not so long, dark current is mainly generated in the vertical transfer unit 12 rather than the photoelectric conversion unit 11, and the photoelectric conversion unit The dark current generated at 11 is negligibly small.

However, when the imaging target of the solid-state imaging device is in a dark place and the exposure time required for imaging becomes long, the dark current generated in the photoelectric conversion unit 11 becomes a magnitude that cannot be ignored.
Therefore, by providing the first OB region 10c in which the photoelectric conversion unit 11 is provided as in the configuration shown in FIG. The dark current values generated in the OB region 10c can be made equal to each other.

As a result, the dark current component in accordance with the actual situation is obtained by subtracting the black reference signal level obtained in the first OB area 10c from the signal level of the effective pixel obtained in the light receiving area 10a during long exposure. It can be removed from the image signal.
(2) In the above embodiment, in the OB region 10b where the photoelectric conversion unit 11 is not provided between the vertical transfer units 12, the pitch of the vertical transfer units 12 is all equal to L2. It is not limited.

FIG. 8 is a cross-sectional view of a solid-state imaging device having such a configuration.
As shown in the figure, in this configuration, in the vertical transfer unit 12 of the OB area 10b, two columns are included in one set, and the intervals between the vertical transfer units 12 included in the same set are included in different sets. It is set narrower than the interval between adjacent vertical transfer units 12.
At this time, the vertical transfer electrodes 9 of the vertical transfer units 12 included in the same group may be integrated with each other as shown in FIG.

FIG. 8 is merely an example, and three or more sets of vertical transfer units 12 in the OB area 10b are set as one set, and the interval between the vertical transfer units 12 may be narrowed as described above. The vertical transfer electrodes 9 of these included vertical transfer portions 12 may be integrally formed.
In this case, from the viewpoint of reducing the mounting area of the solid-state imaging device, the interval between adjacent vertical transfer units 12 in the OB region 10b is set to be smaller than the interval between adjacent vertical transfer units 12 in the light receiving region 10a. Is desirable.

(3) In the above embodiment, the OB region is covered with the single light shielding film 7b made of a tungsten film or the like. However, the present invention is not limited to this configuration.
When the imaging target is illuminated with a high-intensity light source or the imaging target itself is a high-intensity light source, the light incident on the solid-state imaging device may pass through the light shielding film 7b, and the value of the black reference signal Deviation occurs in the direction of increasing.

In particular, as shown in FIG. 7, the first OB region 10 c in which the photoelectric conversion unit 11 is provided needs to improve the light shielding property. If the light shielding property is low, a signal caused by transmission through the photoelectric conversion unit 11. The charge is accumulated in addition to the charge of the dark current component, and the deviation of the black reference signal becomes large.
This phenomenon becomes more prominent when accumulation is performed for a long time.
Therefore, as shown in FIG. 9, it is desirable to improve the light shielding property by using a two-layer structure in which the light shielding film 7 b is covered with another light shielding film 8.
(4) In the above-described embodiment, an example in which the solid-state imaging device according to the present invention is applied to a horizontal interlaced CCD has been described. It doesn't matter. Further, the contents of the above embodiment and the above modification may be combined.

  The present invention can be applied to a solid-state imaging device having an optical black region.

DESCRIPTION OF SYMBOLS 1 Solid-state imaging device 3 A / D conversion part 7a, 7b Light shielding film 8 Light shielding film 9 Vertical transfer electrode 9 Conductive line 10 Semiconductor substrate 10a Light reception area 10b OB area 10c 1st OB area 10d 2nd OB area 11 Photoelectric conversion part DESCRIPTION OF SYMBOLS 12 Vertical transfer part 12a Vertical transfer part 12b Vertical transfer part 12c Vertical transfer part 13 Charge holding part 14 Output part 15 Storage part 16 Hold part 17 Horizontal transfer part 18 Charge transfer part (VOG) part 31 Timing control circuit 32 A / D conversion Unit 33 signal processing unit 34 image signal generation unit

Claims (7)

A plurality of photoelectric conversion units arranged in a matrix in the light receiving region on the substrate irradiated with light;
A plurality of first vertical transfer units that are arranged in parallel in the row direction and vertically transfer the signal charges of the photoelectric conversion units in units of columns;
A plurality of second vertical transfer units arranged in parallel in the row direction in the optical black region covered with the light-shielding film on the substrate and vertically transferring a reference charge corresponding to a dark current in synchronization with the first vertical transfer unit When,
A horizontal transfer unit that horizontally transfers a signal charge read from each first vertical transfer unit and a reference charge read from each second vertical transfer unit;
A solid-state imaging device characterized in that, in all or part of the optical black region, an interval between adjacent second vertical transfer units is narrower than an interval between adjacent first vertical transfer units. The optical black region is further divided into a first optical black region and a second optical black region,
The first optical black region is provided with a photoelectric conversion portion shielded by the light shielding film,
The second optical black region is characterized in that no photoelectric conversion unit is provided, and an interval between adjacent second vertical transfer units is narrower than an interval between adjacent first vertical transfer units. The solid-state imaging device according to claim 1.   3. The solid-state imaging device according to claim 1, wherein a width of the second vertical transfer unit in the row direction is equal to a width of the first vertical transfer unit in the row direction.   4. The solid-state imaging device according to claim 1, wherein the light shielding film is further covered with a light shielding film different from the light shielding film in the optical black region. 5. The second vertical transfer unit includes a vertical transfer path provided so as to extend in the column direction on the substrate and a plurality of vertical transfer electrodes provided above the vertical transfer path,
The vertical transfer electrodes located in the same row are electrically connected,
2. The vertical transfer electrodes corresponding to each of the plurality of vertical transfer paths adjacent in the row direction are integrally formed in the optical black region in which no photoelectric conversion unit is provided. 5. The solid-state imaging device according to any one of items 1 to 4.   6. The solid-state imaging device according to claim 1, wherein horizontal interlaced driving is applied to divide and output a signal of one line in the horizontal direction twice or more.   A solid-state image pickup device comprising the solid-state image pickup device according to claim 1.

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