JP2011107979A - Method, program, and device for designing layout of semiconductor integrated circuit, - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide the layout design method of a semiconductor integrated circuit in which a chip size can be reduced, a program and a layout design device. <P>SOLUTION: The layout design method of a semiconductor integrated circuit includes: a process (step B1) for determining whether there exist primitive cells having metal data in a Y direction in a chip; a process (step B3) for determining whether the primitive cells are vertically adjacent; a process (step B4) for determining whether layers having the metal data in the Y direction in the respective primitive cells are the same; a process (step B5) for determining whether there exist primitive cells having movable spaces among the respective primitive cells; a process (step B6) for determining whether the types of the primitive cells are the same when those determinations are satisfied; a process (step B7, 8) for performing the layout position adjustment of the X coordinates of the primitive cells according to the types of the respective primitive cells: and a process (step B9) for fixing the positions of the primitive cells. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a layout design method, a program, and a layout design apparatus for a semiconductor integrated circuit, and more particularly to a layout design method, a program, and a layout design apparatus for a semiconductor integrated circuit that perform layout design using primitive cells.

  2. Description of the Related Art Conventionally, as a semiconductor integrated circuit layout design method, there is a master slice type semiconductor integrated circuit layout design method in which cells are arbitrarily arranged and wired on a master slice in which transistor elements are formed in advance. For example, in Patent Document 1 (conventional example), in the master slice method, the chip length is designed with a semiconductor integrated circuit for the purpose of shortening the wiring length, preventing unwiring even with many wirings, and improving the efficiency of wiring work. At times, a master slice type semiconductor integrated circuit device is disclosed in which terminals are connected by wiring that passes through a field grid of logic function cells in a straight line through a wiring grid.

  Referring to FIG. 10, in the master slice semiconductor integrated circuit device according to the conventional example, the terminal 4a on the logic function cell 4 is connected to the terminal 7a on the logic function cell 7 by the wiring 31 passing through the wiring grids 15, 26 and 18. It is connected. Further, the terminal 4b on the logic function cell 4 is connected to the logic function cell 10 by the wiring 32 that passes through the feed grids 16, 25, 17, 30 and 15 in order and passes straight through the feedthrough tracks 12 of the logic function cells 6 and 8. It is connected to the upper terminal 10a. Similarly, the terminal 5a on the logic function cell 5 is connected to the logic function cell by the wiring 34 which passes through the wiring grids 21, 25, 20, 29 and 18 in order and passes straight through the feedthrough tracks 12 of the logic function cells 7 and 8. 10 is connected to a terminal 10b on the board. In addition, the terminal 4c on the logic function cell 4 is also connected to the logic function cell by the wiring 33 which passes through the wiring grids 19, 26, 23, 30 and 19 in order and passes straight through the feedthrough tracks 12 of the logic function cells 7 and 9. 10 is connected to a terminal 10c on the board. The terminal 6a on the logic function cell 6 is also connected to the terminal 8a on the logic function cell 8 through the wiring grids 15, 27 and 19 in this order. Here, since the position of the feedthrough track 12 in each basic cell 3 is common to each logic function cell 4-11, the feedthrough track 12 of each logic function cell 4-11 is aligned in a straight line. As a result, the wiring passing through the feedthrough track 12 is in a straight line, so that the number of wiring grids to be used is reduced, and a master-sliced semiconductor integrated circuit device in which the wiring length is short and unwiring is unlikely to be realized can be realized. Has been.

  In the above conventional example, the position of the feedthrough track 12 is the right end of the basic cell 36. However, the position of the feedthrough track 12 in the basic cell 36 may be arbitrary as long as it is common to the logic function cells 4 to 11. . Further, in the above conventional example, the unit of the basic cell 36 is assumed to be 3 grids, and one grid portion is used as a feedthrough track. However, the basic cell unit is set to n (n ≧ 2, n is an integer) grid portion, It is said that the same effect as described above can be obtained even if one grid portion is used as a feedthrough track. Further, in the above conventional example, the position of the feedthrough track 12 is common to all the logic function cells 4 to 11. However, it is not necessarily common to all the logic function cells 4 to 11, and the logic that is frequently used is not necessarily used. It is said that the same effect can be obtained in an example in which the function cell is shared.

JP-A-4-214667 (FIG. 1, paragraphs 0013 to 0016)

  The disclosure of Patent Document 1 is incorporated herein by reference. The following analysis is given by the present invention.

  By the way, in the field of semiconductor integrated circuit layout design, in order to reduce the chip size, primitive cells (in which logic gates such as inverters and NAND gates can be handled by CAD (Computer Assisted Drafting) tools) are minimized. Need to design. However, with the miniaturization of the process, the soft error becomes a problem in the logic, and the circuit size of the primitive cell is increased by mounting a circuit for avoiding the soft error. When a primitive cell having an increased circuit scale is laid out, it is difficult to complete the layout with a minimum size if only one wiring layer is used, and it is necessary to use two or more metal layers. When performing layout design on a chip using such primitive cells, the wiring property deteriorates at the time of chip design due to metal data of two or more layers in the primitive cell. In this trend, in order to reduce the cost of products, there has been an increasing demand for reducing the chip size by eliminating the deterioration of the wiring property due to the metal data in the primitive cells at the time of chip design.

  However, in the above conventional example, by making the feedthrough position in the basic cell common to each logic function cell, the feedthrough tracks of each logic cell can be aligned, but the chip size cannot be reduced. There is. The reason is that the size of the basic cell cannot be minimized because one grid in the basic cell must be secured as a feedthrough track regardless of whether or not the wiring passes. .

  A main object of the present invention is to provide a layout design method, a program, and a layout design apparatus for a semiconductor integrated circuit capable of reducing the chip size.

  According to a first aspect of the present invention, in a semiconductor integrated circuit layout design method for designing a semiconductor integrated circuit layout using a computer, a primitive cell having Y-direction metal data extending in the Y-axis direction in a chip. Determining whether the primitive cells are vertically adjacent to each other, determining whether the layers having the Y-direction metal data in each of the primitive cells are the same, and each of the primitive cells And determining whether there is a primitive cell whose arrangement position is not fixed and whether the type of each primitive cell is the same when the above determinations are satisfied. And adjusting the arrangement position of the X coordinate of the primitive cell according to the type of each primitive cell Characterized in that it and a step of fixing the position of the primitive cells having undergone the position adjustment.

  In the layout design method for a semiconductor integrated circuit according to the present invention, in the step of determining whether the primitive cells are vertically adjacent, the X coordinate of the upper primitive cell of the upper and lower primitive cells is Check whether the X coordinate of the lower primitive cell is within the range of “X coordinate + primitive cell width” or the “X coordinate + primitive cell width” of the upper primitive cell. Accordingly, it is preferable to determine whether the primitive cells are adjacent to each other in the vertical direction.

  In the layout design method of the semiconductor integrated circuit according to the present invention, in the step of adjusting the arrangement position, when the types of the upper and lower primitive cells are the same, the X coordinates of the upper and lower primitive cells are made the same, When the types of primitive cells are different, it is preferable to determine the X coordinate of the upper and lower primitive cells to a desired value.

  In the method of designing a layout of a semiconductor integrated circuit according to the present invention, when the X coordinate of the upper and lower primitive cells is determined as a desired value when the types of the adjacent primitive cells are different from each other, the upper primitive cell is used as a starting point. The position of the leftmost Y-direction metal data in the lower primitive cell and the position of the rightmost Y-direction metal data in the lower primitive cell are determined, and the rightmost Y-direction metal in the upper primitive cell is determined as the end point. A step of determining a position where the data position is matched with the position of the left end Y-direction metal data in the lower primitive cell, and the lower primitive cell is moved from the start point to the end point by the number of wiring grids. And the X coordinate of the Y direction metal data in the same layer in the primitive cell adjacent above and below A step of counting the number, a step of comparing the counted number of matches with the stored number of matches, and a step of clearing the stored number of matches and the X coordinate when the counted number of matches is larger than the stored number of matches. Storing the coincidence number and the X coordinate of the lower primitive cell after the counted coincidence number is equal to the stored coincidence number, or after clearing the stored coincidence number and the X coordinate; If the number of layers with Y-direction metal data in the primitive cell is 2 or more, select the number of matches stored for the layer with the larger number of Y-direction metal data matches and the X coordinate of the lower primitive cell. A step of determining whether the stored coincidence number and the X coordinate of the lower primitive cell are one, the stored coincidence number and the When the side primitive cell has one X coordinate, the process of using the stored X coordinate, and when there are a plurality of stored coincidence numbers and the X coordinates of the lower primitive cell, the upper and lower primitive cells And selecting a coordinate that minimizes the difference in X coordinates.

  According to a second aspect of the present invention, a program for causing a computer to execute a layout design of a semiconductor integrated circuit causes the computer to execute each step of the layout design method for the semiconductor integrated circuit.

  In a third aspect of the present invention, in a semiconductor integrated circuit layout design apparatus for designing a layout of a semiconductor integrated circuit, it is determined whether a primitive cell having Y-direction metal data extending in the Y-axis direction exists in the chip. Means for determining whether the primitive cells are vertically adjacent to each other, means for determining whether the layers having the Y-direction metal data in the primitive cells are the same, and a movable space among the primitive cells Means for determining whether there is a primitive cell whose placement position is not fixed, means for determining whether the types of the primitive cells are the same when the determinations are satisfied, and the primitives Means for adjusting the arrangement position of the X coordinate of the primitive cell according to the type of the cell; It means for fixing the position of the primitive cell was, characterized in that it comprises a.

  In the layout design apparatus of the semiconductor integrated circuit according to the present invention, the means for determining whether the primitive cells are vertically adjacent is the upper and lower primitive cells, and the X coordinate of the upper primitive cell is the lower primitive cell. Check whether the X coordinate of the lower primitive cell is within the range of “X coordinate + primitive cell width” or the “X coordinate + primitive cell width” of the upper primitive cell. Accordingly, it is preferable to determine whether the primitive cells are adjacent to each other in the vertical direction.

  In the layout design apparatus for a semiconductor integrated circuit according to the present invention, the means for adjusting the arrangement position is such that, when the types of the upper and lower primitive cells are the same, the upper and lower primitive cells have the same X coordinate, When the types of primitive cells are different, it is preferable to determine the X coordinate of the upper and lower primitive cells to a desired value.

  In the semiconductor integrated circuit layout design apparatus of the present invention, the means for adjusting the arrangement position determines the X coordinate of the upper and lower primitive cells to a desired value when the types of the adjacent primitive cells are different. As a means, a position where the position of the left end Y-direction metal data in the upper primitive cell is matched with the position of the right end Y-direction metal data in the lower primitive cell is determined, and the upper end is determined as the end point. Means for determining a position for matching the position of the right end Y-direction metal data in the primitive cell and the position of the left end Y-direction metal data in the lower primitive cell, and the lower side from the start point to the end point Means for moving the number of primitive cells by the number of wiring grids, and the same layer in the primitive cell adjacent above and below Means for counting the number of coincidence of the X coordinate of the Y-direction metal data, means for comparing the counted number of coincidence with the stored number of coincidence, and stored when the counted number of coincidence is larger than the stored number of coincidence. Means for clearing the coincidence number and the X coordinate, and if the counted coincidence number is equal to the stored coincidence number, or after clearing the stored coincidence number and the X coordinate, the coincidence number and the lower primitive Means for storing the X-coordinate of the cell, and if the number of layers having Y-direction metal data in the primitive cell is two or more, the number of matches stored for the layer having the larger number of matches in the Y-direction metal data, and Means for selecting the X coordinate of the lower primitive cell, and the stored number of matches and the X coordinate of the lower primitive cell are one. And means for using the stored X coordinate when the stored coincidence number and the X coordinate of the lower primitive cell are one; the stored match number and the X of the lower primitive cell; In the case where there are a plurality of coordinates, it is preferable to include means for selecting a coordinate that minimizes the difference between the X coordinates of the upper and lower primitive cells.

  According to the present invention, the X coordinate of a primitive cell is determined in consideration of the position of two or more metal Y-direction wiring layer metal data in the primitive cell and the type of primitive cell during the layout of the semiconductor integrated circuit. Using primitive cells designed with the minimum size without securing a grid for feedthrough tracks, wiring can pass straight through the primitive cells during chip layout, reducing wiring bending and improving wiring performance In addition, the chip size can be reduced.

1 is a diagram schematically showing the configuration of a system for carrying out a method for designing a layout of a semiconductor integrated circuit according to Embodiment 1 of the present invention. 1 is a flowchart schematically showing an overall flow of a layout design method for a semiconductor integrated circuit according to a first embodiment of the present invention. 3 is a flowchart showing in detail step A3 of FIG. 2 in the layout design method for a semiconductor integrated circuit according to the first embodiment of the present invention. 4 is a flowchart showing in detail step B8 of FIG. 3 in the layout design method for a semiconductor integrated circuit according to the first embodiment of the present invention; FIG. 5 is a layout diagram for each step when adjusting the arrangement position of the same kind of primitive cells in the layout design method for a semiconductor integrated circuit according to the first embodiment of the present invention; FIG. 6 is a layout diagram for each step when adjusting the arrangement position of different types of primitive cells in the layout design method for a semiconductor integrated circuit according to the first embodiment of the present invention; It is an example of a primitive cell having Y direction metal data of two metals or more. FIG. 8 is an example before the arrangement position adjustment of the layout design method of the semiconductor integrated circuit according to the first embodiment of the present invention when the chip layout is performed using the primitive cells of FIG. FIG. 8 is an example after the arrangement position adjustment of the layout design method of the semiconductor integrated circuit according to the first embodiment of the present invention is performed when the chip layout is performed using the primitive cell of FIG. 7. It is the figure which showed the wiring structure of the master slice type semiconductor integrated circuit device which concerns on a prior art example.

  In the semiconductor integrated circuit layout design method according to the embodiment of the present invention, a step of determining whether or not a primitive cell having Y-direction metal data extending in the Y-axis direction exists in the chip (step B1 in FIG. 3); Determining whether the primitive cells are vertically adjacent (step B3 in FIG. 3), determining whether the layers having the Y-direction metal data in each of the primitive cells are the same (step B4 in FIG. 3), , A step of determining whether there is a moveable space among the primitive cells and there is a primitive cell whose placement position is not fixed (step B5 in FIG. 3), A step of determining whether or not the primitive cell types are the same (step B6 in FIG. 3), and the primitive according to the type of each primitive cell. Includes a step of performing position adjustment of the X-coordinate of Buseru (Step B7,8 in FIG. 3), and a step of fixing the position of the primitive cells having undergone the position adjustment (step in FIG. 3 B9), the. Each step of the semiconductor integrated circuit layout design method is performed by causing a computer (semiconductor integrated circuit layout design apparatus) to execute a program.

  A layout design method for a semiconductor integrated circuit according to a first embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a diagram schematically showing the configuration of a system for carrying out a layout design method for a semiconductor integrated circuit according to Embodiment 1 of the present invention.

  Referring to FIG. 1, the system for implementing the semiconductor integrated circuit layout design method according to the first embodiment includes a computer device 101, a server 102, and a network 103.

  The computer device 101 is a device having a computer function such as an engineering workstation, and is a layout design device for a semiconductor integrated circuit. The computer device 101 is communicably connected to the server 102 via the network 103. The computer apparatus 101 receives (downloads) the requested information from the server 102, stores the received information in a local hard disk or memory, etc., and the semiconductor integrated circuit of the semiconductor integrated circuit according to a user operation or an automatic design function. Perform layout design. Details of the operation of the computer apparatus 101 will be described later.

  The server 102 is a system that provides information such as a program and a database stored in the storage unit 102 a in response to a request from the computer apparatus 101. The server 102 is communicably connected to the computer apparatus 101 via the network 103. The server 102 stores information such as an execution program, layout data, a layout library, and a CAD design tool in the storage unit 102a. The server 102 transmits information requested from the computer apparatus 101 to the computer apparatus 101 via the network 103. Here, the layout data is data relating to the layout of the semiconductor integrated circuit. The layout library is a data group related to the layout of a highly versatile semiconductor integrated circuit. The CAD design tool is editing software such as a circuit editor and a layout editor used for CAD design.

  The network 103 is an information communication network such as the Internet, and mediates communication between the computer apparatus 101 and the server 102.

  Next, a layout design method for a semiconductor integrated circuit according to the first embodiment of the present invention will be described with reference to the drawings. FIG. 2 is a flowchart schematically showing the overall flow of the layout design method of the semiconductor integrated circuit according to the first embodiment of the present invention. The flowchart in FIG. 2 corresponds to an operation executed by the computer apparatus (101 in FIG. 1) that has downloaded an execution program or the like necessary for the layout design of the semiconductor integrated circuit from the server (102 in FIG. 1).

  First, when designing the layout of a semiconductor integrated circuit, the computer apparatus (101 in FIG. 1) arranges macros (the circuit parts that have already been designed into blocks for each function), power supply wiring, etc., according to user operations. Floor plan (arrangement plan) is performed (step A1). Next, the computer apparatus (101 in FIG. 1) arranges primitive cells (logic gates that can be handled by a CAD tool) using an automatic arrangement tool (step A2).

  Next, the computer apparatus (101 in FIG. 1) adjusts the arrangement position of the primitive cells (step A3). Here, the processing of step A3 adjusts the arrangement position of the primitive cell having the metal data (hereinafter referred to as “Y-direction metal data”) of the Y-direction wiring layer of two or more metals based on the position of the Y-direction metal data. It is processing to do. Details of step A3 will be described later.

  Next, the computer device (101 in FIG. 1) converts the clock network into a tree-like structure via a buffer using the result of the primitive cell arrangement determined by adjusting the arrangement position of the primitive cell ( CTS (Clock Tree Synthesis) to be generated is performed (step A4). Next, the computer device (101 in FIG. 1) performs wiring for determining a wiring route for the connection between the primitive cells (step A5). Finally, the computer apparatus (101 in FIG. 1) performs STA (Static Timing Analysis) that statically performs timing analysis on the layout result (step A6).

  Next, a detailed flow of arrangement position adjustment (step A3 in FIG. 2) in the semiconductor integrated circuit layout design method according to the first embodiment of the present invention will be described with reference to the drawings. FIG. 3 is a flowchart showing in detail step A3 in FIG. 2 in the layout design method for a semiconductor integrated circuit according to the first embodiment of the present invention.

  After step A2 (see FIG. 2), the computer apparatus (101 in FIG. 1) determines whether or not there is a primitive cell having Y-direction metal data in the chip (step B1). If there is no primitive cell having Y-direction metal data in the chip (NO in step B1), the process of adjusting the arrangement position is terminated, and the process proceeds to step A4 (see FIG. 2).

  When there is a primitive cell having Y-direction metal data in the chip (YES in step B1), the computer apparatus (101 in FIG. 1) adjusts the arrangement position in order with respect to the primitive cell having Y-direction metal data in the chip. The processing to be executed is executed in a loop (step B2). In step B2, steps B3 to B9 are performed.

  In step B2, first, the computer apparatus (101 in FIG. 1) is the upper and lower primitive cells, and the X coordinate of the upper primitive cell is within the range of “X coordinate + primitive cell width” of the lower primitive cell. Or, whether or not the primitive cells are adjacent to each other by checking whether or not the X coordinate of the lower primitive cell is within the range of “X coordinate + primitive cell width” of the upper primitive cell. Is determined (step B3). If the primitive cells are not adjacent vertically (NO in step B3), the process proceeds to a process for adjusting the arrangement position for the next primitive cell having Y-direction metal data.

  If the primitive cells are adjacent vertically (YES in step B3), the computer apparatus (101 in FIG. 1) determines whether or not the same Y-direction metal data layer exists in the vertically adjacent primitive cells. Is determined (step B4). If the same Y-direction metal data layer does not exist in the vertically adjacent primitive cells (NO in step B4), the process proceeds to a process for adjusting the arrangement position of the next primitive cell having the Y-direction metal data.

  When the same Y-direction metal data layer exists in the vertically adjacent primitive cells (YES in step B4), the computer device (101 in FIG. 1) has a space in which the primitive cells can be moved, and Then, it is determined whether or not the arrangement cell is a primitive cell whose position is not fixed (step B5). If the primitive cell cannot be moved (NO in step B5), the process proceeds to a process of adjusting the arrangement position for the next primitive cell having Y-direction metal data.

  If the primitive cell is movable (YES in step B5), the computer device (101 in FIG. 1) determines the type of the primitive cell adjacent vertically (step B6).

  When the adjacent primitive cells are the same type (YES in step B6), the computer apparatus (101 in FIG. 1) executes a process of matching the X coordinates of the upper and lower primitive cells (step B7), and then the step Proceed to B9.

  When the adjacent primitive cells are different types (NO in step B6), the computer apparatus (101 in FIG. 1) executes a process of determining the X coordinates of the upper and lower primitive cells (step B8), and then step B9. Proceed to

  After step B7 or step B8, the computer apparatus (101 in FIG. 1) fixes the position of the primitive cell whose arrangement position has been adjusted (step B9).

  In the case of NO in step B3, in the case of NO in step B4, in the case of NO in step B5, or after step B9, the computer device (101 in FIG. 1) stores all the Y-direction metal data existing in the chip. It is determined whether or not the process for adjusting the arrangement position of the primitive cell is completed. If not, the process moves to the process of adjusting the arrangement position for the primitive cell having the next Y-direction metal data. In this case, the loop process of step B2 is exited, the process of adjusting the arrangement position is terminated, and the process proceeds to step A4 (see FIG. 2).

  Next, details of the step of determining the X coordinates of the upper and lower primitive cells when the adjacent upper and lower primitive cells are different in the layout design method for the semiconductor integrated circuit according to the first embodiment of the present invention (step B8 in FIG. 3). A simple flow will be described with reference to the drawings. FIG. 4 is a flowchart showing in detail step B8 of FIG. 3 in the layout design method of the semiconductor integrated circuit according to the first embodiment of the present invention.

  When the upper and lower adjacent primitive cells are of different types (NO in step B6 in FIG. 3), the computer apparatus (101 in FIG. 1) executes the process of determining the X coordinate of the upper and lower primitive cells (step in FIG. 3). B8) The process from step C2 to step C8 is repeated in a loop for the number of layers of Y-direction metal data in the primitive cell (step C1).

  In step C1, first, the computer apparatus (101 in FIG. 1) starts from the position where the left end Y-direction metal data position in the upper primitive cell matches the right end Y-direction metal data position in the lower primitive cell. The position where the right end Y-direction metal data position in the upper primitive cell and the left end Y-direction metal data position in the lower primitive cell coincide is determined as the end point (step C2).

  After step C2, the computer apparatus (101 in FIG. 1) repeats the processing from step C4 to step C8 in a loop for the number of wiring grids from the start point to the end point determined in step C2 (step C3).

  In step C3, first, the computer apparatus (101 in FIG. 1) counts the number of coincident X coordinates of the Y direction metal data in the vertically adjacent primitive cells (step C4).

  After step C4, the computer apparatus (101 in FIG. 1) compares the counted number with the X coordinate coincidence number of the Y-direction metal data stored in the loop processing at the previous step C3 (step C5). ).

  In step C5, when the counted number is larger than the X coordinate coincidence number of the Y-direction metal data stored in the loop processing in the previous step C3 (“large” in step C5), the computer apparatus (101 in FIG. 1). ) Clears the X coordinate coincidence number and X coordinate of the stored Y-direction metal data (step C6), and then stores the coincidence number and the X coordinate of the lower primitive cell (step C7). The primitive cell on the side is moved by one wiring grid (step C8).

  In step C5, when the counted number is equal to the X coordinate coincidence number of the Y direction metal data stored in the loop processing in the previous step C3 (“equal” in step C5), the computer apparatus (101 in FIG. 1). ) Stores the coincidence number and the X coordinate of the lower primitive cell (step C7), and then moves the lower primitive cell by one wiring grid (step C8).

  In step C5, when the counted number is smaller than the X coordinate coincidence number of the Y direction metal data stored in the loop processing in the previous step C3 ("small" in step C5), the computer device (101 in FIG. 1). ) Moves the lower primitive cell by one wiring grid (step C8).

  After step C8, the computer apparatus (101 in FIG. 1) determines whether or not all the movements of the lower primitive cells to the end point position determined in step C2 have been completed. Step C3 is executed for the primitive cell that has not been moved, and if it has been completed, the loop processing of step C3 is exited.

  After exiting the loop processing in step C3, the computer apparatus (101 in FIG. 1) determines whether or not the processing for determining the X coordinates of the upper and lower primitive cells has been completed. Step C2 is executed for the primitive cells that have not been determined, and if completed, the loop processing of Step C2 is exited.

  After exiting the loop processing in step C2, the computer apparatus (101 in FIG. 1) determines whether or not the number of matching Y-direction metal data layers in the vertically adjacent primitive cells is 2 or more (step C9). ). When the number of matching Y-direction metal data layers in the vertically adjacent primitive cells is less than 2 (NO in step C9), the process proceeds to step C11.

  When the number of layers of Y-direction metal data in the vertically adjacent primitive cells is equal to or greater than 2 (YES in step C9), the computer apparatus (101 in FIG. 1) determines the Y in the vertically adjacent primitive cells. If the number of layers in the direction metal data coincides with two or more, the stored X-coordinate coincidence number of the Y-direction metal data and the X coordinate of the primitive cell in the layer in which the X-coordinate coincidence number in the Y-direction metal data is large Select (step C10), and then proceed to step C11.

  In the case of NO in step C9 or after step C10, the computer apparatus (101 in FIG. 1) determines whether or not the stored X-direction coincidence number of the Y-direction metal data and the X coordinate of the primitive cell are one (1). Step C11).

  When the number of coincident X coordinates of the stored Y-direction metal data and the X coordinate of the primitive cell are one (YES in step C11), the computer device (101 in FIG. 1) sets the stored X coordinate of the primitive cell to the lower side. The X coordinate of the primitive cell is determined (step C12), and then the process proceeds to step B9 (see FIG. 3).

  When there are a plurality of X coordinate coincidence numbers of the stored Y-direction metal data and the X coordinates of the primitive cells (NO in step C11), the computer device (101 in FIG. 1) determines that the difference between the X coordinates of the primitive cells adjacent in the vertical direction is different. The minimum X coordinate is determined as the X coordinate of the lower primitive cell (step C13), and then the process proceeds to step B9 (see FIG. 3).

  In the above embodiment, the lower primitive cell is moved. However, the upper primitive cell may be moved depending on the position of the movable space.

  Next, a layout design method for a semiconductor integrated circuit according to the first embodiment of the present invention will be described using the layout of the semiconductor integrated circuit. FIG. 5 is a layout diagram for each process in the case of adjusting the arrangement position of the same kind of primitive cells in the layout design method of the semiconductor integrated circuit according to the first embodiment of the present invention. FIG. 6 is a layout diagram for each step in the case of adjusting the arrangement position of different types of primitive cells in the layout design method for a semiconductor integrated circuit according to the first embodiment of the present invention.

  In FIGS. 5 and 6, the hatched portion 203 is the metal data of the Y-direction wiring layer of the two or more metal layers in the primitive cells 201 and 202 (hereinafter referred to as “Y-direction metal data”). ).

  FIG. 5 is an example in the case of the same type of primitive cell 201 having Y-direction metal data 203 adjacent vertically. FIG. 5A shows the arrangement positions of the primitive cells 201 after the automatic arrangement. When there is a movable space 204 as shown in FIG. 5B, the upper and lower primitive cells are shown in FIG. 5C. The position of the lower primitive cell 201 is adjusted to a position where the X coordinate of 201 matches, and the position of the Y-direction metal data 203 is adjusted.

  FIG. 6 shows an example in which the upper and lower primitive cells 201 and 202 having Y-direction metal data 203 are of different types. FIG. 6A shows the arrangement positions of different types of primitive cells 201 and primitive cells 202 after automatic arrangement, and when there is a movable space 204 as shown in FIG. 6B, FIG. As shown in FIG. 4D, the position of the left end Y-direction metal data 203 in the upper primitive cell 201 and the position of the right end Y-direction metal data 203 in the lower primitive cell 202 are combined. The lower primitive cell 202 in the wiring grid unit until the position of the right end Y-direction metal data 203 in the upper primitive cell 201 and the position of the left end Y-direction metal data 203 in the lower primitive cell 202 are combined. Each time it is moved, the Y direction metal data 203 in the primitive cell 201 and the primitive cell 202 match. To count that number. The position of the lower primitive cell 202 is adjusted to a position where the number of matching X coordinates of the Y-direction metal data 203 in the upper and lower primitive cells 201 and 202 is maximized.

  The resource of the passing wiring that can be secured by this arrangement position adjustment is expressed as [Equation 1].

[Formula 1]
G _space1 = W / G-M
G _space1 = wiring track capable of passing in a straight line on the primitive cell after the arrangement position adjustment W = width of the primitive cell G = width of the wiring grid M = number of metal data in the Y direction in the primitive cell

If the arrangement position of the number of metal data cells is not adjusted, the resource of the passing wiring is the worst case by the arrangement in the vertical direction of the cell as shown in [Equation 2], and the number of primitive cells adjacent vertically is large. As the value of n increases, the number of wiring grids that can pass on the primitive cell (G _{space2 in} [Expression 2]) decreases, and it becomes difficult for the wiring to pass in a straight line.

[Formula 2]
G _space2 = W / G−M × n
G _space2 = wiring track that can pass in a straight line on the primitive cell when the arrangement position is not adjusted n = number of vertically adjacent primitive cells

  Next, a case where the number of wiring resources through which wiring can pass in a straight line on the primitive cell in the layout design method for a semiconductor integrated circuit according to the first embodiment of the present invention is described.

  FIG. 7 shows an example of a primitive cell 201 having Y-direction metal data 203 of two metals or more. In this example, the total number of vertical wiring grids on the primitive cell 201 (corresponding to “W / G” in [Expression 1] and [Expression 2] above) is 50, and the Y-direction metal in the primitive cell 201 is The number of data 203 (corresponding to “M” in [Expression 1] and [Expression 2]) is 10.

  FIG. 8 is an example in which the layout position adjustment of the layout design method for the semiconductor integrated circuit according to the first embodiment of the present invention is not performed when the chip layout is performed using the primitive cells 201 of FIG. FIG. 9 shows an example in which the layout position adjustment of the layout design method for a semiconductor integrated circuit according to the first embodiment of the present invention is performed when the chip layout is performed using the primitive cell 201 of FIG.

In FIG. 8, since the arrangement positions of the primitive cells 201 are not adjusted, the passing wiring of 10 locations × 3 pieces (corresponding to “M × n” in the above [Expression 2]) is obstructed. In this example, there are 26 wiring tracks 301 (corresponding to “G _space2 ” in [Expression 2]) that can pass through the primitive cells in a straight line.

In FIG. 9, by aligning the positions of the primitive cells 201, the number of inhibition points of the passing wiring is the maximum number of Y-direction metal data 203 in the primitive cells 201 (corresponding to “M” in [Expression 1]). There are only 40 wiring tracks 301 (corresponding to “G _space1 ” in the above [Expression 1]) that can pass through the primitive cells in a straight line.

  According to the first embodiment, the following effects can be obtained.

  As a first effect, when designing a primitive cell, there is an effect that wiring can be improved and a chip size can be reduced without securing a feedthrough track inside the primitive cell. The reason is that by aligning the X-coordinate positions of the Y-direction wiring layer metal data of two or more metals in the primitive cell, the wiring can pass in a straight line on the primitive cell during automatic chip layout. .

  As a second effect, there is an effect that the processing time at the time of wiring can be shortened. The reason is that the wiring passes through the primitive cells in a straight line during the automatic layout of the chip, thereby reducing the bending of the wiring and improving the wiring performance.

DESCRIPTION OF SYMBOLS 1 Semiconductor substrate 2 Basic cell row | line | column area | region 3 Wiring area | region 4-11 Logic function cell 4a, 4b, 4c, 5a, 6a, 7a, 8a, 10a, 10b, 10c Terminal 12 Feed through track 13-30 Wiring grids 31-35 Wiring 36 Basic cell 101 Computer device 102 Server 102a Recording unit 103 Network 201 Primitive cell 202 Primitive cell 203 Y-direction metal data 204 Movable space 301 Wiring track that can pass in a straight line on the primitive cell

Claims (9)

In a semiconductor integrated circuit layout design method for designing a layout of a semiconductor integrated circuit using a computer,
Determining whether there is a primitive cell having Y-direction metal data extending in the Y-axis direction in the chip;
Determining whether the primitive cells are vertically adjacent;
Determining whether the layers having the Y-direction metal data in each of the primitive cells are the same;
Determining whether there is a movable space in each of the primitive cells and there is a primitive cell whose placement position is not fixed;
When satisfying each determination, determining whether the types of the primitive cells are the same;
Adjusting the arrangement position of the X coordinate of the primitive cell according to the type of each primitive cell;
Fixing the position of the primitive cell subjected to the arrangement position adjustment;
A method of designing a layout of a semiconductor integrated circuit, comprising:   In the step of determining whether the primitive cells are adjacent vertically, the X coordinate of the upper primitive cell in the upper and lower primitive cells is within the range of “X coordinate + primitive cell width” of the lower primitive cell, Or, by checking whether the X coordinate of the lower primitive cell is within the range of “X coordinate + primitive cell width” of the upper primitive cell, whether the primitive cell is adjacent vertically The layout design method for a semiconductor integrated circuit according to claim 1, wherein:   In the step of adjusting the arrangement position, when the types of the upper and lower primitive cells are the same, the X coordinates of the upper and lower primitive cells are made the same, and when the types of the upper and lower primitive cells are different, the upper and lower primitive cells 3. The method of designing a layout of a semiconductor integrated circuit according to claim 1, wherein the X coordinate is determined to a desired value. When determining the X coordinate of the upper and lower primitive cells to a desired value when the types of the adjacent primitive cells are different,
The position of the left end Y-direction metal data in the upper primitive cell and the position of the right end Y-direction metal data in the lower primitive cell are determined as a start point, and the upper primitive cell is determined as an end point. Determining a position to match the position of the Y-direction metal data at the right end in the inside and the position of the Y-direction metal data at the left end in the lower primitive cell;
Moving the lower primitive cell from the start point to the end point by the number of wiring grids;
Counting the number of coincident X coordinates of Y-direction metal data in the same layer in the primitive cell adjacent above and below;
Comparing the counted number of matches with a stored number of matches;
Clearing the stored match number and X coordinate if the counted match number is greater than the stored match number;
Storing the coincidence number and the X coordinate of the lower primitive cell after the counted coincidence number is equal to the stored coincidence number, or after clearing the stored coincidence number and the X coordinate;
If the number of layers having Y-direction metal data in the primitive cell is 2 or more, the number of matches stored for the layer with the larger number of matches in the Y-direction metal data, and the X coordinate of the lower primitive cell A process to select;
Determining whether the stored number of matches and the X coordinate of the lower primitive cell are one;
Using the stored X-coordinate when the number of stored matches and the X-coordinate of the lower primitive cell are one;
Selecting a coordinate that minimizes the difference between the X coordinates of the upper and lower primitive cells when there are a plurality of stored coincidence numbers and the X coordinates of the lower primitive cells; and
4. The layout design method for a semiconductor integrated circuit according to claim 3, further comprising:   A program for causing a computer to execute each step of the layout design method for a semiconductor integrated circuit according to any one of claims 1 to 4. In a semiconductor integrated circuit layout design apparatus for designing a layout of a semiconductor integrated circuit,
Means for determining whether a primitive cell having Y-direction metal data extending in the Y-axis direction exists in the chip;
Means for determining whether the primitive cells are vertically adjacent;
Means for determining whether the layers having the Y-direction metal data in each of the primitive cells are the same;
Means for determining whether there is a moveable space among the primitive cells and there is a primitive cell whose placement position is not fixed;
Means for determining whether the types of the primitive cells are the same when satisfying the determinations;
Means for adjusting the arrangement position of the X coordinate of the primitive cell according to the type of each primitive cell;
Means for fixing the position of the primitive cell that has been subjected to the arrangement position adjustment;
A layout design apparatus for a semiconductor integrated circuit, comprising:   The means for determining whether or not the primitive cells are adjacent to each other in the upper and lower sides is the upper and lower primitive cells, and the X coordinate of the upper primitive cell is within the range of “X coordinate + primitive cell width” of the lower primitive cell, Or, by checking whether the X coordinate of the lower primitive cell is within the range of “X coordinate + primitive cell width” of the upper primitive cell, whether the primitive cell is adjacent vertically 7. The layout design apparatus for a semiconductor integrated circuit according to claim 6, wherein:   The means for adjusting the arrangement position adjusts the X coordinate of the upper and lower primitive cells when the upper and lower primitive cells are the same, and when the upper and lower primitive cells are different, 8. The layout design apparatus for a semiconductor integrated circuit according to claim 6, wherein the X coordinate is determined to a desired value. The means for adjusting the arrangement position is a means for determining the X coordinate of the upper and lower primitive cells to a desired value when the types of the primitive cells adjacent to the upper and lower are different.
The position of the left end Y-direction metal data in the upper primitive cell and the position of the right end Y-direction metal data in the lower primitive cell are determined as a start point, and the upper primitive cell is determined as an end point. Means for determining a position for matching the position of the Y-direction metal data at the right end in the inner position and the position of the Y-direction metal data at the left end in the lower primitive cell;
Means for moving the lower primitive cell from the start point to the end point by the number of wiring grids;
Means for counting the number of coincident X coordinates of Y-direction metal data in the same layer in the primitive cell adjacent above and below;
Means for comparing the counted number of matches with the stored number of matches;
Means for clearing the stored number of matches and the X coordinate if the counted number of matches is greater than the stored number of matches;
Means for storing the coincidence number and the X coordinate of the lower primitive cell after the counted coincidence number is equal to the stored coincidence number or after clearing the stored coincidence number and the X coordinate;
If the number of layers having Y-direction metal data in the primitive cell is 2 or more, the number of matches stored for the layer with the larger number of matches in the Y-direction metal data, and the X coordinate of the lower primitive cell Means to choose;
Means for determining whether the stored number of matches and the X coordinate of the lower primitive cell are one;
Means for using the stored X coordinate when the number of stored matches and the X coordinate of the lower primitive cell are one;
Means for selecting a coordinate that minimizes the difference between the X coordinates of the upper and lower primitive cells when there are a plurality of stored coincidences and a plurality of X coordinates of the lower primitive cells;
9. The layout design apparatus for a semiconductor integrated circuit according to claim 8, further comprising:

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