JP2011107259A - Light-emitting element drive device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a light-emitting element drive device which can drive a plurality of backlight horizontal line groups that have differing energization timing, when modulating light levels so as to track the scanning of screen display such as liquid crystal display with a backlight region partitioned, for example using local dimming technology. <P>SOLUTION: A plurality of frame timing signals are distributed to respective drive channels, and pulse signals with differing drive timing are generated to drive current-drive circuits, whereby a current source for LED driving can be divided into at least two groups, and the start of power supply of each group can be driven at arbitrary timing. Thus, the plurality of backlight horizontal line groups that have differing energization timing can be driven. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a light emitting element driving device, and more particularly to an LED driving device having a plurality of channels for driving LEDs (Light Emitting Diodes).

  In recent years, LEDs have been widely used in various devices such as lighting and backlights for liquid crystal TVs (TVs). As a driving technique for adjusting the luminance of the LED, pulse width modulation (PWM) is generally used.

  On the other hand, a backlight driving technique called local dimming is used as a technique for realizing high image quality of a display image in a liquid crystal TV. Local dimming is a technology that divides a liquid crystal TV screen into a plurality of areas (referred to as dimming areas), and controls the dimming of the backlight individually by PWM according to the display image of the liquid crystal TV in each dimming area. is there. High contrast image display can be realized by brightening the bright area of the display image and darkening the dark area.

  In local dimming, dimming control is required in each dimming region, and therefore, a plurality of LED driving devices incorporating a plurality of driving channels for driving LEDs are often used. Each drive channel of these LED drive devices can be dimmed with duty pulses having different duty ratios by independent PWM drive.

  However, when local dimming is realized using an LED driving device, there are the following problems.

  The screen of the liquid crystal TV is displayed by both control of transmission / shielding control (referred to as liquid crystal control) in units of liquid crystal pixels in the liquid crystal panel and light control in units of light control areas in the backlight. In the liquid crystal panel, the display screen includes a large number of liquid crystal pixels in the horizontal direction and a large number of horizontal lines in the vertical direction. On the other hand, in the backlight, one dimming region includes a liquid crystal pixel group including Mp liquid crystal pixels (Mp is an integer of 2 or more) that are continuous in the horizontal direction, and Np lines (Np is 2) that are continuous in the vertical direction. Specified by a horizontal line group including horizontal lines of the above integers). For example, when the display screen includes nine liquid crystal pixel groups in the horizontal direction and five horizontal line groups in the vertical direction, the display screen includes 9 × 5 = 45 dimming areas. In this case, the display screen includes (Mp × 9) × (Np × 5) liquid crystal pixels.

  The liquid crystal control is performed for each horizontal scanning period in units of one horizontal line from the highest line to the lowest line of (Np × 5) horizontal lines by progressive scanning in one frame period. On the other hand, the dimming control is synchronized with the timing of such liquid crystal control from the highest group of the five horizontal line groups to the lowest group in units of one horizontal line group (one horizontal scanning period × Np). To be done.

  One dimming region is irradiated by one LED group including a plurality of LEDs. One LED driving device has, for example, four driving channels for driving four LED groups, respectively. In order to irradiate the above-described 45 dimming areas on the display screen, it is necessary to allocate an integer number of LED driving devices for each horizontal line group. As a result, three LED driving devices are required per horizontal line group, and 3 × 5 = 15 LED driving devices are required for the entire display screen. In this case, 3 drive lines per horizontal line group and 15 drive channels on the entire display screen are not used while being mounted, and as a result, necessary LED drive devices (light emitting element drive devices) The number was also increasing.

  The light-emitting element driving device of the present invention solves the above-described conventional problems, and an object thereof is to reduce the number of light-emitting element driving devices necessary for driving the light-emitting elements.

  In order to solve the above-described problem, a light emitting element driving device according to the present invention includes a plurality of current driving circuits for energizing the light emitting elements by pulse width modulation driving, and drives the plurality of current driving circuits. The pulse signal generating unit for generating the pulse signal and a distributing unit for selecting and outputting a plurality of frame timing signals to each current driving circuit.

  As a result, a plurality of frame timing signals are distributed to the respective driving channels, pulse signals having different driving timings are generated, and the current driving circuit is driven, so that the current driving circuits for driving the light emitting elements are divided into at least two groups. In addition, it is possible to drive the energization start of each group at an arbitrary timing.

  According to the light emitting element driving device of the present invention, when local dimming is used in a liquid crystal display or the like, that is, when dimming is performed following the scanning of a screen display such as a liquid crystal display in a state where the backlight region is divided. It is possible to drive a backlight that spans a plurality of horizontal line groups with one light emitting element driving device. Thereby, even in various TV sets having different numbers of backlight division pixel groups, it is possible to efficiently use a light emitting element driving device having a specific number of channels.

It is a block diagram which shows the structural example of the light emitting element drive device in Embodiment 1 of this invention. It is a schematic diagram which shows the display screen of liquid crystal TV. It is a schematic diagram which shows the scanning timing for every flame | frame in liquid crystal TV. It is a block diagram which shows the structural example containing multiple light emitting element drive devices in Embodiment 1 of this invention. It is a schematic diagram which shows one allocation example of the light control area group of the light emitting element drive device in Embodiment 1 of this invention. It is a schematic diagram which shows another example of allocation of the light control area group of the light emitting element drive device in Embodiment 1 of this invention. It is a schematic diagram which shows another example of allocation of the light control area group of the light emitting element drive device in Embodiment 1 of this invention. It is a related figure which shows the operation example of the distribution part of the light emitting element drive device in Embodiment 1 of this invention. It is a related figure which shows another example of operation | movement of the distribution part of the light emitting element drive device in Embodiment 1 of this invention. It is a related figure which shows another example of operation | movement of the distribution part of the light emitting element drive device in Embodiment 1 of this invention. It is a block diagram which shows the structural example of the distribution part of the light emitting element drive device in Embodiment 1 of this invention. 4 is a timing chart illustrating an operation example of a distribution unit of the light emitting element driving apparatus according to Embodiment 1 of the present invention. It is a block diagram which shows the structural example of the pulse signal generation part of the light emitting element drive device in Embodiment 1 of this invention. It is a wave form diagram which shows the operation example of the pulse signal generation part of the light emitting element drive device in Embodiment 1 of this invention. It is a block diagram which shows the structural example of the current drive part of the light emitting element drive device in Embodiment 1 of this invention. It is a wave form diagram which shows the operation example of the current drive part of the light emitting element drive device in Embodiment 1 of this invention. It is a block diagram which shows the structural example of the light emitting element drive device in Embodiment 2 of this invention. It is a block diagram which shows the structural example of the frame timing signal generation part of the light emitting element drive device in Embodiment 2 of this invention. It is a wave form diagram which shows the operation example of the frame timing signal generation part of the light emitting element drive device in Embodiment 2 of this invention. It is a block diagram which shows the structural example of the light emitting element drive device in Embodiment 3 of this invention. It is a block diagram which shows the structural example of the light emitting element drive device in Embodiment 4 of this invention. It is a detailed block diagram which shows the structural example of the light emitting element drive device in Embodiment 4 of this invention.

  Hereinafter, some examples relating to embodiments for carrying out the present invention will be described with reference to the drawings. In the drawings, elements representing substantially the same configuration, operation, and effect are denoted by the same reference numerals. Symbols A1, A2,..., An represent symbols in which the last numeral is incremented by one from A1 to An, and are also denoted as A1 to An or Ai (i = 1 to n). A symbol on the drawing is also used in the equation as a variable value representing the magnitude of the signal indicated by the symbol.

(Embodiment 1)
FIG. 1 is a block diagram illustrating a configuration example of a light emitting element driving device.

  The light emitting element driving device 10 includes a serial interface unit 11, a register unit 12, a distribution unit 13, a pulse signal generation unit 14, and a current driving unit 15. The configuration of FIG. 1 includes a controller 1 and a light emitting element unit 20 in addition to the light emitting element driving device 10. The light emitting element driving device 10 receives the control signal S1 from the controller 1, generates driving currents J1, J2,..., Jn (n is an integer of 2 or more), and generates the driving currents J1 to Jn as currents. It supplies to the light emitting element part 20 via path | route PJ1, PJ2, ..., PJn (the arrow of each drive current J1-Jn shows the direction of an electric current). The liquid crystal TV (television) includes a liquid crystal panel and a backlight. The backlight includes a light emitting element unit 20.

  The light emitting element unit 20 includes n light emitting element groups LED1, LED2,. Each light emitting element group LED1-LEDn includes one or more light emitting elements. The light emitting element is, for example, an LED (Light Emitting Diode). One end of each light emitting element group LED1-LEDn is called an anode end, and the other end is called a cathode end. The anode ends of the n light emitting element groups LED1 to LEDn are commonly connected to the voltage source ECC via the voltage path PV, and the cathode ends are respectively connected to the n current paths PJ1 to PJn. The plurality of LEDs included in each of the light emitting element groups LED1 to LEDn are arranged such that the forward direction from the anode to the cathode is the direction from the anode end (voltage path PV) to the cathode end (each current path PJ1 to PJn). They are connected in series with each other.

  The voltage source ECC generates the drive voltage VCC, and the drive voltage VCC is supplied to each of the light emitting element groups LED1 to LEDn via the voltage path PV opposite to the current paths PJ1 to PJn with the light emitting element groups LED1 to LEDn interposed therebetween. To supply.

  The controller 1 generates a control signal S1 based on the input video signal VS. The control signal S1 includes m system (m is an integer of 2 or more) frame timing signals EN1, EN2,..., ENm, master clock signal MCLK, serial data SDAT, serial clock SCLK, and latch clock LAT. The serial data SDAT represents binary data synchronized with the serial clock SCLK. The serial data SDAT includes pulse width data WD1, WD2,..., WDn and allocation data ED1, ED2,. The controller 1 generates the pulse width data WD1 to WDn based on the level of the input video signal VS. The pulse width data WD1 to WDn are also called duty data. On the other hand, the controller 1 sets the allocation data ED1 to EDn depending on the arrangement in the backlight of the light emitting element unit 20 driven by the light emitting element driving device 10, regardless of the input video signal VS. For example, the allocation data ED1 to EDn are initially set when the liquid crystal TV is manufactured.

  The controller 1 includes a frame timing signal generation unit 16, and the frame timing signal generation unit 16 generates frame timing signals EN1 to ENm based on the input video signal VS.

  The controller 1 may be composed of a microcomputer in which a program for generating the control signal S1 is incorporated. Furthermore, the controller 1 may be configured by a wired logic circuit such as an FPGA (Field Programmable Gate Array) in which a circuit that generates the control signal S1 is incorporated. Furthermore, the controller 1 may be composed of both a microcomputer and a wired logic circuit.

  The serial interface unit 11 inputs serial data SDAT in synchronization with the serial clock SCLK, and converts the serial data SDAT into parallel data PDAT in units of words using the latch clock LAT.

  The register unit 12 includes a register 12a and a register 12b. The register unit 12 stores and outputs the parallel data PDAT. At this time, the register 12a stores and outputs parallel data format pulse width data WD1 to WDn, and the register 12b stores and outputs parallel data format assignment data ED1 to EDn.

  The distribution unit 13 distributes the m frame timing signals EN1 to ENm to the n systems based on the n allocation data ED1 to EDn from the register 12a, and generates the n system selection signals TR1 to TRn.

  Here, the relationship among the input video signal VS, the frame timing signals EN1 to ENm, and the selection signals TR1 to TRn will be described.

  FIG. 2A is a schematic diagram showing a display screen of a liquid crystal TV. The screen of the liquid crystal TV is displayed as “A”, for example, based on both the liquid crystal control in units of the liquid crystal pixels PX in the liquid crystal panel and the dimming control in units of the dimming region D in the backlight. Is done. Liquid crystal control represents continuous control between transmission and shielding of backlight light in the liquid crystal panel. Dimming control represents control of backlight light in the form of pulse signals with pulse timings based on selection signals TR1 to TRn (that is, pulse positions) and pulse widths based on pulse width data WD1 to WDn. The liquid crystal control may be in units of liquid crystal dots such as red, green, and blue in the liquid crystal pixels, and can be similarly described by replacing the liquid crystal pixels PX with liquid crystal dots.

  The area occupied by the liquid crystal pixel PX is, for example, 1/100 or less (1 / 10,000 in area) in comparison with the dimming area D, but is enlarged for easy understanding in FIG. 2A. In the liquid crystal panel, the display screen includes a large number of liquid crystal pixels PX in the horizontal direction and a large number of horizontal lines HL in the vertical direction. On the other hand, the number of display screens illuminated by the backlight is N for each liquid crystal pixel group PG including M (M is an integer of 2 or more) liquid crystal pixels PX continuous in the horizontal direction and N (N Is divided for each horizontal line group LG including horizontal lines HL, and one dimming region D is specified by one liquid crystal pixel group PG and one horizontal line group LG. For example, as shown in FIG. 2A, when the display screen includes nine liquid crystal pixel groups PG in the horizontal direction and five horizontal line groups LG1, LG2, LG3, LG4, and LG5 in the vertical direction, 9 × 5 = 45 dimming regions D are included. In this case, the display screen includes (M × 9) × (N × 5) liquid crystal pixels PX. The numerical values M and N may change based on the video system of the input video signal VS.

  FIG. 2B is a schematic diagram illustrating scanning timing for each frame in the liquid crystal TV. The vertical direction shows five horizontal line groups LG1 to LG5 as in FIG. 2A, and the horizontal direction shows the passage of time t. The input video signal VS is a signal based on a progressive scanning system that sequentially scans (N × 5) all horizontal lines HL on the display screen. The input video signal VS may include various information related to the video signal. The frame period TF is a periodic period having a predetermined frequency, and is a period required for the input video signal VS to sequentially scan all the horizontal lines HL on the display screen. The frame period TF is approximately 60 Hz, 120 Hz, 180 Hz, or the like, for example. The liquid crystal control is performed by progressive scanning in each frame period TF from the most significant line of (N × 5) horizontal lines HL to the least significant line, one horizontal scanning period TH (= TF / (N × 5)) The timing is delayed in order, as shown in the liquid crystal scanning timing LT. On the other hand, the light control is sequentially delayed from the horizontal line group LG1 to the horizontal line group LG5 by one horizontal scanning group period THG (= TH × N) for each horizontal line group LG in synchronization with the liquid crystal scanning timing LT. At this timing, it is performed as indicated by the light control scanning timing DT.

  After the liquid crystal control of the lowest horizontal line HL at one liquid crystal scanning timing LT is finished, the liquid crystal control of the highest horizontal line HL at the next liquid crystal scanning timing LT is started. Similarly, after the dimming control of the horizontal line group LG5 at one dimming scanning timing DT is completed, the dimming control of the horizontal line group LG1 at the next dimming scanning timing DT is started. As described above, the above-described liquid crystal control and dimming control are sequentially performed in each frame F1, F2, F3, F4,... For each frame period TF. As a result, a liquid crystal frame LF sandwiched between two successive liquid crystal scanning timings LT (indicated by a slanted right-down diagonal line) and a light control frame DF sandwiched between two successive light control scanning timings DT (upward to the right) Are formed). Liquid crystal control in each liquid crystal pixel PX in one horizontal line HL is simultaneously switched at the liquid crystal scanning timing LT and is maintained during the liquid crystal frame LF. Similarly, the dimming control in each dimming region D in one horizontal line group LG is switched simultaneously at the dimming scanning timing DT and is maintained during the dimming frame DF. In FIG. 2B, the dimming scan timing DT coincides with the liquid crystal scan timing LT of the lowest horizontal line HL in each horizontal line group LG, but the liquid crystal scan timing of any horizontal line HL in each horizontal line group LG. It may coincide with LT.

  One dimming region D is irradiated by one of the light emitting element groups LED1 to LEDn (in this sense, the dimming region D is also referred to as an irradiation region). One light-emitting element driving device 10 has, for example, four drive channels that respectively drive four light-emitting element groups LED1 to LED4. In order to irradiate the 45 dimming regions D described above on the display screen, 12 light emitting element driving devices 10 are required by 45 <4 × 12.

  The reference video signal is a partial signal of the input video signal VS, and represents a reference level of the partial signal corresponding to the dimming region D irradiated by each light emitting element group LED1 to LEDn. The controller 1 generates such a reference video signal. The reference video signal is a value obtained by dividing, for example, the maximum level of the partial signals by the dynamic range of the input video signal VS. The pulse width data WD1 to WDn correspond to binary data of the reference video signal. Pulse width data WD1 to WDn with a duty ratio of 100% indicates that the level of the reference video signal matches the dynamic range of the input video signal VS, and pulse width data WD1 to WDn with a duty ratio of 0% Indicates that the signal level is zero.

  FIG. 2C is a block diagram illustrating a configuration example including, for example, twelve light emitting element driving devices 10. Each light emitting element driving device D01, D02,..., D12 is equivalent to the light emitting element driving device 10, and each light emitting element portion L01, L02,. The light emitting element driving devices D01 to D12 generate (n × 12) systems of driving currents JZ and supply them to the light emitting element units L01 to L12, respectively (the arrows of the driving currents JZ indicate the direction of the current). In the display screen of FIG. 2A, an area irradiated by one light emitting element unit 20 and including n dimming areas D is referred to as a dimming area group. Each light emitting element part L01-L12 irradiates a separate light control area group in the display screen of FIG. 2A. The controller 1Z is configured in the same manner as the controller 1, generates 12 systems of control signals S1Z similar to the control signal S1, and supplies them to the light emitting element driving devices D01 to D12, respectively. The control signal S1Z is different from the control signal S1 in that the serial data SDAT included in the control signal S1Z is separate data corresponding to each of the light emitting element driving devices D01 to D12. That is, the pulse width data WD1 to WDn and the allocation data ED1 to EDn included in the serial data SDAT are matched to the light control region groups irradiated by the light emitting element portions L01 to L12 corresponding to the light emitting element driving devices D01 to D12, respectively. ,Be changed.

  FIG. 3A is a schematic diagram showing the same display screen as FIG. 2A and shows an example of assignment of dimming area groups on the display screen. The dimming areas D011, D012, D013, and D014 are respectively irradiated by the four light emitting element groups LED1 to LED4 that are driven by the light emitting element driving device D01. The regions indicated by the light control regions D011, D012, D013, and D014 are light control region groups corresponding to the light emitting element driving device D01. The same applies to the other dimming area groups in FIG. 3A. That is, the display screen shown in FIG. 3A includes light control areas D011 to D121 (12 light control area groups) irradiated by the light emitting element portions L01 to L12 that are driven by the light emitting element driving devices D01 to D12, respectively. The Dimming regions D031 to D034 (indicated by diagonal lines) corresponding to the light emitting element driving device D03 straddle between two horizontal line groups LG. Similarly, the dimming regions D051 to D054 and D071 to D074 (indicated by hatching) corresponding to the light emitting element driving devices D05 and D07 also straddle the two horizontal line groups LG. Regarding the light emitting element driving device D12, there are no three dimming regions irradiated by the light emitting element groups LED2 to LED4.

  In the case of FIG. 3A, the number of light emitting element driving devices is twelve, which can be reduced as compared with the case of allocating an integer of light emitting element driving devices for each horizontal line group LG. Further, the number of invalid drive channels that are mounted but are not used and are wasted is three corresponding to the light emitting element groups LED2 to LED4 driven by the light emitting element driving device D12, and is an integer for each horizontal line group LG. This can be reduced compared to the case of allocating 15 light emitting element driving devices.

  FIG. 3B is a schematic diagram illustrating another example of assignment of dimming area groups. In FIG. 3B, there are three liquid crystal pixel groups PG, and the display screen includes 3 × 5 = 15 dimming areas D. In this case, the dimming areas D011 to D014, D021 to D024, D031 to D034 (three dimming area groups indicated by diagonal lines) respectively corresponding to the light emitting element driving devices D01, D02, and D03 are all two horizontal lines. It straddles the group LG. With respect to the light emitting element driving device D04, there is no one dimming region irradiated by the light emitting element group LED4. In the case of FIG. 3B, the number of light emitting element driving devices is four, which can be reduced as compared with five in the case where an integer number of light emitting element driving devices are assigned to each horizontal line group LG. Further, the number of invalid driving channels is one corresponding to the light emitting element group LED4 driven by the light emitting element driving device D04, compared with five in the case where an integer number of light emitting element driving devices are assigned to each horizontal line group LG. Can be reduced.

  FIG. 3C is a schematic diagram illustrating still another example of assignment of dimming area groups. In this case, dimming regions D011 to D014, D021 to D024, D031 to D034, D041 to D044, D051 to D054 corresponding to the light emitting element driving devices D01, D02, D03, D04, D05, D06, D07, D08, D09, respectively. , D061 to D064, D071 to D074, D081 to D084, and D091 to D094 (9 dimming area groups indicated by hatching) all span four horizontal line groups LG. Regarding the light emitting element driving device D12, there are no four dimming regions irradiated by the light emitting element groups LED2 to LED4. In the case of FIG. 3C, the number of the light emitting element driving devices is 12, which can be reduced as compared with 15 in the case where an integer number of light emitting element driving devices are assigned to each horizontal line group LG. Further, the number of invalid driving channels is three corresponding to the light emitting element groups LED2 to LED4 driven by the light emitting element driving device D12, and is 15 when an integer number of light emitting element driving devices are assigned to each horizontal line group LG. Compared to, it can be reduced.

  Further, although not illustrated, in FIG. 3A, one light emitting element driving device may drive 45 light emitting element groups to irradiate all 45 light control regions.

  The frame timing signals EN1 to ENm described above coincide with the dimming scanning timing DT in the horizontal line groups LG1, LG2,..., LGm (m = 5 in FIG. 2B). In the selection signals TR1 to TRn described above, the dimming areas corresponding to the respective light emitting element groups LED1 to LEDn of one light emitting element driving device are the horizontal line groups LG1 to LGm (that is, the frame timing signals EN1 to ENm). Indicates which horizontal line group it belongs to.

  4A, 4B, and 4C correspond to FIGS. 3A, 3B, and 3C, respectively, of the light emitting element driving devices D01 to D12, the selection signals TR1 to TR4, and the frame timing signals EN1 to EN5. It is a relationship figure which shows a relationship.

  For example, in FIG. 3A, among the dimming areas D031 to D034 respectively corresponding to the light emitting element groups LED1 to LED4 driven by the light emitting element driving device D03, the dimming area D031 is the horizontal line group LG1, and the dimming areas D032 to D034 are horizontal. Each belongs to the line group LG2. As a result, in FIG. 4A, in the light emitting element driving device D03, the selection signal TR1 becomes the frame timing signal EN1, and the selection signals TR2 to TR4 become the frame timing signal EN2. Similarly, FIGS. 4A, 4B, and 4C are obtained from FIGS. 3A, 3B, and 3C, respectively.

  4A, FIG. 4B, and FIG. 4C, the light emitting element driving device indicated by hatching among the light emitting element driving devices D01 to D12 includes two or more frame timing signals among the frame timing signals EN1 to EN5. The light-emitting element driving devices indicated by these diagonal lines correspond to the light control regions indicated by the diagonal lines in FIGS. 3A, 3B, and 3C. That is, the light emitting element driving device indicated by hatching in FIGS. 4A, 4B, and 4C includes two or more frame timing signals in the same light emitting element driving device in FIGS. 3A, 3B, and 3C, respectively. This is due to the fact that the corresponding dimming area indicated by the diagonal lines extends between two or more horizontal line groups LG.

  2C, FIG. 3A to FIG. 3C, and FIG. 4A to FIG. 4C exemplify the case where the number of light emitting element driving devices 10 is twelve or four, but the number of light emitting element driving devices 10 is any other number. It may be.

  FIG. 5 is a block diagram illustrating a configuration example of the distribution unit 13. As described above, the distribution unit 13 distributes the m system frame timing signals EN1 to ENm to the n systems based on the n system allocation data ED1 to EDn, and generates the n system selection signals TR1 to TRn. Distribution unit 13 includes selection circuits 3Q1, 3Q2, ..., 3Qn. The selection circuits 3Q1 to 3Qn select any one of m frame timing signals EN1 to ENm based on the allocation data ED1 to EDn, respectively. Selection circuits 3Q1-3Qn generate selection signals TR1-TRn representing the selected signals, respectively.

  Each of the allocation data ED1 to EDn is a signal in parallel data format having an integer bit width larger than the logarithm of m with 2 as a base so that any one of the frame timing signals EN1 to ENm can be specified. It is. Depending on which of the light emitting element driving devices D01 to D12 shown in FIG. 4A to FIG. 4C the light emitting element driving device 10 including the distribution unit 13 shown in FIG. A relationship with the signals EN1 to EN5 is obtained. As described above, the allocation data ED1 to EDn depend on the arrangement of the light emitting element groups LED1 to LED4 driven by the light emitting element driving devices D01 to D12 in the backlight, as shown in FIGS. 3A to 3C, for example. Thus, for example, it is initially set when the liquid crystal TV is manufactured. The allocation data ED1 to EDn may change based on, for example, the input video signal VS, or may change every time the liquid crystal TV is turned on.

  FIG. 6 is a timing chart illustrating an operation example of the distribution unit 13. The horizontal direction indicates the passage of time t. The frame timing signals EN1 to EN5 are signals that coincide with the dimming scanning timing DT (shown in FIG. 2B) in the horizontal line groups LG1 to LG5, respectively. That is, the frame timing signals EN1 to EN5 are timing signals having a frame period TF, and are timing signals that are sequentially delayed from the frame timing signal EN1 to the frame timing signal EN5 by one horizontal scanning group period THG for each system. is there. In FIG. 6, the distribution unit 13 operates corresponding to the dimming regions D031 to D034 of FIG. 3A and the light emitting element driving device D03 of FIG. 4A. In this case, the selection signal TR1 matches the frame timing signal EN1, and each selection signal TR2 to TR4 matches the frame timing signal EN2. As described above, the selection signals TR1 to TR4 are signals having the frame period TF and the phase of which is set by the distribution unit 13.

  Next, the pulse signal generation unit 14 will be described.

  In FIG. 1, a pulse signal generator 14 generates pulse signals P1, P2,..., Pn based on pulse width data WD1 to WDn, selection signals TR1 to TRn, and a master clock signal MCLK. The pulse signals P1 to Pn are also called duty pulse signals, and the pulse signal generation unit 14 is also called a duty pulse signal generation unit.

  FIG. 7 is a block diagram illustrating a configuration example of the pulse signal generation unit 14. The pulse signal generation unit 14 includes pulse signal generation circuits 4Q1, 4Q2, ..., 4Qn. The pulse signal generation circuit 4Q1 generates the pulse signal P1 based on the pulse width data WD1, the selection signal TR1, and the master clock signal MCLK. Similarly, the pulse signal generation circuit 4Qk generates the pulse signal Pk based on the pulse width data WDk, the selection signal TRk, and the master clock signal MCLK (k = 2 to n). Although one pulse signal generation circuit 4Q1 will be described below, the other pulse signal generation circuits 4Q2 to 4Qn can be described in the same manner.

  The pulse signal generation circuit 4Q1 includes a counter 30, a counter value detection circuit 31, and a logic circuit 32. The master clock signal MCLK determines the resolution of the pulse width in the pulse signal P1 having a PWM (Pulse Width Modulation) waveform. Therefore, the master clock signal MCLK is set to a signal having a predetermined frequency that is sufficiently higher than the frame period TF. The selection signals TR1 to TRn are signals having the frame period TF as described above.

  The counter 30 receives the pulse width data WD1 in parallel data format at the data input terminal INPUT, receives the master clock signal MCLK at the clock input terminal CLK via the logic circuit 32, and receives the selection signal TR1 at the load input terminal LOAD. As a result, the counter 30 outputs a counter output signal DP1 from the data output terminal OUTPUT. The counter 30 counts the master clock signal MCLK by the value of the pulse width data WD1 from the time when the pulse width data WD1 is loaded at the timing of the selection signal TR1, and generates a counter output signal DP1 that represents the elapsed time of the count value. Hereinafter, the counter 30 will be described as a down counter.

  When the selection signal TR1 becomes high level, the counter 30 captures the pulse width data WD1 and simultaneously sets the counter output signal DP1 to pulse width data WD1 (preset operation). Subsequently, the counter 30 decrements the counter output signal DP1 one by one by counting the number of master clock signals MCLK from the pulse width data WD1 (preset value) to zero by the value of the pulse width data WD1. The counter value detection circuit 31 sets the pulse signal P1 to a high level when the counter output signal DP1 is other than zero, and sets the pulse signal P1 to a low level when the counter output signal DP1 is zero. Therefore, the counter value detection circuit 31 sets the pulse signal P1 to the high level from the time when the selection signal TR1 becomes the high level to the time when the counter output signal DP1 becomes zero.

  The logic circuit 32 includes an OR circuit and an AND circuit. When the pulse signal P1 becomes low level, the logic circuit 32 invalidates the input of the master clock signal MCLK to the clock input terminal CLK and stops the counting operation of the counter 30 while the selection signal TR1 is low level. As a result, the counter 30 maintains the counter output signal DP1 at zero, and the counter value detection circuit 31 maintains the pulse signal P1 at the low level. Thereafter, when the selection signal TR1 becomes high level, the stop of the count operation is released, the counter 30 presets the pulse width data WD1 again and starts the count operation, and the counter value detection circuit 31 sets the pulse signal P1 to high level. To.

  When the pulse width data WD1 is zero, the counter 30 immediately sets the counter output signal DP1 to zero when the selection signal TR1 becomes high level. The counter value detection circuit 31 sets the pulse signal P1 to the low level and stops the counting operation of the counter 30.

  As described above, the pulse signal generation circuit 4Q1 generates the pulse signal P1 having a pulse width corresponding to the pulse width data WD1, with the timing of the selection signal TR1 for each frame period TF as the pulse rising point. That is, the pulse signal generation circuit 4Q1 generates a pulse signal P1 having a pulse timing based on the selection signal TR1 and a pulse width based on the pulse width data WD1 or the input video signal VS.

  FIG. 8 is a waveform diagram showing an operation example of the pulse signal generation circuit 4Q1 of FIG. The horizontal direction indicates the passage of time t. In FIG. 8, the bit width of the pulse width data WD1 to WDn is 12 bits.

  In FIG. 8, when the selection signal TR1 becomes high level, the value 1024 of the pulse width data WD1 is taken in, the counter output signal DP1 becomes 1024, and at the same time, the pulse signal P1 becomes high level. Subsequently, in synchronization with the master clock signal MCLK, the counter output signal DP1 is incremented from 1024 to 0 one by one. A period corresponding to the passage from 1024 to 0 of the counter output signal DP1 is the pulse width of the pulse signal P1 corresponding to the pulse width data WD1 = 1024.

  The PWM period that represents the average period of the pulse signal P1 matches the frame period TF, and the PWM frequency that represents the center frequency of the pulse signal P1 matches 1 / TF. If the counter 30 is an L-bit counter (the bit width of the pulse width data WD1 is also L bits), the counter 30 can count a maximum of 2 L (= NPWM) master clock signals MCLK. If the cycle Tclk of the master clock signal MCLK is set to 1 / NPWM (Tclk = TF / NPWM) of the frame cycle TF, the pulse width of the pulse signal P1 (corresponding to the pulse width data WD1) is NPWM gradations, that is, 0. It can be set in a range from × Tclk to (NPWM-1) × Tclk with a resolution of Tclk. On the other hand, if the cycle of the selection signal TR1 (or frame timing signals EN1 to ENm) is set to one per NPWM generation of the master clock signal MCLK, the pulse width of the pulse signal P1 is similarly NPWM gradations. It becomes possible to set. In terms of the duty ratio, the pulse width of the pulse signal P1 can be set within a range of 0 to (NPWM-1) / NPWM and with a resolution of 1 / NPWM.

  For example, in FIG. 8, the counter 30 counts NPWM = 4096 master clock signals MCLK as an L = 12 bit counter (the bit width of the pulse width data WD1 is also L = 12 bits). The period Tclk of the master clock signal MCLK is 1/44096 of the frame period TF (Tclk = TF / 4096), and the pulse width of the pulse signal P1 (corresponding to the pulse width data WD1) is 4096 gradations, that is, 0 × Tclk. To 4095 × Tclk, and can be set with a resolution of Tclk. On the other hand, if the cycle of the selection signal TR1 is set to one out of 4096 master clock signals MCLK, the pulse width of the pulse signal P1 can be set in 4096 gradations. In terms of the duty ratio, the pulse width of the pulse signal P1 can be set within a range of 0 to 4095/4096 and with a resolution of 1/44096.

  Although FIG. 8 shows the operation of the configuration using a 12-bit down counter as the counter 30, the present invention is not limited to this, and a counter having any number of bits may be used. In addition, even when an up counter is used as the counter 30, a configuration having the same function is easily possible. Further, the counter value detection circuit 31 does not necessarily detect zero, and may detect a predetermined non-zero value. Even if the counter value detection circuit 31 is omitted and the carry signal of the counter 30 is used, the same function can be easily realized.

  Further, in FIG. 8, the pulse signal P1 rises at the timing of the selection signal TR1, but the pulse signal P1 may fall at the timing of the selection signal TR1. For example, the counter in the pulse signal generation circuit 4Q1 stops the count operation from the timing of the selection signal TR1 for a period of (TF−WD1 × Tclk), and then the period of WD1 × Tclk until the timing of the next selection signal TR1. Count operation is performed. Thereby, the pulse signal generation circuit 4Q1 can generate the pulse signal P1 that rises at the timing of the selection signal TR1.

  In the above description, the example in which the pulse signal generation unit 14 is configured by a counter has been shown. However, the present invention is not limited to this, and the pulse width data WD1 to WD1 are set using the master clock signal MCLK as a unit of time division. Any circuit may be used as long as it can generate pulse signals P1 to Pn based on WDn.

  FIG. 9A is a block diagram illustrating a configuration example of the current driver 15. The current driver 15 generates drive currents J1, J2,..., Jn based on the pulse signals P1 to Pn, respectively. Further, the current driving unit 15 supplies driving currents J1 to Jn to the light emitting element unit 20 through the current paths PJ1 to PJn, respectively. Current drive unit 15 includes current drive circuits 5Q1, 5Q2, ..., 5Qn. The current drive circuit 5Q1 generates a drive current J1 based on the pulse signal P1, and supplies the drive current J1 to the light emitting element group LED1 via the current path PJ1. Similarly, the current drive circuit 5Qk generates a drive current Jk based on the pulse signal Pk, and supplies the drive current Jk to the light emitting element group LEDk via the current path PJk (k = 2 to n). Each current drive circuit 5Q1 to 5Qn corresponds to the drive channel described above. That is, the current driver 15 has n drive channels. One drive channel may include not only the current drive circuit 5Qk but also the selection circuit 3Qk and the pulse signal generation circuit 4Qk (k = 1 to n). Hereinafter, one current driving circuit 5Q1 will be described, but the other current driving circuits 5Q2 to 5Qn can be described in the same manner.

  The current drive circuit 5Q1 includes a switch element 40 and a constant current circuit 41 as shown in FIG. 9A, for example. The constant current circuit 41 generates a drive current J1 having a predetermined magnitude. The switch element 40 receives the pulse signal P1 at the control terminal, and is turned on in a period in which the pulse signal P1 is at a high level, thereby supplying the drive current J1 to the light emitting element group LED1, and the pulse signal P1 is at a low level. By being turned off in the period, the supply of the drive current J1 to the light emitting element group LED1 is stopped. That is, the current drive circuit 5Q1 generates a PWM pulse-shaped drive current J1 that matches the pulse timing and pulse width of the pulse signal P1, and causes each light emitting element of the light emitting element group LED1 to emit light with a desired luminance.

  The luminance of each light emitting element changes monotonously in accordance with the pulse height of the driving current J1, and is approximately proportional to the duty ratio of the driving current J1 (that is, the pulse width of the driving current J1 with respect to the frame period TF). Here, the pulse height of the drive current J1 is held at a predetermined value, and the luminance of each light emitting element is adjusted by changing the pulse width of the drive current J1. When the pulse width data WD1 does not change, the constant current circuit 41 maintains the brightness of the pulse width light emitting element group LED1 of the drive current J1 with high accuracy. It is configured to maintain J1 with high accuracy. The switch element 40 is formed of, for example, a power MOS (Metal Oxide Semiconductor) transistor. The current driving circuit 5Q1 may change the luminance of the light emitting element group LED1 by changing the pulse height of the driving current J1.

  FIG. 9B is a waveform diagram showing an operation example of the current driver 15. The horizontal direction indicates the passage of time t. The drive currents J1 to J4 are supplied to the light emitting element unit 20 at a predetermined pulse height in synchronization with the selection signals TR1 to TR4 in FIG. 6 for each frame period TF.

  With the configuration described above, the frame timing signals EN1 to ENm generated by the controller 1 are distributed to the drive channels that drive the light emitting element groups LED1 to LEDn by the allocation data ED1 to EDn generated by the controller 1. Can do. As a result, each drive channel can be divided into a plurality of groups and driven at an arbitrary timing. As a result, it becomes possible to drive the light emitting element unit 20 across a plurality of horizontal line groups LG with one light emitting element driving device 10, and to efficiently use the light emitting element driving device 10 used in the entire screen. it can.

  For example, when the dimming regions D031 to D034 are irradiated using four drive channels as shown in FIG. 3A, the horizontal channel group LG1 as shown in FIG. 6 is applied to the drive channel that drives the light emitting element group LED1. Corresponding frame timing signal EN1 is assigned. Further, a frame timing signal EN2 corresponding to the horizontal line group LG2 is assigned to the drive channel for driving each light emitting element group LED2, LED3, LED4. As a result, the light control area D031 can be adjusted at the timing of the horizontal line group LG1, and the light control areas D032 to D034 can be adjusted at the timing of the horizontal line group LG2, and the light control across the two horizontal line groups LG can be performed. The regions D031 to D034 can be dimmed by one light emitting element driving device 10.

  One light emitting element driving device 10 has four drive channels for driving, for example, four light emitting element groups LED1 to LED4. However, one light emitting element driving apparatus 10 has, for example, eight driving channels, and each of the four light emitting element groups LED1 to LED4 may be driven by two driving channels. That is, each light emitting element group LED1 to LEDn may be driven by two or more drive channels. In this case, the light emitting element groups to be driven are the same. By assigning the same frame timing signal to the selection signals of a plurality of driving channels, each light emitting element group is divided into a plurality of groups and driven at an arbitrary timing. Is possible. Thus, by providing a plurality of current drive circuits (that is, a plurality of drive channels) for driving one light emitting element group, the drive current J1 can be increased and the drive capability can be enhanced.

  Thus, according to the light emitting element driving apparatus 10 of the first embodiment, the selection circuit 3Q1 is a timing signal having the frame period TF of the input video signal VS and has a time difference from each other by one horizontal scanning group period THG. One of the two systems of frame timing signals EN1 and EN2 is selected. Further, the selection circuit 3Q2 selects the other of the two systems of frame timing signals EN1 and EN2.

  By configuring the selection circuits 3Q1 and 3Q2 as described above, the light emitting element driving device 10 adjusts the timing of dimming the two dimming regions D respectively irradiated by the light emitting element groups LED1 and LED2 to each other. Only the horizontal scanning group period THG can be changed. As a result, the dimming area group corresponding to one light emitting element driving device 10 can span at least two horizontal line groups LG. For this reason, a plurality of dimming area groups can be arranged close to each other on one display screen (shown in FIGS. 3A to 3C). As a result, the light emitting element driving device 10 having a specific number of driving channels can be efficiently used for various liquid crystal TVs having different numbers of light control regions, and the number of light emitting element driving devices can be reduced. Is possible. Furthermore, since individual designs are not required for these various liquid crystal TVs, development costs can be reduced.

(Embodiment 2)
FIG. 10 is a block diagram illustrating a configuration example of the light emitting element driving device 10A.

  The light emitting element driving apparatus 10A in FIG. 10A differs from the light emitting element driving apparatus 10 in FIG. 1 in that the register unit 12A is partially changed from the register unit 12 and the frame timing signal generation unit 16A is added. It is a point. Furthermore, the controller 1A is partially changed from the controller 1. Since configurations, operations, and effects other than such changes in the second embodiment are the same as those in the first embodiment, description thereof is omitted.

  The controller 1A does not include the frame timing signal generation unit 16. The controller 1A generates a control signal S1A based on the input video signal VS. The control signal S1A includes a frame timing reference signal RTR, a master clock signal MCLK, serial data SDAT, a serial clock SCLK, and a latch clock LAT. The control signal S1A includes a frame timing reference signal RTR instead of the frame timing signals EN1 to ENm. The serial data SDAT includes delay data DD1, DD2,..., DDm in addition to the pulse width data WD1 to WDn and the allocation data ED1 to EDn.

  The controller 1A extracts the frame period TF from the input video signal VS, and generates a frame timing reference signal RTR representing the frame period TF. The delay data DD1 to DDm are data representing a delay from a predetermined point in the light control scanning timing DT shown in FIG. 2B. Typically, the delay data DD1 to DDm are 0, (1 / m) × NPWM, (2 / m) × NPWM,..., ((M−1) / m) × NPWM, respectively. The controller 1A may generate the delay data DD1 to DDm based on the input video signal VS, or may set the delay data DD1 to DDm regardless of the input video signal VS. For example, the controller 1A may change the delay data DD1 to DDm based on the video format of the input video signal VS.

  The serial interface unit 11 inputs serial data SDAT in synchronization with the serial clock SCLK, and converts the serial data SDAT into parallel data PDAT in units of words using the latch clock LAT. The register unit 12A includes a register 12c in addition to the registers 12a and 12b. The register unit 12A stores and outputs the parallel data PDAT. At this time, the register 12c stores and outputs the delay data DD1 to DDm in the parallel data format.

  The frame timing signal generation unit 16A generates frame timing signals EN1 to ENm based on the frame timing reference signal RTR, the master clock signal MCLK, and the delay data DD1 to DDm from the register 12c.

  FIG. 11 is a block diagram illustrating a configuration example of the frame timing signal generation unit 16A. The frame timing signal generation unit 16A includes a counter 50 and coincidence circuits 6Q1, 6Q2, ..., 6Qm. The counter 50 receives the master clock signal MCLK at the clock input terminal CLK, receives the frame timing reference signal RTR at the clear input terminal CLEAR, and outputs the counter output signal CT from the data output terminal OUTPUT. The counter 50 counts the master clock signal MCLK from the time when it is cleared by the frame timing reference signal RTR, and generates a counter output signal CT indicating the elapsed time of the count value. The coincidence circuit 6Q1 compares the counter output signal CT with the delay data DD1, and when it matches, sets the frame timing signal EN1 to high level, and when it does not match, sets the frame timing signal EN1 to low level. Similarly, the coincidence circuit 6Qk compares the counter output signal CT with the delay data DDk, and if it coincides, sets the frame timing signal ENk to high level, and if it does not coincide, sets the frame timing signal ENk to low level (k = 2). ~ M).

  FIG. 12 is a waveform diagram illustrating an operation example of the frame timing signal generation unit 16A. The horizontal direction indicates the passage of time t. In FIG. 12, the counter 50 is an up counter of 12 bits or more, and the delay data DD1 to DDm have a bit width of 12 bits.

  In FIG. 12, when the frame timing reference signal RTR becomes high level, the counter output signal CT becomes 0, and then the counter output signal CT is incremented by 1 from 0 in synchronization with the master clock signal MCLK. For example, the delay data DD1, DD2, and DD3 are set to 0, 1024, and 2048, respectively. Each time the counter output signal CT sequentially matches the delay data DD1 to DD3, the frame timing signals EN1 to EN3 sequentially become high level, and during other non-matching periods, the frame timing signals EN1 to EN3 maintain low level. To do. From the time when the frame timing reference signal RTR becomes high level, the frame timing reference signal RTR becomes high level again after a frame period TF (= 4096 × Tclk) corresponding to 4096 master clock signals MCLK. At this time, the counter output signal CT returns to 0, and the above-described operation is repeated thereafter.

  Here, if DD2-DD1 = DD3-DD2 = TF / (Tclk × m) is set, the frame timing signals EN1 to EN3 of FIG. 12 are sequentially delayed by one horizontal scanning group period THG shown in FIG. Correspond to the frame timing signals EN1 to EN3, respectively.

  Thus, according to the light emitting element driving apparatus 10A of the second embodiment, the light emitting element driving apparatus 10A further includes the frame timing signal generation unit 16A. The frame timing signal generator 16A can generate the frame timing signals EN1 to ENm based on the frame timing reference signal RTR having the frame period TF and the delay data DD1 to DDm. The frame timing signals EN1 to ENm are signals obtained by delaying the frame timing reference signal RTR for the periods corresponding to the delay data DD1 to DDm, respectively.

  With this configuration, the number of control signals S1A generated by the controller 1 can be reduced, and the configuration of the controller 1 can be simplified.

  The frame timing signal generator 16A is configured by the counter 50 and the coincidence circuits 6Q1 to 6Qm. However, the present invention is not limited to this, and other configurations can have the same function. It is.

(Embodiment 3)
FIG. 13 is a block diagram illustrating a configuration example of the light emitting element driving device 10B.

  The light emitting element driving device 10B of FIG. 13 differs from the light emitting element driving device 10 of FIG. 1 in that the register unit 12B is partially changed from the register unit 12 and the distribution unit 13B is changed from the distribution unit 13. It is a point. Since the configuration, operation, and effects other than such changes in the third embodiment are the same as those of the first embodiment, the description thereof is omitted.

  The register unit 12B includes only the register 12a and does not include the register 12b.

  The distribution unit 13B distributes the m system frame timing signals EN1 to ENm to the n systems, and generates the n system selection signals TR1 to TRn. Distribution unit 13B does not receive allocation data from register unit 12B. Distribution unit 13B includes selection circuits 3BQ1, 3BQ2, ..., 3BQn. The selection circuits 3BQ1 to 3BQn select any one of the m systems of frame timing signals EN1 to ENm based on a predetermined connection relationship, and generate selection signals TR1 to TRn representing the selected signals, respectively. The n input paths (or input terminals) through which the pulse signal generation circuits 4Q1 to 4Qn receive the selection signals TR1 to TRn, respectively, are m output paths (or output terminals) from which the controller 1 outputs the frame timing signals EN1 to ENm. ) And the distribution unit 13B are fixedly connected based on a predetermined connection relationship.

  That is, the distribution unit 13B includes m output paths from which the controller 1 outputs the frame timing signals EN1 to ENm, and n input paths from which the pulse signal generation circuits 4Q1 to 4Qn receive the selection signals TR1 to TRn, respectively. Represents a circuit that is fixedly connected based on a predetermined connection relationship. For example, the distribution unit 13B is a wiring network connected in a predetermined relationship, and may not include active elements such as transistors. For example, in the distribution unit 13B, the load input terminal LOAD of the counter 30 in the pulse signal generation unit 14 in FIG. 7 is any one of m output paths through which the frame timing signals EN1 to ENm are output on the printed circuit board. May be connected to one.

  Depending on which of the light emitting element driving devices D01 to D12 shown in FIGS. 4A to 4C matches the light emitting element driving device 10B including the distributing unit 13B, for example, the selection signals TR1 to TR4 and the frame timing signals EN1 to EN5 Is required. The predetermined connection relationship described above is set depending on the arrangement of the light emitting element groups LED1 to LED4 driven by the light emitting element driving devices D01 to D12 in the backlight, as shown in FIGS. 3A to 3C, for example. .

  In FIG. 13, the distribution unit 13B is configured to correspond to the light control regions D031 to D034 in FIG. 3A and the light emitting element driving device D03 in FIG. 4A. In this case, the selection signal TR1 matches the frame timing signal EN1, and each selection signal TR2 to TR4 matches the frame timing signal EN2.

  As described above, according to the light emitting element driving device 10B of the third embodiment, the n input paths through which the pulse signal generation circuits 4Q1 to 4Qn receive the selection signals TR1 to TRn are respectively connected by the controller 1 to the frame timing signals EN1 to EN1. The distribution unit 13B is fixedly connected to any one of the m output paths that output ENm based on a predetermined connection relationship. Thereby, when it is desired to fix the selection in the selection circuit, the light emitting element driving device 10B is advantageous. Further, the register 12b is not necessary, and the selection circuits 3BQ1 to 3BQn are simplified, so that the cost can be reduced.

(Embodiment 4)
FIG. 14 is a block diagram illustrating a configuration example of the light emitting element driving device 10C.

  The light emitting element driving device 10C in FIG. 14 differs from the light emitting element driving device 10 in FIG. 1 in that the current driving unit 15C is partially changed from the current driving unit 15, and the feedback unit 18 and the pulse width modulation unit. 17 is added. Further, a step-up / step-down unit 21 is added to the configuration of FIG. Since the configuration, operation, and effects other than such changes in the fourth embodiment are the same as those of the first embodiment, description thereof is omitted.

  The current driver 15C generates drive currents J1, J2,..., Jn based on the pulse signals P1 to Pn, respectively. Furthermore, the current driver 15C outputs detection voltages VD1, VD2,..., VDn in the current paths PJ1 to PJn, respectively. Current drive unit 15C includes current drive circuits 5CQ1, 5CQ2,..., 5CQn. The current drive circuit 5CQ1 generates a drive current J1 based on the pulse signal P1, and outputs a detection voltage VD1 in the current path PJ1. Similarly, the current drive circuit 5CQk generates a drive current Jk based on the pulse signal Pk and outputs a detection voltage VDk in the current path PJk (k = 2 to n).

  FIG. 15 is a detailed block diagram illustrating a configuration example of the light emitting element driving device 10C. The feedback unit 18 includes an error amplifier 18a and a minimum value detection circuit 18b. The minimum value detection circuit 18b extracts (or samples) the detection voltages VD1 to VDn when the pulse signals P1 to Pn are at the high level, and the minimum voltage among the extracted (or sampled) detection voltages. Is generated as a minimum detection voltage Vmin.

  In other words, the minimum value detection circuit 18b generates a minimum detection voltage Vmin that represents a minimum voltage among the detection voltages at which the pulse signal is at a high level. Further, the minimum value detection circuit 18b holds the detection voltages VD1 to VDn when the pulse signals P1 to Pn are at a high level, respectively. When all the pulse signals P1 to Pn are at a low level, the minimum value detection circuit 18b generates a minimum detection voltage Vmin representing a minimum voltage among the detection voltages held immediately before. As a result, the minimum value detection circuit 18b can use the detection voltage in the on state even when all of the current drive circuits 5CQ1 to 5CQn are in the off state.

  The reference power supply Eref generates a reference voltage Vref. The error amplifier 18a receives the minimum detection voltage Vmin at the inverting input terminal, receives the reference voltage Vref at the non-inverting input terminal, and amplifies a voltage obtained by subtracting the minimum detection voltage Vmin from the reference voltage Vref, thereby generating the error signal S18. Generate. As the minimum detection voltage Vmin becomes larger than the reference voltage Vref, the error signal S18 becomes smaller, and as the minimum detection voltage Vmin becomes smaller than the reference voltage Vref, the error signal S18 becomes larger.

  The pulse width modulation unit 17 includes a pulse width modulation circuit 17a and a predrive circuit 17b. The pulse width modulation circuit 17a compares the error signal S18 with, for example, a triangular wave repetitive voltage having a predetermined pulse width modulation frequency, and becomes a high level when the error signal S18 is equal to or higher than the triangular wave repetitive voltage. A comparison result signal S17a is generated. The predrive circuit 17b generates the pulse width modulation signal S17 by amplifying the comparison result signal S17a. As the error signal S18 increases, the high level period of the pulse width modulation signal S17 becomes longer, and as the error signal S18 becomes smaller, the high level period of the pulse width modulation signal S17 becomes shorter.

  The step-up / step-down unit 21 includes a coil 21a, a switch 21b, a capacitor 21c, and a diode 21d. One end of the coil 21a is connected to the voltage source EIN, and the other end is connected to one end of the switch 21b and the anode of the diode 21d. The other end of the switch 21b is grounded, and the pulse width modulation signal S17 is input to the control terminal. The cathode of the diode 21d is connected to one end of the capacitor 21c and the voltage path PV, and the other end of the capacitor 21c is grounded. The switch 21 may be formed of a switching element such as a power transistor.

  The voltage source EIN generates a predetermined voltage VIN. The switch 21b receives the pulse width modulation signal S17 at its control terminal and is turned on / off by the pulse width modulation signal S17. The coil 21a charges and discharges the electric power from the voltage source EIN by the ON operation and the OFF operation of the switch 21b, respectively. The diode 21d prevents a reverse flow from the voltage path PV during charging, and allows the electric power discharged during discharging to pass in the forward direction. The capacitor 21c charges the passed power and generates a substantially DC drive voltage VCC smoothed in the voltage path PV.

  As described above, the step-up / step-down unit 21 converts the predetermined voltage VIN into the drive voltage VCC, supplies the voltage to the light emitting element groups LED1 to LEDn via the voltage path PV, and also drives the drive voltage VCC based on the pulse width modulation signal S17. Adjust. The step-up / step-down unit 21 is a booster circuit that generates a drive voltage VCC larger than the predetermined voltage VIN.

  The feedback unit 18, the pulse width modulation unit 17, and the step-up / step-down unit 21 constitute a drive voltage generation unit 60. The feedback unit 18 and the pulse width modulation unit 17 constitute a step-up / step-down control unit. That is, the drive voltage generation unit 60 includes a step-up / step-down control unit and a step-up / step-down unit 21.

  As the high-level period of the pulse width modulation signal S17 becomes longer, the ON period of the switch 21b becomes longer, so the charging period of the coil 21a becomes longer, and as a result, the drive voltage VCC increases. When the drive voltage VCC increases, the detection voltages VD1 to VDn also increase. On the contrary, as the high level period of the pulse width modulation signal S17 becomes shorter, the ON period of the switch 21b becomes shorter, so the charging period of the coil 21a becomes shorter, and as a result, the drive voltage VCC becomes smaller. When the drive voltage VCC decreases, the detection voltages VD1 to VDn also decrease. The step-up / step-down unit 21 generates a drive voltage VCC that is approximately proportional to the high level period of the pulse width modulation signal S17, that is, the pulse width of the pulse width modulation signal S17.

  Considering the operations of the feedback unit 18 and the pulse width modulation unit 17 described above, the drive voltage VCC increases as the minimum detection voltage Vmin becomes smaller than the reference voltage Vref, so that the detection voltages VD1 to VDn also increase. It is suppressed that the voltage Vmin becomes smaller than the reference voltage Vref. On the other hand, as the minimum detection voltage Vmin becomes larger than the reference voltage Vref, the drive voltage VCC becomes smaller. Therefore, the detection voltages VD1 to VDn also become smaller, and the minimum detection voltage Vmin is prevented from becoming larger than the reference voltage Vref. The

  As described above, the drive voltage generation unit 60 adjusts the drive voltage VCC so that the minimum detection voltage Vmin of the detection voltages VD1 to VDn is approximately equal to the reference voltage Vref. If the reference voltage Vref is set to the minimum voltage at which the current driving circuits 5Q1 to 5Qn (or the constant current circuit 41) can operate, the operating voltage of the current driving circuits 5CQ1 to 5CQn is secured and the current driving circuits 5CQ1 to 5CQn The power consumption can be minimized.

  Thus, according to the light emitting element driving device 10C of the fourth embodiment, the light emitting element driving device 10C includes the step-up / step-down control unit and adjusts the drive voltage VCC via the step-up / step-down unit 21. Accordingly, the light emitting element driving device 10C can secure the operating voltage of the current driving circuits 5CQ1 to 5CQn and can minimize the power consumption of the current driving circuits 5CQ1 to 5CQn.

  The step-up / step-down unit 21 is composed of a step-up circuit, but may be a step-down circuit or a step-up / down circuit.

(Summary of embodiment)
According to the light emitting element driving apparatus of the present invention, one of the two selection circuits is a timing signal having a frame period of the input video signal, and two systems having a time difference of one horizontal scanning group period from each other. One of the frame timing signals is selected. Further, the other selection circuit selects the other of the two system frame timing signals.

  By configuring each selection circuit as described above, the light emitting element driving device can adjust the timing of dimming the two dimming areas respectively irradiated by the two light emitting element groups for one horizontal scanning group period. Can be changed. Thereby, the light control area group corresponding to one light emitting element drive device can straddle at least two horizontal line groups. For this reason, a plurality of dimming area groups can be arranged in a packed manner so as not to be excessive on one display screen. As a result, a light emitting element driving device having a specific number of driving channels can be efficiently used for various liquid crystal TVs having different numbers of light control regions, and the number of light emitting element driving devices can be reduced. It becomes possible. Furthermore, since individual designs are not required for these various liquid crystal TVs, development costs can be reduced.

  In the above, the described numbers are exemplified for specifically explaining the present invention, and the present invention is not limited to the illustrated numbers. Further, the logic level represented by the high level / low level is exemplified for specifically explaining the present invention, and if the configuration of the logic circuit is changed, the logic level different from the exemplified logic level is shown. Equivalent results can be obtained by combining the above. Moreover, the component comprised by the hardware containing FPGA can also be comprised by software, and the component comprised by software can be comprised also by hardware. Furthermore, by reconfiguring some of all the constituent elements in the above-described embodiment in a combination different from that in the above-described embodiment, effects of different combinations can be obtained.

  The above description of the embodiments is merely an example embodying the present invention, and the present invention is not limited to these examples. Various techniques that can be easily configured by those skilled in the art using the technology of the present invention. It can be expanded to the example.

  The present invention can be used for a light emitting element driving apparatus.

DESCRIPTION OF SYMBOLS 1, 1A, 1Z controller 10, 10A, 10B, 10C, D01-D12 Light emitting element drive device 11 Serial interface part 12, 12A, 12B Register part 12a, 12b, 12c Register 13, 13B Distribution part 14 Pulse signal generation part 15, 15C current drive unit 16, 16A frame timing signal generation unit 17 pulse width modulation unit 17a pulse width modulation circuit 17b pre-drive circuit 18 feedback unit 18a error amplifier 18b minimum value detection circuit 20, L01 to L12 light emitting element unit 21 step-up / step-down unit 30 50 counter 31 counter value detection circuit 32 logic circuit 3Q1-3Qn, 3BQ1-3BQn selection circuit 40 switch element 41 constant current circuit 4Q1-4Qn pulse signal generation circuit 5Q1-5Qn, 5CQ1-5CQn current drive Dynamic circuit 6Q1-6Qm Matching circuit 60 Drive voltage generator DD1-DDm Delay data ED1-EDn Allocation data EN1-ENm Frame timing signal J1-Jn, JZ Drive current LAT Latch clock LED1-LEDn Light emitting element group MCLK Master clock signal P1- Pn pulse signal PDAT parallel data PV voltage path RTR frame timing reference signal S1, S1A, S1Z control signal SCLK serial clock SDAT serial data TF frame period TR1 to TRn selection signal VCC drive voltage VS input video signal WD1 to WDn pulse width data

Claims (16)

  A plurality of current drive circuits for energizing the light emitting element group by pulse width modulation drive, a pulse signal generation unit for generating a pulse signal for driving the plurality of current drive circuits, and each current drive circuit A light emitting element driving apparatus having a distribution unit that selects and outputs a plurality of frame timing signals.   The light emitting element driving device according to claim 1, wherein a plurality of frame timing signals serving as the options are input from the outside.   The light emitting element driving device according to claim 1, wherein a plurality of frame timing signals serving as the options are internally generated using signals input from the outside.   The light emitting element driving device according to claim 1, wherein selection of the frame timing signal is set by a command signal from the outside.   The light emitting element driving device according to claim 1, wherein selection of the frame timing signal is fixedly set by connection of an input terminal.   The light-emitting element driving device according to claim 1, further comprising a power supply unit that supplies power to the other end of the current-driven load.   A driving method in which a pulse width modulation drive is performed by selecting a rising or falling phase of a duty pulse from predetermined timing options when a plurality of current drive circuits are driven by a pulse width modulation drive. A timing signal having a frame period of the input video signal, a first selection circuit for selecting one of two frame timing signals having a time difference from each other for a predetermined period and generating a first selection signal;
A first pulse signal generation circuit for generating a first pulse signal having a pulse position based on the first selection signal;
A first current driving circuit capable of generating a first driving current based on the first pulse signal and supplying the first driving current to a first light emitting element group including one or more light emitting elements via a first current path; And a light emitting element driving device.   Furthermore, the light emitting element drive device of Claim 8 which has a frame timing signal generation part which produces | generates the said frame timing signal.   The light emitting element driving device according to claim 8, wherein the first selection circuit selects one of the two systems of frame timing signals based on predetermined allocation data.   The light emitting element driving device according to claim 8, wherein the first selection circuit selects one of the two systems of frame timing signals based on a predetermined connection relationship.   The light emitting element driving device according to claim 8, wherein the first pulse signal generation circuit adjusts a rising timing of the first pulse signal based on the first selection signal.   The light emitting element driving device according to claim 8, wherein the first pulse signal generation circuit adjusts a falling timing of the first pulse signal based on the first selection signal.   The light emitting element driving apparatus according to claim 8, wherein the first pulse signal generation circuit adjusts a pulse width of the first pulse signal based on the input video signal.   The first pulse signal generation circuit is a partial signal of the input video signal, and is based on a level serving as a reference of a partial signal corresponding to a dimming region irradiated by the first light emitting element group. The light emitting element driving device according to claim 14, wherein a pulse width of one pulse signal is adjusted. further,
A second selection circuit that selects the other of the two frame timing signals and generates a second selection signal;
A second pulse signal generation circuit for generating a second pulse signal having a pulse position based on the second selection signal;
A second driving current is generated based on the second pulse signal, and a second light emitting element group including one or more light emitting elements that is different from the first light emitting element group via a second current path. The light emitting element drive device according to claim 8, further comprising: a second current drive circuit capable of supplying to the first current drive circuit.

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