JP2011103029A - Arithmetic processor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To optimize operation timing of a plurality of processes without providing a task controller. <P>SOLUTION: Arithmetic cores 10[1]-10[3] respectively execute the processes A, B, C. The arithmetic core 10[i] executes the process when an operation control signal Tin[i] input to the arithmetic core 10[i] itself becomes active, generates an active or non-active operation control signal Tout[i] based on operation of the process, and outputs it. A signal generation circuit 30 outputs the operation control signal Tout[0] periodically becoming active. For example, each selection circuit is made to operate such that Tout[0] is input to the arithmetic core 10[1] as Tin[1] and that Tout[1] is input to the arithmetic core 10[2] as Tin[2]. Thereby, based on the operation of the process A, the process B can be operated when the need arises. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to an arithmetic processing apparatus that performs various arithmetic processes.

  In recent years, development of arithmetic processing devices capable of simultaneously executing a plurality of processes has been promoted. A process refers to a certain series of operations, and predetermined arithmetic processing is executed by the process. So-called threads are also a type of process. The process is repeatedly executed according to a predetermined operation timing.

  In an actual application, the optimum operation cycle of a process usually varies from process to process. For this reason, if the operation timings of a plurality of processes are all made the same, a process that does not operate at an optimal operation cycle occurs, and the operation efficiency decreases in the process.

  In order to avoid such a decrease in operating efficiency, a task controller is often provided in an arithmetic processing apparatus capable of executing a plurality of processes (see, for example, Patent Document 1). FIG. 5 shows a schematic block diagram of a conventional arithmetic processing unit having a task controller. The arithmetic processing apparatus of FIG. 5 is provided with arithmetic cores 901 and 902 that each execute a process, and a task controller 903 that controls the operation of each arithmetic core. The task controller 903 controls the arithmetic cores 901 and 902 so that the operation cycle of each process executed by the arithmetic cores 901 and 902 is optimized. Depending on the calculation result of the calculation core 901, it may be necessary to operate the calculation core 902. In this case, the task controller 903 determines whether or not the operation of the operation core 902 is necessary based on the output operation data of the operation core 901 and controls the operation of the operation core 902.

JP 2008-242948 A

  In the arithmetic processing unit of FIG. 5, the number of arithmetic cores is two, but there may be many arithmetic cores whose task controller should control the operation, and the circuit configuration of the task controller is generally complicated. If the task controller can be omitted, the configuration of the arithmetic processing device can be simplified and the power consumption can be reduced. Needless to say, simplification of the configuration is useful.

  Therefore, an object of the present invention is to provide an arithmetic processing apparatus that can realize operation timing optimization of a plurality of processes with a simple configuration.

  In an arithmetic processing apparatus in which a plurality of processes that execute arithmetic processing operate according to any of the operation control signals forming the operation control signal group according to the present invention, the first and second operation controls included in the operation control signal group A signal generation circuit for generating a first operation control signal among the signals, wherein the first process among the first and second processes included in the plurality of processes is operated according to the first operation control signal; While the process is executed, the second process executes an arithmetic process according to the second operation control signal, and the second operation control signal is generated based on the operation of the first process. Features.

  According to the arithmetic processing device, when the first process determines that the second process needs to be executed, the second process is performed through the generation of the second operation control signal based on the operation of the first process. The process is executed. If the generation optimization of the first operation control signal by the signal generation circuit and the generation optimization of the second operation control signal by the first process are performed, the operation timing of each process can be optimized. . In order to realize this, the arithmetic processing device does not require a task controller as shown in FIG. In the arithmetic processing unit, the task controller is not required because the process of the task controller is executed by the process. Therefore, the configuration can be simplified and the power consumption can be reduced.

  Further, for example, a selection circuit that selects an operation control signal for each process from the operation control signal group, or generates an operation control signal for each process from a plurality of operation control signals included in the operation control signal group, You may provide further in the said arithmetic processing apparatus.

  Further, for example, setting data is given to the arithmetic processing unit, and the setting data may include data defining the contents of arithmetic processing of each process and data defining the operation of the selection circuit. .

  Alternatively, for example, setting data may be given to the arithmetic processing unit, and the setting data may include data defining the contents of arithmetic processing of each process and data defining the operation of the signal generation circuit. good.

  According to the present invention, it is possible to provide an arithmetic processing apparatus capable of realizing optimization of operation timings of a plurality of processes with a simple configuration.

  The significance or effect of the present invention will become more apparent from the following description of embodiments. However, the following embodiment is merely one embodiment of the present invention, and the meaning of the term of the present invention or each constituent element is not limited to that described in the following embodiment. .

1 is an overall block diagram of an arithmetic processing apparatus according to an embodiment of the present invention. FIG. 2 is an internal block diagram of one arithmetic core shown in FIG. 1. FIG. 3 is an internal configuration diagram of an ALU array circuit included in the arithmetic core of FIG. 2. It is a figure showing the operation timing relationship example of a some process. It is a schematic block diagram of the conventional arithmetic processing unit.

  Hereinafter, an embodiment of the present invention will be described in detail with reference to the drawings. In each of the drawings to be referred to, the same part is denoted by the same reference numeral, and redundant description regarding the same part is omitted in principle. In addition, in this specification, for the sake of simplification of description, a name corresponding to the code or symbol may be omitted or simplified by describing the code or symbol. For example, an operation control signal Tout [0] to be described later may be expressed as a signal Tout [0] or simply Tout [0] (the same applies to Tout [1] and the like).

  FIG. 1 is an overall block diagram of an arithmetic processing apparatus 1 according to an embodiment of the present invention. The arithmetic processing apparatus 1 includes arithmetic cores 10 [1], 10 [2] and 10 [3], selection circuits 20 [1], 20 [2] and 20 [3], a signal generation circuit 30, and a setting unit. 40.

  A process is executed in each of the arithmetic cores 10 [1] to 10 [3]. A process refers to a series of operations, and a predetermined operation process is executed by the process (or the process itself can be interpreted as an operation process). So-called threads are also a type of process. Processes executed by the arithmetic cores 10 [1], 10 [2], and 10 [3] are referred to as a process A, a process B, and a process C, respectively.

  As shown in FIG. 1, operation control signals Tin [1], Tin [2], and Tin [3] are input to the arithmetic cores 10 [1], 10 [2], and 10 [3], respectively. Operation control signals Tout [1], Tout [2], and Tout [3] are output from the cores 10 [1], 10 [2], and 10 [3], respectively. The signal generation circuit 30 outputs an operation control signal Tout [0].

  Each of the operation control signals Tout [0] to Tout [3] and Tin [1] to Tin [3] is a logic signal and has an active or inactive logic value. The operation control signal Tout [0] having an active logic value is referred to as an active operation control signal Tout [0], and the operation control signal Tout [0] having an inactive logic value is referred to as a non-active operation control signal Tout [0]. ]. The same applies to operation control signals other than Tout [0].

  The selection circuit 20 [1] selects any one of the operation control signals Tout [0], Tout [2], and Tout [3], and uses the selected operation control signal as the operation control signal Tin [1]. Output. The selection circuit 20 [2] selects any one of the operation control signals Tout [0], Tout [1], and Tout [3], and uses the selected operation control signal as the operation control signal Tin [2]. Output. The selection circuit 20 [3] selects any one of the operation control signals Tout [0], Tout [1], and Tout [2], and uses the selected operation control signal as the operation control signal Tin [3]. Output.

  The setting unit 40 stores setting data. The setting data includes first setting data that defines the operation of the signal generation circuit 30, second setting data that defines the operation of the selection circuits 20 [1] to 20 [3], and operations of the processes A, B, and C. And third setting data that defines the content of the process. The timing at which the operation control signal Tout [0] becomes active is defined by the first setting data. The second setting data defines which operation control signal is selected at which timing in the selection circuits 20 [1] to 20 [3].

  Therefore, the signal generation circuit 30 generates the operation control signal Tout [0] that becomes active at the timing according to the first setting data and becomes inactive at other timings. The selection circuit 20 [1] selects and selects one of the operation control signals Tout [0], Tout [2], and Tout [3] according to the second setting data at the timing according to the second setting data. The signal is output as the operation control signal Tin [1]. The same applies to the selection circuits 20 [2] and 20 [3].

  The signal generation circuit 30 may be a circuit including a PLL (Phase-locked loop) or the like, or may be a circuit that generates the operation control signal Tout [0] based on a signal input from the outside.

  FIG. 2 is an internal block diagram of the arithmetic core 10 [1]. The arithmetic core 10 [1] includes an ALU array circuit 11 [1], a data RAM 12 [1] and a command RAM 13 formed by a random access memory. [1], a sequencer 14 [1], and an operation control signal generation circuit 15 [1].

  The internal block diagrams of the arithmetic cores 10 [2] and 10 [3] are the same as those in the arithmetic core 10 [1], and thus the illustration is omitted. ALU array circuit 11 [2] having functions equivalent to the ALU array circuit 11 [1], data RAM 12 [1], command RAM 13 [1], sequencer 14 [1] and operation control signal generation circuit 15 [1], data A RAM 12 [2], a command RAM 13 [2], a sequencer 14 [2], and an operation control signal generation circuit 15 [2] are provided in the arithmetic core 10 [2], an ALU array circuit 11 [1], and a data RAM 12 [1]. , ARAM array circuit 11 [3], data RAM 12 [3], command RAM 13 [3], sequencer 14 having the same functions as command RAM 13 [1], sequencer 14 [1] and operation control signal generation circuit 15 [1] [3] and an operation control signal generation circuit 15 [3] are provided in the arithmetic core 10 [3].

  The process A is executed by the ALU array circuit 11 [1] under the command provided from the command RAM 13 [1], and the process B is executed under the command provided from the command RAM 13 [2]. The process C is executed in [2], and the process C is executed in the ALU array circuit 11 [3] under the command provided from the command RAM 13 [3]. The operation cores 10 [1] to 10 [3] are the same except that the specific contents of the processes executed by the operation cores 10 [1] to 10 [3] are different. Hereinafter, the configuration and operation of the arithmetic core 10 [1] will be described, and description of the arithmetic cores 10 [2] and 10 [3] will be omitted. However, common items of the arithmetic cores 10 [1] to 10 [3] may be described using the variable i or j. The variable i or j is an integer of 1 to 3, and i ≠ j.

  The ALU array circuit 11 [1] is a reconfigurable circuit as shown in FIG. 3, and has a function that enables reconfiguration of the logic circuit. The ALU array circuit 11 [1] performs four arithmetic operations, logical operations, and the like, a plurality of ALUs (Arithmetic and Logic Units) arranged in multiple stages, and a holding circuit (D type) that holds output data of each ALU Flip-flop and the like) and a connection unit for connecting the output data of the preceding ALU to the succeeding ALU by connecting the preceding ALU and the succeeding ALU. The contents of the calculation executed in each ALU and the connection relationship in the connection unit can be changed by changing the third setting data.

  The data RAM 12 [1] stores the output operation data of the ALU array circuit 11 [1] obtained by the operation of the ALU array circuit 11 [1], and the data RAM 12 [1] stores the data stored in the data RAM 12 [1]. 11 [1]. The recording data in the data RAM 12 [i] in the ALU array circuit 11 [i] is transferred to the data in the other ALU array circuit 11 [j] via a data sharing unit (not shown) provided in the arithmetic processing unit 1. The data can be transferred to the RAM 12 [j].

  Therefore, for example, the output operation data of the ALU array circuit 11 [2] obtained by the operation of the ALU array circuit 11 [2] is transferred to the ALU array circuit 11 [1] via the data RAMs 12 [2] and 12 [1]. The ALU array circuit 11 [1] can execute the process A using the output operation data of the ALU array circuit 11 [2]. Conversely, the output operation data of the ALU array circuit 11 [1] obtained by the operation of the ALU array circuit 11 [1] is transferred to the ALU array circuit 11 [2] via the data RAMs 12 [1] and 12 [2]. The ALU array circuit 11 [2] can execute the process B using the output operation data of the ALU array circuit 11 [1].

  The command RAM 13 [1] stores command data representing a command to be provided to the ALU array circuit 11 [1]. In the arithmetic core 10 [1], the command is an instruction for instructing the ALU array circuit 11 [1] to execute predetermined arithmetic processing. The user can execute desired arithmetic processing in each arithmetic core 10 [i] by changing the command data. The command data can be changed by changing the third setting data. The user can store a command string representing the program in each command RAM 13 [i] by giving a program described using a programming language such as C language to the setting unit 40 as the third setting data. Note that the user here is, for example, a developer of an electrical product manufacturer who is a user of the arithmetic processing device 1.

  The sequencer 14 [1] sends address data specifying the address of the command RAM 13 [1] to the command RAM 13 [1] in accordance with the operation control signal Tin [1] and the sequencer control data output from the ALU array circuit 11 [1]. Output. When the address data is given to the command RAM 13 [1], the command RAM 13 [1] outputs the command data stored at the address specified by the address data to the ALU array circuit 11 [1].

  The sequencer control data is for the ALU array circuit 11 [1] itself to control the address data to be supplied to the command RAM 13 [1] based on the calculation result of the ALU array circuit 11 [1]. For example, when a branch process for selecting either “Yes” or “No” occurs in the arithmetic processing of the circuit 11 [1], “Yes” is selected according to the arithmetic result of the circuit 11 [1]. Then, the circuit 11 [1] outputs the first sequencer control data corresponding to the first subroutine. On the other hand, when “No” is selected according to the calculation result of the circuit 11 [1], the circuit 11 [1]. Outputs second sequencer control data corresponding to the second subroutine. When given the first sequencer control data, the sequencer 14 [1] supplies the start address of the program (command) of the first subroutine to the command RAM 13 [1] as address data, while being given the second sequencer control data. Then, the start address of the program (command) of the second subroutine is supplied to the command RAM 13 [1] as address data. As a result, after the output of the first sequencer control data, the arithmetic processing of the first subroutine is immediately executed by the circuit 11 [1], and after the output of the second sequencer control data, the arithmetic processing of the second subroutine is promptly performed. Is executed by the circuit 11 [1].

  The operation control signal generation circuit 15 [1] generates the operation control signal Tout [1] based on the operation control signal Tin [1] and the operation control data output from the ALU array circuit 11 [1], and the generated signal Tout [1] is output. In the process A, the ALU array circuit 11 [1] determines whether or not to activate the operation control signal Tout [1] to be output from its own operation core 10 [1] in addition to a desired operation. Then, the operation control data according to the determined content is output to the circuit 15 [1]. The circuit 15 [1] holds the given operation control data, and outputs the value of the operation control data held when Tin [1] becomes active as the operation control signal Tout [1]. The value of the operation control data when the operation control signal Tout [1] is determined to be active in the process A is active (for example, 1), otherwise, the value is non-active (for example, 0). .

  Each arithmetic core 10 [i] starts executing the process at the timing when the operation control signal Tin [i] input to itself becomes active. Specifically, when the operation control signal Tin [1] given to the sequencer 14 [1] transitions from non-active to active, the sequencer 14 [1] corresponds to the command RAM 13 [1] corresponding to the process A start processing. Thus, the execution of the process A is started. The same applies to the arithmetic cores 10 [2] and 10 [3]. The transition from non-active to active in the operation control signal Tin [i] occurs periodically or non-periodically, so that the corresponding process is repeatedly executed in each arithmetic core 10 [i]. As is clear from the above description illustrating the first and second subroutines, the operation actually executed in the process A may differ from time to time depending on the branch processing in the process A (other processes). The same applies to.

  The setting data including the first, second, and third setting data described above may be provided from the outside, and the user can freely design the setting data according to the contents of the application to be executed by the arithmetic processing device 1. it can. In the arithmetic processing unit 1, the user can freely set each operation control signal through the design of the setting data, so that it can cope with various applications.

  With reference to FIG. 4, an example of operation timing of processes A and B will be described. The process A operates in each section based on the operation timing X that is discretely sequentially visited, and the process B operates in each section that is based on the operation timing Y that is discretely sequentially visited. In FIG. 4, each of the eight arrows described on the upper side corresponds to the operation timing X, and each of the four arrows described on the lower side corresponds to the operation timing Y.

Assume that the reference timings T ₁ , T ₂ , T ₃ , T ₄ , T ₅ , T ₆ , T ₇ , T ₈ ... Visit in this order as time elapses. That is, the reference timing T _{k + 1} is a timing that comes after the reference timing T _k (k is a natural number). It is assumed that the time length between adjacent reference timings is constant (however, it may not be constant).

  In the operation example of FIG. 4, the arithmetic core 10 [1] executing the process A operates according to the operation control signal Tout [0] (in other words, the process A executes arithmetic processing according to the operation control signal Tout [0]. ), The arithmetic core 10 [2] executing the process B operates according to the operation control signal Tout [1] generated by the arithmetic core 10 [1] (in other words, the process B is based on the operation of the process A). The arithmetic processing is executed according to the generated operation control signal Tout [1]). In order to realize this, the selection circuit 20 [1] always selects Tout [0] as Tin [1], or at least at the operation timing X, selects Tout [0] as Tin [1]. Similarly, the selection circuit 20 [2] always selects Tout [1] as Tin [2], or selects Tout [1] as Tin [2] at least at the operation timing Y. Therefore, when realizing the operation example of FIG. 4, the selection circuits 20 [1] and 20 [2] can be omitted from the arithmetic processing unit 1 (in this case, Tout [0] is directly set to Tin [ 1] to the arithmetic core 10 [1] and Tout [1] may be directly input to the arithmetic core 10 [2] as Tin [2].

  The selection circuit may be omitted from the arithmetic processing device 1 depending on the content of the operation to be realized by the arithmetic processing device 1 without being limited to the operation example of FIG. For example, “whether the operation control signal Tin [i] input to the arithmetic core 10 [i] is any of the operation control signals Tout [0] to Tout [3] is fixed (that is, Tout [0] To which Tout [3] is input to the arithmetic core 10 [i] as Tin [i] is determined in advance, and the determination is invariant with the passage of time). If so, the selection circuit 20 [i] can be omitted from the arithmetic processing unit 1. The operation example of FIG. 4 is an example of an operation that satisfies this condition.

The k-th operation timing X coincides with the reference timing T _k . The arithmetic core 10 [1] executes the k-th process A in a section starting from the kth operation timing X and having a predetermined time length. In order to achieve this, the signal generating circuit 30, the Tout [0] and active at the reference timing T _k, the Tout [0] nonactive in timing other than the reference timing T _k.

The k-th process A is particularly expressed as process A [k]. The operation time of one process A is equal to or shorter than the time length between adjacent reference timings T _k and T _{k + 1} . Thus, for example, in the first operation timing X that matches the reference timing T ₁ process A [1] is started running, the process A [1] is completed before the reference timing T _2. Similarly, for example, the process A [2] starts to be executed at the second operation timing X that coincides with the reference timing T _2, and the process A [2] ends by the reference timing T ₃ . The same applies to the process A [3] and the like.

In the operation example of FIG. 4, after one process B is executed for two processes A, one process B is executed for three processes A, and then One process B is executed for two processes A executed. Thereafter, processes A and B are repeatedly executed at the same execution ratio. Specifically, the first, second, third and fourth operation timings Y are reference timings T ₁ , T ₃ , T ₆ and T ₈ , respectively.

The arithmetic core 10 [2] executes the k-th process B in a section starting from the kth operation timing Y and having a predetermined time length. The k-th process B is particularly expressed as process B [k]. The operation time of one process B is twice or less than twice the time length between adjacent reference timings T _k and T _{k + 1} . However, the operation time of the process B [2] may be longer than twice the time length between the reference timings T _k and T _{k + 1} (however, it is 3 times or less).

Accordingly, in the first operation timing Y which coincides with the reference timing T ₁ process B [1] is started running, the process B [1] is completed before the reference timing T _3. In the reference timing T ₃ and the second operation timing Y matching process B [2] is started running, the process B [2] is completed before the reference timing T _6. Process B [3] is started performed in the third operation timing Y which coincides with the reference timing T _6, the process B [3] is completed before the reference timing T _8. The same applies to process B after process B [3].

  Now, “the operation control signal Tout [1] is activated only once for the second execution of the process A, and then the operation control signal Tout [1] is activated only once for the third execution of the process A. Then, a series of operations “activate the operation control signal Tout [1] only once for the second execution of the process A” will be referred to as an operation α for convenience. The operation α is realized by the program of the process A, and the arithmetic processing according to the program is executed by the ALU array circuit 11 [1] (a command sequence representing the program of the process A is stored in the command RAM 13 [1]. )

The program for the process A may be formed so that the operation α is realized regardless of the calculation result of the process A. In this case, ALU array circuit 11 [1], regardless of the operation result of the process A, the operation control data having a value of active reference timing T ₃ earlier in the process A [2] to the circuit 15 [1] The operation control data having an active value before the reference timing T ₆ in the process A [5] is output to the circuit 15 [1], and is active before the reference timing T ₈ in the process A [7]. Is output to the circuit 15 [1]. When operation control data having an active value before the reference timing T _{3 in the} process A [2] is output to the circuit 15 [1], the active operation control signal Tout [1] is output to the circuit at the reference timing T ₃ . 15 [1], process B [2] is started as a result. The operation related to the reference timing other than the reference timing T ₃ is the same.

Alternatively, the operation timing Y may be determined according to the calculation result of the process A. However, in this case, there is a possibility that the operation timing Y differs from that shown in FIG. That is, the operation α itself may be realized according to the calculation result of the process A, or an operation different from the operation α may be realized (for example, 3 according to the calculation result of the process A [4]). th operation timing Y is sometimes become T _5).

  Whether the operation timing Y is determined regardless of the calculation result of the process A or the operation timing Y is determined according to the calculation result of the process A, the operation timing Y is determined based on the operation of the process A. In other words, there is no change (in other words, the active operation control signals Tout [1] and Tin [2] are generated based on the operation of the process A). The calculation result of the process A includes the output calculation data of the ALU array circuit 11 [1] obtained by the calculation of the ALU array circuit 11 [1]. Similarly, the operation result of process B includes output operation data of the ALU array circuit 11 [2] obtained by the operation of the ALU array circuit 11 [2]. The same applies to process C.

  The process B at the point of interest can be performed using the calculation result of the process A executed immediately before the point of interest. That is, for example, the operation core 10 [2] can execute the process B [2] using the operation result of the process A [2] and use the operation result of the process A [5] to process B [3]. And the setting data can be determined so that such an operation is realized. The process of converting the sampling rate of certain data from a relatively high to a relatively low is generally referred to as downsampling, but it corresponds to process A before conversion and process B after conversion. When considered, processing such as downsampling is realized by the above-described operation. It is also possible to execute the process B using the calculation results of the process A for a plurality of past times. That is, for example, the operation core 10 [2] may execute the process B [3] using the operation results of the processes A [4] and A [5].

  Conversely, the process A at the point of interest can be performed using the calculation result of the process B executed immediately before the point of interest. That is, for example, the operation core 10 [1] can execute the processes A [3], A [4], and A [5] using the operation result of the process B [1] and the process B [2]. Processes A [6] and A [7] can be executed using the result of the calculation, and setting data can be determined so that such an operation is realized. The process of converting the sampling rate of certain data from relatively low to relatively high is generally called up-sampling, but it corresponds to process B before conversion and process A after conversion. When considered, processing such as upsampling is realized by the above-described operation. Note that it is also possible to execute the process A using the calculation results of the process B for a plurality of past times. That is, for example, the computation core 10 [1] may execute the processes A [6] and A [7] using the computation results of the processes B [1] and B [2].

  Although the operation timing of the process C is not shown in FIG. 4, the process C can be operated in each section based on the operation timing Z that is discretely sequentially visited. The operation timing Z may be made to coincide with the operation timing X by supplying Tout [0] as Tin [3] to the arithmetic core 10 [3] via the selection circuit 20 [3], or may be selected. The operation timing Z may coincide with the operation timing Y by supplying Tout [1] as Tin [3] to the arithmetic core 10 [3] via the circuit 20 [3]. Alternatively, the operation timing Z may be made different from the operation timings X and Y by supplying Tout [2] as Tin [3] to the arithmetic core 10 [3] via the selection circuit 20 [3].

In the operation example of FIG. 4, each operation timing Y coincides with any operation timing X. That is, the respective timings T ₁ , T ₃ , T ₆ ... Forming the operation timing Y coincide with some of the timings T ₁ , T ₃ , T ₆ . . However, the former timing and the latter timing may be slightly shifted back and forth. That is, for example, the first operation timing Y at which the process B [1] is started may be (T ₁ + ΔT), and the second operation timing Y at which the process B [2] is started is ( T ₃ + ΔT) (ΔT is a positive or negative value in units of time). The same applies to the third and subsequent operation timings Y.

If an operation control signal is not generated by the arithmetic core, the operation control signal Tout [0] generated by the signal generation circuit 30 is input to the arithmetic core 10 [2] as Tin [2]. In this case, the process B [1] is executed by being divided into two sections (ie, a section between T ₁ and T ₂ and a section between T ₂ and T ₃ ). Processing redundancy occurs and processing efficiency decreases. For example, in order to complete the overall calculation of the process B [1], it is necessary to reflect the calculation data in the section between T ₁ and T _{2 in} the calculation in the section between T ₂ and T _3. In order to realize the above, it is necessary to temporarily store the operation data in the data RAM 12 [2] in the former section and to read out the stored operation data in the latter section (the processing efficiency is as much as this process is necessary). Decreases). Furthermore, due to the occurrence of redundancy, the process B [1] cannot be completed in the interval between T ₁ and T _3, and a part of the process B [1] is changed to the interval between T ₃ and T _4. In some cases, it must be used and executed.

  On the other hand, in the arithmetic processing apparatus 1 according to the present embodiment, in addition to the operation control signal Tout [0] from the signal generation circuit 30, the operation control signal Tout [i] from the arithmetic core 10 [i] exists, and Tout [I] is also used to control the operation of each process. For this reason, occurrence of redundancy as described above can be avoided. As a result, it is possible to efficiently process the processes executed by each arithmetic core and reduce the processing time. In the broadcast wave transmission / reception process, many processes involving down-sampling and up-sampling are observed. However, according to the arithmetic processing unit 1, the process involving down-sampling and up-sampling is efficiently performed through the operation shown in FIG. Can be processed automatically. Furthermore, according to the arithmetic processing device 1, since a complicated control circuit such as a task controller that determines the operation of a certain arithmetic core and determines the operation of another arithmetic core is unnecessary, circuit miniaturization and low consumption are achieved. Electricity becomes possible.

<< Deformation, etc. >>
The specific numerical values shown in the above description are merely examples, and as a matter of course, they can be changed to various numerical values. As modifications or annotations of the above-described embodiment, notes 1 to 4 are described below. The contents described in each comment can be arbitrarily combined as long as there is no contradiction.

[Note 1]
In the above-described embodiment, one process is executed by one arithmetic core, but a plurality of processes may be executed by one arithmetic core. In this case, each process included in the plurality of processes may be operated according to an operation control signal generated by the operation of a process other than the process, and the selection operation of the selection circuit may be set so as to realize this. .

[Note 2]
Each selection circuit in the above description selects one of a plurality of input operation control signals based on the second setting data defining the operation of each selection circuit. It is also possible to perform a logical operation (calculation of logical sum or logical product) of the operation control signal and output the result. It is possible to define in the second setting data what kind of logical operation is performed in each selection circuit. For example, the selection circuit 20 [1] performs a logical operation of Tout [0], Tout [2], and Tout [3], and calculates the result of the logical operation as Tin [1] from the selection circuit 20 [1]. You may make it give to core 10 [1]. Similarly, for example, in the selection circuit 20 [2], logical operations of Tout [0], Tout [1], and Tout [3] are performed, and the result of the logical operation is defined as Tin [2], and the selection circuit 20 [2]. To the arithmetic core 10 [2]. The same applies to the selection circuit 20 [3]. More specifically, for example, the selection circuit 20 [2] calculates the logical product of Tout [0], Tout [1], and Tout [3], and selects the Tin [2] having the logical product value. 20 [2] may be given to the arithmetic core 10 [2]. For example, active can be associated with a logical value “1” and non-active can be associated with a logical value “0”.

[Note 3]
In the above-described embodiment, the number of arithmetic cores provided in the arithmetic processing device 1 is three. However, the number of arithmetic cores provided in the arithmetic processing device 1 may be any number as long as it is two or more. The number of processes executed in the arithmetic processing device 1 and the number of selection circuits provided in the arithmetic processing device 1 increase / decrease according to the increase / decrease in the number of arithmetic cores.

[Note 4]
The arithmetic processing device 1 in FIG. 1 can be configured by hardware or a combination of hardware and software. When the arithmetic processing unit 1 is configured using software, a block diagram of a part realized by software represents a functional block diagram of the part. A function realized using software may be described as a program, and the function may be realized by executing the program on a program execution device (for example, a computer).

DESCRIPTION OF SYMBOLS 1 Arithmetic processor 10 [1] -10 [3] Arithmetic core 20 [1] -20 [3] Selection circuit 30 Signal generation circuit 40 Setting part

Claims (4)

In an arithmetic processing device in which a plurality of processes that perform arithmetic processing according to any of the operation control signals forming the operation control signal group operate,
A signal generation circuit for generating a first operation control signal among the first and second operation control signals included in the operation control signal group;
Of the first and second processes included in the plurality of processes, the first process performs arithmetic processing in accordance with the first operation control signal, while the second process performs the second operation control signal. According to
The arithmetic processing unit, wherein the second operation control signal is generated based on an operation of the first process. A selection circuit for selecting an operation control signal for each process from the operation control signal group, or for generating an operation control signal for each process from a plurality of operation control signals included in the operation control signal group; The arithmetic processing apparatus according to claim 1. Setting data is given to the arithmetic processing unit,
The arithmetic processing apparatus according to claim 2, wherein the setting data includes data defining a content of arithmetic processing of each process and data defining an operation of the selection circuit. Setting data is given to the arithmetic processing unit,
The said setting data include the data which prescribes | regulates the content of the arithmetic processing of each process, and the data which prescribes | regulates the operation | movement of the said signal generation circuit, The Claim 1 characterized by the above-mentioned. Arithmetic processing unit.

Images