JP2011101113A - Mac circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an MAC (media access control) circuit for performing periodical self-diagnosis and maintaining integrity, without abandoning reception data from other nodes in any cases, when being online. <P>SOLUTION: The MAC circuit is interposed between the PHY of a physical layer and a CPU to control the access of a communication medium, and includes a transmission buffer memory 2; a TX_WRC 1 for writing transmission data in the transmission buffer memory; a TX_RDC 3 for transmitting a MAC frame to the physical layer; a reception buffer memory 8; an RX_WRC 6 for adding an FCS value to reception data and writing them to the reception buffer memory; an RX_RDC 9 for outputting read reception data to the CPU; and a CHECK circuit 12 for determining first timing for performing self-diagnosis. The TX_RDC 3 reads the reception data output by the RX_RDC 9 according to the first timing, and the CHECK circuit 12 performs self-diagnosis, by comparing the FCS value calculated by the RX_WRC 6 and the TX_RDC 3. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a MAC circuit that generates a MAC (MEDIA ACCESS CONTROL) frame for transmitting data, detects an error in received data, and the like.

  A MAC circuit of Ethernet (registered trademark) generates a MAC frame for transmitting data and checks an error of received data in Layer 2 (data link layer) of an OSI (Open Systems Interconnection) reference model. . These standards are defined by IEEE 802.3.

  FIG. 4 is a functional block diagram showing a configuration of a general MAC circuit. First, the configuration of the MAC circuit will be described with reference to FIG. As shown in FIG. 4, the MAC circuit includes TX_WRC1, transmission buffer memory 2, TX_RDC3, FCS circuit 4, loopback circuit 5, RX_WRC6, FCS circuit 7, reception buffer memory 8, and RX_RDC9. The MAC circuit generally includes a buffer memory (transmission buffer memory 2 and reception buffer memory 8) because the operation timing of the CPU is different from the transmission / reception timing to the PHY. The PHY is configured by an IC chip, for example, and performs signal processing in the layer 1 (physical layer).

  First, data transmission from the CPU will be described. FIG. 5 is a diagram showing an operation at the time of data transmission of a general MAC circuit, and a data flow is indicated by a thick line arrow. First, the CPU transfers the transmission data 1a to the MAC circuit. Next, TX_WRC1 performs write control on the transmission side, and writes the transmission data transferred by the CPU into the transmission buffer memory 2.

  When the writing is completed, the TX_RDC 3 that performs reading control on the transmission side reads the transmission data written in the transmission buffer memory 2. At that time, an FCS (Frame Check Sequence) circuit 4 performs an FCS calculation and creates a MAC frame to which FCS data is added. The created MAC frame data 4a is transmitted to the PHY by TX_RDC3.

  Next, data reception from the PHY will be described. FIG. 6 is a diagram showing the operation of a general MAC circuit when receiving data, and the flow of data is indicated by thick arrows. The reception data 5b from the PHY passes through the loopback circuit 5 and is transferred to the RX_WRC 6 that performs write control on the reception side. Here, the loopback circuit 5 selects whether to receive the data 5b from the PHY or the data 5c from the transmission side based on the switching command 5a from the CPU. Is selecting to receive the data 5b from the PHY.

  The RX_WRC 6 writes the data transferred from the PHY into the reception buffer memory 8. At that time, the FCS circuit 7 performs an FCS calculation and confirms that there is no FCS error. Thereafter, the RX_RDC 9 that performs read control on the reception side reads the data written in the reception buffer memory 8 and transfers the read data 9a to the CPU.

  Next, a conventional self-diagnosis method in the above-described MAC circuit will be described. FIG. 7 is a diagram showing an operation at the time of self-diagnosis of a conventional MAC circuit, and a data flow is indicated by a thick arrow. First, the CPU outputs a loopback command 5a to the loopback circuit 5 to perform self-diagnosis at the initial stage, and transfers data to the MAC circuit. The loopback circuit 5 performs selection to receive data from the transmission side (that is, data output by the TX_RDC3) based on the input loopback command 5a.

  On the other hand, TX_WRC1 writes the data transferred by the CPU to the transmission buffer memory 2. When some data is accumulated in the transmission buffer memory 2, the TX_RDC 3 reads data from the transmission buffer memory 2, adds FCS data to the FCS circuit 4, and transmits the generated data.

  The transmitted data is PHY-transferred and also transferred to the receiving side circuit (that is, RX_WRC6) through the loopback circuit 5. The RX_WRC 6 writes the received data into the reception buffer memory 8. At that time, the FCS circuit 7 performs an FCS error check. Thereafter, the RX_RDC 9 reads the data written in the reception buffer memory 8 and transfers it to the CPU. The CPU confirms that the data transmitted by itself matches the received data, and determines that the circuit is operating normally when the data matches. The CPU cancels the loopback command 5a after confirming the data. As a result, the loopback circuit 5 selects to receive the data 5b from the PHY, and switches the circuit so that the data can be received from the PHY side.

  Patent Document 1 describes an Ethernet (registered trademark) switch that can analyze port traffic from a remote environment and facilitate network diagnosis. The Ethernet (registered trademark) switch includes a plurality of ports, a switching controller that transfers a frame received from a predetermined port among the plurality of ports to another designated port, a control unit, and a storage unit. I have. The control means has a function of setting a frame condition to be captured to the switching controller in accordance with a capture start request received via the network. The switching controller also has a function of copying a frame that matches a set condition as capture data to the storage means.

  The control means may have a function of reading the capture data stored in the storage means in accordance with the capture acquisition request received via the network and transferring it to the other party that issued the capture acquisition request via the network.

  Further, the control means is configured to delete the capture data stored in the storage means according to the request received via the network, to transfer the list of capture data stored in the storage means via the network, It is preferable to provide at least one of the functions for renaming the capture data file name stored in the means.

JP 2008-258846 A

  However, the conventional MAC circuit described with reference to FIGS. 4 to 7 has a problem that the circuit diagnosis cannot be performed online during circuit operation because the self-diagnosis is performed only once at the initial stage. . In other words, if the conventional MAC circuit performs self-diagnosis at the time of online, it is difficult to perform periodic diagnosis in the online state because there is a possibility that received data from other nodes may be discarded during the diagnosis. It becomes a problem in maintaining.

  The Ethernet (registered trademark) switch described in Patent Document 1 enables analysis of port traffic from a remote environment. However, it does not perform self-diagnosis, but has a periodic self-diagnosis function while online. It is not a solution for coexisting with the function of receiving data from other nodes.

  The present invention solves the above-mentioned problems of the prior art, and a MAC circuit that maintains periodicity by performing periodic self-diagnosis without discarding received data from other nodes in any case when online. It is an issue to provide.

  In order to solve the above problems, a MAC circuit according to the present invention is a MAC circuit that is interposed between a physical layer and a central processing unit and controls access to a communication medium, and is transmitted by the central processing unit. A transmission buffer memory for temporarily storing transmission data; a first write control unit for writing transmission data transmitted by the central processing unit into the transmission buffer memory; and transmission data written in the transmission buffer memory. A MAC frame generation unit that reads and generates a MAC frame including an FCS value based on the read transmission data and transmits the MAC frame to the physical layer, and a reception buffer for temporarily storing reception data received from the physical layer The presence of an FCS error is confirmed based on memory and received data received from the physical layer, and the reception A second write control unit that adds the calculated FCS value to the data and writes the received data to the reception buffer memory, and reads the received data written to the reception buffer memory, and outputs the read received data to the central processing unit A read control unit; a self-diagnosis control unit that determines a first timing for performing self-diagnosis using received data received from the physical layer; and the MAC according to the first timing determined by the self-diagnosis control unit A blocking unit that blocks transmission of the MAC frame by the frame generation unit; and a reception unit that transfers the reception data output by the read control unit to the MAC frame generation unit according to a first timing determined by the self-diagnosis control unit. 1 transfer unit, and the MAC frame generation unit is a first determined by the self-diagnosis control unit According to the timing, the reception data output by the read control unit instead of the transmission buffer memory is read through the first transfer unit, and the FCS value is calculated based on the read reception data, and the self-diagnosis is performed. The control unit diagnoses whether there is an abnormality in its own circuit by comparing the FCS value calculated by the second write control unit and the FCS value calculated by the MAC frame generation unit. .

  According to the present invention, it is possible to provide a MAC circuit that performs periodic self-diagnosis and maintains soundness without discarding received data from other nodes in any case when online.

It is a figure which shows the structure of the MAC circuit of the form of Example 1 of this invention. It is a figure which shows the operation | movement at the time of performing a self-diagnosis using the received data of the MAC circuit of the form of Example 1 of this invention. It is a figure which shows the operation | movement at the time of performing a self-diagnosis using the transmission data of the MAC circuit of the form of Example 2 of this invention. It is a functional block diagram which shows the structure of the conventional MAC circuit. It is a figure which shows the operation | movement at the time of the data transmission of the conventional MAC circuit. It is a figure which shows the operation | movement at the time of the data reception of the conventional MAC circuit. It is a figure which shows the operation | movement at the time of the self-diagnosis of the conventional MAC circuit.

  Hereinafter, embodiments of the MAC circuit of the present invention will be described in detail with reference to the drawings.

  1 is a diagram illustrating a configuration of a MAC circuit according to a first embodiment of the present invention. The configuration of the MAC circuit will be described with reference to FIG. The MAC circuit of this embodiment is a circuit that controls access to a communication medium interposed between a physical layer and a central processing unit (CPU). As shown in FIG. 1, TX_WRC1, transmission buffer memory 2, TX_RDC3 , FCS circuit 4, loopback circuit 5, RX_WRC6, FCS circuit 7, reception buffer memory 8, RX_RDC9, counters 10, 11, CHECK circuit 12, buffer control 13, SEL14, counter 15, buffer control 16, SEL17, and SEL18 Composed.

  That is, the difference from the conventional MAC circuit described with reference to FIGS. 4 to 7 is that it includes counters 10 and 11, a CHECK circuit 12, a buffer control 13, a SEL 14, a counter 15, a buffer control 16, a SEL 17 and a SEL 18. It is.

  TX_WRC1 corresponds to the first write control unit of the present invention, and writes the transmission data transmitted by the CPU (central processing unit) to the transmission buffer memory 2. Here, the transmission buffer memory 2 is a memory for temporarily storing transmission data transmitted by the CPU.

  The counter 15 corresponds to the third counter of the present invention, counts the number of times TX_WRC1 has received transmission data transmitted by the CPU, and generates a third set count signal when the count reaches a predetermined number To do.

  The buffer control 16 monitors the free capacity of the transmission buffer memory 2, and notifies the CPU when the memory is about to overflow. The CPU takes measures such as limiting the amount of transmission data in accordance with the warning from the buffer control 16.

  The SEL 17 selects either the output of the transmission buffer memory 2 or the output of the RX_RDC 9 described later and outputs it to the TX_RDC 3 in accordance with a command from the CHECK circuit 12 described later.

  The TX_RDC 3 and the FCS circuit 4 correspond to the MAC frame generation unit of the present invention. The TX_RDC 3 reads the transmission data written in the transmission buffer memory 2, and the FCS circuit 4 performs the FCS calculation based on the read transmission data. , TX_RDC 3 generates a MAC frame including the FCS value and transmits it to the physical layer PHY.

  The loopback circuit 5 selects either the MAC frame that is the output of the SEL 18 or the received data received from the physical layer PHY in accordance with a command from the CPU, and outputs the selected data to the RX_WRC 6.

  The RX_WRC 6 and the FCS circuit 7 correspond to the second write control unit of the present invention. The FCS circuit 7 confirms the presence or absence of an FCS error based on the received data received from the physical layer, and the FCS value calculated for the received data And the RX_WRC 6 writes in the reception buffer memory 8. Here, the reception buffer memory 8 is a memory for temporarily storing reception data received from the physical layer. It is assumed that the above-described transmission buffer memory 2 and reception buffer memory 8 use a FIFO buffer memory in this embodiment.

  The counter 10 corresponds to the first counter of the present invention, and counts the number of times the second write control unit (RX_WRC6) has received the received data from the physical layer, and the count reaches a predetermined number (for example, 100 times). In this case, the first setting count signal is generated.

  The counter 11 corresponds to the second counter of the present invention, and when the first set count signal is generated by the counter 10, the second write control unit (RX_WRC6) during the self-diagnosis has received the received data from the physical layer. The number of times is counted, and a second set count signal is generated when the count number reaches a predetermined number (for example, 10 times).

  The buffer control 13 corresponds to the buffer control unit of the present invention, monitors the free capacity of the reception buffer memory 8, and generates a memory capacity warning signal when the storage amount in the reception buffer memory 8 exceeds a predetermined value.

  The SEL 14 selects either the output of the reception buffer memory 8 or the output of the TX_RDC 3 and outputs it to the RX_RDC 9 in accordance with a command from the CHECK circuit 12 described later.

  The RX_RDC 9 corresponds to the read control unit of the present invention, reads the reception data written in the reception buffer memory 8 through the SEL 14 and outputs the read reception data to the CPU.

  The CHECK circuit 12 corresponds to the self-diagnosis control unit of the present invention, and determines the first timing for performing self-diagnosis using received data received from the physical layer. Specifically, the CHECK circuit 12 determines the first timing based on the first set count signal generated by the counter 10.

  The SEL 18 corresponds to the blocking unit of the present invention, and blocks transmission of the MAC frame by the TX_RDC 3 according to the first timing determined by the CHECK circuit 12.

  The SEL 17 described above corresponds to the first transfer unit of the present invention, and transfers the reception data output by the RX_RDC 9 to the TX_RDC 3 according to the first timing determined by the CHECK circuit 12.

  Next, the operation of the present embodiment configured as described above will be described. FIG. 2 is a diagram illustrating an operation when performing self-diagnosis using received data of the MAC circuit of the present embodiment. In this case, the MAC circuit according to the present embodiment mainly performs self-diagnosis on portions such as RX_WRC6, RX_RDC9, and TX_RDC3 in the circuit to determine whether normal operation is performed.

  First, the counter 10 counts the number of times the RX_WRC 6 has received the reception data 5b from the physical layer PHY. The counter 10 may be configured to count up when the RX_WRC 6 receives the loop back data 5c from the transmission circuit via the loop back circuit 5.

  The counter 10 generates a first setting count signal and outputs it to the CHECK circuit 12 when the count number reaches a predetermined number of times (for example, 100 times). The CHECK circuit 12 determines the first timing based on the first set count signal generated by the counter 10. That is, the MAC circuit of this embodiment performs self-diagnosis using received data once (or a plurality of times) in accordance with the first timing determined by the CHECK circuit 12.

  When the first setting count signal is generated by the counter 10, the CHECK circuit 12 outputs a command signal for stopping reading of transmission data from the transmission buffer memory 2 by the TX_RDC 3 to the CPU. When receiving the command signal, the CPU gives a command to the TX_RDC 3 to stop reading the transmission data from the transmission buffer memory 2 by the TX_RDC 3 and start reading the reception data from the RX_RDC 9.

  Further, the SEL 17 transfers the reception data 13b output from the RX_RDC 9 to the TX_RDC 3 according to the first timing determined by the CHECK circuit 12.

  That is, the TX_RDC 3 and the FCS circuit 4 serving as the MAC frame generation unit read out the reception data 13b output from the RX_RDC 9 instead of the transmission buffer memory 2 via the SEL 17 according to the first timing determined by the CHECK circuit 12. The FCS circuit 4 calculates the FCS value based on the read received data.

  Note that the SEL 18 blocks transmission of the MAC frame by the TX_RDC 3 according to the first timing determined by the CHECK circuit 12.

  The RX_WRC 6 writes the received data in the receive buffer memory 8, causes the FCS circuit 7 to calculate the FCS value, checks the FCS value added to the received data sent from the PHY, and checks whether there is an FCS error To do. When an FCS error occurs, the RX_WRC 6 writes the received data to the receive buffer memory 8, but discards the received data including the FCS error by overwriting with the next data transmitted from the PHY. To do. The RX_WRC 6 writes not only the reception data but also the FCS value calculated by the FCS circuit 7 when writing the reception data to the reception buffer memory 8.

  The RX_RDC 9 reads the received data and the FCS value from the receive buffer memory 8 and outputs the read received data. The output received data is transferred to the CPU and also transferred to the TX_RDC 3 via the SEL 17 as described above. Further, the RX_RDC 9 transfers the read FCS value 13 c to the CHECK circuit 12. That is, the FCS value calculated by the FCS circuit 7 of the second write control unit is transferred to the CHECK circuit 12 by the RX_RDC 9.

  On the other hand, the FCS circuit 4 of the MAC frame generation unit recalculates the FCS value based on the received data transferred to the TX_RDC 3 and transfers the FCS value as the calculation result to the CHECK circuit 12.

  The CHECK circuit 12 compares the FCS value calculated by the second write control unit (FCS circuit 7) with the FCS value calculated by the MAC frame generation unit (FCS circuit 4), thereby detecting an abnormality in the MAC circuit. Diagnose the presence or absence of. Specifically, the CHECK circuit 12 determines that RX_WRC6, RX_RDC9, and TX_RDC3 are operating normally when both FCS values match. On the other hand, if the FCS values do not match, the CHECK circuit 12 notifies the CPU of an error signal.

  If there is an FCS error in the received data received by the RX_WRC 6, the RX_WRC 6 once writes the received data in the receive buffer memory 8 as described above, but the received data received thereafter is received in the receive buffer memory 8 By overwriting, the received data having the FCS error is discarded.

  As described above, when data is overwritten in the reception buffer memory 8 and reception data having an FCS error is discarded, the MAC circuit of the present invention cannot perform self-diagnosis using the reception data. In addition, if an FCS error occurs in all received data transmitted during self-diagnosis, the receiving circuit may stop.

  Therefore, the counter 11 counts the number of times the second write control unit (RX_WRC6) receives the received data from the physical layer during the self-diagnosis when the first setting count signal is generated by the counter 10, and the count number When the number reaches a predetermined number (for example, 10 times), the second set count signal is generated. In this way, the counter 11 counts the number of received data during self-diagnosis, and if the self-diagnosis cannot be completed within the specified value, generates a second setting count signal for stopping the self-diagnosis mode. To the CHECK circuit 12.

  The CHECK circuit 12 stops the self-diagnosis based on the second set count signal generated by the counter 11.

  Here, a method for terminating the self-diagnosis will be described. The CHECK circuit 12 terminates the self-diagnosis by the termination method described below regardless of whether the self-diagnosis is completed or stopped.

  First, the CHECK circuit 12 cancels a signal for preventing the TX_RDC 3 from reading from the transmission buffer memory 2. In the present embodiment, the CHECK circuit 12 outputs a command signal for resuming reading of transmission data from the transmission buffer memory 2 by the TX_RDC 3 to the CPU. The CPU gives a command to the TX_RDC 3 when receiving the command signal, thereby stopping reading of the reception data from the RX_RDC 9 by the TX_RDC 3 and restarting reading of the transmission data from the transmission buffer memory 2.

  Further, the CHECK circuit 12 releases the block by the SEL 18 and switches the circuit so that the SEL 17 stops the transfer of the reception data from the RX_RDC 9 and the transmission data is transferred from the transmission buffer memory 2 to the TX_RDC 3. Thereafter, the MAC circuit performs data transmission / reception as usual.

  Note that the MAC circuit of this embodiment stops the self-diagnosis when the reception buffer memory 8 or the transmission buffer memory 2 is likely to overflow during the self-diagnosis. Specifically, the buffer control 13 monitors the free capacity of the reception buffer memory 8 and generates a memory capacity warning signal when the storage amount in the reception buffer memory 8 exceeds a predetermined value. The CPU outputs a command signal to stop the self-diagnosis to the CHECK circuit 12 in accordance with the memory capacity warning signal generated by the buffer control 13.

  Similarly, the buffer control 16 monitors the free capacity of the transmission buffer memory 2 and generates a warning signal when the storage amount in the transmission buffer memory 2 exceeds a predetermined value. The CPU outputs a command signal to stop the self-diagnosis to the CHECK circuit 12 in accordance with the warning signal generated by the buffer control 16.

  As described above, according to the MAC circuit according to the first embodiment of the present invention, it is possible to perform periodic self-diagnosis without discarding received data from other nodes in any case at the time of online operation, thereby improving the soundness. You can keep keeping. That is, the MAC circuit of the present embodiment performs self-diagnosis using the received data, and the RX_RDC 9 outputs the received data to both the CPU and the TX_RDC 3 (via the SEL 17). There is an advantage that self-diagnosis can be performed in parallel with reception of, and self-diagnosis can be performed without stopping reception from PHY.

  In addition, since the CHECK circuit 12 determines the timing for performing the self-diagnosis based on the number of received data counted by the counter 10, the self-diagnosis can be performed at a timing according to the usage frequency of the MAC circuit, and more appropriately. In addition, the soundness of the MAC circuit can be maintained.

  Furthermore, by providing the counter 11, the MAC circuit of the present embodiment can appropriately stop the self-diagnosis when an FCS error has occurred in the received data.

  If the reception buffer memory 8 is likely to overflow during the self-diagnosis, the CHECK circuit 12 interrupts the self-diagnosis process and returns to the normal transmission / reception mode by a warning from the buffer control 13, so the reception process is interrupted. Never happen.

  Note that when the error count of the counter 11 exceeds a specified value, the CHECK circuit 12 may be configured to issue a request to switch the loopback circuit 5 to the CPU. Upon receiving the request, the CPU switches the loopback circuit 5 to loop back the data transmitted by the CPU.

  That is, the loopback circuit 5 corresponds to the loopback unit of the present invention, and blocks reception of received data from the physical layer to the RX_WRC6 according to the second set count signal generated by the counter 11, and is generated by the TX_RDC3. The received MAC frame is transferred to RX_WRC6.

  The CPU checks whether or not the data transmitted by itself matches the data returned by the loopback, and when the data matches, switches the loopback circuit 5 to restore the original. If they do not match, the CPU repeats transmission / reception of, for example, 5 frames. If the data still does not match, the CPU determines that there is a failed part in the MAC circuit and returns the loopback circuit 5 to its original state.

  While the loopback is in progress, the MAC circuit cannot receive the received data from the PHY, but determines whether there is a cause in the received data from the outside or in the MAC circuit for the FCS error. be able to.

  FIG. 3 is a diagram illustrating an operation when performing self-diagnosis using transmission data of the MAC circuit of the present embodiment. The configuration of the MAC circuit of the present embodiment is the same as that of the first embodiment, and a duplicate description is omitted. However, the CHECK circuit 12 of this embodiment determines a second timing for performing self-diagnosis using transmission data transmitted by the CPU.

  Next, the operation of the present embodiment configured as described above will be described. The MAC circuit in the present embodiment mainly uses the transmission data from the CPU to perform self-diagnosis mainly on portions of TX_WRC1, TX_RDC3, and RX_RDC9 in the circuit to determine whether normal operation is being performed.

  First, the counter 15 counts the number of times TX_WRC1 has received the transmission data transmitted by the CPU, and generates a third setting count signal when the count number reaches a predetermined number, and outputs it to the CHECK circuit 12 .

  The CHECK circuit 12 determines the second timing based on the third set count signal generated by the counter 15. That is, the MAC circuit of the present embodiment performs self-diagnosis using the transmission data once (or a plurality of times) in accordance with the second timing determined by the CHECK circuit 12.

  When the third setting count signal is generated by the counter 15, the CHECK circuit 12 outputs a command signal to the CPU so that transmission of new data by the CPU is stopped. When all the transmission data written in the transmission buffer memory 2 is transmitted, the CHECK circuit 12 outputs a command signal for stopping reading of the reception data from the reception buffer memory 8 by the RX_RDC 9 to the CPU. When receiving the command signal, the CPU gives a command to the RX_RDC 9 to stop reading the transmission data from the reception buffer memory 8 by the RX_RDC 9 and to start reading the transmission data from the TX_RDC 4.

  The SEL 14 corresponds to the second transfer unit of the present invention, and transfers the MAC frame output by the MAC frame generation unit (TX_RDC3) to the RX_RDC 9 according to the second timing determined by the CHECK circuit 12.

  That is, the RX_RDC 9 reads out the MAC frame output from the TX_RDC 3 instead of the reception buffer memory 8 via the SEL 14 according to the second timing determined by the CHECK circuit 12, and outputs the read MAC frame to the CPU. .

  Note that the SEL 18 blocks transmission of the MAC frame by the TX_RDC 3 according to the second timing determined by the CHECK circuit 12.

  The self-diagnosis is performed according to the following procedure. First, the CPU transmits test transmission data to the MAC circuit. TX_WRC1 writes test transmission data in the transmission buffer memory 2.

  Next, the TX_RDC 3 reads the test transmission data written in the transmission buffer memory 2, generates a MAC frame based on the read test transmission data, and transfers it to the RX_RDC 9 via the SEL 14.

  The RX_RDC 9 outputs the read MAC frame to the CPU. The CPU compares the transmitted test transmission data with the received MAC frame, and determines whether the data match. If the data match, the CPU determines that the portions TX_WRC1, TX_RDC3, RX_RDC9 are operating normally. On the other hand, if the data do not match, the CPU determines that one of the circuit portions of TX_WRC1, TX_RDC3, and RX_RDC9 has failed.

  When the self-diagnosis is completed, the CHECK circuit 12 switches the circuit so that the SEL 14 stops the transfer of the MAC frame from the TX_RDC 3 and the reception data is transferred from the reception buffer memory 8 to the RX_RDC 9. Further, the CHECK circuit 12 outputs a command signal to the CPU so that transmission of new data by the CPU is resumed. Further, the CHECK circuit 12 releases the blocking by the SEL 18.

  Further, the CHECK circuit 12 cancels a signal for preventing the RX_RDC 9 from reading from the reception buffer memory 8. In the present embodiment, the CHECK circuit 12 outputs a command signal for resuming reading of received data from the reception buffer memory 8 by the RX_RDC 9 to the CPU. When receiving the command signal, the CPU gives a command to the RX_RDC 9 to stop the reading of the MAC frame from the TX_RDC 3 by the RX_RDC 9 and to restart the reading of the reception data from the reception buffer memory 8. Thereafter, the MAC circuit performs data transmission / reception as usual.

  Note that the MAC circuit of this embodiment stops the self-diagnosis when the reception buffer memory 8 or the transmission buffer memory 2 is likely to overflow during the self-diagnosis. Specifically, the buffer control 13 monitors the free capacity of the reception buffer memory 8 and generates a memory capacity warning signal when the storage amount in the reception buffer memory 8 exceeds a predetermined value.

  The SEL 14 stops the transfer of the MAC frame in response to the memory capacity warning signal generated by the buffer control 13. However, in this embodiment, the buffer control 13 does not directly issue a command to the SEL 14, and the operation is performed via the CPU and the CHECK circuit 12.

  That is, when the memory capacity warning signal is generated by the buffer control 13, the SEL 14 receives a command from the CHECK circuit 12, stops the transfer of the MAC frame from the TX_RDC 3, and receives the received data from the reception buffer memory 8 to the RX_RDC 9 Switch the circuit so that the transfer takes place.

  Further, the RX_RDC 9 returns the read destination to the reception buffer memory 8 again according to the memory capacity warning signal generated by the buffer control 13. Specifically, the CPU that has received the memory capacity warning signal gives a command to the RX_RDC 9, thereby stopping the reading of the MAC frame from the TX_RDC 3 by the RX_RDC 9 and restarting the reading of the reception data from the reception buffer memory 8. .

  As described above, the MAC circuit in the present embodiment does not read the received data written in the reception buffer memory 8 by the RX_RDC 9 during the self-diagnosis, so that the received data in real time during the self-diagnosis as in the first embodiment. Is not output to the CPU, and the received data received during the self-diagnosis is stored in the reception buffer memory 8, and after the self-diagnosis is completed, the received data is sent from the reception buffer memory 8 to the CPU. Therefore, when there is no more free space in the reception buffer memory 8, the reception buffer memory 8 overwrites the old data every time new reception data is received, and discards the reception data without outputting to the CPU. become. The buffer control 13 stops the self-diagnosis according to the free capacity of the reception buffer memory 8 before the above-described problem occurs, and avoids discarding of received data.

  As described above, according to the MAC circuit according to the second embodiment of the present invention, not only can the same effect as the first embodiment be obtained, but also TX_WRC1 can be obtained by performing self-diagnosis using transmission data. Self-diagnosis can be performed for circuit portions that could not be confirmed in the first embodiment. In addition, since the CHECK circuit 12 determines the timing for performing the self-diagnosis based on the number of transmission data counted by the counter 15, the self-diagnosis can be performed at a timing according to the frequency of use of the MAC circuit. In addition, the soundness of the MAC circuit can be maintained.

  If the reception buffer memory 8 is likely to overflow during the self-diagnosis, the CHECK circuit 12 interrupts the self-diagnosis process and returns to the normal transmission / reception mode by the warning of the buffer control 13, so that the received data is discarded. The reception process can be appropriately performed without any problem.

  The MAC circuit according to the present invention can be used for a MAC circuit that controls access to a communication medium by generating a MAC frame for transmitting data, detecting an error in received data, and the like.

1 TX_WRC
2 Transmission buffer memory 3 TX_RDC
4 FCS circuit 5 Loopback circuit 5a Loopback command 5b Received data 5c Loopback data 6 RX_WRC
7 FCS circuit 8 Receive buffer memory 9 RX_RDC
9a Received data 10, 11 Counter 12 CHECK circuit 13 Buffer control 13b Received data 13c FCS value 14 SEL
15 Counter 16 Buffer control 17, 18 SEL

Claims (7)

A MAC circuit for controlling access to a communication medium interposed between a physical layer and a central processing unit,
A transmission buffer memory for temporarily storing transmission data transmitted by the central processing unit;
A first write control unit for writing the transmission data transmitted by the central processing unit into the transmission buffer memory;
A MAC frame generation unit that reads transmission data written in the transmission buffer memory, generates a MAC frame including an FCS value based on the read transmission data, and transmits the MAC frame to the physical layer;
A reception buffer memory for temporarily storing reception data received from the physical layer;
A second write control unit for confirming the presence or absence of an FCS error based on the received data received from the physical layer, and adding the calculated FCS value to the received data and writing to the receive buffer memory;
A read controller that reads the received data written in the reception buffer memory and outputs the read received data to the central processing unit;
A self-diagnosis control unit for determining a first timing for performing self-diagnosis using received data received from the physical layer;
A blocking unit that blocks transmission of the MAC frame by the MAC frame generation unit according to the first timing determined by the self-diagnosis control unit;
A first transfer unit that transfers the received data output by the read control unit to the MAC frame generation unit according to a first timing determined by the self-diagnosis control unit;
The MAC frame generation unit reads the reception data output by the read control unit instead of the transmission buffer memory via the first transfer unit according to the first timing determined by the self-diagnosis control unit. At the same time, the FCS value is calculated based on the read received data,
The self-diagnosis control unit diagnoses whether there is an abnormality in the MAC circuit by comparing the FCS value calculated by the second write control unit with the FCS value calculated by the MAC frame generation unit. Feature MAC circuit. A first counter that counts the number of times the second write control unit receives received data from the physical layer and generates a first set count signal when the count reaches a predetermined number;
2. The MAC circuit according to claim 1, wherein the self-diagnosis control unit determines the first timing based on a first setting count signal generated by the first counter. When the first setting count signal is generated by the first counter, the second write control unit during self-diagnosis counts the number of times received data is received from the physical layer, and the count number is set to a predetermined number. A second counter for generating a second set count signal when reached
3. The MAC circuit according to claim 2, wherein the self-diagnosis control unit stops the self-diagnosis based on a second setting count signal generated by the second counter.   According to the second set count signal generated by the second counter, reception of reception data from the physical layer to the second write control unit is blocked and the MAC frame generated by the MAC frame generation unit is 4. The MAC circuit according to claim 3, further comprising a loopback unit for transferring to the two write control unit. The self-diagnosis control unit determines a second timing for performing self-diagnosis using transmission data transmitted by the central processing unit,
The blocking unit blocks transmission of the MAC frame by the MAC frame generation unit according to the second timing determined by the self-diagnosis control unit,
A second transfer unit that transfers the MAC frame output by the MAC frame generation unit to the read control unit according to the second timing determined by the self-diagnosis control unit;
The read control unit reads the MAC frame output from the MAC frame generation unit instead of the reception buffer memory via the second transfer unit according to the second timing determined by the self-diagnosis control unit. 5. The MAC circuit according to claim 1, wherein the read MAC frame is output to the central processing unit. A third counter that counts the number of times the first write control unit has received the transmission data transmitted by the central processing unit and generates a third set count signal when the count reaches a predetermined number; ,
The MAC circuit according to claim 5, wherein the self-diagnosis control unit determines the second timing based on a third setting count signal generated by the third counter. A buffer control unit that monitors a free capacity of the reception buffer memory and generates a memory capacity warning signal when a storage amount in the reception buffer memory exceeds a predetermined value;
The second transfer unit stops transfer according to the memory capacity warning signal generated by the buffer control unit,
7. The MAC circuit according to claim 5, wherein the read control unit returns the read destination to the reception buffer memory again according to the memory capacity warning signal generated by the buffer control unit.

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