JP2011100950A - Semiconductor memory device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor memory device enabling further miniaturization. <P>SOLUTION: This semiconductor memory device is provided with a semiconductor substrate 10, a plurality of transistors 14a and 14b disposed on the semiconductor substrate 10, a plurality of ferroelectric capacitors 23a and 23b disposed on the plurality of transistors 14a and 14b and including ferroelectric films 21a and 21b disposed between lower electrodes 20a and 20b and upper electrodes 22a and 22b, lower layer contact plugs 17a and 17b that connect the semiconductor substrate 10 with the lower electrodes 20a and 20b, upper layer contact plugs 26a and 26b disposed on the upper electrodes 22a and 22b, and a sharing contact plug 27 disposed between the adjoining upper contact plugs to connect the upper layer contact plugs with the semiconductor substrate, and is characterized in that the sharing contact plug 27 directly touches and connects with the upper layer contact plugs 26a and 26b. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a semiconductor memory device having a ferroelectric capacitor.

  There is a FeRAM (Ferroelectric Random Access Memory) as a next-generation nonvolatile memory that has been developed with the aim of realizing capacity, speed, and cost comparable to DRAM.

Along with the miniaturization of semiconductor memory devices, the miniaturization of ferroelectric capacitors and transistors in the planar direction is necessary in order to highly integrate FeRAM memory cells. Conventionally, for example, both ends of a capacitor (C) are connected between the source and drain of a cell transistor (T), which is used as a unit cell, and a plurality of unit cells are connected in series. In the “body memory” structure, ferroelectric capacitors are formed by one-mask etching, thereby reducing the distance between adjacent ferroelectric capacitors and increasing the density of FeRAM memory cells (for example, Patent Documents). 1).

  However, in the above TC parallel unit series connection type ferromagnetic memory structure, the misalignment between the upper layer contact plug connected to the upper electrode of the ferroelectric capacitor and the wiring connecting the adjacent upper layer contact plug, Considering misalignment between the upper contact plug and the shared contact plug connecting the diffusion layer and the wiring of the semiconductor substrate, for example, in the first direction (perpendicular to the direction in which the plurality of ferroelectric capacitors are arranged in parallel) It is necessary to provide a space for the wiring width in the direction of As a result, there is a problem that a physical limit occurs in miniaturization of a semiconductor memory device.

  In addition, with the recent high integration and high density of semiconductor memory devices, further miniaturization of semiconductor memory devices is desired.

JP 2008-205300 A

  The present invention provides a semiconductor memory device that can be further miniaturized.

  In order to achieve the above object, a semiconductor memory device of one embodiment of the present invention includes a semiconductor substrate, a plurality of transistors provided over the semiconductor substrate, a lower electrode and an upper electrode provided over the transistor. A plurality of ferroelectric capacitors including a ferroelectric film provided therebetween; a lower layer contact plug connecting the semiconductor substrate and the lower electrode; and an upper layer contact plug provided on the upper electrode; A shared contact plug provided between the upper contact plugs and connecting the upper contact plug and the semiconductor substrate, wherein the shared contact plug is in direct contact with and connected to the upper contact plug. .

  According to the present invention, a semiconductor memory device that can be further miniaturized can be provided.

1 is a side sectional view showing a configuration of a semiconductor memory device according to a first embodiment of the present invention. FIG. 4 is a side cross-sectional view showing a third contact plug of the semiconductor memory device according to the first embodiment of the present invention. 1 is a plan view showing a configuration of a semiconductor memory device according to a first embodiment of the present invention. 1 is a side sectional view showing a manufacturing process of a semiconductor memory device according to a first embodiment of the present invention. FIG. 5 is a side sectional view showing a configuration of a semiconductor memory device according to a second embodiment of the present invention. The top view which shows the structure of the semiconductor memory device in the 2nd Embodiment of this invention. FIG. 6 is a side sectional view showing a manufacturing process of a semiconductor memory device according to a second embodiment of the present invention. FIG. 10 is a side sectional view showing a modification of the semiconductor memory device according to the second embodiment of the present invention.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In each figure, the same components are denoted by the same reference numerals.

(First embodiment)
[Configuration in the first embodiment]
The first embodiment is applied to a TC parallel unit serial connection type ferroelectric memory as one aspect of the present invention, and will be described with reference to FIGS. FIG. 1 is a side sectional view showing the configuration of the semiconductor memory device according to the first embodiment of the present invention. FIG. 2 is a side sectional view showing the third contact plug of the semiconductor memory device according to the first embodiment of the present invention. FIG. 3 is a plan view showing the configuration of the semiconductor memory device according to the first embodiment of the present invention.

  As shown in FIG. 1, the semiconductor memory device of the first embodiment includes a semiconductor substrate 10, transistors 14a and 14b, lower layer contact plugs 17a and 17b, ferroelectric capacitors 23a and 23b, and an upper layer contact plug 26a. 26b, a shared contact plug 27, and a contact plug 16 for connecting the diffusion layer 11 of the semiconductor substrate 10 and the shared contact plug 27.

  The semiconductor substrate 10 corresponds to a P-type substrate, and an N-type diffusion layer 11 is provided in the semiconductor substrate 10.

  The transistors 14a and 14b include a gate insulating film 12, a gate electrode 13, and source / drain diffusion layers, and one of the diffusion layers 11 serving as a source or drain and one electrode of the ferroelectric capacitors 23a and 23b are electrically connected. The other of the diffusion layer 11 as a source or drain and the other electrode of the ferroelectric capacitors 23a and 23b are electrically connected.

  The lower contact plugs 17a and 17b are for connecting one of the diffusion layers 11 as the sources or drains of the transistors 14a and 14b and lower electrodes 20a and 20b of ferroelectric capacitors 23a and 23b described later.

  As shown in FIG. 1, the ferroelectric capacitors 23 a and 23 b are provided on the lower contact plugs 17 a and 17 b provided on the semiconductor substrate 10 and the first interlayer insulating film 15 stacked on the semiconductor substrate 10. The lower layer is provided on the laminated film composed of the hydrogen barrier film 18 and the second interlayer insulating film 19 from the lower layer.

The ferroelectric capacitors 23a and 23b are formed on the lower electrodes 20a and 20b, the respective ferroelectric films 21a and 21b formed on the lower electrodes 20a and 20b, and the ferroelectric films 21a and 21b. Upper electrodes 22a and 22b. For the lower electrodes 20a and 20b, for example, a material such as Pt, Ir, or IrO ₂ can be used. For the ferroelectric films 21a and 21b, for example, PZT (Pb (Zr, Ti) O ₃ ), SBT (SrBi ₂ Ta ₂ O ₉ ) or the like can be used. Further, for example, Pt, Ir, IrO ₂ or the like can be used for the upper electrodes 22a and 22b. The protective film 24 is provided on the ferroelectric capacitors 23a and 23b, and the protective film 24 is provided on the surface of the first interlayer insulating film 15 on which the laminated film is not formed. (See FIG. 1).

The hydrogen barrier film 18 is a film for preventing the reaction between the ferroelectric capacitors 23a and 23b and hydrogen. For example, the hydrogen barrier film 18 includes SiN, Al ₂ O ₃ , TiO ₂ , ZrO ₂ , and HfO _2.
Etc. can be used. The protective film 24 has a hydrogen barrier property, and for example, SiN, Al ₂ O ₃ , TiO ₂ , ZrO ₂ , HfO ₂ or the like can be used.

  The upper contact plugs 26a and 26b are formed on the upper electrodes 22a and 22b of the ferroelectric capacitors 23a and 23b, and are in direct contact with the shared contact plug 27. The diffusion layer 11 as the source or drain of the transistors 14a and 14b. Is electrically connected to the other.

  The shared contact plug 27 is used to connect the upper substrate contact plugs 26 a and 26 b electrically connected to the upper electrodes 22 a and 22 b of the ferroelectric capacitors 23 a and 23 b to the semiconductor substrate 10. As shown in FIG. 1, a contact plug that connects the adjacent upper layer contact plugs 26 a and 26 b and the contact plug 16 is defined as a shared contact plug 27.

  As shown in FIG. 2, the shared contact plug 27 is defined by being divided into a first part A (lower part) and a second part B (upper part). The first portion A has a contact width in the second direction between the contact plug 16 and the shared contact plug 27 in the second direction (a direction in which the plurality of ferroelectric capacitors are arranged in parallel). The second part B means a part obtained by subtracting the first part from the shared contact plug 27.

  The outer diameter d1 of the first portion A is formed to be smaller than the outer diameter d2 of the second portion B, and the entire shared contact plug 27 has a vertically long shape.

  The first portion A has a columnar shape. Hereinafter, the case where the side cross section of the semiconductor memory device in the first embodiment is viewed will be described. The width of the first portion A is substantially constant with respect to the second direction (X direction in FIG. 1). On the other hand, the 2nd part B has the shape expanded toward the Z direction upper direction in FIG. That is, the width of the second portion B has a shape in which the width increases as it goes upward in the Z direction.

  As shown in FIGS. 2 and 3, when the second portion B is viewed from the upper surface, the second portion B is determined from the straight line L with respect to the straight line L in the Z direction passing through the center of the outer diameter d1 in the first portion A. The distance to the outer periphery of the part B is provided at substantially equal distances. That is, the cross sections of the second portion B in the second direction (X direction) are all provided with the distance from the straight line L to the outer periphery of the second portion B being substantially equal with respect to the straight line L. Yes. Here, “substantially equidistant” refers to a distance determined by etching formed by isotropic etching.

[Manufacturing Method in First Embodiment]
Next, the manufacturing process of the semiconductor memory device in this embodiment will be described with reference to FIG. FIG. 4 is a side sectional view showing a manufacturing process of the semiconductor memory device according to the first embodiment of the present invention.

  First, the manufacturing process leading to FIG. 4A will be described. An element isolation region (not shown) is formed in the semiconductor substrate 10, a gate insulating film 12 is formed on the surface of the active region of the semiconductor substrate 10, and a gate electrode 13 is formed on the gate insulating film 12. After the gate electrode 13 is formed, a diffusion layer 11 as a source or drain is formed on the surface portion of the active region of the semiconductor substrate 10 at both ends of the gate electrode 13. As a result, the memory cell transistors 14 a and 14 b are formed on the semiconductor substrate 10.

For the gate insulating film 12, for example, a single layer film of SiO ₂ , Si ₃ N ₄ , or SiON, or a composite film in which at least two of them are laminated can be used practically. For the gate electrode 13, for example, a single layer film of any one of silicon polycrystal, refractory metal, and refractory metal silicide, or a composite film in which a refractory metal film or a refractory metal silicide film is stacked on a silicon polycrystal film is used. Can be used practically.

  A first interlayer insulating film 15 is formed on the semiconductor substrate 10 to cover the transistors 14a and 14b. For example, a TEOS film can be used as the first interlayer insulating film 15.

  Thereafter, a photoresist is applied to the entire surface of the first interlayer insulating film 15, a desired resist pattern is formed by photolithography, and then the first interlayer insulating film 15 is dry-etched using the resist pattern as a mask. The first opening that exposes a part of the upper surface of the semiconductor substrate 10 is formed in the first interlayer insulating film 15 by processing. The contact plug 16 is formed by filling the first opening with the material used for the contact plug 16.

  Thereafter, a hydrogen barrier film 18 and a second interlayer insulating film 19 are stacked in this order from the lower layer on the first interlayer insulating film 15 and the contact plug 16 to form a stacked film, and chemical mechanical polishing (Chemical The surface is planarized by mechanical polishing (hereinafter referred to as “CMP”). Then, a second opening penetrating the first interlayer insulating film 15, the hydrogen barrier film 18, and the second interlayer insulating film 19 is formed by the same method as described above, and the first material is used for the lower contact plugs 17a and 17b. 2 openings are filled to form lower layer contact plugs 17a, 17b.

  Lower electrodes 20a and 20b of the ferroelectric capacitors 23a and 23b are formed on the second interlayer insulating film 19 and the lower contact plugs 17a and 17b, and further, the ferroelectric films 21a and 21b are formed on the lower electrodes 20a and 20b. Upper electrodes 22a and 22b are formed. For example, after the layers for forming the lower electrodes 20a and 20b, the ferroelectric films 21a and 21b, and the upper electrodes 22a and 22b are stacked, the lower electrode is formed by one mask etching that is collectively processed using a common mask layer. Ferroelectric capacitors 23a and 23b are formed by 20a and 20b, ferroelectric films 21a and 21b, and upper electrodes 22a and 22b (see FIG. 4A). At this time, the hydrogen barrier film 18 and the second interlayer insulating film 19 are etched so that the upper surface of the first interlayer insulating film 15 is partially exposed.

For the lower electrodes 20a and 20b, for example, a Pt film, an Ir film, an IrO ₂ film, an SRO film or the like can be used as a single layer or a stacked layer, and these thin films are formed by sputtering or CVD. Further, for example, PZT, SBT or the like can be used practically for the ferroelectric films 21a and 21b. These thin films are formed by sputtering or MOCVD. Furthermore, as with the lower electrodes 20a and 20b, for example, a Pt film, an Ir film, an IrO ₂ film, an SRO film, or the like can be used as the upper electrodes 22a and 22b in a single layer or a stacked layer.

  A protective film 24 is formed on the upper and side surfaces of the ferroelectric capacitors 23a and 23b and the exposed first interlayer insulating film 15 (see FIG. 4A).

  Next, the manufacturing process leading to FIG. 4B will be described. A third interlayer insulating film 25 is formed on the protective film 24, and the surface is planarized by CMP. Thereafter, a third opening and a fourth opening are formed by photolithography and RIE. The third opening is formed so as to penetrate the third interlayer insulating film 25 and the protective film 24 and to expose the upper electrode 22a in the ferroelectric capacitor 23a. Similarly, the fourth opening is formed so as to penetrate the third interlayer insulating film 25 and the protective film 24 and to expose the second upper electrode 22b in the second ferroelectric capacitor 23b. The third and fourth openings are filled with the material used for the upper contact plugs 26a and 26b, and the upper contact plugs 26a and 26b are formed by planarizing the surface by CMP (see FIG. 4B). The upper contact plugs 26a and 26b are, for example, a laminated film of a barrier metal layer, a tungsten layer, or an aluminum layer from the lower layer.

Next, the manufacturing process leading to FIG. First, a photoresist is applied to the entire surface of the third interlayer insulating film 25 and the upper contact plugs 26a and 26b, and a resist pattern is formed so that a fifth opening can be formed above the contact plug 16 by photolithography. (Refer FIG.4 (c)). Thereafter, isotropic etching is performed on the third interlayer insulating film 25 by using this resist pattern, and the third interlayer insulating film 25 is etched in an isotropic manner as shown in FIG. The shape will be made. Isotropic etching is performed until at least part of the upper contact plugs 26a and 26b is exposed. A part of the side surface (side wall) of the upper layer contact plugs 26a and 26b is etched by isotropic etching. As a result, a recess is formed in a part of the side wall above the upper contact plugs 26a and 26b. The method of isotropic etching is not limited, and wet etching using an HNO ₃ solution containing buffer HF may be used, for example, or dry etching may be used.

  Thereafter, anisotropic etching is performed using the resist pattern, and a fifth opening is formed so as to expose the upper surface of the contact plug 16 (see FIG. 4D).

Further, the fifth opening is filled with the material used for the shared contact plug 27, the surface is planarized by CMP, and the shared contact plug 27 is formed (see FIG. 4E).
As the contact plug 16, the upper contact plugs 26a and 26b, and the shared contact plug 27, for example, a barrier metal layer, a tungsten film, an aluminum film, or a copper film may be used from the lower layer.

  As described above, since there is no need for a wiring layer for connecting a certain upper layer contact plug 26a and the upper layer contact plug 26b adjacent to one of the upper layer contact plugs 26a and the shared contact plug 27, a semiconductor memory device capable of further miniaturization. Can provide.

  Conventionally, when a plurality of wiring layers formed in the first direction at a constant interval are misaligned with the shared contact plugs 27 formed in the first direction at a constant interval, for example, a certain wiring There is a possibility that the adjacent shared contact plug 27 contacts the layer, and the upper layer contact plugs 26a and 26b may not be connected to the wiring layer. However, in the first embodiment of the present invention, the wiring layer is not used. So there is no such worry. As a result, the influence due to misalignment is reduced.

  Further, since the wiring layer for connecting the upper contact plugs 26a and 26b is not required, it is possible to provide another wiring layer in a portion where the wiring layer is not required. As a result, the wiring layer can be efficiently used, and a semiconductor memory device that can be further miniaturized and a manufacturing method thereof can be provided. For example, metal wiring on memory cells is used for bit lines, parallel wiring of word lines for reducing resistance, and various signal lines, but this role can be assigned to a separate wiring layer. it can. As a result, the manufacturing cost of the semiconductor memory device can be reduced.

(Second Embodiment)
[Configuration in Second Embodiment]
A semiconductor memory device according to a second embodiment of the present invention will be described with reference to FIGS. FIG. 5 is a side sectional view showing the configuration of the semiconductor memory device according to the second embodiment of the present invention. FIG. 6 is a plan view showing the configuration of the semiconductor memory device according to the second embodiment of the present invention.

  The semiconductor memory device according to the second embodiment is different from the semiconductor memory device according to the first embodiment in the shapes of the upper contact plugs 26a and 26b and the shared contact plug 27, and the other components are as follows. It has the same configuration. Therefore, in the following description, detailed description of the same components as in the first embodiment is omitted, and different components (upper layer contact plugs 26a and 26b and shared contact plug 27) will be described. In order to simplify the description, the shared contact plug 27 will be described first.

<Shared contact plug>
The shared contact plug 27 is for connecting upper layer contact plugs 26a and 26b, which will be described later, and the semiconductor substrate 10. In the second embodiment, the shared contact plug 27 has a columnar shape.

<Upper contact plug>
The plurality of upper layer contact plugs 26a and 26b have the same shape, and the third part C (lower part) and the fourth part D (upper part) of the upper layer contact plugs 26a and 26b are the same as in the first embodiment. explain. The third portion C means a portion formed by anisotropic etching remaining after isotropic etching, and the fourth portion D is a portion obtained by subtracting the third portion C from the upper contact plugs 26a and 26b. Means.

  The third portion C has a columnar shape, and when the side cross section of the semiconductor memory device in the second embodiment is viewed, the width of the third portion C in the second direction is substantially constant. . The outer diameter of the third portion C is smaller than the outer diameter of the fourth portion D, and the upper contact plugs 26a and 26b as a whole are vertically long. The fourth portion D has a shape that expands upward in the Z direction in FIG. The width of the fourth portion D has a shape in which the width increases as it goes upward in the Z direction.

  As shown in FIG. 6, when the fourth portion D is viewed from the upper surface, a straight line in the Z direction passing through the center of the outer diameter of the third portion C is used as a reference from the straight line to the outer periphery of the fourth portion D. Are provided at substantially equal distances. In other words, every cross section in the second direction of the fourth portion D is provided with the outer periphery of the fourth portion D at substantially equal distances with respect to the straight line. Thus, upper contact plugs 26 a and 26 b are provided so as to be in contact with shared contact plug 27.

[Manufacturing Method in Second Embodiment]
Next, a manufacturing process of the semiconductor memory device according to the second embodiment will be described with reference to FIG. FIG. 7 is a side sectional view showing a manufacturing process of the semiconductor memory device according to the second embodiment of the present invention.

  The method for manufacturing the semiconductor memory device according to the second embodiment differs from the method for manufacturing the semiconductor memory device according to the first embodiment in the formation method of the upper contact plugs 26a and 26b and the shared contact plug 27. About another process, it has the same process. Therefore, in the following description, detailed description of steps similar to those of the first embodiment will be omitted, and different process portions will be described.

  First, since the process leading to FIG. 7A is the same as the process leading to FIG. 4A in the first embodiment, description thereof will be omitted and FIG. 7B will be described.

  After the formation of the third interlayer insulating film 25 (see FIG. 7A), a photoresist is applied to the entire surface of the third interlayer insulating film 25, and a desired resist pattern is formed by photolithography technique. The third interlayer insulating film 25 is processed by dry etching using the resist pattern as a mask to form a sixth opening exposing the upper surface of the contact plug 16 in the third interlayer insulating film 25. The sixth opening is filled with a material used for the shared contact plug 27, and the surface is flattened by CMP to form the shared contact plug 27 (see FIG. 7B).

  Thereafter, a photoresist is applied again on the third interlayer insulating film 25 and the shared contact plug 27 to form a resist pattern for forming the upper contact plugs 26a and 26b (see FIG. 7C).

  Using this resist pattern, isotropic etching is performed on the third interlayer insulating film 25, and the third interlayer insulating film 25 is isotropically etched as shown in FIG. Will be made. Isotropic etching is performed until at least a part of the shared contact plug 27 is exposed. A part of the side surface (side wall) of the upper part of the shared contact plug 27 is etched by isotropic etching. As a result, a recess is formed in a part of the side wall above the shared contact plug 27.

  Thereafter, the etching is performed using the resist pattern, and a seventh opening is formed so as to partially expose the surfaces of the upper electrodes 22a and 22b of the ferroelectric capacitors 23a and 23b (FIG. 7D). )reference).

  Further, the seventh opening is filled with the material used for the upper contact plugs 26a and 26b, and the surface is flattened by CMP to form the upper contact plugs 26a and 26b (see FIG. 7E). As the upper contact plugs 26a and 26b and the shared contact plug 27, for example, a barrier metal layer, a tungsten film, an aluminum film, or a copper film may be used from the lower layer.

  As described above, since there is no need for a wiring layer for connecting a certain upper layer contact plug 26a and the upper layer contact plug 26b adjacent to one of the upper layer contact plugs 26a and the shared contact plug 27, a semiconductor memory device capable of further miniaturization. Can provide.

  Similarly to the first embodiment, since the wiring layer is not used in the second embodiment of the present invention, for example, the possibility that an upper contact plug adjacent to a certain wiring layer is in contact with the wiring layer or the upper layer is connected to the wiring layer. There is no worry about the possibility of the contact plug not being connected. As a result, the influence due to misalignment is reduced. Further, the manufacturing cost of the semiconductor memory device can be reduced.

In each embodiment of the present invention, the material of the upper contact plugs 26a and 26b and the shared contact plug 27 is copper. Since copper has a relatively low resistance, the contact resistance between the upper contact plugs 26a and 26b and the shared contact plug 27 can be reduced.

  Note that the present invention is not limited to the above-described embodiment, and various modifications can be made without departing from the scope of the invention in the implementation stage. For example, as shown in FIG. 8, the first embodiment and the second embodiment may be combined. FIG. 8 is a sectional view showing a modification of the semiconductor memory device according to the second embodiment of the present invention.

  Specifically, the shape of the upper contact plugs 26a and 26b may be the same as that of the second embodiment, and the shape of the shared contact plug 27 may be the same as that of the first embodiment. As a result, as in the first and second embodiments, a semiconductor memory device that can be further miniaturized and a method for manufacturing the same can be provided. Further, in this case, the upper contact plug can be used even if the outer diameter d1 of the second portion B in the first embodiment and the outer diameter of the fourth portion D in the second embodiment are used. 26a, 26b and the shared contact plug 27 can be brought into contact with each other. As a result, the influence on misalignment between the upper contact plugs 26a and 26b and the shared contact plug 27 can be further reduced as compared with the first and second embodiments. In addition, manufacturing costs can be reduced.

  Furthermore, the above embodiments include inventions at various stages, and various inventions can be extracted by appropriately combining a plurality of disclosed constituent elements. For example, even if some constituent requirements are deleted from all the constituent requirements shown in the embodiment, the problem described in the column of the problem to be solved by the invention can be solved, and the effect described in the column of the effect of the invention Can be extracted as an invention.

DESCRIPTION OF SYMBOLS 10 ... Semiconductor substrate 11 ... Diffusion region 12 ... Gate insulating film 13 ... Gate electrode 14 ... Transistor 15 ... First interlayer insulating film 16 ... Third lower layer contact plug 17 ... Lower layer contact plug 18 ... Hydrogen barrier film 19 ... Second Interlayer insulating films 20a, 20b ... lower electrodes 21a, 21b ... ferroelectrics 22a, 22b ... upper electrodes 23a, 23b ... ferroelectric capacitors 24 ... protective film 25 ... third interlayer insulating films 26a, 26b ... upper layer contact plugs 27 ... Shared contact plug

Claims (6)

A semiconductor substrate;
A plurality of transistors provided on the semiconductor substrate;
A plurality of ferroelectric capacitors provided on the transistor and including a ferroelectric film provided between the lower electrode and the upper electrode;
A lower contact plug connecting the semiconductor substrate and the lower electrode;
An upper contact plug provided on the upper electrode;
A common contact plug provided between adjacent upper layer contact plugs and connecting the upper layer contact plug and the semiconductor substrate;
The semiconductor memory device, wherein the shared contact plug is in direct contact with and connected to the upper contact plug. 2. The semiconductor memory device according to claim 1, wherein the shared contact plug is provided so as to engage with a concave portion provided on the upper portion of the upper contact plug. 3. The semiconductor memory device according to claim 1, wherein the lower part of the shared contact plug has a columnar shape, and the upper part of the shared contact plug has a shape expanding upward. When the shared contact plug is viewed from above, the distance from the straight line to the outer periphery of the shared contact plug is substantially equidistant based on a vertical straight line passing through the center of the cross section at the lower part of the shared contact plug. 4. The semiconductor memory device according to claim 3, wherein: 5. The semiconductor memory device according to claim 1, wherein the lower portion of the upper contact plug is further in a columnar shape, and the upper portion of the upper contact plug has a shape expanding upward. When the upper contact plug is viewed from above, the distance from the straight line to the outer periphery of the upper contact plug is substantially equidistant with reference to a vertical straight line passing through the center of the cross section at the lower part of the upper contact plug. 6. The semiconductor memory device according to claim 5, wherein:

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