JP2011097775A - Power supply device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a power supply device that minimizes internal loss of a switching regulator when power efficiency varies due to variability in output load and manufacturing of the switching regulators. <P>SOLUTION: The power supply device includes: a switching regulator that converts an input voltage into an output voltage corresponding to a load so as to output the output voltage and to supply power to the load, an input voltage monitoring means for monitoring the input voltage supplied to the switching regulator, an input current monitoring means for monitoring an input current supplied to the switching regulator, an input-power calculation means for calculating input power supplied to the switching regulator on the basis of the input voltage and the input current, a power determining means for determining whether the input power calculated after outputting the output voltage exceeds a predetermined target power consumption or not, and an operation-mode control means for shifting the operation mode of the switching regulator to another operation mode to reduce the input power when determined that the input power exceeds the predetermined target power consumption. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a power supply apparatus, and more particularly to a power supply apparatus used in an image processing apparatus having functions such as a scanner, a facsimile machine, and a copying machine.

  A power supply device that drives various devices using electricity needs to output various levels of voltage, and switching regulators and series regulators are often used as means for outputting various levels of voltage. Switching regulators have the characteristic that the efficiency is reduced at low current consumption. Series regulators have the characteristic that the regulator loss increases at high current output because the efficiency is determined by the input / output potential difference. For this reason, in order to realize low power consumption, a PFM (Pulse Frequency Modulation) system that reduces the FET drive frequency at the time of low current output is used for the switching regulator. However, although the PFM method can reduce power consumption, the ripple voltage of the output voltage is increased. Therefore, as a method for solving the problem of the ripple voltage increase of the PFM method, there is known a device that monitors the output current and switches to a series regulator when the current consumption is low and to a switching regulator when the current consumption is high.

  For example, for the purpose of providing a DC-DC converter capable of preventing deterioration in conversion efficiency due to a change in input voltage, a switching regulator and a linear regulator that control the output voltage obtained by converting the input voltage to a constant voltage, a switching regulator, A control circuit that operates either one of the linear regulators. The control circuit monitors the input voltage, the output voltage, and the output current, and based on the monitoring result, the switching regulator and the linear regulator There has been disclosed a DC-DC converter characterized by selecting and operating an efficient regulator (see Patent Document 1).

JP 2007-082273 A

  The conventional configuration that monitors the output current and switches to the series regulator when the current consumption is low and switches to the switching regulator when the current consumption is high can improve the power efficiency. However, the current-power due to the output load variation and the switching regulator manufacturing variation Since the efficiency variation is not taken into consideration, there is a problem in that the internal loss of the switching regulator cannot be optimized to the minimum when the power efficiency variation occurs.

  Although the configuration of Patent Document 1 certainly has the effect of improving the efficiency of the DC-DC converter, it does not take into account the current-power efficiency variation due to the manufacturing variation of the switching regulator and the variation of the output load. When this occurs, the problem that the internal loss of the switching regulator cannot be optimized to the minimum has not been solved.

  Against the background of the above problems, an object of the present invention is to provide a power supply device that minimizes the internal loss of a switching regulator when there is a variation in power efficiency due to variations in output load and manufacturing variations of the switching regulator. .

Means for Solving the Problems and Effects of the Invention

A power supply device for solving the above problems is
A switching regulator that converts the input voltage into an output voltage corresponding to the load and outputs the output voltage, supplies power to the load, input voltage monitoring means for monitoring the input voltage to the switching regulator, and monitors the input current to the switching regulator Based on the input current monitoring means, the input power calculating means for calculating the input power to the switching regulator based on the input voltage and the input current, and the input power calculated after outputting the output voltage is a predetermined target power consumption. An operation mode for transitioning the operation mode of the switching regulator to an operation mode in which the input power is smaller when it is determined that the input power exceeds a predetermined target power consumption. And a control means.

  With the above configuration, even if there is a variation in power efficiency due to variations in output load and manufacturing variations of the switching regulator, the internal loss of the switching regulator can be optimized to be small.

  In the power supply device of the present invention, in the operation mode of the switching regulator, the operation mode capable of outputting the output current in a state where the current-power efficiency distribution characteristic of the switching regulator is good is set as the default operation mode.

  With the above configuration, it is possible to reduce the probability of changing the operation mode, reduce the opportunity to use the power efficiency at a location where the power efficiency is poor, and optimize the internal loss of the switching regulator.

  Further, the power supply apparatus of the present invention includes an average power consumption calculating means for calculating an average power consumption in the switching regulator, and the operation mode control means does not change the average power consumption in the switching regulator. The switching regulator is operated so as to reduce the instantaneous current consumption at.

  With the above configuration, the internal current of the switching regulator is reduced by reducing the instantaneous current consumption compared to the regulator where the power efficiency is higher where the current is smaller than where the current-power efficiency distribution of the switching regulator is concentrated. Loss can be optimized with small loss. In addition, since the instantaneous current consumption is reduced, the energy of electromagnetic waves radiated from the power supply device can be reduced.

  Further, the power supply apparatus of the present invention includes an average power consumption calculating means for calculating an average power consumption in the switching regulator, and the operation mode control means does not change the average power consumption in the switching regulator. The switching regulator is operated so as to increase the instantaneous current consumption at.

  With the above configuration, the instantaneous current consumption is increased for the regulator where the power efficiency is higher where the current is larger than where the current-power efficiency distribution of the switching regulator is concentrated. Loss can be optimized with small loss.

  The power supply apparatus of the present invention further includes load resistance adjusting means for adjusting the load resistance in the load, and the operation mode control means increases the load resistance from the normal state and increases the instantaneous current consumption in the switching regulator. The switching regulator is operated as follows.

  Even with the above configuration, the instantaneous current consumption is increased by increasing the instantaneous current consumption with respect to the regulator in which the power efficiency is higher at the location where the current is larger than the location where the current-power efficiency distribution of the switching regulator is concentrated. Internal loss can be optimized smaller.

  Further, the input current monitoring means in the power supply device of the present invention connects a low resistance having a low resistance value in series with an input power supply path that is a path through which input power is supplied to the switching regulator. The generated potential difference is amplified, and the result of AD conversion of the amplified potential difference is defined as an input current.

  With the above configuration, it is possible to suppress power consumption that occurs when the input current is monitored. By using a low resistance, a potential difference generated with a low resistance can be reduced. Even if the potential difference generated by the low resistance is reduced, the potential difference can be measured by the AD converter by performing voltage amplification.

  Further, the input power supply path in the power supply device of the present invention includes an FET connected in parallel with a low resistance, and when the input current is not monitored, the current flowing through the low resistance is bypassed to the FET.

  With the above configuration, it is possible to suppress a loss that occurs at a low resistance when the input current is not monitored.

  The power supply apparatus of the present invention further includes output current monitoring means for monitoring the output current of the switching regulator, and output current determination means for determining whether or not the output current is abnormal.

  With the above configuration, by monitoring the output current, it becomes possible to detect the behavior of the current that could not be assumed at the time of design.

  The power supply apparatus of the present invention further includes power supply stopping means for stopping the supply of power to the load when it is determined that the output current is abnormal.

  With the above configuration, when an abnormal current occurs, the supply of power can be safely stopped.

  The operation mode control means in the power supply device of the present invention transitions the operation mode of the switching regulator to an operation mode in which the output current is smaller when the output current exceeds a predetermined peak value.

  With the above configuration, energy of electromagnetic waves radiated from the power supply device can be suppressed.

  Further, the operation mode control means in the power supply device of the present invention sets the operation mode of the switching regulator at a frequency exceeding the threshold when the output current exceeds a predetermined output current threshold for each frequency. Transition to an operation mode with a smaller value.

  With the above configuration, the energy of the electromagnetic wave having a specific frequency radiated from the power supply device can be suppressed.

The figure which shows the basic composition of a power supply device. The figure which shows the circuit structure of the voltage generation part by a prior art. The flowchart explaining the electric power supply by a prior art. The figure explaining the power efficiency of a switching regulator. The figure which shows the circuit structure of the voltage generation part of this invention. The flowchart explaining an operation mode control process. The figure which shows an example of an operation mode. The figure explaining the power efficiency of the switching regulator in this invention. The figure which shows another example of an input electric power detection part. The figure which shows the circuit structure of the voltage generation part of this invention (modification). The flowchart explaining an output current abnormality determination process. The flowchart explaining an operation mode control process (modification).

  Hereinafter, embodiments of a power supply device according to the present invention will be described with reference to the drawings. FIG. 1 shows a configuration diagram of the power supply device. As shown in FIG. 1, the power supply device 100 includes a power supply unit 1 and a voltage generation unit 2, and the voltage generation unit 2 supplied with power from the power supply unit 1 generates various levels of voltage according to the load 3. Generate and output. In the load 3, the voltage from the voltage generation unit 2 is input, and the CPU 4 operates using the RAM 6 as a work area based on the contents stored in the ROM 5. The control unit 30 including the CPU 4 includes the mechanical drive unit 7 and communication control. The unit 8 and the sensor unit 9 are controlled. Note that the CPU 4 has the input power calculation means, input current monitoring means, power determination means, operation mode control means, average power consumption calculation means, load resistance adjustment means, output current monitoring means, output current determination means, power supply of the present invention. Corresponds to stopping means.

  The load 3 is a component of an image processing apparatus having functions such as a scanner, a facsimile machine, and a copying machine. In this case, the mechanical drive unit 7 carries a document or paper, the communication control unit 8 performs network communication or fax communication, and the sensor unit 9 detects the position of the document or paper. is there.

  FIG. 2 shows a circuit configuration of the voltage generator 2 according to the prior art. The voltage generator 2 uses the voltage VCC0 supplied from the power supply unit 1 to generate VCC1 by a switching regulator (hereinafter referred to as REG) 1 (31) and supplies power to the load 41. The load 41 includes the control unit 30. Also, VCC2 is generated by REG2 (32), and power is supplied to the load 42. The load 42 includes an external I / F (not shown) of the CPU 4, a communication control unit 8, and a sensor unit 9. Also, VCC3 is generated by REG3 (33), and power is supplied to the load 43. The load 43 includes the mechanical drive unit 7.

  Unlike a series regulator, a switching regulator is expected to have higher power efficiency as the output current is higher. Therefore, it is common to generate a power supply voltage corresponding to each load using the switching regulator as described above.

  With reference to FIG. 3, the power supply according to the prior art will be described. When the supply of power from the power supply unit 1 is started (S11), the voltage generation unit 2 having a switching regulator starts generating a power supply voltage corresponding to each load (41 to 43) (S12). Then, the power supply voltage is applied to each load from the voltage generator 2, and the operation of each load starts (S13).

  The power efficiency of the switching regulators (REG1 to REG3) will be described with reference to FIG. As described above, the switching regulator is used to generate the power supply voltages (VCC1 to VCC3) of the loads (41 to 43). However, switching regulators vary in load current-power efficiency characteristics due to variations in manufacturing. If this load current-power efficiency characteristic is not used at a suitable location, the internal loss of the switching regulator increases and wasteful power consumption occurs.

  Here, as an example, the efficiency variation of the switching regulator due to the manufacturing variation of REG1 (31) (hereinafter referred to as REG1) will be described. As shown in FIG. 4, the relationship between the output current I of REG 1 and the power efficiency η is expressed as a graph 61. Therefore, the operation of REG1 is controlled so that the load current becomes I11 at which the maximum power efficiency η11 (internal loss is minimized) of REG1 can be obtained. However, even when the load current I11 is the same, the power efficiency η differs depending on the manufacturing variation of REG1, and when the relationship between the output current I and the power efficiency η is expressed as shown in the graph 62, the power efficiency η when the load current is I11 is η12, and the maximum power efficiency cannot be obtained. When the relationship between the output current I and the power efficiency η is expressed as shown in the graph 63, the power efficiency η when the load current is I11 is η13, and the maximum power efficiency cannot be obtained. Thus, the power efficiency η is lowered, and the internal loss of REG1 is increased.

  In FIG. 4, it can also be seen that the power efficiency η of REG1 changes as the load current I changes.

  As described above, the conventional power supply method does not take into account variations in load current-power efficiency due to manufacturing variations of switching regulators. Therefore, variations in output efficiency and power efficiency variations due to manufacturing variations of switching regulators occur. However, there is a problem that the internal loss of the switching regulator cannot be optimized to the minimum.

  The configuration of the present invention for solving the above problem will be described below. Since the method for minimizing the internal loss of the switching regulators (REG1, REG2, REG3) is the same, here, a method for optimizing the internal loss of the switching regulator 1 by taking REG1 as an example will be described.

  First, the details of the voltage generation unit 2 will be described with reference to FIG. In addition to REG1 (31), the voltage generation unit 2 includes an input current detection unit 300 of the REG1 including the input current detection resistor 301, a REG1 output adjustment coil 302 for outputting constant power to the equivalent load 305, an equivalent load A REG1 output adjusting co-capacitor 303 for leveling the power supply to the 305 is provided. And it has AMP1 which is an amplifier which amplifies the voltage of both ends of the input current detection resistor (low resistance of the present invention, hereinafter referred to as “low resistance”) 301. Then, the output voltage of AMP1 is input to the AD converter 330, and the equivalent load resistor 306 and the equivalent load capacitor 307 that transmit the input current information of REG1 to the CPU 4 are optimally controlled. Note that the input current detection unit 300, the AMP1, the AD converter 330, and the CPU 4 correspond to the input current monitoring means of the present invention.

Reference numeral 340 denotes a control line for the equivalent load 305 of the CPU 4. With this control line 340, the CPU 4 performs the following control on the equivalent load 305, for example.
Change of operation mode (for example, change as in operation modes A, B, and C in FIG. 7).

  A method for measuring input power using the power generation unit 2 of the present invention will be described. The potential difference between both ends (N300, N301: input power supply path) of the low resistance 301 is amplified by an input current detection voltage amplification operational amplifier (hereinafter abbreviated as “operational amplifier”) 314 of the REG 1 (31), and is supplied to the AD converter 330. input. Here, when the value of the voltage amplification adjusting resistors 310 and 312 of the operational amplifier 314 is 10 kΩ and the value of the voltage amplification adjusting resistors 311 and 313 is 1 kΩ, a value 10 times the potential difference between both ends of the low resistance 301 is AD converted. Input to the device 330.

  Since the resistance value of the low resistance 301 is known by the above configuration, (potential difference between both ends of the low resistance 301) / (resistance value of the low resistance 301) is obtained based on the input voltage information to the AD converter 330. As a result, the input current of REG1 can be detected. The AD converter 330 corresponds to the input voltage monitoring means of the present invention.

  Further, by inputting the input voltage VCC0 ′ to REG1 to the AD converter 330, the input voltage to REG1 can be measured. Therefore, the CPU 4 can monitor the input power of REG1 in real time by calculating (input current of REG1) × (input voltage to REG1) after AD conversion.

  An operation mode control process executed by the CPU 4 for optimizing the internal loss of the REG 1 to the minimum based on the calculated input power information will be described with reference to FIG. The difference from the conventional method (see FIG. 3) is that operation mode selection (step S201), input power calculation (step S202), target power consumption determination (step S203), and operation mode determination (step S204) are added. (Steps S200 and S205 will be separately described later). Hereinafter, these details will be described, and the description of the same configuration as in FIG. 3 will be omitted.

  First, as in FIG. 3, when the supply of power from the power supply unit 1 is started (S11), the voltage generation unit 2 starts generating a power supply voltage corresponding to the equivalent load 305 (S12). Next, the CPU 4 operates the REG 1 in accordance with the initial setting operation mode (“default operation mode” of the present invention) stored in advance in the ROM 5 (S201).

  The operation mode defines how much output current is output at what timing as shown in FIG. For example, in the operation mode A, the output current I1 is continuously output during the time T1 after the time t1. In the operation mode B, the output current I2 is output for the time t2 in the cycle T2. In the operation mode C, the output current I3 is output for a time t3 at a period T3.

  As the initial operation mode, it is desirable to set an operation mode in which when a large number of switching regulators are prepared, an output current can be obtained in which portions with good characteristics of the current-power efficiency distribution of the switching regulator are concentrated. As a result, the probability of changing the operation mode can be reduced, the opportunity for use in places with poor power efficiency when the operation mode is selected can be reduced, and the internal loss of the switching regulator can be reduced and optimized.

  Returning to FIG. 6, the CPU 4 calculates the input power in the REG 1 operating in the initial setting operation mode by the above-described method (S202). Then, the CPU 4 determines whether or not the input power is equal to or less than the target power consumption stored in the ROM 5 in advance. For example, when the operation mode time is set to T0 (for example, 1 minute), [(VCC0 × I1in + VCC0 × I2in + VCC0 × I3in) × t] is integrated for T0 time (input power in the operation mode time) and the target power consumption Judge by comparison. Here, VCC0: voltage supplied from the power supply unit 1, I1in: REG1 input current, I2in: REG2 input current, I3in: REG3 input current.

  Returning to FIG. 6, when the input power is equal to or lower than the target power consumption (S203: Yes), the CPU 4 determines the initial setting operation mode as the current operation mode (S204). Thereafter, the power supply voltage is applied to the equivalent load 305 according to the control command of the CPU 4 and the operation of the equivalent load 305 is started (S13).

  On the other hand, when the input power exceeds the target power consumption (S203: No), the CPU 4 returns to step S201 and selects another operation mode (operation mode B or C if the initial setting operation mode is operation mode A). Then, the calculation of the input power (S202) and the comparison between the input power and the target power consumption (S203) are performed until the input power becomes equal to or less than the target power consumption. Accordingly, an operation mode that can optimize the internal loss of the switching regulator to the minimum can be determined according to the variation in the load.

  When the input power exceeds the target power consumption (S203: No), in step S201, instead of selecting another operation mode, in the current operation mode, the output current value or output current output timing (output time, period) ) May be changed.

  When the input power exceeds the target power consumption, the load (that is, the equivalent load 305) includes a variable resistor (not shown). When the input power exceeds the target power consumption (S203: No), the CPU 4 controls Thus, the instantaneous power consumption of the switching regulator may be increased by changing the value of the variable resistor.

  The above process may be repeatedly executed at a predetermined timing during power supply.

  The power efficiency η of the switching regulator (REG1, REG2, REG3) in the configuration of FIG. 5 will be described using REG1 as an example with reference to FIG. Even if the power efficiency η of REG1 varies due to manufacturing variations, the operation mode of REG1 is sequentially changed to a state in which the load current A, the load current B, and the load current C are obtained, and the target power consumption determination (step S203 in FIG. 6) is performed. By carrying out the operation, it is possible to determine an operation mode in which the power loss of REG1 becomes smaller.

  Assuming that the optimum power efficiency η0 is an efficiency at which the internal loss of REG1 is minimized, when the relationship between the load current I of REG1 and the power efficiency η is represented by a graph 61, the operation mode is changed, that is, the load current I is changed. Thus, the load current A that can obtain the optimum power efficiency η0 is found, and the REG1 is operated with this state as a new operation mode. Similarly, when the relationship between the load current I of REG1 and the power efficiency η is represented by the graph 63, by changing the load current I, the load current C that can obtain the optimum power efficiency η0 is found, and this state is newly set. REG1 is operated as a simple operation mode. By doing so, the internal loss of the switching regulator can be optimized to be small according to variations in the switching regulator and the load.

  Another example of the configuration of the input power detection unit 300 included in the voltage generation unit 2 in FIG. 5 will be described with reference to FIG. A bypass P-channel FET 400 is connected in parallel to the low resistance 301 for detecting input current included in the input power supply path (between N (node) 300 and N301). For example, the control signal SIG1 from the CPU 4 is input to the switching circuit 410 including the transistor 413 and the resistors 411 and 412, and the FET 400 is turned on / off based on the output signal from the switching circuit 410.

  Here, when the input current of REG1 is not detected (for example, the timing of step S205 in FIG. 6), the control signal SIG1 for turning on the FET 400 is output from the CPU 4 to the switching circuit 410. Since the internal resistance of the FET 400 is sufficiently lower than the value of the low resistance 301, it is possible to prevent all current from flowing through the FET 400 and consuming power at the low resistance 301.

  On the other hand, when detecting the input current of REG1 (for example, the timing of step S200 in FIG. 6), the control signal SIG1 for turning off the FET 400 is output from the CPU 4 to the switching circuit 410. As a result, all of the current flows through the low resistance 301, and the input current of REG1 can be detected.

  Another example of the configuration of the present invention will be described with reference to FIG. Since this configuration is a modification of FIG. 5, the same components as those in FIG. 5 are denoted by the same reference numerals, and detailed description thereof is omitted here. A difference from the configuration of FIG. 5 is that an output current detection resistor (hereinafter, simply referred to as “resistance”) 304 of REG1 and AMP2 (the configuration is the same as that of AMP1) are added. The AD converter 330, CPU 4, output current detection resistor 304, and AMP2 correspond to the output current monitoring means of the present invention.

  In the configuration of FIG. 10, the voltage generated at both ends of the resistor 304 is amplified by the AMP 2 with a predetermined amplification factor, and input to the AD converter 330 to perform AD conversion, thereby calculating the voltage. The CPU 4 can calculate the output current of REG 1 by dividing the voltage by the known value of the resistor 304. Further, the product of the output current of REG1 and the output voltage VCC1 'of REG1 can be the output power of REG1.

  The output current abnormality determination process executed by the CPU 4 will be described with reference to FIG. First, the output current in REG1 is calculated using the method described above (S31). Next, it is determined whether or not the output current is abnormal. For example, it is determined that the output current is abnormal when a state where the output current exceeds a predetermined threshold continues for a predetermined time. When it is determined that the output current is abnormal (S32: Yes), the CPU 4 stops the supply of power to the equivalent load 305 of REG1 (S33).

  The operation mode control process in the configuration of FIG. 10 will be described using FIG. Since this process is a modification of FIG. 6, the same components as those in FIG. 6 are denoted by the same reference numerals, and detailed description thereof is omitted here.

  First, similarly to FIG. 6, when the supply of power from the power supply unit 1 is started (S11), the voltage generation unit 2 starts generating a power supply voltage corresponding to the equivalent load 305 (S12). Next, the CPU 4 operates the REG 1 according to the initial setting operation mode stored in advance in the ROM 5 (S201).

  Next, by the method described above, the CPU 4 calculates the output current in the REG1 that is operating in this initial setting operation mode (S202a). Subsequently, the CPU 4 calculates an output current for each frequency based on, for example, an FFT (Fast Fourier Transform) calculation result of the output current (S202b).

Then, the CPU 4 determines whether or not it is necessary to change the operation mode. For example, when at least one of the following is established, it is determined that the operation mode needs to be changed.
• When the output current exceeds a predetermined peak value.
・ When the output current for each frequency exceeds a predetermined output current threshold

  When it is not necessary to change the operation mode (S203a: Yes), the CPU 4 determines the initial setting operation mode as the current operation mode (S204). Thereafter, the power supply voltage is applied to the equivalent load 305 in accordance with a control command from the CPU 4, and the operation starts (S13).

  On the other hand, when it is necessary to change the operation mode (S203a: No), the CPU 4 returns to step S201, and other operation modes (for example, operation mode B or C if the initial setting operation mode is operation mode A). The output current is calculated (S202a), the output current is measured for each frequency (S202b), and whether or not the operation mode is to be changed (S203) is determined until it is no longer necessary to change the operation mode.

  Of course, in the configuration of FIG. 10, a bypass P-channel FET 400 may be connected in parallel to the low resistance 301 for detecting the input current. In this case, the FET 400 is turned off before step S201 in FIG. 12 (same as the timing of step S200 in FIG. 6), and turned on after step S204 in FIG. 12 (same as the timing of step S205 in FIG. 6). State.

  Although the embodiments of the present invention have been described above, these are merely examples, and the present invention is not limited to these embodiments, and the knowledge of those skilled in the art can be used without departing from the spirit of the claims. Various modifications based on this are possible.

  The present invention can also be applied to an apparatus using a switching regulator other than the image processing apparatus.

DESCRIPTION OF SYMBOLS 1 Power supply part 2 Voltage generation part 3 Load 4 CPU (input power calculating means, input current monitoring means, power determination means, operation mode control means, average power consumption calculating means, load resistance adjusting means, output current monitoring means, output Current judgment means, power supply stop means)
31 Switching regulator 1 (REG1)
41-43 Load 300 Input current detection part (input current monitoring means)
301 Input current detection resistor (low resistance)
304 Output current detection resistor (output current monitoring means)
305 Equivalent load 330 AD converter (input voltage monitoring means, input current monitoring means, output current monitoring means)
400 FET
AMP1 amplifier (input current monitoring means)
AMP2 amplifier (output current monitoring means)

Claims (11)

A switching regulator that converts the input voltage into an output voltage corresponding to the load, outputs the output voltage, and supplies power to the load; and
Input voltage monitoring means for monitoring the input voltage to the switching regulator;
An input current monitoring means for monitoring an input current to the switching regulator;
Based on the input voltage and the input current, input power calculation means for calculating input power to the switching regulator;
Power determination means for determining whether or not the input power calculated after outputting the output voltage exceeds a predetermined target power consumption;
When it is determined that the input power exceeds a predetermined target power consumption, an operation mode control means for transitioning the operation mode of the switching regulator to an operation mode in which the input power becomes smaller;
A power supply apparatus comprising:   2. The power supply device according to claim 1, wherein in the operation mode of the switching regulator, an operation mode capable of outputting an output current in a state in which a current-power efficiency distribution characteristic of the switching regulator is favorable is set as a default operation mode. Average power consumption calculating means for calculating the average power consumption in the switching regulator,
The operation mode control means operates the switching regulator so as to reduce an instantaneous current consumption in the switching regulator without changing an average power consumption in the switching regulator. Power supply. Average power consumption calculating means for calculating the average power consumption in the switching regulator,
The operation mode control means operates the switching regulator so as to increase an instantaneous current consumption in the switching regulator without changing an average power consumption in the switching regulator. Power supply. Load resistance adjusting means for adjusting load resistance in the load,
3. The power supply device according to claim 1, wherein the operation mode control unit operates the switching regulator so as to increase the load resistance from a normal state and increase an instantaneous current consumption in the switching regulator. .   The input current monitoring means connects a low resistance having a low resistance value in series with an input power supply path which is a path through which input power is supplied to the switching regulator, and amplifies a potential difference generated at the low resistance. The power supply device according to any one of claims 1 to 5, wherein the input current is a result of AD conversion of an amplified potential difference. The input power supply path includes a FET connected in parallel to the low resistance,
The power supply device according to claim 6, wherein when the input current is not monitored, a current flowing through the low resistance is bypassed to the FET. Output current monitoring means for monitoring the output current of the switching regulator;
Output current determination means for determining whether or not the output current is abnormal;
The power supply device according to claim 1, further comprising:   The power supply device according to claim 8, further comprising: a power supply stop unit that stops supply of power to the load when it is determined that the output current is abnormal.   The operation mode control means causes the operation mode of the switching regulator to transition to an operation mode in which the output current becomes smaller when the output current exceeds a predetermined peak value. The power supply device described in 1.   The operation mode control means sets the operation mode of the switching regulator when the output current exceeds a predetermined threshold value of the output current for each frequency so that the current value at a frequency exceeding the threshold value is smaller. The power supply device according to claim 10, wherein transition is made to an operation mode.

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