JP2011096172A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To interconnect a plurality of masters and slaves with low latency and at a low cost. <P>SOLUTION: The semiconductor device has a transfer system circuit (13) including first interfaces (201, 301) to be used for data transfer and second interfaces (202, 302) to be used for transferring a signal for arbitrating contention at data transfer. The first interface includes parallel/serial conversion circuits (132, 142) for converting parallel data to serial data. The transfer speed of the data output from the parallel/serial conversion circuit is set higher than the signal transfer speed in the second interface. The second interface includes arbiters (133, 143) for arbitrating contention at data transfer from a plurality of transmitting circuits. After arbitration of the arbiters, a large amount of data can be transferred through the first interfaces. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a semiconductor device and further to an interconnect technology between circuit blocks in the semiconductor device.

  A technology for connecting electronic circuit components to each other is called an interconnect technology. This interconnect technology includes a technology for connecting circuit blocks on a semiconductor chip. A technology for mounting many functions on one semiconductor chip is called a system-on-chip (SoC). In this SoC, the processing performance of the entire system is often determined by the interconnection between circuit blocks built on a semiconductor chip. Therefore, in designing the SoC, it is extremely important how to design an interconnect between circuit blocks. Interconnects have evolved from parallel to serial, and 1-16 bit serial interconnects operating at several GHz, such as PCI Express and Serial Advanced Technology Attachment (SATA), are widely used as industry standards.

  Japanese Patent Laid-Open No. 2004-133867 discloses a technique for operating a bus arbitration request and a bus arbitration response at high speed and operating data / address at a low speed, and for handling a bus arbitration request with priority at high speed. The technology is described.

No. 2000-250851

  According to the conventional serial interconnect, it is difficult to arbitrate when a plurality of masters simultaneously access to one slave simultaneously. For example, PCI Express and SATA are one-to-one interconnects. Therefore, when connecting a plurality of masters and slaves, it is necessary to interpose a “hub” having a plurality of interconnects. Since the hub once captures the packets received from these interfaces and retransmits them, it takes a long time to pass the packets. In addition, since a large-capacity buffer for storing received packets is required, it is difficult to reduce manufacturing costs. Such a problem is not taken into consideration in Patent Document 1.

  An object of the present invention is to provide a technique for realizing an interconnect for connecting a plurality of masters and slaves with low latency and low cost.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  The following is a brief description of an outline of typical inventions disclosed in the present application.

  That is, a semiconductor device includes a plurality of transmission side circuits, a reception side circuit that receives output data of the transmission side circuit, and a transfer system circuit interposed between the transmission side circuit and the reception side circuit. Composed. At this time, the transfer system circuit uses a first interface used for data transfer from the transmission side circuit to the reception side circuit, and a signal for arbitrating competition of data transfer from the plurality of transmission side circuits. And a second interface used for transmission. The first interface includes a parallel / serial conversion circuit that converts parallel data from the transmission side circuit into a serial format, and the transfer rate of output data of the parallel / serial conversion circuit is the second interface. It is set to be higher than the signal transmission speed in. The second interface includes an arbiter that arbitrates contention of data transfer from the plurality of transmission side circuits based on a signal output in parallel form from the transmission side circuit.

  According to the above configuration, since a large amount of information can be transferred from the transmission side circuit to the reception side circuit by the first interface, low latency and high throughput are realized in communication from the transmission side circuit to the reception side circuit. can do. Further, according to the above configuration, a large-capacity buffer for storing received packets becomes unnecessary, which achieves a reduction in the cost of the semiconductor device.

  The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows.

  In other words, it is possible to provide a technique for realizing an interconnect for connecting a plurality of masters and slaves with low latency and low cost.

1 is a block diagram illustrating a configuration example of an SoC as an example of a semiconductor device according to the present invention. It is a block diagram of a configuration example of a request packet transfer system circuit in the SoC. It is a block diagram of a configuration example of a response packet transfer system circuit in the SoC. It is a circuit diagram of a basic configuration example of a common clock system. It is a circuit diagram of a basic configuration example of the source synchronization method. FIG. 3 is a circuit diagram of a configuration example of an address decoder and a parallel / serial conversion circuit in the request packet transfer system circuit. It is a circuit diagram of a configuration example of a repeater in the request packet transfer system circuit. It is a block diagram of a configuration example of a serial-parallel conversion circuit in the request packet transfer system circuit. It is a circuit diagram of a configuration example of a shift register included in the serial-parallel conversion circuit. It is an operation | movement timing diagram of the principal part in the said SoC. It is another operation | movement timing diagram of the principal part in the said SoC. It is explanatory drawing of each signal in request packet transfer. It is explanatory drawing of each signal in response packet transfer. It is explanatory drawing of the connection state of an initiator and a target. It is a block diagram which shows another structural example of the said SoC. FIG. 16 is an operation timing chart of the main part in the configuration shown in FIG. 15. It is an operation | movement timing diagram of the principal part in another structural example of the said SoC. It is explanatory drawing of each signal in request packet transfer. It is explanatory drawing of each signal in response packet transfer.

1. First, an outline of a typical embodiment of the invention disclosed in the present application will be described. Reference numerals in the drawings referred to in parentheses in the outline description of the representative embodiments merely exemplify what are included in the concept of the components to which the reference numerals are attached.

  [1] A semiconductor device (10) according to a typical embodiment of the present invention includes a plurality of transmission side circuits (11, 12) and reception side circuits (14, 15) that receive output data of the transmission side circuit. And a transfer system circuit (13) interposed between the transmission side circuit and the reception side circuit. At this time, the transfer system circuit uses a first interface (201, 301) used for data transfer and a signal used for arbitrating data transfer contention from the plurality of transmission side circuits. 2 interfaces (202, 302). The first interface includes a parallel / serial conversion circuit (132, 142, 152, 162) for converting parallel format data from the transmission side circuit into a serial format, and output data of the parallel / serial conversion circuit. The transfer speed is set to be higher than the signal transmission speed in the second interface. The second interface includes an arbiter (133, 143, 153, 163) that arbitrates contention of data transfer from the plurality of transmission side circuits based on a signal output in parallel form from the transmission side circuit.

  [2] In the above [1], a selector (134, 145, 154, 164) for selectively transmitting an output signal of the parallel-serial conversion circuit to a subsequent circuit, and a subsequent stage of the selector, Repeaters (135, 145, 155, 165) for shaping the waveform of the output signal of the selector can be provided.

  [3] In the above [2], the parallel-serial conversion circuit is configured to select the parallel-format data sequentially to form a serial-format information transmission signal (132F), and the selection circuit selection operation And a flip-flop circuit (132D) for generating a control signal capable of controlling the above.

  [4] In the above [3], a serial / parallel conversion circuit (136, 146, 156, 166) for converting the output signal of the repeater into parallel format data can be arranged after the repeater.

[5] In the above [3], a first clock generation circuit (16) for generating a first clock signal and a second clock signal having a frequency higher than that of the first clock signal based on the first clock signal. A second clock generation circuit (132G) to be formed can be provided. In this case, transmission of a signal for arbitrating data transfer contention from the plurality of transmission side circuits is performed in synchronization with the first clock signal by a common clock method,
The output data of the selection circuit is transferred in synchronization with the second clock signal by the source synchronization method.

  [6] In the above [5], the wiring in the first interface can be made thinner than the wiring in the second interface.

  [7] In the above [5], the second clock generation circuit may include a PLL circuit that forms the second clock signal by multiplying the first clock signal.

  [8] In the above [5], the serial / parallel conversion circuit may be configured to convert the output signal of the repeater into parallel data in synchronization with the second clock signal.

  [9] In the above [3], a clock generation circuit (16) for generating a clock signal having a predetermined frequency is provided, and signal transmission for arbitrating data transfer contention from the plurality of transmission side circuits is performed in the above-described manner. The output data of the selection circuit can be transferred in synchronization with the waveform rising edge and the waveform falling edge of the clock signal.

  [10] In the above [8], a plurality of the reception side circuits are provided, and the arbiter (133, 143) can select one of the plurality of reception side circuits by decoding the input address signal. A decoder can be included.

2. Details of Embodiments Embodiments will be further described in detail.

<Embodiment 1>
FIG. 1 shows a SoC (System On a Chip) as an example of a semiconductor device according to the present invention. The SoC 10 includes, but is not limited to, initiators 11 and 12, a packet transfer system circuit 13, targets 14 and 15, and a low-speed clock generation unit 16. One of a single crystal silicon substrate and the like can be formed by a known semiconductor integrated circuit manufacturing technique. Formed on a semiconductor substrate. The initiators 11 and 12 are devices that issue commands to devices connected according to the SCSI (Small Computer System Interface) standard, and are, for example, masters such as a CPU (Central Processing Unit). The targets 14 and 15 are devices that receive instructions from the initiators 11 and 12, and are slaves such as semiconductor memories. For example, the initiator 11 (or 12) transmits a request packet (access request) to the target 14 (or 15), and the target 14 (or 15) transmits a response packet (access response) to the initiator 11 (or 12). By doing so, transfer is performed. The packet transfer system circuit 13 performs packet transfer between the initiators 11 and 12 and the targets 14 and 15. Such a packet transfer system circuit 13 includes a request packet transfer system circuit 13A and a response packet transfer system circuit 13B. The request packet transfer circuit 13A transfers the request packet from the initiator 11 or 12 to the target 14 or 15. The response packet transfer system circuit 13B transfers the response packet from the initiator 11 or 12 to the initiator 11 or 12. Arbitration of request packets from the initiators 11 and 12 is performed by the request packet transfer system circuit 13A, and arbitration of response packets from the targets 14 and 15 is performed by the response packet transfer system circuit 13B. The low-speed clock generation unit 16 forms a low-speed clock signal that is a basic clock signal of the SoC 10. This low-speed clock signal is transmitted to the initiators 11 and 12, the packet transfer system circuit 13, and the targets 14 and 15.

  FIG. 2 shows a configuration example of the request packet transfer circuit 13A.

  The request packet transfer circuit 13A includes address decoders 131 and 141, parallel / serial conversion circuits 132 and 142, arbiters 133 and 143, selectors 134 and 144, repeaters 135 and 145, and serial / parallel conversion circuits 136 and 146.

  The initiators 11 and 12 include an access request transmission signal req, an address signal add, an access request end signal eop, an exclusive control request signal lck, an access priority signal pri, an access type signal opc, write data data, a byte enable signal be, and an access An original identifier signal src and an access identifier signal tid are output.

  The address decoder 131 takes in the access request transmission signal req and the address signal add from the initiator 11 and decodes them to generate access request signals for the arbiters 133 and 143. An access request signal for the arbiter 133 is transmitted to the arbiter 133, and an access request signal for the arbiter 143 is transmitted to the arbiter 143.

  The address decoder 141 takes in the access request transmission signal req and the address signal add from the initiator 12 and decodes them to generate access request signals for the arbiters 133 and 143. An access request signal for the arbiter 133 is transmitted to the arbiter 133, and an access request signal for the arbiter 143 is transmitted to the arbiter 143.

  The parallel / serial conversion circuit 132 takes in the access request transmission signal req, the address signal add, the access type signal opc, the write data data, the byte enable signal be, the access source identifier signal src, and the access identifier signal tid from the initiator 11. The information transmission signal CAD synchronized with the high-speed clock signal is formed. The formed information transmission signal CAD is transmitted to the selectors 134 and 144.

  The parallel / serial conversion circuit 142 receives the access request transmission signal req, the address signal add, the access type signal opc, the write data data, the byte enable signal be, the access source identifier signal src, and the access identifier signal tid from the initiator 12. The information transmission signal CAD synchronized with the high-speed clock signal is formed. The formed information transmission signal CAD is transmitted to the selectors 134 and 144.

  The arbiter 133 corresponds to the target 14 and has a function of arbitrating access requests from the initiators 11 and 12 to the target 14. An access request is made to the arbiter 133 from the address decoders 131 and 141. The arbiter 133 receives the access request end signal eop, the exclusive control request signal lck, and the access priority signal pri from the initiators 11 and 12. The arbiter 133 arbitrates when an access request to the target 14 conflicts. In this arbitration, it is determined whether or not other initiators are excluded by the exclusive control request signal lck, and the priority of the access is determined. The arbiter 133 forms an access permission signal to the parallel / serial conversion circuits 132 and 142 and a selection signal to the selector 134 based on the arbitration result. For example, when the access request from the initiator 11 is given priority, the access permission signal to the parallel / serial conversion circuit 132 is asserted, and the information transmission signal CAD from the parallel / serial conversion circuit 132 is selectively selected by the selector 134. Is transmitted to the repeater 135. When the access request from the initiator 12 is given priority, the access permission signal to the parallel / serial conversion circuit 142 is asserted, and the selector 134 selects the information transmission signal CAD from the parallel / serial conversion circuit 142. Is transmitted to the repeater 135.

  Based on the selection signal from the arbiter 133, the selector 134 selectively transmits the information transmission signal CAD from the parallel / serial conversion circuits 132 and 142 to the repeater 135 at the subsequent stage. The repeater 135 shapes the information transmission signal CAD transmitted from the selector 134 and transmits the signal to the serial / parallel conversion circuit 136.

  The arbiter 143 corresponds to the target 15 and has a function of arbitrating access requests from the initiators 11 and 12 to the target 15. The arbiter 143 receives an access request signal from the address decoders 131 and 141. The arbiter 143 receives an access request end signal eop, an exclusive control request signal lck, and an access priority signal pri from the initiators 11 and 12. The arbiter 143 arbitrates when an access request to the target 15 conflicts. In this arbitration, it is determined whether or not other initiators are excluded by the exclusive control request signal lck, and the priority of the access is determined. The arbiter 143 forms an access permission signal to the parallel / serial conversion circuits 132 and 142 and a selection signal to the selector 144 based on the arbitration result. For example, when the access request from the initiator 11 is given priority, the access permission signal to the parallel / serial conversion circuit 132 is asserted, and the information transmission signal CAD from the parallel / serial conversion circuit 132 is selectively selected by the selector 144. Is transmitted to the repeater 145. When the access request from the initiator 12 has priority, the access permission signal to the parallel / serial conversion circuit 142 is asserted, and the information transmission signal CAD from the parallel / serial conversion circuit 142 is selected by the selector 144. Is transmitted to the repeater 145.

  Based on the selection signal from the arbiter 143, the selector 144 selectively transmits the information transmission signal CAD from the parallel / serial conversion circuits 132 and 142 to the subsequent repeater 145. The repeater 145 shapes the information transmission signal CAD transmitted from the selector 144 and transmits the signal to the serial / parallel conversion circuit 146.

  The serial / parallel conversion circuit 136 exchanges an access request transmission signal req, an access permission signal gnt, and an access end signal eop with the arbiter 133 and the target 14. The serial / parallel conversion circuit 136 converts the information transmission signal CAD transmitted from the repeater 135 into parallel data. The signals obtained by this conversion, that is, the address signal add, the access type signal opc, the write data data, the byte enable signal be, the access source identifier signal src, and the access identifier signal tid are transmitted to the target 14.

  The serial / parallel conversion circuit 146 exchanges an access request transmission signal req, an access permission signal gnt, and an access end signal eop with the arbiter 143 and the target 15. The serial / parallel conversion circuit 146 converts the information transmission signal CAD transmitted from the repeater 145 into parallel data. The signals obtained by this conversion, that is, the address signal add, the access type signal opc, the write data data, the byte enable signal be, the access source identifier signal src, and the access identifier signal tid are transmitted to the target 15.

  The high speed side interface 201 is formed including the parallel / serial conversion circuits 132 and 142, and the low speed side interface 202 is formed including the arbiters 133 and 143.

  FIG. 3 shows a configuration example of the response packet transfer circuit 13B.

  The response packet transfer system circuit 13B includes source decoders 151 and 161, parallel / serial conversion circuits 152 and 162, an arbiter 153, a selector 154, a repeater 155, and serial / parallel conversion circuits 156 and 166.

  The targets 14 and 15 output an access request signal r_req, an access source identifier signal r_src, an access end signal r_eop, an access response type signal r_opc, read data r_data, and an access identifier signal r_tid.

  The source decoder 151 takes in the access request signal r_req and the access source identifier signal r_src from the target 14 and decodes them to generate access request signals for the arbiters 153 and 163. An access request signal for the arbiter 153 is transmitted to the arbiter 153, and an access request signal for the arbiter 163 is transmitted to the arbiter 163.

  The source decoder 161 takes in the access request signal r_req and the access source identifier signal r_src from the target 15 and decodes them to generate access request signals for the arbiters 153 and 163. An access request signal for the arbiter 153 is transmitted to the arbiter 153, and an access request signal for the arbiter 163 is transmitted to the arbiter 163.

  The parallel / serial conversion circuit 152 takes in the access response transmission signal r_req, the access source identifier signal r_src, the access response type signal r_opc, the read data r_data, and the access identifier signal r_tid from the target 14 and transmits the information transmission signal to the high-speed clock signal. R_CAD is formed. The formed information transmission signal R_CAD is transmitted to selectors 154 and 164.

  The arbiter 153 corresponds to the initiator 11 and has a function of arbitrating access requests from the targets 14 and 15 to the initiator 11. An access request signal is transmitted from the source decoders 151 and 161 to the arbiter 153, and an access response end signal r_eop is transmitted from the targets 14 and 15. The arbiter 153 generates an access permission signal to the parallel / serial conversion circuits 152 and 162 and a selection signal to the selector 154 based on the arbitration result of the access request to the initiator 11.

  Based on the selection signal from the arbiter 153, the selector 154 selectively transmits the information transmission signal R_CAD from the parallel / serial conversion circuits 152 and 162 to the repeater 155 at the subsequent stage. The repeater 155 shapes the information transmission signal R_CAD transmitted from the selector 154 and transmits the signal to the serial / parallel conversion circuit 136.

  The arbiter 163 corresponds to the initiator 12 and has a function of arbitrating access requests from the targets 14 and 15 to the initiator 12. The arbiter 163 receives the access request signal from the source decoders 151 and 161 and the access response end signal r_eop from the targets 14 and 15. The arbiter 163 forms an access permission signal to the parallel / serial conversion circuits 152 and 162 and a selection signal to the selector 164 based on the arbitration result of the access request to the initiator 12.

  Based on the selection signal from the arbiter 163, the selector 164 selectively transmits the information transmission signal R_CAD from the parallel / serial conversion circuits 152 and 162 to the repeater 165 at the subsequent stage. The repeater 165 shapes the information transmission signal R_CAD transmitted from the selector 164 and transmits the signal to the serial / parallel conversion circuit 166.

  The serial / parallel conversion circuit 156 exchanges an access request signal r_req, an access permission signal r_gnt, and an access end signal r_eop with the arbiter 153 and the initiator 11. The serial / parallel conversion circuit 156 converts the information transmission signal R_CAD transmitted from the repeater 155 into parallel data. Each signal obtained by this conversion, that is, an access source identifier signal r_src, an access response type signal r_opc, read data r_data, and an access identifier signal r_tid are transmitted to the initiator 11.

  The serial / parallel conversion circuit 166 exchanges an access request signal r_req, an access permission signal r_gnt, and an access end signal r_eop with the arbiter 163 and the initiator 12. The serial / parallel conversion circuit 156 converts the information transmission signal R_CAD transmitted from the repeater 155 into parallel data. Each signal obtained by this conversion, that is, an access source identifier signal r_src, an access response type signal r_opc, read data r_data, and an access identifier signal r_tid are transmitted to the initiator 11.

  The high speed side interface 301 is formed including the parallel / serial conversion circuits 152 and 162, and the low speed side interface 302 is formed including the arbiters 153 and 163.

  Here, a synchronization method in packet transfer performed in the request packet transfer system circuit 13A and the response packet transfer system circuit 13B will be described.

  As a synchronization method in data transfer, a common clock method and a source synchronization method can be exemplified.

  In the common clock system, for example, as illustrated in FIG. 4, the data transmission side circuit 401 and the reception side circuit 402 operate by receiving the same clock signal from the common clock generation unit 403. However, in a circuit having a high operating frequency, there is a risk that a difference in data occurs at the timing of data transfer. Therefore, the source synchronization method is used in higher-speed circuits. In this source synchronization method, for example, as shown in FIG. 5, the clock signal generated by the clock generation unit 503 is transmitted from the transmission side circuit 501 in parallel with the data and received by the reception side circuit 502 with the same delay time. Is done. Since the timing of the data signal with respect to the clock signal generated by the clock generation unit 503 is directly transmitted to the reception side circuit 502, good data transfer is possible. In this example, the signals of the low speed side interfaces 202 and 302 are transmitted by the common clock method, and the signals of the high speed side interfaces 201 and 301 are transferred by the source synchronous method. For example, when the transmission side circuit 401 is the initiator 11 or 12, the reception side circuit 402 is the target 14 or 15. For example, when the transmission side circuit 501 is the parallel-serial conversion circuit 132 or 142, the reception side circuit 502 is the repeater 135 or 145. When the transmission side circuit 501 is the repeater 135 or 145, the reception side circuit 502 is the serial / parallel conversion circuit 136 or 146. In the request packet transfer circuit 13A shown in FIG. 2, the signals of the low-speed interface 202 include signals necessary for arbitration of access requests, that is, an access request transmission signal req, an access request permission signal gnt, and an access request. An end signal eop, an exclusive control request signal lck, and an access priority signal pri are included. In the request packet transfer circuit 13A shown in FIG. 2, the signal of the high speed side interface 201 includes an information transmission signal CAD for performing information transmission. In the response packet transfer system circuit 13B shown in FIG. 3, the signals of the low-speed interface 302 include signals necessary for arbitrating access requests, that is, an access response transmission signal r_req, an access response permission signal r_gnt, and an access response. An end signal r_eop is included, and a signal of the high speed side interface 301 includes an information transmission signal R_CAD. In the common clock method, the low-speed clock signal generated by the low-speed clock generation unit 16 is used, and in the source synchronous method, the high-speed clock signal generated based on the low-speed clock signal is used.

  FIG. 6 shows a configuration example of the address decoder 131 and the parallel / serial conversion circuit 132.

  The address decoder 131 includes 2-input AND gates 131A and 131B. In the AND gates 131A and 131B, an access request signal is formed by performing a logical operation on the access request transmission signal req from the initiator 11 and the 39th bit address signal add [39] from the initiator 11. It has become so. According to this configuration, the access request signal to the arbiter 133 and the access request signal to the arbiter 143 are selectively asserted according to the logic of the address signal add [39] of the 39th bit.

  The parallel / serial conversion circuit 132 includes a gnt generation circuit 132A, an addition circuit 132B, a control signal selection circuit 132C, a flip-flop circuit 132D, a strobe generation circuit 132E, a selection circuit 132F, and a high-speed clock generation unit 132G.

  The high-speed clock generation unit 132G is, for example, a PLL (Phase Locked Loop) circuit, and synchronizes with the low-speed clock signal by multiplying the low-speed clock signal generated by the low-speed clock generation unit 16, and the low-speed clock signal A high-speed clock signal having a higher frequency than the signal is formed. The formed high-speed clock signal is transmitted to the flip-flop circuit 132D, the selectors 134 and 144, etc. for source synchronization. The gnt generation circuit 132A is a circuit that determines whether or not data can be transmitted based on the access request transmission signal req and the access permission signal. The serial / parallel conversion circuit 156 has data for one cycle of the low-speed clock signal. Can be transmitted, the access request permission signal gnt is set to the high level. The adder circuit 132B adds “1” to the output signal of the flip-flop circuit 132D. The control signal selection circuit 132C selects the output signal of the adder circuit 132B when the access request permission signal gnt is high level, and selects the output signal of the flip-flop circuit 132D when the access request permission signal gnt is low level. The flip-flop circuit 132D takes in the output signal of the control signal selection circuit 132C in synchronization with the high-speed clock signal. The output signal of the flip-flop circuit 132D is a 3-bit control signal. This 3-bit control signal is transmitted to the selection circuit 132F and the strobe generation circuit 132E. The strobe generation circuit 132E forms a strobe signal strobe indicating the validity of the output signal of the parallel / serial conversion circuit 132. When the 3-bit control signal is “000”, the strobe signal strobe is at a low level, and when the 3-bit control signal is other than “000”, the strobe signal strobe is at a high level. The strobe signal strobe is transmitted to the selectors 134 and 144. The selection circuit 132F sequentially converts parallel output signals from the initiator 11 into serial signals according to the output signals of the flip-flop circuit 132D. By the selection operation of the selection circuit 132F, an information transmission signal CAD [31: 0] having a 32-bit configuration is formed. This information transmission signal CAD [31: 0] is transmitted to the selectors 134 and 144.

  Here, the parallel output signals from the initiator 11 are added [39:28], 0, add [27: 4], opc [7: 0], data [127: 96], data [95:64], data. [63:32], data [31: 0], be [15: 0], src [7: 0], and tid [7: 0], the information transmission signal CAD [31: 0] is as follows: It is formed.

  When the control signal is “001”, the information transmission signal CAD [31: 0] is set to add [39:28], 0. When the control signal is “010”, the information transmission signal CAD [31: 0] is the add [27: 4], opc [7: 0] information transmission signal CAD [31: 0] when the control signal is “011”. ] Is data [127: 96]. When the control signal is “100”, the information transmission signal CAD [31: 0] is set to data [95:64]. When the control signal is “101”, the information transmission signal CAD [31: 0] is set to data [63:32]. When the control signal is “110”, the information transmission signal CAD [31: 0] is set to data [31: 0]. When the control signal is “111”, the information transmission signal CAD [31: 0] is set to be [15: 0], src [7: 0], and tid [7: 0].

  The address decoder 141 has the same configuration as the address decoder 131, and the parallel / serial conversion circuit 142 has the same configuration as the parallel / serial conversion circuit 132. The source decoders 151 and 161 can be configured in the same manner as the address decoder 131, and the parallel / serial conversion circuits 152 and 162 can be configured in the same manner as the parallel / serial conversion circuit 132.

  FIG. 7 shows a configuration example of the repeater 135.

  The repeater 135 is formed by combining flip-flop circuits 135A and 135B and inverters 135C and 135D. The output signal of the flip-flop circuit 135A is transmitted to the data input terminal D of the subsequent flip-flop circuit 135B. Inverters 135C and 135D are connected in series with each other. The output of the inverter 135C is transmitted to the clock input terminal of the flip-flop circuit 135A, and the output of the inverter 135D is transmitted to the clock input terminal of the flip-flop circuit 135B. One bit of the strobe signal strob or the information transmission signal CAD [31: 0] is transmitted to the data input terminal of the flip-flop circuit 135A through the selector 134. A high-speed clock signal is transmitted to the inverter 135C via the selector 134. Such a circuit configuration is provided as many as the number of input signals to the repeater 135. In this example, since the strobe signals strob and CAD [31: 0] are transmitted via the selector 134, 33 circuits formed by coupling the flip-flop circuits 135A and 135B and the inverters 135C and 135D are provided. In each circuit, waveform shaping of the corresponding input signal is performed.

  The other repeaters 145, 155, and 165 may have the same configuration as the repeater 135.

  FIG. 8 shows a configuration example of the serial / parallel conversion circuit 136.

  The serial / parallel conversion circuit 136 includes shift registers 136A, 136B, 136C, and 136D, a write control circuit 136E, a read selection circuit 136F, a read control circuit 136G, and an access permission signal generation circuit 136H. Strobe signals strobe, CAD [31: 0], and a high-speed clock signal are transmitted to the shift registers 136A, 136B, 136C, and 136D through the repeater 135. A mask signal is transmitted from the write control circuit 136E to the shift registers 136A, 136B, 136C, and 136D. The shift registers 136A, 136B, 136C, and 136D are masked for writing by the mask signal. A strobe signal strobe and a high-speed clock signal are transmitted to the write control circuit 136E through the repeater 135. The write control circuit 136E changes the value of the mask signal each time data for one cycle of the low-speed clock signal is transmitted to the shift registers 136A, 136B, 136C, and 136D, thereby changing the shift registers 136A, 136B, Control is performed so that writing is performed in the order of 136C and 136D. The read selection circuit 136F selects the output signals of the shift registers 136A, 136B, 136C, and 136D based on the read control signal 136G, thereby adding [39:28], 0, add [27: 4], opc. [7: 0], data [127: 96], data [95:64], data [63:32], data [31: 0], be [15: 0], src [7: 0], tid [ 7: 0]. An access request transmission signal req, an access permission signal gnt, and an access end signal eop are transmitted to the read control circuit 136G. The read control circuit 136G changes the value of the read control signal every time data of one cycle of the low-speed clock signal is read, so that the read is performed in the order of the shift registers 136A, 136B, 136C, and 136D. Control. The access permission signal generation circuit 136H sets the access permission signal to a high level when the serial / parallel conversion circuit 136H can receive data. The access permission signal generation circuit 136H calculates the amount of transmitted data based on the access request transmission signal req and the access permission signal gnt, and calculates the received data amount based on the access request signal and the access end signal. measure. If the difference between the transmitted data amount and the received data amount is within a certain value, the access permission signal is asserted. In this example, since the shift registers 136A, 136B, 136C, and 136D can hold data for four cycles of the low-speed clock signal, the access permission signal is negated when data for four cycles of the low-speed clock signal is received. Like to do. When the received data amount is larger than the transmitted data amount, the access request signal erq is asserted.

  The serial / parallel conversion circuit 146 has the same configuration as the serial / parallel conversion circuit 136. The other serial / parallel conversion circuits 156 and 166 can be configured in the same manner as the serial / parallel conversion circuit 136.

  FIG. 9 shows a configuration example of the shift register 136A.

  The shift register 136A includes a two-input AND gate 901 and flip-flop circuits 902 to 908 each having an enable terminal. An AND logic between the mask signal and the strobe signal strobe is obtained by the AND gate 901, and an output signal of the AND gate 901 is transmitted to the enable terminals EN of the flip-flop circuits 902 to 908. CAD [31: 0] is transmitted to the data input terminal D of the flip-flop circuit 902, and the high-speed clock signal is transmitted to the clock input terminal of the flip-flop circuit 902. When the enable terminals EN of the flip-flop circuits 902 to 908 are set to the high level, the value of the data output terminal Q is updated with the value of the data input terminal D in synchronization with the waveform rising edge of the high-speed clock signal. When the enable terminal EN of the flip-flop circuits 902 to 908 is at a low level, the value of the data output terminal Q is not updated.

  The other shift registers 136B, 136C, and 136D may have the same configuration as the shift register 136.

  FIG. 10 shows the operation timing of the main part in the request packet transfer circuit 13A.

  Signals related to access request, access permission, and access termination, that is, req, gnt, eop and r_req, r_gnt, r_eop are generated by the low-speed clock signal generated by the low-speed clock generation unit 16 by the common clock method (see FIG. 4). Synchronously transmitted to the subsequent circuit. In contrast, the information transmission signals CAD and R_CAD are transferred to the subsequent circuit in synchronization with the high-speed clock signal generated by the high-speed clock generation unit 132G by the source synchronization method (see FIG. 5).

  According to the first embodiment, the following operational effects are obtained.

  (1) In general, a signal synchronized with a low-speed clock signal is relatively easy to process in a circuit, but the amount of information that can be transmitted within a predetermined time is small. On the other hand, a signal synchronized with a high-speed clock signal is difficult to handle, but a large amount of information can be transmitted within a certain time. Therefore, in the request packet transfer system circuit 13A and the response packet transfer system circuit 13B, the high-speed interfaces 201 and 301 used for data transfer from the transmission side to the reception side, respectively, and arbitration of the data transfer contention. Low-speed interfaces 202 and 302 used for signal transmission are provided. The high-speed interfaces 201 and 301 transfer data in synchronization with the high-speed clock signal, and the low-speed interfaces 202 and 302 transmit signals for arbitration in synchronization with the low-speed clock signal. The high-speed interfaces 201 and 301 include parallel / serial conversion circuits 132, 142, 152, and 162 for converting parallel data into serial data. The transfer rate of the output data of the parallel / serial conversion circuit is set to be higher than the signal transmission rate in the low speed side interfaces 202 and 302. According to such a configuration, a signal for arbitration is transmitted to the low-speed interfaces 202 and 302, so that the data transfer contention is arbitrated. After this arbitration, a large amount of information can be transferred at high speed in the serial format via the high-speed interfaces 201 and 301. Therefore, low latency and high throughput can be realized in communication from the transmission side to the reception side. . Further, in such data transfer, there is no need to interpose a hub having a plurality of interconnects, so a large-capacity buffer for storing received packets becomes unnecessary, and the cost of the SoC 10 can be reduced. .

  (2) In the high-speed interfaces 201 and 301, the parallel-format data from the transmission-side circuit is converted into serial data by the parallel / serial conversion circuits 132, 142, 152, and 162, and transferred. By increasing the amount of information that can be transmitted within a unit time on a signal line, the number of signal lines used for data transfer can be reduced, thereby reducing the circuit scale. This is advantageous in reducing the cost of the SoC 10.

  Here, as signals in the request packet transfer, for example, as shown in FIG. 12, req, gnteoop, lck, pri [3: 0], add [39:16], add [15: 3], opc [7: 0], data [127: 0], be [15: 0], src [7: 0], and tid [7: 0] are present. In this case, according to the first embodiment, add [39:16], add [15: 3], opc [7: 0], data [127: 0], be [15: 0], src [7: 0], tid [7: 0] can be aggregated into CAD [31: 0], so that the signal used for data transfer is compared to the case where it is not aggregated into CAD [31: 0] (conventional method). The number of lines can be greatly reduced. As signals in response packet transfer, for example, as shown in FIG. 13, r_req, r_gnt, r_eop, r_src [7: 0], r_opc [7: 0], r_data [127: 0], r_tid [7: 0] exists, r_src [7: 0], r_opc [7: 0], r_data [127: 0], r_tid [7: 0] can be aggregated into CAD [31: 0]. According to this, the number of signal lines used for data transfer can be greatly reduced as compared with the case where the data is not aggregated into CAD [31: 0] (conventional method).

  (3) As described above, the high-speed interfaces 201 and 301 perform data transfer in synchronization with the high-speed clock signal, and the low-speed interfaces 202 and 302 transmit signals for arbitration in synchronization with the low-speed clock signal. Transmission is performed, and a signal transmitted via the low-speed interfaces 202 and 302 can be assigned to the upper layer wiring of the semiconductor substrate. In general, in the multilayer wiring of a semiconductor substrate, the wiring width is wider and the wiring thickness is thicker as the upper layer is higher. Therefore, the wiring resistance is small and the CR time constant is small. For this reason, by assigning a signal transmitted through the low speed side interfaces 202 and 302 to the upper wiring of the semiconductor substrate, it is possible to avoid an undesirably reduced transmission speed in the low speed side interfaces 202 and 302. .

  Further, as described above, when the signal transmitted through the low speed side interfaces 202 and 302 is assigned to the upper layer wiring of the semiconductor substrate, the signal transmitted through the high speed side interfaces 201 and 301 is transmitted to the semiconductor substrate. Cannot be assigned to upper layer wiring. As a result, the signal wiring for transmitting the signal transmitted via the high speed side interfaces 201 and 301 is narrower than the low speed side interfaces 202 and 302, and the wiring thickness is reduced. It gets thinner. For this reason, since the wiring resistance there increases, the CR time constant also increases. Therefore, the SoC 10 employs the source synchronization method (see FIG. 5) for the high-speed interfaces 201 and 301. Thereby, the high-speed clock signal generated by the high-speed clock generation unit 132G is transmitted from the transmission side in parallel with the information transmission signal CAD and received by the reception side with the same delay time. The information transmission signal CAD can be transferred without any trouble. Further, by thinning the wires as described above, more wires can be formed on the substrate.

  (4) When the inductive coupling (three-dimensional coupling) method as described in, for example, Japanese Patent Application Laid-Open No. 2005-228981 is employed, a large amount of wiring is required. Becomes prominent.

  (5) For example, in FIGS. 2 and 3, when the repeater is arranged on the input side of the selectors 134, 144, 154, 164, the repeater corresponds to the number of input terminals in the selectors 134, 144, 154, 164. Is required. On the other hand, as shown in FIGS. 2 and 3, when repeaters 135, 145, 155, and 165 are arranged at the subsequent stage of selectors 134, 144, 154, and 164, the number of repeaters is the same as the number of selectors. Since it is sufficient to provide, the number of selectors can be reduced.

<Embodiment 2>
For example, as shown in FIG. 14A, it is difficult to connect the initiator (I) and the target (T) completely one-to-one even with a serial interface having a small number of signal lines. If the number of initiators (I) is 100 and the number of targets (T) is 100, the number of bonds between the initiator (I) and the target (T) is 10,000 (= 100 × 100). Therefore, as shown in FIG. 14B, it is necessary to reduce the number of links by interposing a router (R) between the initiator (I) and the target (T). When there are a plurality of targets ahead of the router, since the target is specified by an address signal, it is necessary to fetch the address into the router.

  FIG. 15 shows a configuration example of the request packet transfer circuit 13A in the case where there are a plurality of targets ahead of the router as described above.

  The request packet transfer circuit 13A shown in FIG. 15 is greatly different from that shown in FIG. 2 in order that the router functions as a router, so that the arbiters 133 and 143 incorporate address decoders. Correspondingly, two targets 14 and 17 are provided. Also, request processing circuits 138 and 148 for processing the access request transmission signal are provided, but the address signal is not decoded here. The address signal is decoded by the arbiter 133, and the access request destination is determined to be the target 14 or 17 by the decoding result. Corresponding to the targets 14 and 17, serial / parallel conversion circuits 136 and 137 are provided. The serial / parallel conversion circuits 136 and 137 have the same configuration.

  FIG. 16 shows the operation timing of the main part in the request packet transfer system circuit 13A shown in FIG. As shown in FIG. 16, the upper bits of the address signal are transmitted to the arbiter 133 in synchronization with the low-speed clock signal, and the upper bits of the address signal are decoded by the decoder in the arbiter 133. An access request destination is determined based on the decoding result.

  Here, as signals in the request packet transfer, for example, as shown in FIG. 18, req, gnteoop, lck, pri [3: 0], add [39:16], add [15: 3], opc [7 : 0], data [127: 0], be [15: 0], src [7: 0], and tid [7: 0]. In this case, according to the second embodiment, req, gnteoop, lck, pri [3: 0], add [39:16] are transmitted in synchronization with the low-speed clock signal by the low-speed side interface 202 by the common clock method. Is done. On the other hand, add [15: 3], opc [7: 0], data [127: 0], be [15: 0], src [7: 0], and tid [7: 0] are CAD [31: 0]. And is transferred in synchronization with the high-speed clock signal by the high-speed interface 201. For this reason, in the configuration shown in FIG. 15 as well, the number of signal lines used for data transfer can be significantly reduced as compared with the case where the data is not consolidated into CAD [31: 0] (conventional method).

  Also in the response packet transfer system circuit 13B, as shown in FIG. 15, an address decoder is built in an arbiter having a function as a router, and two targets can be provided corresponding to the arbiter. In this case, as each signal in the response packet transfer, for example, as shown in FIG. 13, r_req, r_gnt, r_eop, r_src [7: 0], r_opc [7: 0], r_data [127: 0], r_tid [7 : 0] exists, r_src [7: 0] is transmitted by the low speed side interface 202 in synchronization with the low speed clock signal by the common clock method. r_opc [7: 0], r_data [127: 0], and r_tid [7: 0] are aggregated into CAD [31: 0] and transferred in synchronization with the high-speed clock signal by the high-speed interface 201. Therefore, also in the response packet transfer system circuit, the number of signal lines used for data transfer can be significantly reduced as compared with the case where the data is not aggregated into CAD [31: 0] (conventional method).

  Although the invention made by the present inventor has been specifically described based on the embodiments, it is needless to say that the present invention is not limited thereto and can be variously modified without departing from the gist thereof.

  For example, transmission of a signal for arbitrating data transfer contention from a plurality of initiators is performed in synchronization with the rising edge of the waveform of the low-speed clock signal, and transfer of output data of the selection circuit is performed by the low-speed clock signal. It may be performed in synchronization with the waveform rising edge and the waveform falling edge. For example, in the configuration shown in FIG. 6, a circuit that forms a clock signal in synchronization with the waveform rising edge and waveform falling edge of the low-speed clock signal generated by the low-speed clock generation unit 16 instead of the high-speed clock generation unit 132G. By providing, as shown in FIG. 11, CAD transfer can be performed in synchronization with the waveform rising edge and waveform falling edge of the low-speed clock signal. The same can be said when the configuration shown in FIG. 15 is adopted. That is, when the configuration shown in FIG. 15 is adopted, as shown in FIG. 17, the access destination is determined based on the decoding result of the higher address, and the waveform of the low-speed clock signal rises relative to the access destination. The CAD is transferred in synchronization with the edge and the waveform falling edge.

10 SoC
11, 12 Initiator 13 Packet transfer system circuit 13A Request packet transfer system circuit 13B Response packet transfer system circuit 14, 15 Target 16 Low speed clock generator 131, 141 Address decoder 131A, 131B AND gate 132, 142 Parallel / serial conversion circuit 132A gnt Generation circuit 132B Addition circuit 132C Control signal selection circuit 132D Flip-flop circuit 132E Strobe generation circuit 132F Selection circuit 132G High-speed clock generation unit 133, 143 Arbiter 134, 144 Selector 135, 145 Repeater 136, 146 Serial / parallel conversion circuit 136A, 136B, 136C, 136D Shift register 136E Write control circuit 136F Read selection circuit 136G Read Control circuit 136H Access permission signal generation circuit 151, 161 Source decoder 152, 162 Parallel / serial conversion circuit 153, 163 Arbiter 154, 164 Selector 155, 165 Repeater 155A, 155B Flip-flop circuit 156, 166 Serial / parallel conversion circuit 201, 301 High speed side interface 202, 302 Low speed side interface 902-907 Flip-flop circuit

Claims (10)

Multiple transmitter circuits,
A receiving circuit that receives output data of the transmitting circuit;
A transfer system circuit interposed between the transmission side circuit and the reception side circuit, and a semiconductor device comprising:
The transfer system circuit includes a first interface used for data transfer;
A second interface used to transmit a signal for arbitrating data transfer contention from the plurality of transmission-side circuits,
The first interface includes a parallel / serial conversion circuit that converts parallel data from the transmission side circuit into a serial format, and the transfer rate of output data of the parallel / serial conversion circuit is the second interface. Is set faster than the signal transmission speed in
2. The semiconductor device according to claim 1, wherein the second interface includes an arbiter that arbitrates contention for data transfer from the plurality of transmission side circuits based on a signal output in parallel form from the transmission side circuit. A selector for selectively transmitting the output signal of the parallel-serial conversion circuit to a subsequent circuit;
The semiconductor device according to claim 1, further comprising: a repeater that is arranged at a subsequent stage of the selector and performs waveform shaping of an output signal of the selector. The parallel-serial conversion circuit includes: a selection circuit that forms a serial-format information transmission signal by sequentially selecting the parallel-format data;
The semiconductor device according to claim 2, further comprising: a flip-flop circuit that forms a control signal capable of controlling a selection operation of the selection circuit.   4. The semiconductor device according to claim 3, wherein a serial / parallel conversion circuit for converting an output signal of the repeater into parallel format data is disposed at a subsequent stage of the repeater. A first clock generation circuit for generating a first clock signal;
A second clock generation circuit that forms a second clock signal having a frequency higher than that of the first clock signal based on the first clock signal;
Transmission of a signal for arbitrating data transfer contention from the plurality of transmission side circuits is performed in synchronization with the first clock signal by a common clock method,
4. The semiconductor device according to claim 3, wherein the output data of the selection circuit is transferred in synchronization with the second clock signal by a source synchronization method.   6. The semiconductor device according to claim 5, wherein the wiring in the first interface is made thinner than the wiring in the second interface.   6. The semiconductor device according to claim 5, wherein the second clock generation circuit includes a PLL circuit that forms the second clock signal by multiplying the first clock signal.   6. The semiconductor device according to claim 5, wherein the serial / parallel conversion circuit converts the output signal of the repeater into parallel data in synchronization with the second clock signal. Including a clock generation circuit for generating a clock signal of a predetermined frequency;
Transmission of a signal for arbitrating data transfer contention from the plurality of transmission side circuits is performed in synchronization with a waveform rising edge of the first clock signal,
4. The semiconductor device according to claim 3, wherein the output data of the selection circuit is transferred in synchronization with a waveform rising edge and a waveform falling edge of the clock signal. A plurality of the receiving side circuits are provided,
9. The semiconductor device according to claim 8, wherein the arbiter includes a decoder capable of selecting one of the plurality of receiving side circuits by decoding an input address signal.

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