JP2011095965A - Electronic apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an electronic apparatus that adjusts a clock skew between digital circuits at low cost. <P>SOLUTION: The electronic apparatus includes: a phase adjustment circuit 12 which delays a first clock signal CK1, and generates a second clock signal; a control circuit 15 which operates synchronously with the first clock signal CK1; a control circuit 25 which operates synchronously with a second clock signal CK2, and inputs/outputs data to/from the control circuit 15; a synchronization decision unit 153 which determines synchronization between the control circuits 15 and 25; and a delay quantity control unit 141 which determines the delay quantity of the second clock signal CK2 based on the determination result. The phase adjustment circuit 12 includes: a gate circuit 120 which delays the first clock signal CK1; and a power supply circuit 121 which supplies a power supply voltage based on the delay quantity to the gate circuit 120, and a clock skew between the control circuits 15 and 25 is suppressed by changing the power supply voltage of the gate circuit 120. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to an electronic device, and more particularly to an improvement of an electronic device capable of adjusting a clock skew between digital circuits.

  In general, when two digital circuits are operating in synchronization with the same clock signal, a phase difference occurs in the clock signal supplied to each digital circuit, and the phenomenon that synchronization between these digital circuits is lost, A so-called clock skew occurs. Data cannot be normally transferred between digital circuits in which clock skew has occurred. In order to eliminate such a clock signal phase difference, it is necessary to adjust the phase of the clock signal supplied to one of the digital circuits.

  The phase adjustment of the clock signal can be performed by delaying the clock signal by a time sufficiently shorter than the period. When the clock signal is low speed, the delay amount of the clock signal can be adjusted by using another high speed clock signal and delaying the low speed clock signal by a predetermined number of pulses of the high speed clock signal. .

  However, such a method cannot be taken when the clock signal is high-speed. For this reason, the phase of a clock signal is adjusted by adjusting the phase of a sine wave using a PLL (Phase Locked Loop) and converting the sine wave into a rectangular wave (for example, Patent Document 1). Further, the phase of the clock signal is adjusted by delaying the clock using a delay element and selecting one of the delay elements having different numbers of connections (for example, Patent Document 2).

JP 05-216556 JP 59-151219

  The phase adjustment method described in Patent Document 1 has a problem of high cost because the phase adjustment of the clock signal is performed by adjusting the phase of the sine wave using the PLL. Further, the phase adjustment method described in Patent Document 2 has a problem in that a large number of delay elements are connected in series and these delay elements are operated, leading to an increase in chip size and an increase in power consumption. Further, since the delay amount is adjusted by adjusting the number of delay elements connected, there is a problem that the delay amount cannot be adjusted continuously.

  SUMMARY An advantage of some aspects of the invention is that it provides an electronic device capable of adjusting a clock skew between digital circuits. In particular, an object of the present invention is to provide an electronic device that can easily adjust clock skew between digital circuits even when the frequency of a clock signal is high. It is another object of the present invention to provide phase adjustment of a clock signal with a simple configuration and to provide such an electronic device at low cost.

  An electronic device according to a first aspect of the present invention includes a clock generation circuit that generates a first clock signal, a semiconductor gate circuit that generates a second clock signal by delaying the first clock signal, and a first clock signal. A first digital circuit that operates, a second digital circuit that operates in synchronization with the second clock signal, and inputs / outputs data to / from the first digital circuit, and a synchronization between the first digital circuit and the second digital circuit Synchronization determination means for determining the delay amount, delay amount control means for determining the delay amount of the second clock signal based on the determination result, power supply voltage adjustment means for supplying a power supply voltage based on the delay amount to the semiconductor gate circuit, It is configured with.

  According to such a configuration, the delay in the semiconductor gate circuit is determined by determining the synchronization between the first digital circuit and the second digital circuit and controlling the power supply voltage supplied to the semiconductor gate circuit based on the determination result. The phase of the second clock signal can be adjusted by changing the amount. For this reason, even when the clock signal is high-speed, the clock skew of the first digital circuit and the second digital circuit can be suppressed without increasing the cost.

  According to a second aspect of the present invention, in addition to the above configuration, the power supply voltage adjusting means includes a temperature compensation thermistor, and controls the power supply voltage of the semiconductor gate circuit based on the temperature detected by the thermistor. Configured as follows. According to such a configuration, it is possible to control the power supply voltage supplied to the semiconductor gate circuit using the thermistor and to perform temperature compensation of the delay amount in the semiconductor gate circuit.

  According to a third aspect of the present invention, in addition to the above-described configuration, the synchronization determination unit receives a response signal from the other after one of the first digital circuit and the second digital circuit outputs a request signal to the other. The synchronization between the first digital circuit and the second digital circuit is determined based on the access time until the time. According to such a configuration, it can be easily determined whether or not the first digital circuit and the second digital circuit are synchronized with each other.

  According to a fourth aspect of the present invention, in addition to the above-described configuration, the delay amount control unit controls the power supply voltage adjustment unit, and the first digital circuit and the second digital circuit are controlled based on the determination result of the synchronization determination unit. A range of a delay amount in which data can be input / output between digital circuits is obtained, and a delay amount of the semiconductor element is determined based on the range of the delay amount.

  According to such a configuration, the range of the delay amount in which data can be input and output between the first digital circuit and the second digital circuit is obtained, and the power supply voltage of the semiconductor gate circuit is controlled based on the range of the delay amount. By doing so, the first digital circuit and the second digital circuit can be synchronized more accurately. For example, by supplying a power supply voltage corresponding to the center of the range of the delay amount to the semiconductor gate circuit, it is possible to make the semiconductor gate circuit less susceptible to the influence of fluctuations in the power supply voltage and temperature.

  The electronic device according to the present invention can adjust a clock skew between digital circuits. In particular, even when the frequency of the clock signal is high, the clock skew between the digital circuits can be easily adjusted. Further, by realizing the phase adjustment of the clock signal with a simple configuration, it is possible to provide an inexpensive electronic device that suppresses the occurrence of clock skew.

It is the block diagram which showed the example of 1 structure of the electronic device 100 by embodiment of this invention. FIG. 2 is a block diagram illustrating a detailed configuration example of a main part of the electronic device 100 in FIG. 1, and illustrates an internal configuration example of the phase adjustment circuit 12, the processor 14, and the control circuit 15. 3 is a flowchart illustrating an example of a delay amount determination process in the electronic device 100 of FIG. 1. It is the flowchart which showed an example of the access time measurement process (step S103) in FIG.

  FIG. 1 is a block diagram illustrating a configuration example of an electronic device 100 according to an embodiment of the present invention. The electronic device 100 includes a main board 1 and a sub board 2 that can mutually input and output data via a serial communication line. The clock signal used in the sub board 2 is supplied from the main board 1, and data input / output between the main board 1 and the sub board 2 is performed in synchronization with the clock.

  On the main board 1, a clock generator 11, a phase adjustment circuit 12, an LVDS driver 13, a processor 14, and a control circuit 15 are provided. Further, an LVDS receiver 23 and a control circuit 25 are provided on the sub-board 2.

  The clock generator 11 is a clock generation circuit that generates the first clock signal CK1. The first clock signal CK1 is a periodic signal that serves as a reference for the control circuits 15 and 25 on the main board 1 and the sub board 2 to perform a synchronous operation. For example, the first clock signal CK1 having a frequency of 50 MHz or more and a waveform close to a sine wave instead of a rectangular wave is generated using a crystal oscillator.

  The phase adjustment circuit 12 is a delay unit that delays the first clock signal CK1 and generates the second clock signal CK2 by using the characteristics of the semiconductor switching element. By supplying the second clock signal CK2 whose phase is adjusted on the main board 1 to the sub board 2, the clock skew between the main board 1 and the sub board 2 is suppressed. The amount of delay in the phase adjustment circuit 12 is specified by the delay control signal DL from the processor 14, and the phase of the clock signal CK2 is adjusted by adjusting the power supply voltage supplied to the semiconductor switching element based on the delay control signal DL. Adjustments are made. For this reason, even if the first clock signal CK1 is high-speed, it is possible to perform phase adjustment with high accuracy without using an expensive circuit such as a PLL.

  The LVDS driver 13 is a transmission circuit that sends the second clock signal CK2 to the sub-board 2 via a twist line by a low-amplitude differential signal system (LVDS). The LVDS receiver 23 is a receiving circuit that receives the second clock signal CK <b> 2 from the LVDS driver 13 and outputs it to the control circuit 25. The small-amplitude differential signal method is a communication method in which a small-amplitude differential signal is output from the transmission side, and one of the reception signals is inverted and added on the reception side. It is a communication method suitable for high-speed transmission over a relatively long distance.

  The control circuits 15 and 25 are digital circuits provided on different substrates 1 and 2, for example, semiconductor integrated devices called ASICs (Application Specified Integrated Circuits), and via communication cables connecting these substrates 1 and 2. Thus, bidirectional serial communication can be performed. The control circuits 15 and 25 operate in synchronization with the clock signals CK1 and CK2, respectively, and the serial communication is also performed in clock synchronization.

  Further, the control circuit 15 determines the synchronization with the control circuit 25 and outputs the determination result to the processor 14. This synchronization determination is processing for determining whether or not synchronization is established based on the access time and error rate for the control circuit 25, and is performed based on an instruction from the processor 14. The processor 14 controls the delay amount in the phase adjustment circuit 12 based on the result of the synchronization determination.

  FIG. 2 is a block diagram showing a detailed configuration example of the main part of the electronic device 100 of FIG. 1, and shows one configuration example inside the phase adjustment circuit 12, the processor 14, and the control circuit 15.

  The control circuit 15 includes a main control unit 151, a data input / output unit 152, and a synchronization determination unit 153, and is a synchronization circuit that operates based on the first clock signal CK1. The main control unit 151 is a circuit for realizing the original function of the control circuit 15 in cooperation with the control circuit 25. The data input / output unit 152 is a circuit that performs data input / output with the control circuit 25 on the sub-board 2, and performs serial communication based on instructions from the main control unit 151 and the synchronization determination unit 153. The synchronization determination unit 153 is a synchronization determination unit that determines the synchronization of the control circuits 15 and 25 based on an instruction from the processor 14, and the determination result is output to the processor 14.

  The synchronization determination is made based on the access time and error rate when data writing or data reading is performed on the control circuit 25. For example, a series of processes of writing data to the internal register of the control circuit 25 and then reading the data in the internal register are repeated to check whether the data writing and data reading are correctly performed. Then, the ratio at which correct data cannot be read, that is, the error rate is obtained. If the error rate exceeds the determination threshold, it is determined that synchronization is not established, and if it is equal to or less than the determination threshold, it is determined that synchronization is established.

  Further, when the data input / output unit 152 performs an error check and the data read access time becomes long when an error occurs, the data input / output unit 152 measures the access time, and if the access time exceeds the determination threshold, It can also be determined that synchronization has been achieved if it is determined that the image has not been removed. That is, if the control circuit 25 outputs redundant data together with the read data, and the control circuit 15 performs an error check on the read data based on the redundant data and makes a retransmission request when an error occurs, the error rate is set. Instead, the access time can be used. Note that the control circuits 15 and 25 can perform data writing and data reading with a certain probability even if they are not completely synchronized with each other. Therefore, the synchronization determination can be performed accurately by performing data writing or data reading a plurality of times and measuring the access time.

  The processor 14 includes a delay amount control unit 141 and a D / A converter 142. The delay amount control unit 141 determines the delay amount in the phase adjustment circuit 12 based on the determination result of the synchronization determination unit 153, and generates delay control information corresponding to the delay amount. This delay control information is converted into an analog voltage signal by the D / A converter 142 and output to the phase adjustment circuit 12 as a delay control signal DL.

  When determining the delay amount, the delay amount control unit 141 determines the delay amount for performing the synchronization determination, and the delay control signal DL corresponding to the delay amount is output from the processor 14. Next, the delay amount control unit 141 instructs the synchronization determination unit 153 to perform synchronization determination, and acquires the determination result. In this way, by acquiring the synchronization determination result for each delay amount with respect to two or more delay amounts, the processor 14 can determine the delay amount with which the control circuits 15 and 25 can be synchronized with each other.

  The phase adjustment circuit 12 includes a gate circuit 120 and a power supply circuit 121. The gate circuit is a signal delay unit that delays the first clock signal CK1 to generate the second clock signal CK2. On the other hand, the power supply circuit 121 is power supply voltage adjusting means for supplying power to the gate circuit 120, and controls the power supply voltage based on the delay control signal DL to adjust the delay amount in the gate circuit 120.

  The gate circuit 120 is configured as a logic circuit composed of semiconductor switching elements, for example, a gate circuit of a complementary metal oxide semiconductor (CMOS). The power of the gate circuit 120 is supplied by the power supply circuit 121, and the voltage thereof is controlled based on the delay control signal DL. That is, the delay amount of the first clock signal CK1 in the gate circuit 120 is controlled by the delay control signal DL.

  In such a gate circuit 120, it is well known that the response of the semiconductor switching element decreases and the amount of delay increases due to a decrease in power supply voltage. Further, since the amplitude of the second clock signal CK2 is decreased due to the decrease in the power supply voltage, the time until the threshold of the LVDS driver 13 is reached is increased. If the delay amount is controlled using such characteristics of the gate circuit 120, highly accurate adjustment can be realized with a simple configuration. In particular, when the waveform of the first clock signal CK1 is close to a sine wave instead of a rectangular wave, the delay amount can be adjusted with high accuracy.

  The power supply circuit 121 includes an operational amplifier OP, a transistor TR, resistors R1 to R3, and a thermistor Rt. A power supply voltage corresponding to the delay control signal DL is generated by a voltage follower circuit including the operational amplifier OP and an emitter follower circuit including the transistor TR. Is supplied to the gate circuit 120. Further, the temperature compensation is performed by changing the amplification factor of the delay control signal DL according to the resistance value of the thermistor Rt.

  The operational amplifier OP is a differential amplifier circuit that has an inverting input terminal and a non-inverting input terminal and operates by a potential difference between these input terminals. The delay control signal DL from the processor 14 is input to the non-inverting input terminal of the operational amplifier OP, and the inverting input terminal is connected to the ground potential via the resistor R1 and the thermistor Rt. The output terminal is connected to the base terminal of the transistor TR, and the output voltage of the operational amplifier OP is fed back to the inverting input terminal between the base and emitter of the transistor TR and the resistor R2. That is, the operational amplifier OP constitutes a non-inverting amplifier circuit that amplifies the delay control signal DL, and the amplification factor is determined by the resistance values of the resistors R1 and R2 and the thermistor Rt.

  The transistor TR is an NPN bipolar transistor having a collector terminal connected to a constant voltage source and an emitter terminal connected to the ground potential via a resistor R3, and constitutes an emitter follower circuit. Therefore, the amplified delay control signal DL can be applied as a power supply voltage to the power supply terminal of the gate circuit 120 connected to the emitter terminal of the transistor TR.

  The thermistor Rt is an element whose resistance value changes according to temperature, and compensates the temperature characteristic of the gate circuit 120 by changing the amplification factor of the delay control signal DL by the operational amplifier OP according to temperature. It is well known that the response characteristic of the semiconductor switching element has temperature dependency. By using a temperature compensation thermistor Rt in the power supply circuit 121, a change in the delay amount due to the temperature characteristic of the gate circuit 120 can be reduced. Can be suppressed.

  The electronic device according to the present embodiment utilizes the fact that the delay amount of the gate circuit 120 is dependent on the power supply voltage when the clock skew occurs due to the transmission delay of the clock signal from the main board 1 to the sub board 2. Thus, the clock skew can be eliminated. That is, the processor 14 obtains a delay amount necessary to synchronize the control circuits 15 and 25, and the phase adjustment circuit 12 generates the second clock signal CK2 obtained by delaying the first clock signal CK1, whereby the control circuit 15 and 25 are synchronized. At this time, the second clock signal CK2 input to the control circuit 25 is a signal delayed by an integral multiple of the cycle of the first clock signal CK1 input to the control circuit 15.

  Steps S101 to S107 in FIG. 3 are flowcharts illustrating an example of a delay amount determination process in the electronic device 100 in FIG. This flowchart is executed based on an external delay amount determination instruction. For example, it may be executed at the time of product inspection before factory shipment, maintenance at the time of shipment, or may be executed at the time of powering on the electronic device 100.

  Here, the range of the delay control signal DL that can synchronize the control circuits 15 and 25 is obtained by changing the delay control signal DL from 1 to 255 and performing synchronization determination in each case. The median value of the range obtained in this way is set as the optimum value of the delay control signal DL.

  First, the delay amount control unit 141 initializes a variable j for changing the delay control signal DL (step S101). Here, j is set to the minimum value 1, but it is desirable to set the minimum voltage at which the phase adjustment circuit 12 can operate. Next, the delay control information j is output from the delay amount control unit 141 to the D / A converter 142, and the voltage j is output as the delay control signal DL to the phase adjustment circuit 12 (step S102).

  The delay amount control unit 141 waits for a predetermined time until the output of the D / A converter 142 is stabilized, and then instructs the synchronization determination unit 153 to perform synchronization determination. Based on this synchronization determination instruction, the synchronization determination unit 153 instructs the data input / output unit 152 to read data a predetermined number of times from the control circuit 25, and measures the access time (step S103). Next, the synchronization determination unit 153 compares the measured access time with a predetermined determination threshold value, and performs synchronization determination (step S104). That is, if the access time exceeds the determination threshold, it is determined that synchronization is not established, and if it is equal to or less than the determination threshold, it is determined that synchronization is established.

  When the synchronization determination ends, the delay amount control unit 141 counts up the variable j (step S105). At this time, if j does not exceed the maximum value 255, the process returns to step S102 and the same synchronization determination is repeated (step S106). On the other hand, when j exceeds the maximum value, the delay amount is determined based on the range of the delay amount that can be obtained by the determination process of 255 times (step S107). For example, the median value of the range of the delay control signal DL that has been synchronized is set as the optimum delay control signal DL.

  In this way, by performing the synchronization determination while changing the delay amount, the range of the delay amount that can be synchronized can be determined. Then, by determining the delay amount based on the range of the delay amount, it is possible to determine the delay amount with a sufficient margin.

  Steps S201 to S206 in FIG. 4 are flowcharts illustrating an example of the access time measurement process (step S103) in FIG. This flowchart is executed by the synchronization determination unit 153 based on the synchronization determination instruction from the delay amount control unit 141.

  First, the synchronization determination unit 153 clears a timer for measuring the access time (step S201). Further, a variable i for counting the number of times of data reading is initialized and i = 1 is set (step S202). Next, the data input / output unit 152 is instructed to read data from the control circuit 25. Based on this read instruction, the data input / output unit 152 sends a data read request signal to the control circuit 25 and receives a response signal from the control circuit 25. The data input / output unit 152 separates read data and redundant data from the response signal, and checks reception errors using the redundant data. If an error is detected in this error check, the data read or retransmission request signal is repeatedly sent to the control circuit 25 until correct data can be received.

  When one data read is thus completed, the synchronization determination unit 153 counts up the variable i (step S204). At this time, if i does not exceed the predetermined number of repetitions, the process returns to step S203 and the same data reading is repeated (step S205). On the other hand, if i exceeds the number of repetitions, the count value of the timer is read, and the access time required for reading data a predetermined number of times is acquired (step S206).

  Thus, the synchronization determination can be easily performed by obtaining the access time for data reading or data writing and comparing it with the determination threshold. In addition, the synchronization determination can be performed accurately by measuring the access time required for performing two or more times of data reading or data writing.

  In this embodiment, as a preferred application example of the present invention, an example in which the control circuits 15 and 25 are provided on different substrates 1 and 2, respectively, has been described. There is no limitation in such cases. For example, even when the control circuits 15 and 25 are electronic devices provided on the same substrate, the present invention can be applied if clock skew can occur.

  In this embodiment, an example in which a clock signal is transmitted from the main board 1 to the sub board 2 by the LVDS method has been described, but the present invention is not limited to such a case. That is, even in the case of an electronic device that transmits a clock signal by a method other than LVDS, the present invention can be applied if a clock skew can occur.

DESCRIPTION OF SYMBOLS 1 Main board | substrate 2 Sub board | substrate 11 Clock generator 12 Phase adjustment circuit 13 LVDS driver 14 Processor 15 Control circuit 23 LVDS receiver 25 Control circuit 100 Electronic device 120 Gate circuit 121 Power supply circuit OP Operational amplifier TR Transistor 141 Delay amount control part 142 D / A converter 151 main control unit 152 data input / output unit 153 synchronization determination unit CK1, CK2 clock signal DL delay control signal R1-R3 resistance Rt thermistor

Claims (4)

A clock generation circuit for generating a first clock signal;
A semiconductor gate circuit for generating a second clock signal by delaying the first clock signal;
A first digital circuit that operates in synchronization with a first clock signal;
A second digital circuit that operates in synchronization with the second clock signal and inputs / outputs data to / from the first digital circuit;
Synchronization determination means for determining synchronization between the first digital circuit and the second digital circuit;
A delay amount control means for determining a delay amount of the second clock signal based on the determination result;
Electronic equipment comprising power supply voltage adjusting means for supplying a power supply voltage based on the delay amount to the semiconductor gate circuit.   2. The electronic apparatus according to claim 1, wherein the power supply voltage adjusting means includes a temperature compensation thermistor, and controls the power supply voltage of the semiconductor gate circuit based on a temperature detected by the thermistor.   The synchronization determination means includes the first digital circuit and the second digital circuit based on an access time from when one of the first digital circuit and the second digital circuit outputs a request signal to the other and until a response signal is received from the other. The electronic device according to claim 1, wherein synchronization of two digital circuits is determined.   The delay amount control means controls the power supply voltage adjusting means, and obtains a range of delay amounts in which data can be input / output between the first digital circuit and the second digital circuit based on the determination result of the synchronization determination means. 2. The electronic device according to claim 1, wherein a delay amount of the semiconductor gate circuit is determined based on a range of the delay amount.

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