JP2011091337A - Mos image sensor, method of driving mos image sensor, and imaging device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a novel structure that erases signal charges in a floating gate for an MOS image sensor having a structure configured such that signal charges are injected into the floating gate and a signal corresponding to the signal charges is read out. <P>SOLUTION: The MOS image sensor includes a photoelectric conversion portion PD formed in a semiconductor substrate 51, a pixel portion 52a having a semiconductor memory WT including the floating gate FG into which electric charges accumulated in the photoelectric conversion portion PD are injected and which is provided above the semiconductor substrate 51, and a readout portion 55 which reads out the signal corresponding to the electric charges injected into the floating gate FG. The pixel portion 52a includes a tunnel insulating film 7 provided between the semiconductor substrate 51 and floating gate FG, an impurity diffusion layer 12 provided in the semiconductor substrate 51, and a tunnel insulating film 15 formed on the impurity diffusion layer 12, the floating gate FG being provided even on the tunnel insulating film 15. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a MOS image sensor, a method for driving a MOS image sensor, and an imaging apparatus.

  A conventional MOS type image sensor is called a rolling shutter (focal plane shutter) method. Even if the exposure time of each line is constant, the exposure start timing is shifted for each line. There has been a problem that an image after shooting is distorted when the image is taken. For example, if the subject (train) moves from right to left during the exposure period, the subject (train) after photographing becomes an image deformed into a rhombus. Further, when the subject moves from the bottom to the top on the screen, the image after shooting is “shrinked”, and conversely, when the subject moves from the top to the bottom on the screen, the image after shooting is “stretched”.

  A MOS type image sensor that solves such a problem is disclosed in Patent Document 1. In the MOS image sensor disclosed in Patent Document 1, a semiconductor memory having a floating gate is provided for each pixel portion. Then, the charge generated in the photodiode of the pixel portion is injected into the floating gate of the pixel portion, and a signal corresponding to the charge injected into the floating gate is read.

  According to the MOS type image sensor disclosed in Patent Document 1, since the source follower amplifier and the selection transistor are not included, the number of transistors per pixel portion can be reduced, and even when miniaturization progresses, Sensitivity can be improved. Further, the charge is isolated by the potential barrier of the insulating film between the floating gate and the substrate, and unnecessary charge due to dark current or excessive light is not mixed into the charge injected into the floating gate, so that SN can be improved. .

  In Patent Document 1, as a method for erasing the charge injected into the floating gate, a negative voltage is applied to the gate electrode of the semiconductor memory, and a positive voltage is applied to the semiconductor substrate, thereby discharging the charge in the floating gate to the substrate side. How to do is described.

  In this method, at least a part of the electric charge in the floating gate is also discharged to the photodiode. For this reason, after the erasing operation, the exposure of the photodiode cannot be started unless the charge in the photodiode is completely discharged to, for example, a separately prepared drain. Therefore, the ratio of the exposure period in one imaging sequence is reduced, leading to a decrease in signal amount (S / N degradation) and loss of imaging opportunities.

JP 2002-280537 A

  The present invention has been made in view of the above circumstances, and in a MOS image sensor having a structure in which a signal charge is injected into a floating gate and a signal corresponding to the signal charge is read out, the signal charge in the floating gate is erased. An object is to provide a new structure and method.

  The MOS type image sensor of the present invention is formed in a semiconductor substrate and is provided above the semiconductor substrate into which a photoelectric conversion unit that accumulates electric charges generated by photoelectric conversion and the electric charge accumulated in the photoelectric conversion unit is injected. A pixel unit having a semiconductor memory including a floating gate and a gate electrode provided at a position opposite to the floating gate, and a reading unit for reading out a signal corresponding to the charge injected into the floating gate. A first insulating film provided between the semiconductor substrate and the floating gate, an impurity diffusion layer provided in the semiconductor substrate, and a second insulating film formed on the impurity diffusion layer And the floating gate or another floating gate electrically connected to the floating gate is the second isolation gate. It is provided on the film.

  The imaging device of the present invention applies voltages having opposite polarities to the MOS type image sensor, the gate electrode of the semiconductor memory, and the impurity diffusion layer, respectively, and charges the floating gate to the second A drive unit that performs charge discharge driving for tunneling the insulating film and discharging it to the impurity diffusion layer.

  The MOS image sensor driving method of the present invention is the MOS image sensor driving method, wherein voltages having opposite polarities are applied to the gate electrode and the impurity diffusion layer of the semiconductor memory, respectively. The charges in the floating gate are discharged to the impurity diffusion layer by tunneling the second insulating film.

  According to the present invention, there is provided a novel structure and method for erasing a signal charge in a floating gate in a MOS image sensor having a structure for injecting a signal charge into a floating gate and reading out a signal corresponding to the signal charge. Can do.

The figure which shows schematic structure of the MOS type image sensor for describing one Embodiment of this invention The figure which shows schematic structure of the pixel array in the MOS type image sensor shown in FIG. The equivalent circuit diagram which shows the internal structure of the pixel part in the pixel array shown in FIG. 2 is a diagram showing a schematic configuration of a pixel unit in the pixel array shown in FIG. 2 and a readout unit and a vertical drive scanning circuit in the MOS image sensor shown in FIG. The figure which showed the example of a plane layout of the pixel part shown in FIG. Cross-sectional schematic diagram of line VI-VI shown in FIG. Sectional schematic diagram of the VII-VII line shown in FIG. VIII-VIII cross-sectional schematic diagram shown in FIG. The figure which showed another example of the planar layout of the pixel part shown in FIG. XX cross-sectional schematic diagram shown in FIG. Timing chart for explaining a method of driving the MOS type image sensor shown in FIG.

  Embodiments of the present invention will be described below with reference to the drawings.

  FIG. 1 is a diagram showing a schematic configuration of a MOS type image sensor for explaining an embodiment of the present invention. This MOS image sensor is used by being mounted on an imaging device such as a digital camera and a digital video camera, an imaging module mounted on an electronic endoscope, a camera-equipped mobile phone, or the like.

  As shown in FIG. 1, the MOS image sensor 5 includes a pixel array 52, a vertical drive scanning circuit 53, a drive control circuit 54, a readout unit 55, a signal line 56, and a horizontal drive scanning circuit formed on a semiconductor substrate 51. 57.

  The pixel array 52 includes a plurality of pixel portions arranged in a two-dimensional manner, details of which will be described later. In an example to be described later, the plurality of pixel units are arranged by arranging a plurality of pixel unit rows composed of a plurality of pixel units arranged in the horizontal direction in the vertical direction orthogonal to the horizontal direction or a plurality of pixel units arranged in the vertical direction. A plurality of pixel section rows are arranged in the horizontal direction.

  The vertical drive scanning circuit 53 drives a plurality of pixel units included in the pixel array 52, and can select and drive a plurality of pixel unit rows one by one.

  The drive control circuit 54 comprehensively controls the vertical drive scanning circuit 53, the reading unit 55, and the horizontal drive scanning circuit 57.

  The readout unit 55 includes a readout circuit provided corresponding to each of the plurality of pixel unit columns. Details of the reading unit 55 will be described later.

  The horizontal drive scanning circuit 57 includes a switch connected to each of a plurality of readout circuits included in the readout unit 55 and a control circuit that controls on / off of the switches. When this switch is turned on, a signal read by the reading circuit is output to the signal line 56.

  FIG. 2 is a schematic plan view showing a schematic configuration of the pixel array in the MOS type image sensor shown in FIG. As shown in FIG. 2, the pixel array 52 includes a plurality of pixel portions 52a (denoted as Pixel in the drawing), a capacitor 52b, a read control line RL, a write control line WL, a reset control line RST, and a reset power source. A line Vrst, a charge erasing line EL, and a signal line BL are included. As described above, the plurality of pixel portions 52a are arranged two-dimensionally (in the example of FIG. 2 in the form of a square lattice) in the horizontal direction X and the vertical direction Y on the semiconductor substrate 51. The capacitor 52b is provided corresponding to each pixel unit column.

  The pixel unit 52a receives light and generates a charge corresponding to the amount of light received, and outputs a signal corresponding to the generated charge.

  One read control line RL, write control line WL, reset control line RST, reset power supply line Vrst, and charge erasing line EL are provided for one pixel portion row. The read control line RL, the write control line WL, the reset control line RST, and the charge erasing line EL are connected to each pixel portion 52a and the vertical drive scanning circuit 53 in the corresponding pixel portion row, respectively. The reset power line Vrst is connected to each pixel unit 52a in the corresponding pixel unit row and a power source (not shown).

  One signal line BL is provided for one pixel portion column. The signal line BL is connected to each pixel unit 52a of the pixel unit column corresponding thereto, a capacitor 52b corresponding to the pixel unit column, and a readout circuit in the readout unit 55 corresponding to the pixel unit column.

  FIG. 3 is a diagram showing a schematic configuration of the pixel portion 52a in the pixel array 52 shown in FIG. As shown in FIG. 3, the pixel unit 52a includes a reset transistor RSTr, a write transistor WT that is a semiconductor memory, a read transistor RT, a photoelectric conversion unit PD, and a charge erasing unit SE.

  The photoelectric conversion unit PD accumulates charges obtained by photoelectric conversion. The photoelectric conversion unit PD is composed of, for example, a photodiode formed in the semiconductor substrate 51. For example, an n-type impurity layer can be formed in a p-well layer formed on an n-type silicon substrate, and a photodiode can be formed by a pn junction between the n-type impurity layer and the p-well layer. A p-type impurity layer is provided on the surface of the n-type impurity layer, and the n-type impurity layer is a so-called embedded photodiode formed inside the n-type silicon substrate instead of the outermost surface of the n-type silicon substrate. The layer can be fully depleted. Note that a pair of electrodes and a photoelectric conversion layer sandwiched between the electrodes are provided above the semiconductor substrate 51, one of the pair of electrodes and the photoelectric conversion unit PD are electrically connected, and the charge generated in the photoelectric conversion layer is converted to the photoelectric conversion unit. It may be configured to accumulate in the PD.

  The reset transistor RSTr discharges charges accumulated in the photoelectric conversion unit PD and resets the potential of the photoelectric conversion unit PD to a predetermined potential. A reset control line RST is connected to the gate electrode RG of the reset transistor RSTr. A reset power supply line Vrst is connected to the drain region of the reset transistor RSTr.

  The write transistor WT has a floating gate FG provided on a tunnel insulating film formed on the semiconductor substrate 51, and a write control gate WCG which is a gate electrode provided at a position facing the floating gate FG. ing.

  The source region of the write transistor WT is a photoelectric conversion unit PD. A write control gate WCG of the write transistor WT is connected to a write control line WL. By applying a write voltage to the write control gate WCG via the write control line WL, the photoelectric control is performed by FN tunnel injection, direct tunnel injection, or the like that injects charges using a Fowler-Nordheim (FN) tunnel current. The charges accumulated in the conversion unit PD are injected and accumulated in the floating gate FG.

  In the example of FIG. 3, the write transistor WT has a two-terminal structure in which the drain region is omitted, thereby simplifying the configuration.

  As the two-terminal device, there are a resistor, a coil, a capacitor, a diode, and the like, but there is no active device such as switching or signal amplification. In addition, it is understood as common sense that a transistor which is an active device for performing pixel selection, reset, signal recording, signal reading, etc. in a general MOS image sensor does not function with two terminals, and no one tries to do so. It was. However, since the configuration of the pixel portion 52a shown in FIG. 3 has a structure in which the writing transistor WT and the reading transistor RT share the floating gate FG, it is understood that there is no problem even if the writing transistor WT has a two-terminal structure. It was.

  This is because the signal can be read on the read transistor RT side, and the write transistor WT has only charge transfer for writing (charge injection to the floating gate FG) and erasing (charge extraction from the floating gate FG). It is because it is good if it can be done. Therefore, in the MOS type image sensor 5, the write transistor WT has a two-terminal structure. Note that the write transistor WT may have a three-terminal structure provided with a drain region.

  The read transistor RT includes a floating gate FG electrically connected to the floating gate FG of the write transistor WT, a read control gate RCG that is a gate electrode connected to the read control line RL and the charge erasing line ELb, a source region, , A three-terminal MOS transistor having a drain region.

  The source region of the read transistor RT is grounded. The drain region of the read transistor RT is connected to the signal line BL. The floating gate FG of the read transistor RT may be integrated with the floating gate FG of the write transistor WT, or two floating gates may be connected by wiring separately from the floating gate FG of the write transistor WT. May be. In the example of FIG. 3, the floating gate FG of the read transistor RT and the floating gate FG of the write transistor WT are integrated.

  The charge erasing unit SE includes an impurity diffusion layer 12 formed in the semiconductor substrate 51, and a floating gate FG extends over the impurity diffusion layer 12. A charge erasing line ELa is connected to the impurity diffusion layer 12.

  4 is a diagram showing an internal configuration of the pixel unit 52a shown in FIG. 2 and the readout unit 55 and the vertical drive scanning circuit 53 shown in FIG.

  As shown in FIG. 4, the vertical drive scanning circuit 53 includes a switch 53a, a switch 53b, a switch 53c, a switch 53d, a switch 53e, and a control circuit 53f.

  The switches 53 a are provided corresponding to all the pixel unit rows, and are connected between the readout control line RL of the corresponding pixel unit row and the DA converter 551 in the readout unit 55. The switch 53 a is ON / OFF controlled by the read control circuit 550 in the read unit 55.

  The switch 53b is provided corresponding to all the pixel unit rows, and is connected between the write control line WL and the WCG voltage control unit 58 of the corresponding pixel unit row. The switch 53b is ON / OFF controlled by a control circuit 53f in the vertical drive scanning circuit 53. The WCG voltage control unit 58 is included in an imaging device in which the MOS type image sensor 5 is mounted.

  The WCG voltage control unit 58 outputs a write voltage large enough to allow tunneling of the tunnel insulating film during a charge write operation in which charges accumulated in the photoelectric conversion unit PD are injected into the floating gate FG. Further, the WCG voltage control unit 58 performs write control to discharge the charge injected into the floating gate FG to the impurity diffusion layer 12 during the charge erasing operation for discharging the charge injected into the floating gate FG to the impurity diffusion layer 12. An erase voltage to be applied to the gate WCG is output.

  The switches 53c are provided corresponding to all the pixel unit rows, and are connected between the reset control line RST and the reset pulse supply unit 59 of the corresponding pixel unit row. The switch 53 c is ON / OFF controlled by a control circuit 53 f in the vertical drive scanning circuit 53. The reset pulse supply unit 59 is included in an imaging device in which the MOS type image sensor 5 is mounted.

  The reset pulse supply unit 59 generates and outputs a reset pulse for turning on the reset transistor RSTr. The control circuit 53f turns on the switch 53c only at the timing when the photoelectric conversion unit PD should be reset, such as immediately before the start of exposure of the photoelectric conversion unit PD, and turns off the switch 53c otherwise.

  The switch 53d is provided corresponding to all the pixel unit rows, and is connected between the charge erasing line ELa and the erasing voltage supply unit 60 of the corresponding pixel unit row. The switch 53e is provided corresponding to all the pixel unit rows, and is connected between the charge erasing line ELb and the erasing voltage supply unit 60 of the corresponding pixel unit row. The switches 53d and 53e are on / off controlled by a control circuit 53f in the vertical drive scanning circuit 53. The erasing voltage supply unit 60 is included in an imaging device in which the MOS type image sensor 5 is mounted.

  In the charge erasing operation, the erase voltage supply unit 60 supplies the erase voltage to be applied to the read control gate RCG to the charge erase line ELb, and supplies the erase voltage to be applied to the impurity diffusion layer 12 to the charge erase line ELa. The control circuit 53f turns on the switches 53d and 53e only during the charge erasing operation, and turns off the switches 53d and 53e otherwise.

  The readout unit 55 includes a readout control circuit 550, a DA converter 551, a counter 552, and a precharge circuit 553 that are provided in common for all the pixel unit columns, and a readout circuit 554 that is provided independently for each pixel unit column. With.

  The read circuit 554 includes transistors 554a and 554b, a sense amplifier 554c, and a latch circuit 554d.

  The transistor 554a is provided between the signal line BL of the corresponding pixel portion column and the sense amplifier 554c, and controls connection between the signal line BL and the sense amplifier 554c. The transistor 554b is provided between the signal line BL of the corresponding pixel portion column and the precharge circuit 553, and controls supply of the voltage supplied from the precharge circuit 553 to the signal line BL.

  The sense amplifier 554c monitors the voltage of the signal line BL connected through the transistor 554a, and outputs a detection signal to the latch circuit 554d when the voltage changes. For example, the sense amplifier output is inverted by detecting that the voltage of the signal line BL has dropped.

  The latch circuit 554d holds the count value of the counter 552 when the detection signal is input.

  The counter 552 is an N-bit counter (for example, N = 8 to 12), and resets the count value to the initial value and starts counting in response to an instruction from the drive control circuit 54. The DA converter 551 converts the count value of the counter 552 (a combination of N 1s and 0s) into an analog signal, and outputs a read voltage that monotonously changes (for example, gradually increases or decreases) to the read control line RL of each pixel unit row. Is supplied via a switch 53a.

  The read control circuit 550 controls on / off of the transistors 554a and 554b. Further, the read control circuit 550 performs on / off control of the switch 53a included in the vertical drive scanning circuit 53, and performs control for supplying a read voltage to the read control line RL of an arbitrary pixel unit row.

  The precharge circuit 553 supplies a predetermined voltage to the signal line BL connected via the transistor 554b to precharge the capacitor 52b connected to the signal line BL.

  Here, a signal reading operation by the reading unit 55 will be described. First, the switch 554b is turned on to precharge the capacitor 52b, and the switch 554a is turned on to make the signal line BL and the sense amplifier 554c conductive. In a state where the capacitor 52b is precharged, the switch 53a is turned on, and application of a read voltage to the read control gate RCG is started.

  After the start of application of the read voltage, the read transistor RT becomes conductive when the read voltage exceeds the threshold voltage of the read transistor RT. At this time, the potential of the signal line BL that has been precharged drops. This is detected by the sense amplifier 554c and an inverted signal is output.

  The latch circuit 554d holds (latches) a count value corresponding to the value of the read voltage when the inverted signal is received. Thus, the count value can be read and held as a signal corresponding to the threshold voltage of the read transistor RT (a signal corresponding to the amount of charge injected into the floating gate FG).

  Note that reading of a signal corresponding to the threshold voltage of the reading transistor RT can be realized by a configuration other than the reading unit 55.

  For example, a constant current source is provided instead of the capacitor 52b, and a constant current is applied to the drain region of the read transistor RT by the constant current source in a state where a constant voltage is applied to the read control gate RCG. The source is operated as a source follower circuit. Then, by detecting the voltage of the source region of the read transistor RT, a signal corresponding to the threshold voltage of the read transistor RT can be read.

  FIG. 5 is a schematic plan view illustrating a planar layout example of the pixel unit 52a illustrated in FIG. In the example shown in FIG. 5, the reset transistor RSTr is arranged on the left side of the photoelectric conversion unit PD, and the write transistor WT, the read transistor RT, and the charge erasing unit SE are arranged in the vertical direction on the right side of the photoelectric conversion unit PD. Has been placed.

  A drain region 9 of the reset transistor RSTr is arranged on the left side of the photoelectric conversion unit PD with a little space therebetween. A gate electrode RG of the reset transistor RSTr is disposed between the drain region 9 and the photoelectric conversion unit PD.

  In the example of FIG. 5, the floating gate FG of the write transistor WT and the floating gate FG of the read transistor RT are integrated, and this floating gate FG passes from the formation region of the write transistor WT to the formation region of the read transistor RT. The linear shape extends in the vertical direction over the region where the charge erasing portion SE is formed.

  The write control gate WCG of the write transistor WT is substantially U-shaped so as to face a part of the left side surface, a part of the right side surface of the floating gate FG, and a side surface of the upper side in the vertical direction. It is formed in a shape obtained by vertically inverting the letter U. A substantially U-shaped gate insulating film 8 is formed between the write control gate WCG and the floating gate FG.

  In the formation region of the read transistor RT, the drain region 10 and the source region 11 of the read transistor RT are arranged in the horizontal direction with the floating gate FG interposed therebetween. The read control gate RCG of the read transistor RT is formed above the floating gate FG sandwiched between the drain region 10 and the source region 11.

  A floating gate FG is present in the formation region of the charge erasing unit SE, and the impurity diffusion layer 12 is formed at a position overlapping therewith.

  The photoelectric conversion unit PD is formed from a position that does not overlap with the write transistor WT (outside the formation region of the write transistor WT indicated by a broken line) to a position that overlaps with the write transistor WT. The photoelectric conversion unit PD is constituted by an impurity layer formed in the semiconductor substrate 51. In this impurity layer, a portion overlapping the write transistor WT is denoted by reference numeral 2b, and other portions are denoted by reference numeral 2a. Is attached.

  6 is a schematic cross-sectional view taken along the line VI-VI shown in FIG. As shown in FIG. 6, charges injected into the floating gate FG from the photoelectric conversion unit PD (electrons in the example of FIG. 6) are formed on the surface portion in the semiconductor substrate 51 (p-type silicon substrate in this example) below the floating gate FG. A semiconductor layer 4 of a conductive type (p-type in the example of FIG. 6) having a charge opposite in polarity to the majority carrier as a carrier is formed. The semiconductor layer 4 is disposed so as to overlap the entire floating gate FG included in the write transistor WT in plan view. In the example of FIG. 6, the semiconductor layer 4 can be formed by injecting a p-type impurity (for example, boron) into the semiconductor substrate 51.

  As shown in FIG. 6, the photoelectric conversion unit PD is composed of n-type impurity layers 2 a and 2 b formed in the semiconductor substrate 51. The photoelectric conversion unit PD is disposed at a predetermined distance from the surface of the semiconductor substrate 51, and a p-type impurity layer having a conductivity type opposite to that of the photoelectric conversion unit PD is between the photoelectric conversion unit PD and the surface of the semiconductor substrate 51. 3 is formed. With such a configuration, the photoelectric conversion unit PD becomes a so-called embedded type and is completely depleted.

  As shown in FIG. 6, the photoelectric conversion unit PD is formed in the semiconductor substrate 51 so as to extend from a region other than the region where the write transistor WT is formed to below the semiconductor layer 4 in the region. . In FIG. 6, the n-type impurity layer 2a and the n-type impurity layer 2b are separated by broken lines, but they are actually formed integrally.

  As shown in FIG. 6, the write control gate WCG is disposed at a position facing the side of the floating gate FG. A gate insulating film 8 is formed between the write control gate WCG and the side portion of the floating gate FG and between the write control gate WCG and the semiconductor substrate 51.

  As shown in FIG. 6, an insulating film 7 (hereinafter referred to as a charge injection tunnel insulating film 7) is formed between the floating gate FG and the semiconductor substrate 51. . An element isolation layer 6 is formed in a region of the semiconductor substrate 51 where each component is not provided in the plan view shown in FIG.

  In this MOS type image sensor 5, the semiconductor layer 4 is provided on the surface portion in the semiconductor substrate 51 below the floating gate FG, thereby increasing the voltage consumption in the depletion layer generated in the semiconductor substrate 51 below the floating gate FG. Is preventing. By providing the semiconductor layer 4, the potential difference applied to the charge injection tunnel insulating film 7 can be increased. As a result, the charge injection efficiency from the photoelectric conversion unit PD to the floating gate FG can be increased without increasing the write voltage.

  FIG. 7 is a schematic cross-sectional view taken along the line VII-VII shown in FIG. On the semiconductor substrate 51 between the drain region 10 and the source region 11 of the read transistor RT, the gate insulating film whose thickness in the direction perpendicular to the surface of the semiconductor substrate 51 is larger than the tunnel insulating film 7 for charge injection shown in FIG. 14 is formed. A floating gate FG is formed on the gate insulating film 14, and an insulating film 13 is formed on the floating gate FG. A read control gate RCG is formed on the insulating film 13.

  FIG. 8 is a schematic cross-sectional view taken along line VIII-VIII shown in FIG. As shown in FIG. 8, the impurity diffusion layer 12 is formed in the semiconductor substrate 51 below the floating gate FG. Between the impurity diffusion layer 12 and the floating gate FG, the thickness in the direction perpendicular to the surface of the semiconductor substrate 51 is larger than that of the tunnel insulating film 7 for charge injection shown in FIG. 6 and shown in FIG. An insulating film 15 (hereinafter referred to as a charge erasing tunnel insulating film 15) smaller than the gate insulating film 14 is provided.

  FIG. 9 is a diagram showing another example of the planar layout of the pixel portion shown in FIG. FIG. 10 is a schematic cross-sectional view taken along line XX shown in FIG. The layout shown in FIG. 9 is different from FIG. 5 in that the impurity diffusion layer 12 of the charge erasing portion SE is formed so as to straddle from one side to both sides of the floating gate FG.

  Thus, in the MOS image sensor 5, the charge erasing unit SE is provided in addition to the photoelectric conversion unit PD, the reset transistor RSTr, the write transistor WT, and the read transistor RT. The impurity diffusion layer 12 of the charge erasing unit SE is formed of a semiconductor having a majority carrier of charges having the same polarity as the charge injected from the photoelectric conversion unit PD to the floating gate FG. For example, an n-type semiconductor is formed if the charge injected into the floating gate FG is an electron, and a p-type semiconductor is formed if the charge is a hole.

  Further, a charge erasing tunnel insulating film 15 is provided on the impurity diffusion layer 12, and a floating gate FG is provided thereon. A charge erasing line ELa is connected to the impurity diffusion layer 12, and an erasing voltage is applied from the erasing voltage supply unit 60 when the switch 53d is turned on.

  That is, during the charge erasing operation, an erasing voltage is applied to the write control gate WCG, the read control gate RCG, and the impurity diffusion layer 12, respectively. By reversing the polarity of the erase voltage applied to the write control gate WCG and the read control gate RCG and the polarity of the erase voltage applied to the impurity diffusion layer 12, the charges accumulated in the floating gate FG The film 15 is tunneled and discharged to the impurity diffusion layer 12. With such a mechanism, the charge erasing unit SE has a mechanism for erasing charges in the floating gate FG.

  The thicknesses of the charge injection tunnel insulating film 7, the gate insulating film 14 of the read transistor RT, and the charge erasing tunnel insulating film 15 are as follows: the charge injection tunnel insulating film 7 <the charge erasing tunnel insulating film 15 <. A gate insulating film 14 is formed. This is due to the following reasons (1) and (2).

  (1) In the charge write operation and signal read operation, a positive voltage is applied to the write control gate WCG and the read control gate RCG. In particular, a voltage of about 15 V, for example, is applied during the charge write operation. At this time, it is necessary that charges be tunneled through the tunnel insulating film 7 for charge injection, but the gate insulating film 14 and the charge erasing tunnel insulating film 15 are applied. The charge must not tunnel. This is because when charge in the source and drain of the read transistor RT and the impurity diffusion layer 12 is injected into the floating gate FG, it becomes a noise source and S / N deteriorates. Therefore, during the charge write operation, the respective film thicknesses are set under the condition that charges are tunneled in the charge injecting tunnel insulating film 7 and charges are not tunneled in the gate insulating film 14 and the charge erasing tunnel insulating film 15. It is necessary to decide. Therefore, the condition of the charge injection tunnel insulating film 7 <the charge erasing tunnel insulating film 15 and the gate insulating film 14 is satisfied. When the write voltage applied to the write control gate WCG during charge write operation is 15 V, the thickness of the charge injection tunnel insulating film 7 is 1 nm to 3 nm and the thickness of the charge erasing tunnel insulating film 15 is about 2 nm to 10 nm. If there is, S / N deterioration can be sufficiently prevented.

  (2) When a tunnel current flows through the gate insulating film 14 of the read transistor RT, charges are trapped in a trap or the like in the gate insulating film 14, and as a result, the threshold voltage of the read transistor RT changes, and accurate signal reading is performed. It becomes impossible. Therefore, in order to eliminate this change in threshold voltage, it is necessary to increase the thickness of the gate insulating film 14 so that a tunnel current does not flow through the gate insulating film 14 in all driving sequences. Further, the charge erasing tunnel insulating film 15 needs to have a thickness that does not tunnel charges during a charge write operation and a signal read operation, but allows a charge to tunnel during a charge erase operation. Therefore, the condition of the charge erasing tunnel insulating film 15 <the gate insulating film 14 is satisfied.

  Next, a method for driving the MOS type image sensor configured as described above will be described.

  FIG. 11 is a timing chart illustrating a method for driving the MOS image sensor shown in FIG. In FIG. 11, “WCG / RCG” indicates a voltage applied to the write control gate WCG and the read control gate RCG. “DD” indicates an erase voltage applied to the impurity diffusion layer 12. “RG” indicates a voltage applied to the gate electrode RG of the reset transistor RSTr. FIG. 11 is a timing chart in the case of moving image shooting by driving the MOS type image sensor 5 with a rolling shutter, and shows each voltage applied to the nth pixel portion row.

  After the charge accumulated in the photoelectric conversion unit PD in the exposure period of the (N-1) frame immediately before the N frame is injected into the floating gate FG, the control circuit 53f switches the switch 53c corresponding to the nth pixel unit row. And a reset pulse is applied to the gate electrode of the reset transistor RSTr. Thereby, the reset transistor RSTr is turned on, and the electric charge accumulated in the photoelectric conversion unit PD is discharged to the drain region 9 of the reset transistor RSTr. Next, the control circuit 53f turns off the switch 53c corresponding to the nth pixel portion row, and starts an N frame exposure period of the nth pixel portion row.

  After the exposure period starts, the (N-1) frame signal readout operation starts. First, the read control circuit 550 turns on the transistors 554a and 554b corresponding to all the pixel portion columns to conduct the signal line BL and the sense amplifier 554c, and precharges the potential of the signal line BL. Next, the read control circuit 550 turns on the switch 53a corresponding to the nth pixel portion row, and starts supplying the read voltage to the read control gate RCG of each pixel portion 52a in the nth pixel portion row. . At the same time as the switch 53a is turned on, the counter 552 resets the count value and starts counting.

  At the moment when the read voltage exceeds a certain value, the drain signal of the read transistor RT flows, the charge accumulated in the capacitor 52b of the signal line BL is discharged, and the potential of the signal line BL returns to the value before the precharge. The digital count value at that time is latched (held) in the latch circuit 554d.

  When a signal (digital count value) is read from each pixel portion 52a in the nth pixel portion row and latched in the latch circuit 554d, the read control circuit 550 includes the transistors 554a and 554b and the pixel portion in the nth row. The switch 53a corresponding to the row is turned off.

  Next, when the latch circuit 554d corresponding to one pixel unit column is selected by the control of the horizontal drive scanning circuit 57, a signal is read from the latch circuit 554d to the signal line 56 and the MOS image sensor 5 is externally connected. Is output. The horizontal drive scanning circuit 57 sequentially selects the latch circuits 554d corresponding to all the pixel portion columns and reads out signals for one line. Thereby, the signal read operation of the (N-1) frame is completed.

  After the signal reading operation is completed, the charge erasing operation is started, and the control circuit 53f turns on the switch 53b, the switch 53d, and the switch 53e corresponding to the nth pixel portion row, and turns on the write control gate WCG and the read control gate RCG. A negative voltage of the same level is applied, and a positive voltage is applied to the impurity diffusion layer 12. Thereby, the charges in the floating gate FG are discharged to the impurity diffusion layer 12.

  Next, the control circuit 53f turns off the switch 53b, the switch 53d, and the switch 53e corresponding to the nth pixel portion row, and ends the charge erasing operation.

  At the end of the exposure period of the Nth frame after the end of the charge erasing operation, the control circuit 53f turns on the switch 53b corresponding to the nth pixel portion row and applies a positive write voltage to the write control gate WCG. To do. Thereby, charges accumulated in the photoelectric conversion unit PD from the start of exposure of the N frame are injected into the floating gate FG. Since light enters the photoelectric conversion portion PD even during application of the write voltage, the charge due to this light is also injected into the floating gate FG. When the control circuit 53f turns off the switch 53b corresponding to the nth pixel portion row, the exposure period of the nth pixel portion row ends. Thereafter, the photoelectric conversion unit PD reset, N frame signal read, charge erase, and (N + 1) frame charge write operations are repeated. The signal read operation may be performed at any time after the end of the write operation for injecting the charge accumulated in the photoelectric conversion unit PD during the exposure period to the start of the charge erase operation. In addition, the reset operation of the photoelectric conversion unit PD may be performed after the N frame signal read operation or during the operation.

  As described above, according to the MOS image sensor 5, the negative voltage is applied to the write control gate WCG and the read control gate RCG, and the positive voltage is applied to the impurity diffusion layer 12 of the charge erasing unit SE. Electric charges in the FG can be discharged to the impurity diffusion layer 12. According to this configuration, the charge in the floating gate FG is not discharged to the photoelectric conversion unit PD. For this reason, the exposure can be started without resetting the photoelectric conversion unit PD after the charge erasing operation. That is, the charge erasing operation can be performed during the exposure period, and the ratio of the exposure period to one frame period can be prevented from decreasing.

  Further, according to the MOS type image sensor 5, the semiconductor insulating layer 4 provided on the surface portion in the semiconductor substrate 51 below the floating gate FG does not increase the write voltage applied to the write control gate WCG, but increases the tunnel insulating film. The voltage applied to 7 can be increased. As a result, the charge injection efficiency can be improved while reducing power consumption.

  In the MOS type image sensor 5, as shown in FIG. 6, the write control gate WCG is arranged at a position facing the side of the floating gate FG. With this configuration, the overlap area between the write control gate WCG and the floating gate FG is increased, and the capacitance formed by the write control gate WCG / gate insulating film 8 / floating gate FG can be increased. As a result, the voltage applied to the charge injection tunnel insulating film 7 can be increased, and the charge injection efficiency can be further improved.

  Further, in the MOS type image sensor 5, the photoelectric conversion unit PD is configured to extend from the light receiving region to below the semiconductor layer 4. In this way, by extending the photoelectric conversion unit PD under the semiconductor layer 4 (preferably the entire range overlapping with the semiconductor layer 4 in plan view), the charge of the photoelectric conversion unit PD is injected by FN tunnel injection or direct tunnel injection. In the case of injection into the floating gate FG, an electric field can be applied from the photoelectric conversion unit PD to the floating gate FG in a substantially vertical direction by a voltage applied to the write control gate WCG. As a result, the charge of the photoelectric conversion unit PD is easily accelerated toward the floating gate FG, and a tunnel current can be efficiently generated.

  In the above description, the charge read out as a signal has been described as an electron. However, when this is a hole, all of the n-type and p-type are reversed in FIGS. 5 to 10 and the corresponding description. The applied voltage may be reversed.

  In the above description, the photoelectric conversion unit PD is a photodiode, and charges generated by the photodiode are injected into the floating gate FG. However, the present invention is not limited to this. Instead of the photoelectric conversion unit PD in the semiconductor substrate, a charge storage unit (for example, an n-type impurity layer) for storing charges is provided, and a pair of electrodes and a photoelectric conversion layer sandwiched between them are provided above the semiconductor substrate. Alternatively, the charge storage portion may be electrically connected to one of the pair of electrodes, the charge generated in the photoelectric conversion layer may be stored in the charge storage portion, and the charge may be injected into the floating gate FG.

  As described above, the following items are disclosed in this specification.

  The disclosed MOS image sensor is formed in a semiconductor substrate, and stores a photoelectric conversion unit that accumulates charges generated by photoelectric conversion, and the semiconductor substrate into which the charges accumulated in the photoelectric conversion unit are injected. A pixel unit having a semiconductor memory including a floating gate and a gate electrode provided at a position opposite to the floating gate, and a reading unit for reading out a signal corresponding to the charge injected into the floating gate. A first insulating film provided between the semiconductor substrate and the floating gate, an impurity diffusion layer provided in the semiconductor substrate, and a second insulating film formed on the impurity diffusion layer And the floating gate or another floating gate electrically connected to the floating gate is the second gate It is provided on top of the Enmaku.

  With this configuration, the charge in the floating gate can be extracted to the impurity diffusion layer. For this reason, the charge in the floating gate does not move to the photoelectric conversion unit, and it is possible to prevent the ratio of the exposure period in one frame period from decreasing.

  In the disclosed MOS image sensor, the thickness of the first insulating film in the direction perpendicular to the surface of the semiconductor substrate is smaller than the thickness of the second insulating film in the direction perpendicular to the surface of the semiconductor substrate.

  With this configuration, it is possible to prevent the charge from being injected from the impurity diffusion layer into the floating gate when the charge is injected into the floating gate.

  In the disclosed MOS image sensor, the pixel portion includes a read transistor having a floating gate electrically connected to the floating gate and having a threshold voltage that changes in accordance with the amount of charge injected into the floating gate. The readout unit reads out a signal corresponding to the threshold voltage of the readout transistor, and is perpendicular to the surface of the semiconductor substrate of the third insulating film between the floating gate of the readout transistor and the semiconductor substrate. The thickness in the direction is larger than the thickness of the second insulating film in the direction perpendicular to the surface of the semiconductor substrate.

  With this configuration, it is possible to prevent electric charges from being trapped in the trap in the third insulating film, and it is possible to accurately perform the signal reading operation.

  In the disclosed MOS type image sensor, the impurity diffusion layer is formed of a semiconductor having majority carriers of charges having the same polarity as the charges injected into the floating gate.

  In the disclosed MOS image sensor, the semiconductor is an n-type semiconductor.

  The disclosed imaging device applies voltages having opposite polarities to the MOS image sensor, the gate electrode of the semiconductor memory, and the impurity diffusion layer, respectively, and charges the floating gate to the second gate. A drive unit that performs charge discharge driving for tunneling the insulating film and discharging it to the impurity diffusion layer.

  The disclosed MOS type image sensor driving method is a method for driving the MOS type image sensor, wherein voltages having opposite polarities are applied to the gate electrode and the impurity diffusion layer of the semiconductor memory, respectively. The charges in the floating gate are discharged to the impurity diffusion layer by tunneling the second insulating film.

5 MOS type image sensor 4 Semiconductor layer 7 Tunnel insulating film 12 for charge injection Impurity diffusion layer 15 Tunnel insulating film 51 for charge erasing Semiconductor substrate 52a Pixel unit 55 Read unit FG Floating gate PD Photoelectric conversion unit WT Write transistor RT Read transistor WCG Write Control gate RCG Read control gate

Claims (7)

A photoelectric conversion unit that is formed in the semiconductor substrate and accumulates charges generated by photoelectric conversion, a floating gate provided above the semiconductor substrate into which the charges accumulated in the photoelectric conversion unit are injected, and opposite thereto A pixel portion having a semiconductor memory including a gate electrode provided at a position;
A readout unit that reads out a signal corresponding to the charge injected into the floating gate;
A first insulating film provided between the semiconductor substrate and the floating gate; an impurity diffusion layer provided in the semiconductor substrate; and a first insulating film formed on the impurity diffusion layer. Two insulating films,
A MOS type image sensor in which the floating gate or another floating gate electrically connected to the floating gate is provided on the second insulating film. The MOS image sensor according to claim 1,
A MOS type image sensor in which a thickness of the first insulating film in a direction perpendicular to the surface of the semiconductor substrate is smaller than a thickness of the second insulating film in a direction perpendicular to the surface of the semiconductor substrate. The MOS image sensor according to claim 1 or 2,
The pixel portion includes a readout transistor having a floating gate electrically connected to the floating gate and having a threshold voltage that changes according to the amount of charge injected into the floating gate,
The reading unit reads a signal corresponding to a threshold voltage of the reading transistor;
The thickness of the third insulating film between the floating gate of the read transistor and the semiconductor substrate in the direction perpendicular to the surface of the semiconductor substrate is the thickness of the second insulating film in the direction perpendicular to the surface of the semiconductor substrate. Larger MOS type image sensor. The MOS type image sensor according to any one of claims 1 to 3,
A MOS type image sensor in which the impurity diffusion layer is formed of a semiconductor having a majority carrier of charges having the same polarity as the charges injected into the floating gate. The MOS image sensor according to claim 4,
A MOS image sensor, wherein the semiconductor is an n-type semiconductor. The MOS image sensor according to any one of claims 1 to 5,
Charges that are applied to the gate electrode of the semiconductor memory and the impurity diffusion layer, respectively, with opposite polarities, and charge in the floating gate is tunneled through the second insulating film and discharged to the impurity diffusion layer. An imaging apparatus comprising: a drive unit that performs discharge driving. A method for driving a MOS image sensor according to any one of claims 1 to 5,
MOS that discharges the charges in the floating gate to the impurity diffusion layer by tunneling the second insulating film by applying voltages having opposite polarities to the gate electrode and the impurity diffusion layer of the semiconductor memory, respectively. Type image sensor drive method.

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