JP2011091324A - Semiconductor device and method of manufacturing the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device including a fin FET adaptable to microfabrication of a semiconductor device and furthermore capable of precisely controlling a height of a fin. <P>SOLUTION: The semiconductor device 10 includes: a fin 11 formed on a substrate; a plurality of semiconductor layers 14 and 16 constituting the fin 11; an insulating layer 15 interposed between the plurality of semiconductor layers 14 and 16; and a gate electrode 12 covering the fin 11. Furthermore, a channel region is formed in side walls of the plurality of semiconductor layers 14 and 16 in contact with the gate electrode 12. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a semiconductor device having a fin-type structure and a method for manufacturing a semiconductor device having a fin-type structure.

  The degree of integration of the semiconductor device doubled every 18 to 24 months according to Moore's law. However, gate tunnel leak current cannot be ignored from the vicinity of the 90 nm node, and thinning of the gate oxide film of the MOSFET has almost stopped. In addition, it is difficult to control the short channel effect, and the gate length is becoming finer. As a result, even if parameters other than the gate oxide film thickness and the gate length are miniaturized, it is difficult to improve the performance of the MOSFET.

  Since the 90 nm node, mobility improvement engineering using mechanical stress such as DSL (Dual Stress Liner) and embedded SiG has been performed. The mechanical stress technology considered for manufacturing is almost adopted up to the 45 nm node. From the 45 nm node onward, scaling of the apparent gate oxide film is progressing by increasing the dielectric constant of the gate oxide film such as High-K, Metal-Gate (HKMG).

  As a technique next to the HKMG, a fin field effect transistor (finFET) has been proposed for 22 nm and beyond (see, for example, Patent Document 1). This is expected as a semiconductor device structure that can withstand miniaturization rather than improving the performance of the MOSFET. That is, it is a proposal of a MOSFET structure suitable for semiconductor miniaturization, and a method for dramatically improving MOSFET performance has not yet been proposed.

An example of the structure of a conventional finFET is shown in FIG.
A fin-shaped semiconductor layer 131 protruding on the semiconductor substrate and an insulating layer 132 formed on the fin-shaped semiconductor layer 131 are formed. A U-shaped gate electrode 133 is formed so as to cover from one side surface of the fin-shaped semiconductor layer 131 to the opposite side surface. FIG. 27 shows a fin-shaped semiconductor layer including two p-MOS type fin field effect transistors (pFET) 134 and one n-MOS type fin field effect transistor (nFET) 135.
The finFET 130 is formed by such a structure.

However, in the finFET 130 configured as described above, the driving power of the pFET 134 is usually lower, and in order to balance the nFET 135 and the pFET 134, the driving current must be adjusted by the number of fins. This is a problem in a circuit in which the gate length of the finFET 130 is a discrete value and the beta ratio (NP ratio) is important. There are also concerns about leakage current.
For example, FIG. 28 shows a configuration example of a finFET when the drive currents of nFET and pFET are made uniform. If the current ratio of N and P is 1.5, the drive current can be adjusted by setting two finFETs 137 having nFETs and three finFETs 136 having pFETs as shown in FIG.

  In addition, as a method for solving the above-described problem, it has been proposed to form a plurality of fin heights directly or indirectly (for example, Patent Document 2, Patent Document 3, Patent Document 4, Patent Document 5, (See Patent Document 6).

In addition, various manufacturing methods for forming finFETs having a plurality of types of heights have been proposed for the semiconductor device having a configuration in which the heights of the plurality of fins are formed. For example, finFETs having different heights are formed by providing a step in a semiconductor layer for forming fins and processing the semiconductor layer provided with the step into fins (for example, Patent Document 2 and Patent Document 2). 3, Patent Document 4 and Patent Document 6). Further, after fins having the same height are formed, fins having different heights are formed by etching the fins to a predetermined height (see, for example, Patent Document 1).
Further, a fin including a chemical injection species and a fin not including a chemical species are formed by injecting a chemical injection species including germanium without changing the physical height of the fin, thereby inactivating the bottom of the fin. It has been proposed. In this method, the vertical dimension of the semiconductor fin in the injected fin can be adjusted by adjusting the depth of the implanted chemical species (see, for example, Patent Document 5).

US Pat. No. 6,413,802 Japanese Patent Laid-Open No. 2007-149942 JP 2008-124423 A JP 2008-141177 A Special table 2007-535153 gazette JP 2005-251873 A

M.Miyao, et al., “Low-temperature SOI (Si-on-insulator) formation by lateral solid-phase epitaxy,” J. Appl. Phys. 64 (6), 15 Sep. 1988, pp. 3018. Eiji Fujii, “Dependence of growth length of single silicon crystals on scanning direction of laser beam in lateral seeding process,” J. Appl. Phys. 63 (8), 15 Apr. 1988, pp. 2633.

However, in the above-described finFET configuration shown in FIG. 27, it is necessary to form p-type and n-type semiconductor devices in a cell whose height is determined by the distance between Vdd and GND M1 according to the conventional semiconductor physical layout. is there. For this reason, in order to form at least one pFET and nFET fin, two or more fins in total are required. Thus, the required number of fins hinders miniaturization of the semiconductor device.
In the semiconductor device in which a plurality of fin heights are formed directly or indirectly as described above, it is difficult to precisely control the fin height.

  In order to solve the above-described problems, the present invention provides a semiconductor device including a finFET that can cope with miniaturization of a semiconductor device and can precisely control the height of the fin, and a method of manufacturing the semiconductor device. To do.

  A semiconductor device according to the present invention includes a fin formed on a base, a plurality of semiconductor layers constituting the fin, an insulating layer interposed between the plurality of semiconductor layers, and a gate electrode covering the fin. The Then, channel regions are formed in the side wall portions of the plurality of semiconductor layers in contact with the gate electrode.

  The manufacturing method of the semiconductor device of the present invention includes a step of forming a laminated substrate by laminating an insulating layer and a semiconductor layer on a substrate. Then, a step of processing the stacked semiconductor layer and insulating layer into a fin shape, a step of forming a gate insulating film covering the fin-shaped semiconductor layer and the insulating layer, and forming a gate electrode on the gate insulating film Process.

According to the semiconductor device of the present invention and the semiconductor device according to the method of manufacturing a semiconductor device of the present invention, a plurality of semiconductor layers are formed in the fin. Can be formed by two fins.
Further, by interposing an insulating layer between the semiconductor layers to be stacked, this insulating layer serves as an etching stopper, and the height of the plurality of semiconductor layers stacked in the fin can be precisely controlled.

  According to the present invention, the semiconductor device can be miniaturized by forming a plurality of semiconductor devices with one fin. In addition, by using the insulating layer as an etching stopper, each semiconductor layer to be stacked can be manufactured with precise height control.

It is a figure which shows the structure of 1st Embodiment of the semiconductor device of this invention. It is a figure which shows the structure of 1st Embodiment of the semiconductor device of this invention. It is a figure which shows the structure of 1st Embodiment of the semiconductor device of this invention. It is a figure which shows the structure of 1st Embodiment of the semiconductor device of this invention. It is a figure which shows the structure of 1st Embodiment of the semiconductor device of this invention. A is a configuration diagram of an inverter circuit using the semiconductor device of the present invention. B is a configuration diagram of an inverter circuit using a conventional semiconductor device. A is a configuration diagram of a NAND circuit using the semiconductor device of the present invention. B is a configuration diagram of a NAND circuit using a conventional semiconductor device. A and B are diagrams showing a configuration of an embodiment of a semiconductor device of the present invention. A is a configuration diagram of an SRAM using the semiconductor device of the present invention. B is a configuration diagram of an SRAM using a conventional semiconductor device. It is a figure which shows the structure of 2nd Embodiment of the semiconductor device of this invention. AC is a figure which shows the selectable discrete value of the gate length of finFET. AC is a figure which shows the selectable discrete value of the gate length of finFET. It is a figure which shows the structure of 3rd Embodiment of the semiconductor device of this invention. A to C are manufacturing process diagrams of a laminated substrate using a smart cut method. D to G are manufacturing process diagrams of a laminated substrate using the smart cut method. A to E are manufacturing process diagrams of a laminated substrate using a horizontal solid phase growth method. A to D are manufacturing process diagrams of the semiconductor device according to the first embodiment of the present invention. E to H are manufacturing process diagrams of the first embodiment of the semiconductor device of the present invention. I and J are manufacturing process diagrams of the first embodiment of the semiconductor device of the present invention. KM is a manufacturing process diagram of the first embodiment of the semiconductor device of the invention. N to O are manufacturing process diagrams of the first embodiment of the semiconductor device of the present invention. P to R are manufacturing process diagrams of the semiconductor device according to the first embodiment of the present invention. It is a manufacturing process figure of 2nd Embodiment of the semiconductor device of this invention. It is a manufacturing process figure of 2nd Embodiment of the semiconductor device of this invention. It is a manufacturing process figure of 2nd Embodiment of the semiconductor device of this invention. FIG. 4A is a plan view of a finFET for explaining a relationship between a work function of a gate electrode and a channel impurity. B is a cross-sectional view of the finFET for explaining the relationship between the work function of the gate electrode and the impurity of the channel. It is a schematic block diagram of the conventional semiconductor device. It is a schematic block diagram of the conventional semiconductor device.

Examples of the best mode for carrying out the present invention will be described below, but the present invention is not limited to the following examples.
The description will be given in the following order.
1. 1. First embodiment of semiconductor device 2. Second embodiment of semiconductor device 3. Third embodiment of semiconductor device Manufacturing method of semiconductor device

<1. First Embodiment of Semiconductor Device>
[Schematic configuration of semiconductor device]
Hereinafter, specific embodiments of the semiconductor device of the present invention will be described.
FIG. 1 is a perspective view of a semiconductor device having a fin-type structure according to this embodiment.

  As shown in FIG. 1, a fin-type electric field in which a channel region of an upstanding thin semiconductor layer (fin) 11 is covered with a gate electrode 12 on a base (not shown) and sandwiched between the gate electrodes 12 from the left and right side surfaces of the channel region. An effect transistor (finFET) 10 is formed.

For example, a thin semiconductor layer (fin) 11 standing on a silicon substrate is formed. The fin 11 has a structure in which a first conductivity type, for example, a p-type first semiconductor layer 14 and a second conductivity type, for example, an n-type second semiconductor layer 16 are stacked.
In the fin 11, the insulating layer 15 is formed on the second semiconductor layer 16, and the first semiconductor layers 14 having different channel types are formed on the insulating layer 15. An insulating layer 13 is formed on the uppermost layer of the fin 13.
Thus, the fin 11 of the finFET 10 includes the insulating layer 13 and a plurality of stacked semiconductor layers.

A gate electrode 12 is formed so as to cover the fin 11 described above.
The gate electrode 12 is formed in a U shape so as to cover the channel region of the first semiconductor layer 14 and the second semiconductor layer 16 of the fin 11 from one side surface to the other side surface facing each other.
The gate electrode 12 is preferably made of a material having a midgap work function. By using this, it is possible to set an np symmetrical threshold voltage.

With the above configuration, the p-MOS type fin field effect transistor (pFET) 17 and the n-MOS type fin field effect transistor (nFET) 18 can be formed by one fin. That is, by forming one finFET, finFETs having two different transistor characteristics can be formed.
As described above, by forming a plurality of semiconductor layers through the insulating layer, a plurality of types of finFETs can be formed in one fin.

  Thus, by forming two types of finFETs in one fin, in the circuit element formed by the combination of the N-type semiconductor and the P-type semiconductor in the conventional semiconductor device, in many cases, the area Can be halved. For this reason, by using the finFET of the present embodiment having the above-described configuration, the semiconductor device can be miniaturized. In particular, with respect to the problem that the MOSFET performance does not dramatically increase after the 22 nm node, this problem can be solved by forming a finFET having the above-described configuration to achieve more aggressive miniaturization of the MOSFET. .

  In the finFET 10 described above, the gate length of the transistor can be arbitrarily set by arbitrarily setting the height of the pFET 17 and the height of the nFET 18. For example, the height of the pFET 17 and the height of the nFET 18 are set to 2: 1. By setting in this way, in the finFET 10, the gate length of the pFET 17 can be doubled that of the nFET 18.

  As described above, by forming the heights of the pFET and the nFET at an arbitrary ratio in the finFET 10, the designer can arbitrarily select the gate length of the finFET. In particular, by separating the upper layer and the lower layer by the insulating layer, the height of the finFET can be accurately controlled, and the gate length of the finFET can be accurately formed.

  In the description of the present embodiment, the heights of the fins, the semiconductor layer, and the insulating layer indicate the dimensions of the constituent portions measured in the direction perpendicular to the semiconductor substrate from the surface of the semiconductor substrate. For example, the height of the fin is a dimension measured from the bottom of the fin formed on the upper surface of the semiconductor substrate to the upper surface of the fin.

  In the above-described finFET, pFETs may be stacked via an insulating layer, or nFETs may be stacked via an insulating layer. In addition, three or more semiconductor layers can be stacked. In this case as well, when three or more stacked semiconductor layers are stacked, pFETs and nFETs can be freely combined. In addition, when three or more semiconductor layers are stacked, the semiconductor layers are stacked with an insulating layer interposed between the semiconductor layers.

[Example of formation of via contact to finFET]
Next, formation of via contacts of the pFET 17 and the nFET 18 in the finFET 10 of the above-described embodiment will be described.
In the above-described finFET 10, via contacts are formed on the source and drain of the pFET 17 and the nFET 18, thereby connecting to a wiring (not shown) of the semiconductor device.

In the finFET 10, via contacts are formed in each of the stacked layers via the insulating layer 15. In other words, the semiconductor layer to be used can be selected from the first semiconductor layer 14 and the second semiconductor layer 16 in the finFET 10 by changing the position in the height direction in which the via contact is formed.
Further, the channel length of the transistor can be selected by changing the position in the length direction of the fin forming the contact of the finFET 10, that is, the distance between the via contacts formed in the source / drain of the pFET 17 or nFET 18.

In the finFET 10, when it is desired to form a contact only on the upper pFET 17, a via contact 19 is formed from the top of the finFET 10 to a position where it is connected to the first semiconductor layer 14, as shown in FIG.
With this configuration, only the pFET 17 can be driven without driving the nFET 18 in the finFET 10.

In the finFET 10, when it is desired to connect the pFET 17 and the nFET 18, a via contact 19 is formed from the top of the finFET 10 to a position where it is connected to the second semiconductor layer 16 as shown in FIG. 3. At this time, the via contact 19 is formed on the surface of the source / drain of the semiconductor layer so as to cover the surface of the fin.
With this configuration, the finFET 10 can be driven by being connected to the nFET 18 and the pFET 17.

  In addition, when it is desired to form a contact only in the nFET 18 formed in the lower layer of the finFET 10, the lower second semiconductor layer 18 and the insulating layer 15 are made higher than the upper first semiconductor layer 14 as shown in FIG. , Extending from the gate electrode 12. A via contact 19 is connected to the extended second semiconductor layer 16. With such a configuration, in the finFET 10, only the lower nFET 18 can be driven.

  Further, when a contact is formed only on the nFET 18 formed in the lower layer of the finFET 10, the insulating layer 20 may be formed on the extended second semiconductor layer 16 as shown in FIG. 5. The insulating layer 20 is formed on the extended second semiconductor layer 16 and insulating layer 15 to the same height as the first semiconductor layer 14 and insulating layer 13. Then, by forming a via contact 19 connected from the insulating layer 20 to the second semiconductor layer 18, a contact to the nFET 18 is formed.

As described above, even in the finFET 10 having the configuration in which the pFET 17 and the nFET 18 are stacked, an arbitrary driving method is selected by changing the connection method of the via contact 19 to the stacked semiconductor layers forming the fin 11. be able to.
For example, the pFET 17 or the nFET 18 can be driven independently. Further, the pFET 17 and the nFET 18 can be connected and driven.
A circuit function can be imparted to the finFET 10 of the present embodiment described above by combining the gate electrode 12 and the way of connecting the via contact.

[Example 1 of semiconductor device using finFET: inverter circuit]
Next, an embodiment of a semiconductor device in which a circuit is configured using the above-described finFET will be described.
FIG. 6A shows a top view of a configuration example of an inverter circuit formed by using the above-described finFET of this embodiment. For comparison, FIG. 6B shows a top view of a configuration example of an inverter circuit when a conventional MOSFET is used.
In the example of the inverter of this embodiment shown in FIG. 6A, the gate electrode G1, the power supply voltage (VDD) 25, the ground (GND) 26, and the contact (NP connection) 24 that connects the pFET 17 and the nFET 18 in the finFET. Prepare.

  In the finFET shown in FIG. 6A, similarly to the semiconductor device shown in FIG. 1, the pFET 17 is formed in the upper layer, and the nFET 18 is formed in the lower layer through the insulating layer. Then, one end of the lower nFET 18 is formed so as to extend from the pFET 17 as in the finFET configuration shown in FIGS. 4 and 5.

As shown in FIG. 3 described above, the NP connection 24 is a via contact formed by connecting to the stacked first semiconductor layer and the second semiconductor layer, and the pFET 17 stacked in the finFET by this contact. And nFET 18 are connected.
The gate electrode G1 is formed to cover the channel regions of the pFET 17 and the nFET 18 as in the configuration shown in FIG.
As shown in FIG. 2, the VDD 25 is a via contact that is connected only to the pFET 17 formed in the upper layer of the fin.
A GND 26 is connected to the nFET 18 extending from the pFET 17 by a via contact that connects only to the nFET 18 having the configuration shown in FIG. 4 or 5 described above.

  The inverter having the conventional structure includes a pMOS region 27 and an nMOS region 28 as shown in FIG. 6B. A common gate electrode G1 is provided for the pMOS region 27 and the nMOS region 28. Then, VDD is connected to the source of the pMOS region 27. Further, an NP connection by contact is provided to the drain of the pMOS region 27 and the source of the nMOS region 28. The drain of the nMOS region 28 is connected to GND.

By using the finFET of this embodiment, an inverter can be configured with an area for forming one finFET. On the other hand, as described above, the conventional inverter requires a region for forming the pMOS and a region for forming the nMOS on the substrate.
Therefore, in the finFET of this embodiment, the area for forming the inverter circuit can be integrated into one finFET by combining the gate electrode and the contact connected to the pFET and the nFET. Therefore, the semiconductor device can be miniaturized by using the finFET of this embodiment.

[Example 2 of Semiconductor Device Using FinFET: NAND Circuit]
Next, an embodiment of a NAND circuit using the finFET of this embodiment will be described.
FIG. 7A shows a top view of a configuration example of a NAND circuit formed using the above-described finFET of this embodiment. For comparison, FIG. 7B shows a top view of a configuration example of a NAND circuit when a conventional MOSFET is used.
In the example of the NAND circuit of this embodiment shown in FIG. 7A, in the gate electrodes G1 and G2, the power supply voltage (VDD) 25, the ground (GND) 26, and the finFET, a contact (NP connection) that connects the pFET 17 and the nFET 18 ) 24.

  In the finFET shown in FIG. 7A, similarly to the semiconductor device shown in FIG. 1, the pFET 17 is formed in the upper layer, and the nFET 18 is formed in the lower layer through the insulating layer. Then, one end of the lower nFET 18 is formed so as to extend from the pFET 17 as in the finFET configuration shown in FIGS. 4 and 5.

As shown in FIG. 3 described above, the NP connection 24 is a via contact formed by connecting to the stacked first semiconductor layer and the second semiconductor layer, and the pFET 17 stacked in the finFET by this contact. And nFET 18 are connected.
The gate electrode G1 and the gate electrode G2 in the region where the pFET 17 and the nFET 18 are stacked are formed so as to cover the channel region of the finFET as in the configuration shown in FIG.

Further, as shown in FIGS. 8A and 8B, the gate electrode G2 on the side where only the nFET 18 is extended covers the channel region of the fin composed of the nFET 18 and the insulating layers 31A and 31B formed on the nFET 18. Is formed. In FIG. 8A, the insulating layer 31A formed on the nFET 18 is formed up to the same height as the pFET and the insulating layer formed on the nFET 18. That is, it is formed similarly to the insulating layer 20 of the finFET shown in FIG. A gate electrode 33 is formed to cover the insulating layer 31A.
In FIG. 8B, the insulating layer 31B is formed with the thickness of the insulating layer interposed between the nFET 18 and the pFET 17 being maintained. That is, it is formed in the same manner as the insulating layer 15 of the finFET shown in FIG. A gate electrode 33 is formed to cover the insulating layer 31B.

  At both ends of the pFET 17, as shown in FIG. 2 described above, VDD 25 is formed by a via contact connected only to the pFET 17 formed in the upper layer of the fin. Further, the GND 26 is connected to the end of the nFET 18 extending from the pFET 17 by a via contact that connects only to the nFET 18 having the configuration shown in FIG. 4 or FIG.

  The NAND circuit having a conventional structure is composed of a pMOS region 29 and an nMOS region 30 as shown in FIG. 7B. Also, common gate electrodes G 1 and G 2 are provided for the pMOS region 29 and the nMOS region 30. Then, VDD is connected to the source of the pMOS region 29. Further, the pMOS region 27 and the nMOS region 28 are provided with NP connection by wiring.

By using the finFET of this embodiment, a NAND circuit can be configured with an area for forming one finFET. On the other hand, as described above, a NAND circuit having a conventional structure requires a region for forming a pMOS and a region for forming an nMOS on a substrate.
Therefore, in the finFET of this embodiment, the area for forming the NAND circuit can be integrated into one finFET by combining the gate electrode and the contact connected to the pFET and the nFET. Therefore, the semiconductor device can be miniaturized by using the finFET of this embodiment.

[Example 3: Semiconductor Device Using FinFET: SRAM]
Next, an embodiment of the SRAM using the finFET of this embodiment will be described.
FIG. 9A shows a top view of a configuration example of the SRAM formed using the above-described finFET of the present embodiment. For comparison, FIG. 9B shows a top view of a configuration example of an SRAM when a conventional MOSFET is used.

First, the configuration of the conventional SRAM shown in FIG. 9B will be described.
The SRAM shown in FIG. 9B is a 6-transistor SRAM structure that uses a conventional planar MOSFET.
The SRAM shown in FIG. 9B includes a semiconductor region 34 formed on the surface of a semiconductor substrate (not shown), a gate electrode 35 formed on the semiconductor substrate base, and a wiring 36. Further, an nMOS region 38 and an nMOS region 39 are formed with the pMOS region 37 interposed therebetween. In the pMOS region 37, two transistors, pFET 40 and pFET 41, are formed. Further, nFET 42 and nFET 43 are formed in the nMOS region 38, and four transistors of nFET 44 and nFET 45 are formed in the nMOS region 39.

  In the example of the SRAM of this embodiment shown in FIG. 9A, in the gate electrodes 48 and 49, the power supply voltage (VDD) 25, the ground (GND) 26, the bit line (BL) 32, and the finFET, the pFET 17 and the nFET 18 are connected. A contact (NP connection) 24 to be connected is provided.

The SRAM configured using the finFET of this embodiment shown in FIG. 9A is configured by forming finFET 46 and finFET 47 having the same configuration as the semiconductor device shown in FIG. 1 and connecting them with via contacts and gate electrodes. ing.
In the finFET 46 and the finFET 47, similarly to the semiconductor device shown in FIG. 1, the pFET 17 is formed in the upper layer, and the nFET 18 is formed in the lower layer through the insulating layer. In the finFET 46 and the finFET 47, both ends of the lower layer nFET 18 are formed so as to extend from the pFET 17 as in the finFET configuration shown in FIGS.

An NP connection 24 is formed at one end of the pFET 17 and a VDD 25 is formed at the other end.
As shown in FIG. 3 described above, the NP connection 24 is a via contact formed by connecting to the stacked first semiconductor layer and the second semiconductor layer, and the pFET 17 stacked in the finFET by this contact. And nFET 18 are connected.
The gate electrode 48 is formed so as to cover the channel region of the finFET as in the configuration shown in FIG.
The gate electrode 48 of the finFET 46 and the NP connection 24 of the finFET 47 are connected to each other, and the gate electrode 48 of the finFET 47 and the NP connection 24 of the finFET 46 are connected to each other.

Further, the VDD 25 formed in the pFET 17 is formed by a via contact connected only to the pFET 17 formed in the upper layer of the fin, as shown in FIG. 2 described above.
In the nFET 18 extended from the pFET 17, a GND 26 is connected to the end of the pFET 17 on the side where the VDD 25 is formed by a via contact connected only to the nFET 18 having the configuration shown in FIG. 4 or 5 described above. Further, in the nFET 18 extending from the pFET 17, a gate electrode 49 and BL 32 are formed at the end portion on the side where the NP connection 24 is formed.

  As shown in FIGS. 8A and 8B, the gate electrode 49 where only the nFET 18 extends is formed so as to cover the channel region of the finFET composed of the nFET 18 and the insulating layers 31A and 31B formed on the nFET 18. Has been. The BL 32 formed in the nFET 18 is formed by a via contact connected only to the nFET 18 having the configuration shown in FIG. 4 or 5 described above.

By configuring the SRAM using the finFET of the present embodiment, the area used on the substrate can be integrated up to the area of two finFETs. On the other hand, as described above, an SRAM having a conventional structure requires a region for forming a pMOS and a region for forming an nMOS on a substrate, and particularly requires a region for forming six pFETs or nFETs. there were.
Therefore, in the finFET of the present embodiment, the SRAM semiconductor formation area can be reduced by combining the gate electrode and the contact connected to the pFET and the nFET. Therefore, by using the finFET of this embodiment, the area necessary for forming the semiconductor device can be reduced, and the semiconductor device can be miniaturized.

<2. Second Embodiment of Semiconductor Device>
In the first embodiment described above, the case where the pFET and the nFET are formed in one fin has been described. In the configuration of the finFET of this embodiment, semiconductor layers having the same conductivity type may be formed as the types of semiconductors to be combined.
FIG. 10 shows a perspective view of a finFET having a structure in which transistors of the same channel type are stacked.

  In a finFET 50 shown in FIG. 10, standing thin semiconductor layers (fins) 51, 52, and 53 are formed on a base (not shown). A gate electrode 54 is formed so as to cover the channel regions of the fins 51, 52, and 53 and to be sandwiched from the left and right side surfaces of the channel region.

  The fin 51 and the fin 52 have a configuration in which upper semiconductor layers 56 and 60 and lower semiconductor layers 58 and 62 are stacked with insulating layers 57 and 61 interposed therebetween. In the fins 51 and 52, the semiconductor layers stacked via the insulating layers 57 and 61 are semiconductor layers of the first conductivity type or the second conductivity type. When the first conductivity type semiconductor layer is formed in the lower semiconductor layers 58 and 62, the first conductivity type semiconductor layer is also formed in the upper semiconductor layers 56 and 60. When the second conductive type semiconductor layer is formed in the lower semiconductor layers 58 and 62, the second conductive type semiconductor layer is similarly formed in the upper semiconductor layers 56 and 60. Further, an insulating layer 59 is formed on the upper semiconductor layers 56 and 60.

  Further, the lower semiconductor layers 58 and 62 are formed so that the height of the semiconductor layers is smaller than that of the upper semiconductor layers 56 and 60. For example, the upper semiconductor layers 56 and 60 are formed at a height of 2/3 with respect to the height of the entire semiconductor layer in the fins 51 and 52, and the lower semiconductor layers 58 and 62 are as high as 1/3. Form with. The ratio between the height of the upper semiconductor layer and the height of the lower semiconductor layer can be set arbitrarily. For example, the lower semiconductor layer can be formed by 1/3 of the upper semiconductor layer, and the lower semiconductor layer and the upper semiconductor layer can be formed in other ratios. At this time, it is preferable to make the height of the lower semiconductor layer smaller than the height of the upper semiconductor layer.

The fin 53 includes a semiconductor layer 64 of the first conductivity type or the second conductivity type, and an insulating layer 63 formed on the semiconductor layer 64. The semiconductor layer 64 is formed in the same channel type as the upper semiconductor layers 56 and 60 formed on the fins 51 and 52 and the lower semiconductor layers 58 and 62.
The semiconductor layer 64 formed on the fin 53 is formed at the same height as the semiconductor layers 58 and 62 below the fin 51 and the fin 52 described above. Then, by forming the insulating layer 63 on the semiconductor layer 64, the height of the fin 53 is formed to be the same as that of the fin 51 and the fin 52. The insulating layer 64 is formed in the fin 51 and the fin 52 at the same height as the upper insulating layers 55 and 59 to the insulating layers 57 and 61 interposed in the semiconductor layer.

In general, in the finFET, the length of the side surface portion in contact with the gate electrode in the semiconductor layer formed on the fin is the gate length. For this reason, as described above, the number of gate lengths that can be selected is increased by stacking semiconductor layers having different heights via an insulating layer.
When a transistor having the same height as the fin is formed as in the prior art, the gate length is determined by the height of the fin, and thus the gate length needs to be controlled by the number of fins. For this reason, in order to set the strength of the transistor, the gate length that can be selected by the designer is discretized, and the number of discrete values is small.
On the other hand, in the finFET of the present embodiment described above, semiconductor layers having different heights are formed in the fins via insulating layers, and fins having different semiconductor layer heights are formed. Thus, since there are two or more types of semiconductor layers, not only the number of fins but also fins having different semiconductor layer heights can be selected. Therefore, the number of discrete gate lengths that can be selected by the designer is increased more than twice as compared with the conventional finFET.

FIG. 11 shows selectable discrete values of the gate length of the finFET having the above-described fins having semiconductor layers with different heights when three fins are formed.
FIG. 11A shows selectable gate lengths in the case where a semiconductor layer having a height of 1/3 is formed on one of the three fins. FIG. 11B shows selectable gate lengths when a semiconductor layer having a height of 1/2 is formed on one of the three fins. For comparison, FIG. 11C shows gate lengths that can be selected when a semiconductor layer having the same height is formed on three fins of the conventional structure.

As shown in FIG. 11A, when a semiconductor layer having a height of 1/3 is formed on one fin, discrete values selectable for the gate length are 0.3, 0.6, 1, 1.3. , 1.6, 2, 2.3 and 3.
Further, as shown in FIG. 11B, when a semiconductor layer having a height of 1/2 is formed on one fin, discrete values selectable for the gate length are 0.5, 1, 1.5, 2 , 2.5 and 3 types.
On the other hand, as shown in FIG. 11C, the conventional fin has three types of 1, 2 and 3.
Thus, by forming fins with different heights of the semiconductor layer, the number of discrete gate lengths can be increased more than twice as compared with the conventional finFET.

FIG. 12 shows selectable discrete values of the gate length of the finFET having the fins having the semiconductor layers with different heights when two fins are formed.
FIG. 12A shows selectable gate lengths in the case where a semiconductor layer having a height of 1/3 is formed on one of the two fins. FIG. 12B shows selectable gate lengths in the case where a semiconductor layer having a height of 1/2 is formed on one of the two fins. For comparison, FIG. 12C shows gate lengths that can be selected when a semiconductor layer having the same height is formed on two fins having a conventional structure.

As shown in FIG. 12A, when a semiconductor layer having a height of 1/3 is formed on one fin, discrete values selectable for the gate length are 0.3, 0.6, 1, 1.3. And 2 types.
As shown in FIG. 12B, when a semiconductor layer having a height of 1/2 is formed on one fin, discrete values selectable for the gate length are 0.5, 1, 1.5, and 2 There are four types.
On the other hand, as shown in FIG. 12C, there are two types, 1 and 2, in the conventional fin.
As described above, even when the number of fins is two, the number of discrete gate lengths can be increased more than twice that of the conventional finFET by forming fins having different semiconductor layer heights. Can do.

<3. Third Embodiment of Semiconductor Device>
Next, FIG. 13 shows a finFET having a structure in which the number of discrete gate lengths can be made larger than that of a conventional finFET, like the finFET of the second embodiment described above.
In the finFET 70 shown in FIG. 13, standing thin semiconductor layers (fins) 71, 72, 73 are formed on a base (not shown). A gate electrode 74 is formed so as to cover the channel regions of the fins 71, 72, and 73 and to be sandwiched between the left and right side surfaces of the channel region.

The fin 71 and the fin 72 have a configuration in which upper semiconductor layers 76 and 80 and lower semiconductor layers 78 and 82 are stacked with insulating layers 77 and 81 interposed therebetween. In the fin 71 and the fin 72, the semiconductor layers stacked via the insulating layers 77 and 81 are semiconductor layers of the first conductivity type or the second conductivity type, and the semiconductor layers 78 and 82 in the lower layer and the semiconductor layers in the upper layer. A semiconductor layer of the same conductivity type is formed on the semiconductor layers 76 and 80. Furthermore, insulating layers 75 and 79 are formed on the upper semiconductor layers 76 and 80.
In addition, the lower semiconductor layers 78 and 82 are formed with a smaller semiconductor layer height than the upper semiconductor layers 76 and 80. For example, the lower semiconductor layers 78 and 82 are formed at half the height of the upper semiconductor layers 76 and 80.

In the fin 73, an upper semiconductor layer 84 and a lower semiconductor layer 86 are stacked with an insulating layer 85 interposed therebetween. In the fin 73, the semiconductor layer stacked via the insulating layer 85 is a semiconductor layer of the first conductivity type or the second conductivity type, and the semiconductor layer of the first conductivity type is formed in the lower semiconductor layer 86. In this case, the first conductive type semiconductor layer is also formed in the upper semiconductor layer 84.
Further, when the second conductive type semiconductor layer is formed in the lower semiconductor layer 86, the second conductive type semiconductor layer is similarly formed in the upper semiconductor layer 84. Further, an insulating layer 83 is formed on the upper semiconductor layer 84.

In addition, the concentration of impurities doped in the upper semiconductor layer 84 in the fin 73 is sufficiently higher than that in the lower semiconductor layer 86 and the semiconductor layers 76, 78, 80, and 82 formed in the fins 71 and 72. Highly structured. In the semiconductor layer 84 on the upper layer of the fin 73, the threshold voltage (Vth) of the transistor formed of the semiconductor layer 84 is made higher than the Vth of the transistor formed of the other semiconductor layer by making the impurity concentration sufficiently higher than that of the other semiconductor layers. Also make it high enough.
Note that the semiconductor layer 86 under the fin 73 and the semiconductor layers 76, 78, 80, and 82 formed in the fins 71 and 72 are doped with impurities at the same concentration, or doped with impurities. There is no configuration.

As described above, the semiconductor layer to be driven can be selected by increasing Vth of the semiconductor layer 84 above the fin 73 and reducing the current driving force.
That is, when driving the finFET 70, if a voltage equal to or lower than Vth of the semiconductor layer 84 having a high impurity concentration is applied to the gate electrode 74, the transistor including the lower semiconductor layer 86 is driven, but the semiconductor layer 84 having a high impurity concentration is driven. The transistor that does not drive. Therefore, by using a voltage equal to or lower than Vth of the semiconductor layer 84 for driving the finFET 70, the gate length of the fin 73 can be substantially limited to the height of the lower semiconductor layer 86. As a result, the gate length of only the lower semiconductor layer 86 can be the gate length of the fin 73. Therefore, fins 73 having different gate lengths can be formed with respect to the fins 71 and 72, and finFETs having transistors having different gate lengths can be formed.

In the second embodiment described above, the gate length is directly changed by changing the height at which the semiconductor layer is formed. On the other hand, in the third embodiment, the gate length is indirectly increased by changing the threshold voltage of some semiconductor layers by doping impurities without changing the height at which the semiconductor layer in the fin is formed. Can be changed.
By providing transistors with different gate lengths, the number of discrete gate lengths can be increased more than twice that of the conventional finFET, as in the case of the finFET of the second embodiment described above.

<4. Manufacturing Method of Semiconductor Device>
Next, a method for manufacturing the finFET of the above-described embodiment will be described. The finFET of the above-described embodiment is manufactured using a laminated substrate in which a semiconductor layer and an insulating layer are laminated on a substrate.
Therefore, prior to the description of the finFET manufacturing method, an example of the manufacturing method of the multilayer substrate will be described. As the multilayer substrate manufacturing method, the following smart cut method and lateral solid phase growth method are used. In addition, the manufacturing method of the laminated base used for manufacturing finFET is not restricted to these methods, The laminated base manufactured by the other method can also be used.

[Manufacturing method of laminated substrate 1: Smart cut method]
First, a method for manufacturing a laminated substrate using the smart cut method will be described with reference to the drawings.
As shown in FIG. 14A, a bond base 90 made of a semiconductor material such as silicon is prepared. Then, as shown in FIG. 14B, an insulating layer 91 is formed on the surface of the bond substrate 90 by a thermal oxidation method.

Next, as shown in FIG. 14C, hydrogen ions 93 are implanted into the bond substrate 90 on which the insulating layer 91 made of an oxide film or the like is formed. By implanting hydrogen ions 93, a micro cavity is formed in the bond substrate 90. By controlling the position where hydrogen ions 93 are implanted, the position where the cavity is formed, particularly the position in the thickness direction of the bond substrate from the insulating layer 91 is controlled.
Next, as shown in FIG. 15D, the bond base 90 into which hydrogen ions 93 are implanted is turned over, and the surface on which the insulating layer 91 is formed is bonded to a support base 92 made of a semiconductor material such as silicon.

Then, as shown in FIG. 15E, the bonding substrate 90 is heated to about 500 ° C. while being bonded to the supporting substrate 92. By heating the bond substrate 90 in the state where the hydrogen ions 93 are implanted, hydrogen embrittlement 93A is caused in the substrate at the position where the hydrogen ions 93 are implanted.
Then, after the hydrogen embrittlement occurs, as shown in FIG. 15F, the bond base 90A on the support base 93 side is left from the position where the hydrogen embrittlement 93A occurs, and the position higher than the position where the hydrogen embrittlement 93A occurs is left. The bond substrate 90B is peeled off. And the surface of the peeling surface of bond board | substrate 90A is grind | polished, and also it heats to 1000-1100 degreeC.
Through the above steps, a laminated structure of an insulating layer and a semiconductor layer is formed on the supporting base 92 by the insulating layer 91 and the bond base 90A.

Further, the steps shown in FIGS. 14A to 14C are performed, and the insulating layer side of the bond substrate in which hydrogen ions are implanted on the support substrate 92 on which the insulating layer 91 and the semiconductor layer (bond substrate 90A) shown in FIG. 15F are formed. Paste together. Then, after hydrogen embrittlement occurs in the bond substrate by heating, the bond substrate is peeled off from the hydrogen embrittled position.
By repeating the above steps, as shown in FIG. 15G, the insulating layer 91, the semiconductor layer (bond substrate 90A), the insulating layer 91C, and the semiconductor layer (bond substrate 90C) are insulated from the semiconductor layer on the support substrate 92. A laminated substrate composed of layers can be formed.

  The thickness of each layer is, for example, 60 nm, 30 nm, 40 nm, and 150 nm for the insulating layer 91, the semiconductor layer (bond base 90A), the insulating layer 91C, and the semiconductor layer (bond base 90C). The thickness of each layer of the laminated substrate can be appropriately selected and adjusted according to the height of the semiconductor layer to be laminated in the finFET to be formed and the generation.

[Lamination Substrate Manufacturing Method 2: Lateral Solid Phase Growth Method]
Next, a method for manufacturing a laminated substrate using the lateral solid phase growth method will be described with reference to the drawings.
As shown in FIG. 16A, a semiconductor substrate 94 made of silicon or the like having an insulating layer 95 made of an oxide film or the like formed on the surface by a thermal oxidation method or the like is prepared.
Next, as shown in FIG. 16B, the insulating layer 95 is patterned by removing a part of the insulating layer 95 using photolithography, etching, or the like, and a part of the semiconductor substrate 94 is exposed. Then, on the insulating layer 95 and the exposed semiconductor substrate 94 layer, semiconductor layers 97 and 98, for example, amorphous Si thin films are formed to 10 to 100 nm using a CVD (Chemical Vapor Deposition) method. At this time, the semiconductor substrate 94 exposed from the insulating layer 95 becomes the seed region 96, and the semiconductor layer 96 formed on the seed region 96 becomes a single crystal layer. On the other hand, the semiconductor layer 98 formed on the insulating layer 95 is an amorphous layer.

Next, by performing lateral solid phase epitaxial growth (LSPE) on the semiconductor layer 97 made of a single crystal layer and the semiconductor layer 98 made of an amorphous layer, the amorphous layer becomes a single crystal layer. By this lateral solid phase epitaxial growth, a semiconductor layer 97 of a single crystal layer is formed on the semiconductor substrate 94 and the insulating layer 95 as shown in FIG. 16C.
As the lateral solid phase epitaxial growth method, for example, an annealing method or a laser method is used.
As an annealing method, for example, M. Miyao, et al., “Low-temperrature SOI (Si-on-insulator) formation by lateral solid-phase epitaxy,” J Appl Phys. 64 (6), 15 sep. 1988, The method described in pp. 3018 (Non-patent Document 1) can be applied. As a laser method, for example, Eiji Fujii, “Dependence of growth length of single silicon crystals on scanning direction of laser beam in lateral seeding process,” J. Appl Phys. 63 (8), 15 Apr. 1988, pp. 2633 (Non-Patent Document 2) can be applied.

In the annealing method, for example, after the semiconductor layer is formed by the CVD method as described above, the amorphous layer on the insulating layer and the single crystal layer on the seed region are annealed at 550 to 600 ° C. for 6 to 30 hours. To process. By this annealing treatment, the amorphous layer formed on the insulating layer becomes a single crystal layer.
In the laser method, for example, after forming the semiconductor layer by the CVD method as described above, the amorphous layer on the insulating layer and the single crystal layer on the seed region are irradiated with cw Ar ⁺ laser. For example, the temperature of the semiconductor layer rises to about 450 ° C. by irradiating the cw Ar ⁺ laser with conditions of a width of 16 μm, an output of 20 W, and a scanning speed of 1 cm / s. By this laser irradiation, the amorphous layer formed on the insulating layer becomes a single crystal layer.

Next, as shown in FIG. 16D, the surface of the single-crystallized semiconductor layer 97 is polished and planarized using a CMP (Chemical Mechanical Polishing) method or the like.
Through the above steps, a laminated structure of an insulating layer and a semiconductor layer, which is composed of the insulating layer 95 and the semiconductor layer 97, is formed on the semiconductor substrate 94.

Further, an operation similar to the step shown in FIG. 16A is performed on the surface of the semiconductor layer 97 shown in FIG. 16D to form an insulating layer by a thermal oxidation method or the like. Then, as shown in FIG. 16B, patterning of the insulating layer and formation of a semiconductor layer including a single crystal layer and an amorphous layer are performed. And as shown to FIG. 16C, an amorphous layer is made into a single-crystal layer by performing a horizontal direction solid phase epitaxial growth by an annealing method or a laser method.
By repeating the above steps, as shown in FIG. 16E, a laminated substrate composed of a semiconductor layer and an insulating layer, which is composed of an insulating layer 95, a semiconductor layer 97, an insulating layer 95A, and a semiconductor layer 97A, is formed on a supporting substrate 94. Can be formed.

  The thickness of each layer is, for example, 60 nm, 30 nm, 40 nm, and 150 nm for the insulating layer 95, the semiconductor layer 97, the insulating layer 95A, and the semiconductor layer 97A. The thickness of each layer of the laminated substrate can be appropriately selected and adjusted according to the height of the semiconductor layer to be laminated in the finFET to be formed and the generation.

  In the laser method described above, in the step shown in FIG. 16B, the formed semiconductor layers 97 and 98 have a lateral solid phase growth distance of 5 μm or more around the seed region 96 of the exposed semiconductor layer. A single crystal semiconductor layer 97 is formed over the insulating layer 95. For this reason, the seed region 96 needs to be arranged on the semiconductor substrate 94 by patterning the insulating layer 95 so as not to increase with respect to the lateral solid phase growth distance.

  In the above-described method for manufacturing a laminated substrate, the case where two semiconductor layers and two insulating layers are formed has been described. However, by repeating each step, three or more semiconductor layers and insulating layers may be formed. it can.

[First Embodiment of Manufacturing Method of Semiconductor Device]
Next, a first embodiment of a method for manufacturing a semiconductor device will be described using the laminated substrate manufactured by the above-described method. The first embodiment of the method for manufacturing a semiconductor device is a method for manufacturing the semiconductor device according to the first and second embodiments described above. The following method for manufacturing a semiconductor device will be described using a plan view and a cross-sectional view taken along a broken line in the plan view.

First, as shown in FIGS. 17A and 17B, a laminated substrate in which the second insulating layer 102, the second semiconductor layer 103, the first insulating layer 104, and the first semiconductor layer 105 are laminated on the semiconductor substrate 101 is prepared. FIG. 17B shows a cross-sectional view taken along line BB shown in FIG. 17A.
As the laminated substrate, a laminated substrate produced using the above-described smart cut method or lateral solid phase growth method can be used, and a laminated substrate produced by other methods can also be used.

Next, as shown in FIG. 17C, a mask 106 that opens the region 107 is formed on the laminated substrate with a hard mask such as a resist or an oxide film to a thickness of, for example, 100 nm. Then, as shown in FIG. 17D, the upper first semiconductor layer 105 and the first insulating layer 104 are etched in the opening region 107. FIG. 17D shows a cross-sectional view taken along the line DD shown in FIG. 17C.
At this time, the opening region 107 is formed on the semiconductor substrate 101 in a region where a finFET in which a semiconductor layer is formed only in the lower layer shown in FIGS. 8A and 8B is formed.
Then, after etching the upper first semiconductor layer 105 and the first insulating layer 104, the mask 106 is removed. Note that in the case where a hard mask made of an oxide film is used as the mask 106, the mask 106 can be removed at the same time in the step of etching the first insulating layer 104.

In the step of etching the upper first semiconductor layer 105 described above, the first insulating layer 104 can be used as an etching stopper. In the step of etching the first insulating layer 104, the second semiconductor layer 103 can be used as an etching stopper.
Thus, when the layers are etched, the lower layer can be used as an etching stopper because the semiconductor layer and the insulating layer are stacked. For this reason, the etching of each layer in the depth direction can be performed in a self-aligned manner in the etching process. Therefore, by using a laminated substrate, it is possible to prevent variations in the height of the semiconductor layer due to etching in manufacturing the finFET, and to form the finFET with high accuracy.

Next, as shown in FIGS. 18E and 18F, an insulating layer 108 made of, eg, SiN having a thickness of 50 nm is formed on the entire surface of the semiconductor substrate 101. FIG. 18F illustrates a cross-sectional view taken along line FF illustrated in FIG. 18E.
The insulating layer 108 is formed so as to fill the opening region 107 as shown in FIG. 18F. Then, the surface of the insulating layer 108 is planarized using a CMP method or the like.
By this step, two regions having different numbers of stacked layers can be formed on the semiconductor substrate 101. That is, a three-layer first stacked region 109 including the second insulating layer 102, the second semiconductor layer 103, and the insulating layer 108 can be formed. Further, a five-layer second stacked region 110 including the second insulating layer 102, the second semiconductor layer 103, the first insulating layer 104, the first semiconductor layer 105, and the insulating layer 108 may be formed on the semiconductor substrate 101. it can.
Further, in the first stacked region 109 and the second stacked region 110, the insulating layer 108 is planarized using a CMP method or the like, so that the upper layer is formed flat regardless of the number of stacked semiconductor layers and insulating layers. Can do.

Next, as shown in FIG. 18G, the first stacked region 109 and the second stacked region 110 are etched to form fins 111 and 112 made of thin semiconductor layers and insulating layers standing on the substrate. As shown in FIG. 18H, the fin 111 is formed by etching the first stacked region 109 including the second semiconductor layer 103 and the insulating layer 108 described above. FIG. 18H shows a cross-sectional view taken along line HH shown in FIG. 18G.
The fin 112 is formed on the semiconductor substrate 101 by etching the second stacked region 110 including the second semiconductor layer 103, the first insulating layer 104, the first semiconductor layer 105, and the insulating layer 108.
Etching is performed on the second semiconductor layer 103, the first insulating layer 104, the first semiconductor layer 105, and the insulating layer 108 after patterning so as to leave a mask only in a portion where a fin is formed. The patterning of the mask can be performed simultaneously in the first stacked region 109 and the second stacked region 110, respectively, or can be performed in separate steps.
In the above-described process, since the upper layers of the first stacked region 109 and the second stacked region 110 are planarized by forming the insulating layer 108, the fins 111 and the fins 112 having different numbers of layers can be formed at the same height. it can.

Next, a gate insulating film (not shown) is formed using a thermal oxide film or a high dielectric constant film (high-k material). Then, as shown in FIG. 19I, the gate electrode 113 is formed.
First, a gate insulating film and a gate electrode material layer made of a mid gap metal such as tungsten (W) alone or a laminate of the mid gap metal and polysilicon are formed on the semiconductor substrate 101. Then, a patterned mask is formed on the gate electrode material layer, and the gate insulating film and the gate electrode material layer are etched into the shape of the gate electrode. By this step, the gate electrode 113 can be formed on the fin 111 and the fin 112 as shown in FIG. 19I. Further, as shown in FIG. 19J, the gate electrode 113 is formed in a U-shape so as to cover the channel region of the fin 111 and the fin 112 from one side surface to the opposite side surface.

  By forming the fin structure 111 and the fin structure 112 and the gate electrode 113 on the semiconductor substrate 101 in the above steps, a finFET including the fin structure 111 and the fin structure 112 can be manufactured.

  In the above-described manufacturing process of the semiconductor device, for example, a first conductivity type, for example, a p-type first semiconductor layer is formed in the first semiconductor layer 105, and a second conductivity type, for example, an n-type first semiconductor layer 103 is formed in the second semiconductor layer 103. Two semiconductor layers are formed. As a result, the fin 112 and the gate electrode 113 can form a finFET in which the pFET and the nFET shown in FIG. 1 are stacked. Further, the fin 111 and the gate electrode 113 can form a finFET having only the lower nFET shown in FIG.

  In addition, a first conductivity type, for example, a p-type first semiconductor layer is formed in the first semiconductor layer 105, and a p-type second semiconductor layer is also formed in the second semiconductor layer 103. Accordingly, a finFET having a configuration in which the pFETs illustrated in FIG. 10 are stacked can be formed by the fin 112 and the gate electrode 113.

In the manufacture of the above-described finFET, the height of the first semiconductor layer and the second semiconductor layer formed in the finFET is determined when the stacked substrate is formed by using the stacked substrate on which the first insulating layer is formed. Is done. Therefore, the height of each semiconductor layer is changed in the step of forming the finFET by using a laminated substrate in which the thickness of the semiconductor layer is formed in advance in accordance with the height of each semiconductor layer of the finFET. Therefore, it is not necessary to use a film forming process or an etching process.
For example, when the finFET is formed using a substrate on which the first insulating layer 104 is not formed, the semiconductor layer needs to be etched to an arbitrary height when the fin 111 is formed. It is difficult to perform this etching accurately, and the height of the semiconductor layer varies. In this case, the gate length of the finFET varies.
However, by using the laminated substrate on which the first insulating layer is formed, the first insulating layer can be used as an etching stopper, and the semiconductor layer can be etched accurately in a self-aligned manner. For this reason, the height of the semiconductor layer can be made uniform, and the gate length of the finFET can be formed uniformly as designed.
Therefore, in the step of forming the finFET, it is not necessary to control the height of the semiconductor layer, and a semiconductor layer having a uniform height can be formed in the plurality of fins. For example, as shown in FIG. 19J, the second semiconductor layer 103 can be formed at the same height in the fin 111 and the fin 112.

[Method of forming via contact]
Next, a method for forming a via contact in the finFET formed in the above process will be described.
First, an interlayer insulating layer 114 made of, for example, USG-SiO ₂ (Un-doped Silicate Glass: undoped silicon oxide film by plasma CVD) is formed on the semiconductor substrate on which the finFET is formed so as to cover the finFET.
Then, as shown in FIG. 20K, a contact hole 115 is formed in the interlayer insulating layer 114. The contact hole 115 is formed up to the surface of the second insulating layer 102 on the semiconductor substrate 101 as shown in FIGS. 20L and 20M. 20L represents a cross-sectional view taken along the line LL illustrated in FIG. 20K, and FIG. 20M represents a cross-sectional view taken along the line MM illustrated in FIG. 20K. Therefore, the insulating layer 108, the first semiconductor layer 105, the first insulating layer 104, and the second semiconductor layer 103 of the fins 111 and 112 are exposed from the portion where the contact hole 115 is formed.
The contact hole 115 is opened to the lower part of the fins 111 and 112 in order to form the via contact so as to connect to both the first semiconductor layer and the second semiconductor as shown in FIG.

Next, as shown in FIG. 21N, contact holes 116 are formed. As shown in FIG. 21O, the contact hole 116 is formed partway through the first insulating layer 104 so as to expose the first semiconductor layer 105 of the fin 112. FIG. 21O shows a cross-sectional view taken along line OO shown in FIG. 21N.
Since the contact hole 116 is formed so that the via contact is connected only to the first semiconductor layer as shown in FIG. 2, the contact hole 116 is opened until the upper semiconductor layer of the fin 112 is exposed.
The contact hole 115 and the contact hole 116 described above are formed, for example, by forming a patterned mask by opening a position where the contact hole is to be formed using known photolithography, and etching the interlayer insulating layer 114.
The contact hole 116 is formed, for example, by changing the conditions for forming the contact hole 115 and stopping the etching at the position where the first semiconductor layer 105 of the fin 112 is exposed when the interlayer insulating layer 114 is etched.

Next, a conductive material made of tungsten (W) or the like is formed on the interlayer insulating layer 114 so as to fill the formed contact holes 115 and 116. Then, excess conductive material on the interlayer insulating layer 114 is removed by using, for example, a CMP method.
Through the above steps, as shown in FIG. 22P, a conductive material can be embedded in the contact holes 115 and 116 to form the via contact 117.
At this time, as shown in FIGS. 22Q and 22R, the via contact 117 is formed in the contact hole 115 so as to be in electrical contact with the first semiconductor layer 105 and the second semiconductor layer 103 of the fin 112. Further, the fin 111 is formed so as to be in electrical contact with the second semiconductor layer 103. Furthermore, the via contact 117 is formed in the contact hole 116 so as to be in electrical contact with only the first semiconductor layer 105 of the fin 112 as shown in FIG. 22Q. 22Q represents the QQ line sectional view shown in FIG. 22P, and FIG. 22R represents the RR line sectional view shown in FIG. 22P.

  Through the above steps, a via contact connected to an arbitrary semiconductor layer can be formed in a finFET in which a semiconductor layer is stacked via an insulating layer. Then, after forming the via contact, a wiring or the like can be formed using a conventional LSI (Large Scale Integration) manufacturing process.

  In the above-described method for manufacturing a semiconductor device, a case is described in which a finFET is formed using a stacked substrate having two semiconductor layers with an insulating layer interposed between a first semiconductor layer and a second semiconductor layer. At this time, the number of stacked semiconductor layers can be arbitrarily changed by increasing the number of semiconductor layers formed on the stacked substrate. For example, a fin having three or more semiconductor layers can be formed by setting three or more semiconductor layers to be stacked with an insulating layer interposed therebetween. Further, by changing the depth of the contact hole for forming the via contact, the via contact can be connected to an arbitrary layer even in a finFET including three or more semiconductor layers.

[Second Embodiment of Manufacturing Method of Semiconductor Device]
Next, a second embodiment of the semiconductor device manufacturing method will be described. The manufacturing method of the second embodiment is a manufacturing method according to the semiconductor device of the third embodiment described above.
In the following description, only the steps different from those of the first embodiment of the semiconductor device manufacturing method described above will be described, and the description of the steps overlapping with the manufacturing method of the first embodiment will be omitted.

First, as in the first embodiment of the semiconductor device manufacturing method described above, the second insulating layer 102, the second semiconductor layer 103, the first insulating layer 104, and the first semiconductor layer 105 are stacked on the semiconductor substrate 101. A laminated substrate is prepared.
Next, as shown in FIG. 23, after a resist layer 118 is formed on the first semiconductor layer 105, the resist layer 118 in a region where impurity ions are implanted is removed, and an opening 119 is formed. Then, for example, impurity ions of the first conductivity type are implanted from the opening 119 to form the semiconductor layer 120 having a threshold voltage (Vth) higher than that of other semiconductor layers. At this time, a sufficient amount of impurity ions is implanted so that the semiconductor layer 120 has a desired threshold voltage or higher.

  After the formation of the semiconductor layer 120 in the above-described steps, the steps up to the steps shown in FIGS. 18G and 18H are performed in the same manner as in the first embodiment, and as shown in FIG. Fins 121 are formed. Through the above-described process, the fin 121 including the first semiconductor layer 120 into which impurities are implanted at a high concentration can be formed. Then, as shown in FIG. 25, the first semiconductor layer 120 having a high impurity concentration and the via contact 117 connected to the second semiconductor layer 103 are formed as in the manufacturing method of the first embodiment.

By forming the fin 121 in a region where impurity ions are implanted into the semiconductor layer at a high concentration, the threshold voltage of the semiconductor layer 120 formed over the fin 121 can be improved. Then, by using this fin 121 to form a finFET, a finFET having the configuration shown in FIG. 13 that can reduce the current driving force of the upper semiconductor layer and can select the semiconductor layer to be driven is manufactured. be able to.
Accordingly, a finFET is manufactured in which the gate length can be indirectly changed by changing the threshold voltage of some semiconductor layers by doping impurities without changing the height at which the semiconductor layer in the fin is formed. be able to.

[Relationship between FinFET Gate Electrode and Channel Impurity]
Next, the relationship between the work function of the gate electrode of finFET and the impurity of the channel in the semiconductor device of the present invention will be described.
A plan view of the finFET is shown in FIG. 26A. FIG. 26B shows a cross-sectional view of the finFET shown in FIG. The finFET shown in FIG. 26 is a plan view and a cross-sectional view of a semiconductor device having the same configuration as that of the semiconductor device shown in FIG. To do.

In the finFET 10 shown in FIGS. 26A and 26B, the fin 11 and the gate electrode 12 are formed on an insulating layer 122 made of SiO ₂ or the like formed on a substrate surface (not shown). The fin 11 includes an insulating layer 13, a first semiconductor layer 14, an insulating layer 15, and a second semiconductor layer 16 in order from the upper layer. Further, the first semiconductor layer 14 forms a pFET 17, and the second semiconductor layer 16 forms an nFET 18.

  FIG. 26B shows the configuration of the gate electrode 12 of the finFET 10 and the fin 11 directly below the gate electrode 12. That is, the first semiconductor layer 14 and the second semiconductor layer 16 shown in FIG. 26B represent channel regions of the pFET 17 and the nFET 18.

The finFET 10 performs, for example, a fully depleted (FD) type operation in which no impurities are present in the NP channel.
By employing a mid-gap metal for the gate den electrode 12, Vth is about 0.5 V, but a single channel impurity (without impurities) is formed of a single gate electrode material.
Table 1 shows combinations of polarities of the gate electrode, the channel, and the source / drain.

The type of transistor formed in the finFET is the polarity of the transistor when the finFET is formed on the substrate, and matches the polarity of the source / drain of the finFET.
By using a mid-gap work function material for the gate electrode, an NP-symmetric threshold voltage (Vth) can be set.
Conventionally, the nFET channel contains p-type impurities, and the gate electrode contains n-type impurities at a high concentration. The pFET channel contains n-type impurities, and the gate electrode contains p-type impurities at a high concentration.
On the other hand, in the finFET of this embodiment, the gate electrode 12 is a work function of a single silicon midgap by performing a full depletion (FD) operation by reducing the impurity concentration of the channel. Even when about 55 eV is used, a practical threshold value can be obtained.

  The present invention is not limited to the configuration described in the above-described embodiment, and various modifications and changes can be made without departing from the configuration of the present invention.

  10, 46, 47, 50, 70, 130, 136, 137 finFET, 11, 51, 52, 53, 71, 72, 73, 111, 112, 121 fin, 12, 35, 48, 49, 54, 74, 113, 133 Gate electrode, 13, 15, 20, 31A, 31B, 55, 57, 59, 61, 63, 75, 77, 79, 81, 83, 85, 91, 95, 95A, 108, 122, 132 Insulation Layer, 14, 105 first semiconductor layer, 16, 103 second semiconductor layer, 17, 40, 41, 134 pFET, 18, 42, 43, 44, 45, 135 nFET, 19,117 via contact, 24 NP connection, 25 Power supply voltage (VDD), 26 Ground (GND), 27, 29, 37 pMOS region, 28, 30, 38, 39 nMOS region, 32 bits Line (BL), 34 semiconductor region, 36 wiring, 56, 58, 60, 62, 64, 76, 78, 80, 82, 84, 86, 97, 97A, 98, 120, 131 semiconductor layer, 90, 90A, 90B, 90C Bond substrate, 92 Support substrate, 93 Hydrogen ion, 94, 101 Semiconductor substrate, 96 Seed region, 102 Second insulating layer, 104 First insulating layer, 106 Mask, 107 Open region, 109 First stacked region, 110 Second laminated region, 114 interlayer insulating layer, 115, 116 contact hole, 118 resist layer, 119 opening

Claims (11)

Fins formed on the substrate;
A plurality of semiconductor layers constituting the fin; and an insulating layer interposed between the plurality of semiconductor layers;
A gate electrode covering the fin,
A semiconductor device, wherein a channel region is formed in a side wall portion of the plurality of semiconductor layers in contact with the gate electrode. The semiconductor layer comprises a first semiconductor layer and a second semiconductor layer;
The semiconductor device according to claim 1, wherein the gate electrode is made of a midgap work function material.   The semiconductor device according to claim 2, wherein the first semiconductor layer and the second semiconductor layer constitute transistors having different channel types.   The said 1st semiconductor layer and the said 2nd semiconductor layer comprise the transistor of the same channel type, The height of the said 1st semiconductor layer and the said 2nd semiconductor layer in the said fin is different. Semiconductor device.   The first semiconductor layer and the second semiconductor layer constitute the same type of transistor, and the first semiconductor layer and the second semiconductor layer have different heights at the fins, and the first semiconductor layer The semiconductor device according to claim 2, wherein an impurity concentration contained in the semiconductor layer is higher than an impurity concentration contained in the second semiconductor layer.   The semiconductor device according to claim 2, wherein a height ratio between the first semiconductor layer and the second semiconductor layer is 2 to 3: 1.   In the plurality of semiconductor layers, a via contact connected to a semiconductor layer formed in an upper layer through the insulating layer, a via contact connected to a lower semiconductor layer through the insulating layer, and the upper semiconductor layer The semiconductor device according to claim 1, further comprising at least one via contact selected from via contacts simultaneously connected to the lower semiconductor layer. Forming a laminated substrate by laminating an insulating layer and a semiconductor layer on the substrate;
Processing the laminated semiconductor layer and the insulating layer into a fin shape;
Forming a gate insulating film that covers the fin-shaped semiconductor layer and the insulating layer;
Forming a gate electrode on the gate insulating film. A method of manufacturing a semiconductor device.   The method for manufacturing a semiconductor device according to claim 8, further comprising a step of removing the semiconductor layer formed in the upper layer of the fin-shaped semiconductor layer by etching.   The method for manufacturing a semiconductor device according to claim 8, further comprising a step of injecting a high-concentration impurity into the semiconductor layer of the multilayer substrate.   The method for manufacturing a semiconductor device according to claim 8, wherein in the step of forming the stacked substrate, the insulating layer and the semiconductor layer are stacked on the substrate using a smart cut method or a horizontal solid phase growth method.

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