JP2011090423A - Computer and power supply - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a computer for reducing standby power. <P>SOLUTION: A #1DC/DC converter 113 which supplies power to a PMC 150 when a computer 10 is put in a power-off state operates, and a #2DC/DC converter 115 which supplies power to an EC101 stops. An MPU 301 monitors the charging state of a battery set 311, and when determining that charging is required, transmits a wake signal through a T terminal to the PMC. The PMC operates the #2DC/DC converter to supply power to the EC. The EC receives the set value of charging from the MPU through an SM bus, and makes a charger 103 start charging. When charging is completed, the EC resets the PMC, and makes the #2DC/DC converter stop. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a technique for reducing standby power of a computer to which an AC adapter is connected.

  A notebook type portable computer (hereinafter referred to as a notebook PC) operates on a battery in a mobile environment, and operates on an office environment while charging the battery with an AC adapter that converts an AC voltage into a DC voltage. When the notebook PC operates in the office environment, it is necessary to always charge the battery for use in the mobile environment. Therefore, even when the notebook PC is in a power-off state, it is necessary to charge it when the charge capacity of the battery is low. At this time, since it is necessary to supply power to the control circuit for detecting the charging state of the battery and starting charging, the power consumption of the notebook PC in the power-off state (hereinafter referred to as standby power) increases. To do.

  Patent Document 1 discloses a technique for reducing power consumption during shutdown in a computer device equipped with a battery. In this document, the M power supply system is turned off when AC power is present at the time of shutdown. And even if the charge control circuit receives power supply from the M power supply system, in order not to impair the charging function during the power-off, (1) during the power-off, until the charging process is completed, A function to maintain and turn off the M power supply system after the end of charging. (2) During power off, when the AC power supply is detected, for example, when the AC adapter is removed and attached, the M power supply system is turned on. Functions that can be performed, (3) A function that can turn on the M power supply system when battery attachment / detachment is detected during power off, and (4) a function that can turn on the M power supply system after a certain period of time during power off. Has been.

JP 2004-192350 A

  The European Commission has approved a compulsory standard (EuP Tier-2) that reduces power consumption in off-mode and standby mode for notebook PCs shipped to EU member states after 2013 to 0.5 W or less. In order to satisfy this standard, it is necessary to reduce standby power from the present level, and further, it is required to further reduce standby power from the viewpoint of the global environment.

  When the system is left in a power-off state for a long time, the remaining capacity of the battery decreases to a level that requires charging due to self-discharge. In the method described in Patent Document 1, in order to start charging at this time, it is necessary to measure the time with a timer provided in the gate array circuit, turn on the M power supply system once, and determine the necessity for charging. In this case, the M power supply system is turned off after charging. In order to maintain the remaining capacity of the battery above the set reference value, it is necessary to set the time interval of the timer to a short time such as about 1 minute. Therefore, it is necessary to frequently turn on / off the M power supply system in order to determine whether or not the battery needs charging. Moreover, since there are many cases where the remaining capacity does not decrease as a result when the M power supply system is turned on, there is a need for a technique that can further reduce standby power compared to the method of Patent Document 1. Yes.

  Accordingly, an object of the present invention is to provide a computer capable of reducing standby power. Furthermore, the objective of this invention is providing the power supply device and battery pack which are used for such a computer. Another object of the present invention is to provide a method for reducing standby power in a computer equipped with a battery pack.

  The computer according to the present invention operates while receiving power from the AC adapter and charging the battery pack. In a computer that is supplied with power from the AC adapter, it is necessary to charge the battery pack even when the computer is in a power-off state, which consumes standby power. The battery pack includes a processor that monitors the state of charge of the battery. The first controller receives information on the state of charge of the battery from the processor via the data bus, and manages the state of charge of the battery based on the information. The regulator supplies power to the first controller. The second controller stops the regulator when the AC adapter is connected to the computer and the computer is powered off. Then, when the wake signal is received from the processor, the regulator is operated. The wake signal is a signal output from the processor when a change occurs in the state of charge of the battery and processing by the first controller is necessary.

  When the computer is in a power-off state, the second controller stops the regulator before receiving the wake signal, so that standby power consisting of power consumption of the first controller and power loss of the regulator can be eliminated. According to the present invention, since the second controller operates the regulator only when the wake signal is received, the first controller can operate only when the battery pack needs to perform management or processing relating to the charging state. . The processor can generate a wake signal when it determines that the battery needs to be charged. Therefore, the battery can be charged even when the remaining capacity decreases due to spontaneous discharge even when the power is off, or when the AC adapter is connected in the power off state after being used in a mobile environment. Can do.

  The first controller can receive a setting value for the charger through the data bus from the processor after receiving power from the regulator. The first controller and regulator can operate and control the charger only when the battery pack actually requires charging. The first controller can reduce standby power by stopping the regulator after charging is completed. The processor can generate the wake signal when it determines that lighting control of the display device that displays the state of charge of the battery is necessary. Therefore, the first controller can display information indicating that the remaining capacity is equal to or less than a predetermined value or is equal to or greater than the predetermined value on the display device. At this time, the first controller can receive data for controlling the display device from the processor through the data bus after receiving power from the regulator.

  When the battery pack includes a detection resistor or a temperature detection element for the first controller to detect attachment of the battery pack, the processor transmits the wake signal through a common signal line connected to the detection resistor or the temperature detection element. Can be sent to a second controller. By using a common signal line, it is not necessary to add pins to the terminals of the battery pack, so that modification of the battery pack and the computer can be minimized. At this time, the common signal line is provided with a switch that is turned off in conjunction with the operation of the regulator, so that the first controller can correctly recognize the mounting state of the battery pack through the common signal line. . The wake signal may be sent to the second controller through a dedicated signal line connected to the processor and the second controller. In this case, it is not necessary to provide a switch on the dedicated line.

  According to the present invention, a computer capable of reducing standby power can be provided. Furthermore, according to the present invention, a power supply device and a battery pack used for such a computer could be provided. Furthermore, the present invention can provide a method for reducing standby power in a computer equipped with a battery pack.

2 is a functional block diagram showing a schematic configuration of a notebook PC. FIG. It is a functional block diagram which shows the structure of a power supply device. It is a figure which shows the operation state of the DC / DC converter according to the power supply state of notebook PC, and the main devices which are supplying electric power. It is a functional block diagram which shows the structure of PMC. It is a flowchart explaining the procedure for reducing the standby power of a notebook PC. It is a functional block diagram which shows the other example of a structure of a power supply device.

  FIG. 1 is a functional block diagram showing a schematic configuration of a notebook PC 10 according to an embodiment of the present invention. Throughout this specification, the same elements described in the drawings are denoted by the same reference numerals, and redundant description will be omitted. The CPU 11 is an arithmetic processing unit having a central function of the notebook PC 10 and is connected to a memory controller hub (MCH) 13. The MCH 13 is a device that processes high-speed data transfer in the notebook PC 10, a memory controller function for controlling an access operation to the main memory 15, and a data transfer speed between the CPU 21 and other devices. Includes a data buffer function to absorb the difference. A main memory 15, a graphic processing unit (GPU) 17, and an I / O controller hub (ICH) 23 are connected to the MCH 13.

  The main memory 15 is a volatile RAM used as an area for reading a program executed by the CPU 11 and a work area for writing processing data. A liquid crystal display (LCD) 19 is connected to the GPU 17. ICH23, ICH31, USB (Universal Serial Bus), Serial ATA (AT Attachment), SPI (Serial Peripheral Interface) bus, PCI (Peripheral Component Interconnect) bus, PCI-Express bus, LPC (Low Pin Count) bus, etc. And control data transfer related to peripheral input / output devices connected to each port.

  FIG. 1 shows a state where only the hard disk drive (HDD) 21 and the USB port 25 are connected to the ICH 23. Further, the power supply device 100 and the flash ROM 29 are connected to the ICH 23 via the LPC bus 27. The flash ROM 29 is a non-volatile memory that can be electrically rewritten. The flash ROM 29 is a device driver for controlling input / output devices, conforms to the ACPI (Advanced Configuration and Power Interface) standard, and has a power supply and a housing. The system BIOS that manages the temperature of the computer, and POST (Power-On Self Test) that performs hardware testing and initialization when the notebook PC 10 is started up are stored.

  FIG. 2 is a functional block diagram showing the configuration of the power supply apparatus 100. The power supply apparatus 100 includes a part of the notebook PC 10, an AC adapter 200 that converts AC voltage into DC voltage and supplies power to the notebook PC 10, and a battery pack 300 that is attached to the casing of the notebook PC 10. ing. The AC adapter 200 is a type that is connected to the notebook PC 10, but may be a type that is incorporated into the notebook PC 10. The battery pack 300 is a battery device that complies with a standard called Smart Battery System (hereinafter referred to as SBS) proposed by Intel Corporation and Duracell Corporation. A battery pack conforming to the standard is also called an intelligent battery.

  The battery pack 300 includes a battery set 311 in which three lithium ion battery cells are connected in series as main components in the housing, a sense resistor 309, a discharge control FET 307, a charge control FET 305, an AFE (analog front). An end 303, an MPU (micro processing unit) 301, and a thermistor 313 are provided. The battery pack 300 and the notebook PC 10 are connected by five terminals: a + terminal, a C terminal, a D terminal, a T terminal, and a − terminal. The discharging current from the battery set 311 and the charging current for the battery set 311 flow between the notebook PC 10 through the charging / discharging circuit via the + terminal and the − terminal. The C terminal and the D terminal are respectively connected to the clock terminal and the data terminal of the MPU 301, and the T terminal is connected to a thermistor 313 that measures the temperature inside the battery pack 300.

  The AFE 303 and the MPU 301 can exchange data with each other. The AFE 303 is a semiconductor integrated circuit that includes an analog input terminal that acquires the cell voltage of each battery cell and an analog input terminal that acquires the voltage across the sense resistor 309. The AFE 303 further includes an analog output terminal that outputs a signal for controlling on / off of the discharge control FET 307 and the charge control FET 305. The AFE 303 measures the cell voltage, converts it into a digital value, and sends it to the MPU 301. The AFE 303 also measures the charging current and discharging current flowing through the battery set 311 from the voltage detected by the sense resistor 309, converts them into digital values, and sends them to the MPU 301.

  The MPU 301 is a semiconductor integrated circuit including a RAM, a ROM, a flash memory, a timer, and the like in a single package in addition to a CPU of about 8 to 16 bits. The MPU 301 monitors the charge amount and the discharge amount based on the voltage and current received from the AFE 303 and calculates the remaining capacity of the battery set 311. The MPU 301 also includes an overcurrent protection function, an overvoltage protection function (also referred to as an overcharge protection function), and a low voltage protection function (also referred to as an overdischarge protection function). When an abnormality is detected in the pack 300, the discharge control FET 307 and / or the charge control FET 305 are turned off and protected through the AFE 303. The overcurrent protection function, the overvoltage protection function, and the low voltage protection function are configured by programs executed by the MPU 301. The MPU 301 sets the charging current and charging voltage suitable for the battery set 311, the remaining capacity value (%) for controlling the lighting of the LEDs 123 and 125, and the remaining capacity value for starting charging of the battery set 311 set by the user ( %) In flash memory.

From the MPU 301, the clock line (CLOCK) and the data line (DATA) are connected to the embedded controller (EC) 101 on the notebook PC 10 side via the C terminal and the D terminal, respectively, and between the MPU 301 and the EC 101, Communication is possible. In the SBS standard, an SM bus (System Management Bus) interface based on the I ² C bus is used for communication between the MPU 301 and the EC 101. When the MPU 301 determines that charging is necessary as a result of monitoring the remaining capacity of the battery set 311, the MPU 301 issues a charging request to the EC 101. Since the life of the lithium ion battery can be extended if the state of low charge is continued, the user can set the ratio of the remaining capacity to the full charge capacity at the start of charging, for example, 90%. Can be set to

  When the MPU 301 determines that the battery set 311 needs to be charged with reference to the data stored in the flash memory, the charging current and charging voltage set values to be set in the charger 103 are set in the register. The EC 101 becomes a master device of the SM bus and reads the contents of the register at a regular frequency such as 2 seconds. When the EC 101 reads the set value, it is set in the charger 103 and causes the charger 103 to start operation. The MPU 301 can stop the operation of the charger 103 by designating the current or voltage set value to be set in the charger to zero. The MPU 301 refers to the data stored in the flash memory, sets a control value indicating the state of the remaining capacity of the battery set 311 in the register, and the EC 101 that has read the control value controls the display of the LEDs 123 and 125.

  For example, the MPU 301 sets a control value in the register to turn on the LED 123 when the remaining capacity is equal to or higher than a predetermined value set for starting charging, and turns on the LED 125 when the remaining capacity is lower than a predetermined value. Set the control value in the register. The MPU 301 outputs a wake signal to the PMC 150 through the T terminal when it is determined that the battery set 111 needs to be charged or when it is determined that either the LED 123 or the LED 125 needs to be lit.

  The common signal line to which the thermistor 313 is connected is pulled up to a predetermined voltage. The thermistor 313 is attached to the circuit board of the battery pack 300, and the resistance changes according to a change in temperature inside the housing. The EC 101 detects that the battery pack 300 is attached to the notebook PC 10 based on the voltage of the signal line to which the thermistor 313 is connected, or stops charging when the temperature inside the housing deviates from a predetermined value. can do. The battery pack 300 may be separately provided with a temperature detection element that directly measures the surface temperature of the battery set 311 in order to ensure safety during charging. In that case, the EC 101 can detect the attachment of the battery pack 300 by providing a detection resistor instead of the thermistor. Note that power is supplied from the battery set 311 to the devices inside the battery pack 300 while the battery pack 300 is not charged.

  Next, elements constituting the power supply device 100 of the notebook PC 10 will be described. The power supply apparatus 100 includes an EC 101, a charger 103, a power management controller (PMC) 150, DC-DC converters 113 to 119, and the like. The EC 101 is a microcomputer composed of an 8- to 16-bit CPU, ROM, RAM, and the like, and further includes a multi-channel A / D input terminal, a D / A output terminal, a timer, and a digital input / output terminal. Yes. The EC 101 can execute a program related to the temperature and power management inside the notebook PC 10 independently of the CPU 11. The EC 101 is connected to the MPU 301 via the C terminal, the D terminal, and the T terminal. The remaining capacity of the battery set 311, the setting value set in the charger 103, the control value for controlling the LED display, and the like are communicated with the MPU 301. Can be acquired.

  The EC 101 becomes a bus master when communicating with the MPU 301 and periodically reads data set in the register of the MPU 301. When the notebook PC 10 operates with the power supplied by the battery pack 300 (power-on state), the EC 101 periodically refers to the register of the MPU 301 to acquire the remaining capacity state and displays it on the LCD 19. When the notebook PC 10 operates with power supplied from the AC adapter 200 (power-on state), the EC 101 periodically refers to the register of the MPU 301 to acquire the remaining capacity state, and operates the charger 103 as necessary. Let Up to now, when the notebook PC 10 is in the power-off state and the AC adapter 200 is connected, the battery set 311 needs to be charged, so the # 2 DC / DC converter 115 and the EC 101 are operated, so the standby power increases. Was. As described below, in this embodiment, the # 2 DC / DC converter 115 and the EC 101 are operated only when the MPU 301 determines that charging is necessary or when it is determined that lighting control of the LEDs 123 and 125 is necessary. Reduce standby power.

  The EC 101 is connected to the LPC bus 27 and can communicate with the CPU 11. When the power state of the notebook PC changes, an operating system (OS) or BIOS executed by the CPU 11 instructs the EC 101 to control the DC / DC converter. The EC 101 is connected to the charger 103 by a setting line (SET) for setting a setting value and an enable line (EN) for controlling start and stop of the operation, and can control the operation of the charger 103. The EC 101 is connected to the PMC 150 through an SPI (System Packet Interface) line and a reset line (RST), and can control the PMC 150. The EC 101 also has a keyboard controller function, and is connected to a keyboard (not shown).

  The PMC 150 is a semiconductor integrated circuit that is connected to the wake switch 109, the voltage detection circuit 105, the LEDs 121 to 125, and the power switch 127, and controls the operation of the DC / DC converters 115, 117, and 119 based on instructions from the EC 101. is there. The PMC 150 is further connected to DC / DC converters 115, 117, and 119 through an enable line (EN). The enable line (EN) for the # 2 DC / DC converter 115 is also connected to the inverter 111. The inverter 111 is a logic element that inverts the logic of the input signal. The configuration of the PMC 150 will be described in detail later with reference to FIG.

  The voltage detection circuit 105 detects the output voltage of the AC adapter 200 connected to the notebook PC 10 and sends a voltage detection signal to the PMC 150. In this specification, when it is described that the AC adapter 200 is connected to the notebook PC 10, it means that the output voltage of the AC adapter 200 is applied to the notebook PC 10. The wake switch 109 is connected between the T terminal of the battery pack 300 and the PMC 150, and is on / off controlled by the output of the inverter 111. The wake switch 109 can send a wake signal to the PMC 150 when the inverter 111 is turned on. When the wake switch 109 is turned off by the output of the inverter 111, the EC 101 is not affected by the PMC 150, and the potential of the shared signal line reflecting the change in the resistance value of the thermistor 313 can be detected. . The LEDs 121, 123, and 125 are attached to the casing of the notebook PC 10. The LED 121 is lit when the AC adapter 100 is connected to the notebook PC 10. The LED 123 is lit when the remaining capacity of the battery set 311 is greater than or equal to a predetermined value, and the LED 125 is lit when the remaining capacity of the battery set 311 is less than or equal to a predetermined value.

  The power switch 127 is attached to the casing of the notebook PC 10 and can be pressed to operate the DC / DC converters 115, 117, and 119 when the notebook PC 10 is in a power-off state, so that the power-on state can be achieved. The charger 103 performs switching control of the output voltage of the AC adapter 200 and outputs it to the + terminal of the battery pack 300, and charges the battery set 311 by a constant current constant voltage method (CC-CV: Constant Current Constant Voltage). The DC / DC converters 113, 115, 117, and 119 are regulators that convert a DC voltage supplied from the AC adapter 200 or the battery pack 300 into a plurality of voltages necessary for operating the notebook PC 10. The power is supplied to each device based on the power supply section defined according to. The # 1 DC / DC converter 113 is a series regulator, and the # 2 DC / DC converter 115, the # 3 DC / DC converter 117, and the # 4 DC / DC converter 119 are switching regulators.

  The notebook PC 10 supports an ACPI (Advanced Configuration and Power Interface) power saving function and a plug-and-play method. ACPI defines five sleeping states S1 to S5. FIG. 3 shows operating states of the DC / DC converters 113, 115, 117, and 119 according to the power supply state of the notebook PC 10, and main devices that supply power. In the notebook PC 10, only the S0 state, the S3 state, and the S4 state are defined. In the S1 state and the S2 state, power is supplied to devices in the same range as the S3 state, and in the S5 state, the same range as the S4 state is supplied. Supply power to the device. The S0 state includes both the case where the AC adapter 200 is connected and the case where it is not connected in the power-on state.

  The S1, S2, and S3 states include both the case where the AC adapter is connected and the case where the AC adapter is not connected in a state in which the time until activation is shortened. In the S1 state, the system context is maintained. The S2 state is the same as the S1 state except that the CPU 11 and system cache contexts are lost. In the S3 state, the contexts of the MCH 13 and the ICH 23 disappear in addition to the S2 state, but the storage of the main memory 15 is retained. The S3 state is called so-called suspend or suspend to RAM, and the notebook PC 10 turns off power to devices other than the main memory 15, ICH23, EC101, MCH13, and PMC150.

  The S4 state is the state that takes the longest time to start among the ACPI supported, and is called so-called suspend to disk or hibernation. When the notebook PC 10 changes from the S0 state to the S4 state, the OS stores the context immediately before the notebook PC 10 in the HDD 21. The S5 state is so-called soft-off, and the power supply range is the same as the S4 state except that the OS does not store the context in the HDD 21. When the notebook PC 10 transitions from the S0 state to the S4 state or the S5 state, power to devices other than the PMC 150 is stopped when the AC adapter is not connected, and power is supplied to the PMC 150 when the AC adapter 200 is connected. At the same time, the power supplied to the EC 101 is controlled based on the wake signal generated by the MPU 301.

  Next, the power supply state will be described from the viewpoint of the operation of the DC / DC converter. The # 1 DC / DC converter 113 supplies power to the PMC 150, and operates in all power states when the notebook PC 10 is supplied with power from the AC adapter 200 or the battery pack 300. The # 2 DC / DC converter 115 supplies power to the EC 101 and operates regardless of whether or not the AC adapter 200 is connected in the S3, S2, S1, and S0 states. The # 2 DC / DC converter 115 operates or stops based on the wake signal when the AC adapter 200 is connected in the S4 or S5 state, and stops when the AC adapter 200 is not connected.

  The # 3 DC / DC converter 117 supplies power to the main memory 15, ICH 23, and MCH 13, operates in the S3, S2, S1, and S0 states, and stops in other power supply states. The # 4 DC / DC converter 119 supplies power to the CPU 11, HDD 21, LCD 19, and GPU 17, etc., operates in the S0 state, and stops in other power supply states. The EC 101 can control the DC / DC converters 115, 117, and 119 via the PMC 150 to supply power to devices defined according to the power state of the notebook PC 10.

  FIG. 4 is a functional block diagram showing the configuration of the PMC 150. The PMC 150 includes a wake signal latch circuit 151, a power-on signal latch circuit 153, an OR circuit 155, a power-on circuit 161, and battery state latch circuits 157 and 159. The wake signal latch circuit 151 is connected to the wake switch 109, the EC 101, and the voltage detection circuit 105. The wake signal latch circuit 151 latches the wake signal sent from the MPU 301 while receiving the voltage detection signal from the voltage detection circuit 105, and outputs it to the OR circuit 155. The power-on signal latch circuit 153 is connected to the power switch 127 and EC101. The power-on signal latch circuit 153 latches the power-on signal sent from the power switch 127 and outputs it to the OR circuit 155.

  The EC 101 monitors the latch state of the wake signal latch circuit 151 and the power-on signal latch circuit 153 through the SPI line. The EC 101 also releases the latch of the wake signal latch circuit 151 and the power-on signal latch circuit 153 through the reset line. When there is an output from the OR circuit 155, the power-on circuit 161 outputs an enable signal to the DC / DC converters 115, 117, and 119 based on the setting from the EC 101 through the SPI line. When the EC 101 monitors the states of the wake signal latch circuit 151 and the power-on signal latch circuit 153 and determines that the wake signal latch circuit 151 is in the latched state, the EC 101 includes only the # 2 DC / DC converter 115 in the power-on circuit 161. Is set to output an enable signal. When the EC 101 determines that the power-on signal latch circuit 153 is in the latched state, the EC 101 sets the power-on circuit 161 to output an enable signal to the DC / DC converters 115, 117, and 119.

  The battery state latch circuit 157 latches a signal received from the EC 101 via the SPI line when the remaining capacity of the battery set 311 is equal to or greater than a predetermined value, and turns on the LED 123. The battery state latch circuit 159 latches a signal received from the EC 101 when the remaining capacity of the battery set 311 is equal to or less than a predetermined value through the SPI line, and lights the LED 125. The LED 121 is turned on by a voltage detection signal from the voltage detection circuit 105.

  1, 2, and 4 simply illustrate the main hardware configuration and connection relationship in order to describe the present embodiment. Many devices are used to configure the battery pack 300 and the notebook PC 10, but these are well known to those skilled in the art and are not necessary for the description of the present embodiment, so the description thereof is omitted. A person skilled in the art can arbitrarily select a plurality of blocks shown in the figure as one integrated circuit, or conversely, a single block can be divided into a plurality of integrated circuits. The range is included in the scope of the present invention.

  Next, the operation of the power supply apparatus 100 will be described. FIG. 5 is a flowchart showing a procedure for reducing the standby power of the notebook PC 10. In block 401, the AC adapter 200 is connected to the notebook PC 10, and the notebook PC 10 is operating in the power-on state (S0 state). The voltage detection circuit 105 outputs a voltage detection signal, and the LED 121 is lit. The PMC 150 outputs an enable signal, and the DC / DC converters 113, 115, 117, and 119 are all operating. In block 403, a transition operation from the S0 state to the S3, S4, or S5 state is performed by the user through the keyboard or the mouse. The OS operates only the DC / DC converter selected through the EC 101 so as to conform to the power status of the migration destination. Here, it is assumed that the state is shifted to the power-off state (S5 state).

  Receiving the instruction of the power supply state of the migration destination from the OS, the EC 101 disables the enable line of the PMC 150 and stops the # 2 DC / DC converter 115, # 3 DC / DC converter 117, and # 4 DC / DC converter 119. Therefore, at this time, only the # 1D / DC converter 113 is operating, and the standby power of the notebook PC 10 is the lowest. Since the enable line (EN) for the # 2 DC / DC converter 115 of the PMC 105 is set to disable, the output of the inverter 111 is turned on and the wake switch 109 is turned on. However, since power is not supplied from the # 2 DC / DC converter 115 to the EC 101, the EC 101 cannot communicate with the MPU 301 to receive the charging set value and operate the charger 103. When the time during which the battery is not charged becomes longer, the remaining capacity of the battery set 311 decreases due to spontaneous discharge and power consumption of the AFE 303 and the MPU 301. Alternatively, immediately after the power is supplied from the battery pack 300, the remaining capacity is reduced.

  In block 405, when the MPU 301 determines that the battery set 311 has a remaining capacity that needs to be charged, the MPU 301 writes a set value for charging to a register that communicates with the EC 101 via the SM bus, and also uses a common signal connected to the T terminal. A pulse-like wake signal is output through the line. Alternatively, when the MPU 301 determines that the remaining amount of the battery set 311 has changed to a state where the lighting control of the LEDs 123 and 125 is necessary, the MPU 301 writes a control value to the register and further outputs a wake signal. When the remaining capacity of the battery set reaches a value that requires some processing by the EC 101, the wake signal operates the # 2 DC / DC converter 115 to communicate with the EC 101 in order to request the EC 101 that is stopped. It is a signal to make it possible.

  The port connected to the T terminal of the MPU 301 has a high impedance when no wake signal is output. The wake signal is sent to the PMC 150 through a signal line shared by the EC 101 for temperature detection. Since the voltage detection circuit 105 outputs a voltage detection signal, the wake signal is latched by the wake signal latch circuit 151 in block 407 and output to the power-on circuit 161 through the OR circuit 155. The EC 101 monitors that the wake signal latch circuit 151 has latched the wake signal through the SPI line, and powers on the block 409 to send an enable signal to the # 2 DC / DC converter 115 to the power on circuit 161. The circuit 161 is set.

  In block 411, the # 2 DC / DC converter 115 starts its operation and the wake switch 109 is turned off, but the output of the wake signal from the OR circuit is continued by the wake signal latch circuit 151. In block 413, the EC 101 supplied with power from the # 2 DC / DC converter 115 starts operation. In block 415, the EC 101 detects a voltage value corresponding to the resistance value of the thermistor 313 through the T terminal, and determines whether or not the battery pack 300 is attached to the notebook PC 10. The output of the wake signal by the MPU 301 in block 405 means that the battery pack 300 is attached to the notebook PC 10, but when it is subsequently disconnected or a predetermined voltage cannot be detected from the shared signal line. Return to block 405.

  In block 417, the EC 101 becomes the bus master and reads the register of the MPU 301 at regular intervals such as 2 seconds. In block 419, when the EC 101 determines that the setting value for charging is written in the register of the MPU 301, the process shifts to block 421 and the EC 101 performs charging processing. When the EC 101 determines that the control values for lighting control of the LEDs 123 and 125 are written in the register of the MPU 301, the process proceeds to block 431, and the EC 101 controls the PMC 150 to turn on or off the LED 123 or LED 125. . The LEDs 125 and 123 continue to be lit until the battery state latch circuits 157 and 159 are reset by the EC 101. The reset is performed when the EC 101 receives a control value indicating reset from the MPU 301.

  In block 421, the setting value received by the EC 101 from the MPU 301 is set in the charger 103, and when the charger 103 is enabled, the charger 103 starts charging the battery set 311. When the MPU 301 determines that the charging of the battery set 311 is completed in block 423, the EC 101 notifies the EC 101, and in block 425, the EC 101 sets the charger 103 to disabled. In block 427, the EC 101 resets the wake signal latch circuit 151, the wake signal output from the OR circuit 155 is stopped, the block # 429 stops the operation of the # 2 EC / DC converter 115, and the wake switch 109 is turned on. And return to block 405.

  According to the above procedure, when the AC adapter 200 is connected to the notebook PC 10, the # 2 DC / DC converter 115 can be stopped except when necessary for charging or LED lighting control. Can be reduced. In block 405, when the power switch 127 is pressed, the EC 101 monitors the latch state of the power-on signal latch circuit 153 and sends an enable signal to the power-on circuit 161 to the DC / DC converters 115, 117, and 119. Set to output. When the voltage detection circuit 105 does not detect the voltage, the wake signal latch circuit 151 does not latch even if it receives the wake signal. Therefore, the wake signal is not output to the OR circuit 155, and the # 2 DC / DC converter 115 operates. do not do.

  FIG. 6 is a functional block diagram showing another example of the power supply device according to the present embodiment. The power supply device 500 differs from the power supply device 100 only in the configuration of a signal line through which a wake signal is sent from the MPU 301 to the PMC 150. In the power supply apparatus 500, a dedicated signal line via the W terminal is provided between the MPU 301 and the PMC 150. Since the dedicated signal line is independent of the signal line to which the thermistor 313 is connected, the wake switch 109 provided in the power supply apparatus 100 is not necessary. The operation of the power supply device 500 is the same as that of the power supply device 100 except that the operation of the wake switch 109 is eliminated.

  Although the present invention has been described with the specific embodiments shown in the drawings, the present invention is not limited to the embodiments shown in the drawings, and is known so far as long as the effects of the present invention are achieved. It goes without saying that any configuration can be adopted.

10 ... Notebook PC
DESCRIPTION OF SYMBOLS 100 ... Power supply device 200 ... AC adapter 300 ... Battery pack

Claims (16)

A computer to which an AC adapter can be connected and a battery pack comprising a battery and a processor for monitoring the state of charge of the battery can be attached,
A charger for charging the battery;
A first controller that receives information about the state of charge of the battery from the processor via a data bus and manages the state of charge of the battery;
A regulator for supplying power to the first controller;
The regulator is stopped when the AC adapter is connected to the computer and the computer is in a power-off state, and the regulator is operated when a wake signal generated by the processor is received based on the state of charge of the battery A computer having a second controller.   The computer of claim 1, wherein the processor generates the wake signal when determining that the battery needs to be charged.   3. The computer according to claim 1, wherein the first controller receives a setting value for the charger through the data bus from the processor after receiving power from the regulator. 4.   The computer according to claim 1, wherein the first controller stops the regulator through the second controller after charging is completed.   The computer according to any one of claims 1 to 4, wherein the processor generates the wake signal when it is determined that lighting control of a display device that displays a state of charge of the battery is necessary.   The computer according to claim 5, wherein the first controller receives data for controlling the display device from the processor through the data bus after receiving power from the regulator.   The battery pack includes a detection resistor or a temperature detection element for the first controller to detect attachment of the battery pack, and the wake signal is transmitted through a common signal line connected to the detection resistor or the temperature detection element. The computer according to claim 1, which is sent to the second controller.   8. The computer according to claim 7, wherein the shared signal line is provided with a switch that is turned off when the regulator operates.   The computer according to any one of claims 1 to 6, wherein the wake signal is sent to the second controller through a dedicated signal line connected to the processor and the second controller. A power supply for a computer to which an AC adapter can be connected,
A battery pack comprising a battery and a processor for monitoring the state of charge of the battery;
A first controller that receives information about the state of charge of the battery from the processor via a data bus and manages the state of charge of the battery;
A regulator for supplying power to the first controller;
A second controller configured to stop the operation of the regulator when the AC / DC adapter is connected to the computer and the computer is in a power-off state and to operate the regulator when receiving a wake signal from the processor; Having a power supply. A charger, a first controller that controls the charger, a regulator that supplies power to the first controller, and a second controller that controls the regulator can be attached to a computer to which an AC adapter is connected. A battery pack,
Battery,
A processor that monitors the state of charge of the battery and sends information about the state of charge of the battery over the data bus to the first controller;
The second controller stops the operation of the regulator when the computer is in a power-off state, and the processor wakes a signal for operating the regulator when sending information about the charging state to the first controller. Is sent to the second controller.   The first controller has a detection resistor or a temperature detection element for detecting attachment of the battery pack, and the processor outputs the wake signal through a common signal line connected to the detection resistor or the temperature detection element. The battery pack according to claim 11 to be sent.   The battery pack according to claim 11, wherein the processor sends the wake signal through a dedicated signal line connected to the second controller. A method for reducing standby power in a computer to which an AC adapter is connected and a battery pack including a battery and a processor that monitors a state of charge of the battery is mounted,
Providing the computer with a controller for managing the state of charge of the battery;
Transitioning the computer to a power-off state and stopping the operation of the controller;
When the processor sends information about the state of charge of the battery to the controller, the processor sends a wake signal to the computer to start operation of the controller;
A method of reducing standby power, comprising: starting the operation, and receiving the information on the state of charge of the battery from the processor.   The reduction method according to claim 14, wherein the processor sends the wake signal when the state of charge of the battery requires a predetermined process by the controller. The reduction method according to claim 14 or 15, wherein the predetermined process is a display process related to charging of the battery or a charged state of the battery.

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