JP2011088277A - Image forming device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To efficiently perform automatic light quantity control at high speed without useless lighting of a surface-emitting type semiconductor laser light source. <P>SOLUTION: A plurality of laser beams output from the light source are separated into first laser beams for measuring light quantity and second laser beams for scanning a photoreceptor. In an APC control unit 402, voltage corresponding to the measured light quantity of the first laser beams is output, and a correction value by laser beam is calculated so that the voltage becomes a control target value with respect to each laser beam. A drive electric current value common in the respective laser beams is calculated, and a threshold value electric current value is calculated so as to achieve α times as large as a target value with respect to each laser beam when driving is performed by a drive electric current which is α times (α is a positive number) as large as the calculated drive electric current value. Based on the respective calculated values, the light quantity of each laser beam is controlled, and during the control, each stabilization is determined. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to an image forming apparatus that forms an image using a multi-beam.

In an image forming apparatus that forms an image using electrophotography, an electrostatic latent image formed on a photosensitive drum is exposed by a semiconductor laser beam (laser beam) to form an electrostatic latent image, and a developer is used. Development is performed to form an image.
In such an image forming apparatus, one to four, and at most about eight laser beams are emitted from one semiconductor element of the semiconductor laser light source.
In recent years, a surface-emitting type semiconductor laser light source (Biccel: VCSEL) has been put into practical use, and an image forming apparatus capable of forming a high-definition and high-speed image using this surface-emitting type semiconductor laser light source has been proposed. ing.

For example, in a general image forming apparatus, a light source unit (semiconductor laser array) in which a plurality of semiconductor laser light sources are arranged in a lattice shape, or a plurality of surface emitting semiconductor laser light sources are arranged in a lattice shape on the same chip. When the light source unit is provided, as shown in FIG. 21, the light source unit 1001 is adjusted so that the arrangement direction of the plurality of light sources has an angle θ with respect to the rotation axis of a deflector such as a polygon mirror. Has been placed.
In (a) of the figure, the light source unit 1001 is arranged such that the light source a 1, b 1, c 1, light source a 2, b 2, c 2, The arrangement directions of a3, b3, and c3 and light sources a4, b4, and c4 are shown tilted so as to have an angle θ with the vertical axis, and the horizontal axis in the figure represents the main scanning direction. Indicates.

Since the light source unit 1001 is arranged at an angle θ with respect to the rotation axis of the deflector, each of the light sources a1 to c4 has different main scanning in the main scanning direction as shown in FIG. The position will be exposed.
Here, of each light source, when one pixel (one pixel) is constituted by two light sources, that is, light sources a1 and a2, light sources a3 and a4, light sources b1 and b2, light sources b3 and b4, light sources c1 and c2, When the light sources c3 and c4 are each realized by one pixel, pixels d1 to d6 constituted by two light sources are formed as shown in FIG.
Then, in the sub-scanning direction which is the vertical direction in the figure, when the distance between the centers of the pixels constituted by the two light sources is equivalent to 600 dpi, the center distance between the two light sources constituting one pixel is equivalent to 1200 dpi, and the pixel density On the other hand, the light source density is doubled.

Therefore, by changing the light quantity ratio of the light source that constitutes one pixel, the center of gravity of the pixel can be shifted in the sub-scanning direction, and high-precision pixel formation can be realized.
A surface-emitting type semiconductor laser light source can emit about 40 laser beams from one chip.
Therefore, high-definition and high-speed image formation is possible by using a surface emitting semiconductor laser light source for forming a latent image of the image forming apparatus.
By the way, when a surface emitting semiconductor laser light source is used for latent image formation, a high-definition latent image cannot be formed at high speed simply by replacing the semiconductor laser light source with a surface emitting semiconductor laser light source.

For example, a laser device that generates a laser beam used for forming a latent image needs to control the amount of emitted laser beam so that it becomes a target amount of light. Therefore, it is necessary to manage the light amount of the laser beam in a light emitting region where a large number of laser beams are generated.
Therefore, when the number of laser beams increases, it is clear that it takes a long time to control the amount of light when performing the same amount of light control as that using a semiconductor laser light source with a small number of laser beams. The advantage of high-speed image formation associated with the application of the light source cannot be fully exhibited.
For this reason, if control such as thinning out the light amount control of the laser beam is added, it becomes difficult to achieve high-definition image formation.

Various techniques have been proposed for the reasons described above.
Conventionally, the light amount of the laser beam is determined based on a current correction value set for each laser beam of a plurality of light sources and a predetermined common drive current for driving the light sources in common. And an automatic light amount control means (auto power control, auto power control: APC) that feeds back and controls the current light amount value, and the current correction value and the common current are calculated by digital calculation, and converted to digital analog There has been an image forming apparatus (see, for example, Patent Document 1) that converts current into an amount of current using a circuit (digital analog converter: Digital Analog Converter: DAC).

  In such an image forming apparatus, the laser beam light amounts of a plurality of light sources are not controlled independently, but the relationship between the light amount of each light source and the drive current has substantially the same characteristics in a one-chip surface-emitting type semiconductor laser light source. Focusing on this point, the amount of light emitted from a current source common to all channels is controlled by the current correction value of each light source, so that automatic light amount control can be performed more efficiently and digital calculation is used. Thus, it is possible to perform automatic light quantity control at a higher speed than the sample hold method (analog method) using a conventional capacitor.

However, in the conventional image forming apparatus described above, the automatic light amount control is performed until the control period ends even if the current correction value and the common current are settled during the period from the start to the middle of the control. In the latter half of the control period, the surface-emitting type semiconductor laser light source was turned on unnecessarily for the light amount value feedback of the automatic light amount control because it was continuously executed.
Further, the automatic light quantity control is necessary when the change in the ambient temperature of the surface emitting semiconductor laser light source is large. The ambient temperature increases from the start of printing of the image forming apparatus to the printing of several sheets. Since the ambient temperature of the surface-emitting type semiconductor laser light source after printing a plurality of sheets is substantially constant, it is not necessary to perform automatic light quantity control in the second half of printing a plurality of sheets. That's enough.

However, in the conventional automatic light amount control of the image forming apparatus, the automatic light amount control is performed from the beginning to the end of the control period regardless of the number of printed sheets, and lighting for that purpose is also performed.
As described above, in the conventional image forming apparatus, the surface emitting semiconductor laser light source is turned on unnecessarily during the automatic light quantity control, so that the deterioration of the surface emitting semiconductor laser light source is accelerated and the service life of the image forming apparatus is increased. There was a problem that it had been shortened.
In particular, the surface-emitting type semiconductor laser light source has a short lifetime compared to the conventional semiconductor laser light source, and thus the above-described useless lighting of the surface-emitting type semiconductor laser light source has been a serious problem.
Further, since an image forming apparatus equipped with a surface emitting semiconductor laser light source is required to print a large number of sheets, it is an urgent problem to prevent the surface emitting semiconductor laser light source from being turned on unnecessarily.

As mentioned above, the conventional devices that control the laser beam light quantity of multiple light sources have focused on speeding up automatic light quantity control, so that it is sufficient to consider the number of times the surface emitting semiconductor laser light source is turned on. I could not say.
In addition, since the life of the surface emitting semiconductor laser light source is shorter than that of the conventional semiconductor laser light source, there is a possibility that the life of the image forming apparatus may be shortened if the automatic light quantity control is repeatedly turned on as in the past. .
Therefore, in an image forming apparatus using a surface emitting semiconductor laser light source, there is a need for a technique for performing automatic light quantity control of each laser beam quantity of a plurality of light sources at high speed and suppressing the automatic light quantity control to the minimum number of times necessary. ing.

  The present invention has been made in view of the above points, and an object of the present invention is to enable automatic light quantity control to be performed at high speed and efficiently without wastefully turning on a surface emitting semiconductor laser light source.

  In order to achieve the above object, the present invention provides a light source that outputs a plurality of laser beams, each of the laser beams output from the light source, a first laser beam for measuring the amount of light, and a photoconductor. Separating means for separating the second laser light for scanning, photoelectric conversion means for outputting a voltage corresponding to the measured light quantity of the first laser light, and each of the lasers output by the photoelectric conversion means First calculation means for calculating a correction value for each laser beam for controlling the amount of light for each laser beam such that the voltage for each laser beam becomes a control target value for each laser beam; Based on the correction value for each laser beam for each laser beam, a second calculation unit that calculates a drive current value common to each laser beam, and the drive current calculated by the first calculation unit and the second calculation unit, respectively. Value α (α is a positive number) times Third driving means for calculating a threshold current value so that a photoelectric conversion output is α times the target value for each laser beam of the first calculating means when driven by a dynamic current; and the first calculating means. And the control means for controlling the light quantity of each laser beam based on the values respectively calculated by the second calculation means and the third calculation means, and when the light quantity of each laser light is controlled by the control means, An image forming apparatus including a settling determination unit that determines the settling of each of the first calculation unit, the second calculation unit, and the third calculation unit is provided.

Further, the settling determination unit determines that the difference between the current calculation value and the previous calculation value of the first calculation unit, the second calculation unit, and the third calculation unit is within a preset range as settling. It is preferable to use a means for determining that the case outside the preset range is not settling.
Further, the settling determination means determines the number of times that the difference between the current calculation value and the previous calculation value of the first calculation means, the second calculation means, and the third calculation means is within a preset range. It is preferable to have a means for counting.
The settling determination means may have means for determining whether or not the counted value has reached a preset value.
Further, the preset range or the preset value may be set from a control unit that controls the entire image forming apparatus.

  The image forming apparatus according to the present invention can perform automatic light quantity control at high speed and efficiently without uselessly turning on the surface emitting semiconductor laser light source.

1 is a block diagram illustrating a functional configuration of an image forming apparatus according to an embodiment of the present invention. It is a figure which shows the structure of the optical apparatus of the image forming apparatus shown in FIG. It is explanatory drawing of paper interval APC. It is a figure which shows the structure of the part which drives VCSEL shown in FIG. FIG. 3 is a graph showing output characteristics of laser light output by the VCSEL shown in FIG. 2.

FIG. 5 is a diagram showing a table structure for storing initial values for controlling the VCSEL in the ROM area of the microcontroller shown in FIG. 4. FIG. 5 is a diagram illustrating an internal configuration of a DEV calculation unit included in the drive current calculation unit illustrated in FIG. 4. It is a figure which shows the internal structure of the TH calculating part with which the drive current calculating part shown in FIG. 4 is provided. It is a figure which shows the internal structure of SW calculating part with which the drive current calculating part shown in FIG. 4 is provided. FIG. 5 is a block diagram showing a detailed internal configuration of the driver shown in FIG. 4.

It is a figure explaining the input-output signal of the APC mode control part shown in FIG. It is a figure which shows the mode transition of the APC mode control part shown in FIG.7 and FIG.11. It is the figure which showed the timing chart of the signal produced | generated when APC_MODE is mode0. It is the figure which showed the timing chart of the signal produced | generated when APC_MODE is mode1 or mode2.

It is a block diagram with which it uses for description with respect to the setting with respect to each enable signal production | generation part of SW, DEV, and TH. It is a block diagram with which it uses for description of the setting with respect to each enable signal production | generation part of SW, DEV, and TH similarly. It is also a block diagram for explaining the setting for each enable signal generation unit of SW, DEV, and TH. It is a block diagram with which it uses for description of the setting with respect to a timing generation part.

It is a block diagram which shows the structure which discriminate | determines settling of control object SW, DEV, and TH, and controls the LDON signal after settling. It is a flowchart figure which shows the setting discrimination | determination process by the settling discrimination | determination part shown in FIG. It is explanatory drawing of the light source unit by which the several surface emitting semiconductor laser light source is arrange | positioned at the grid | lattice form.

Hereinafter, embodiments for carrying out the present invention will be specifically described with reference to the drawings.
In addition, this invention is not limited to the Example mentioned later.
〔Example〕
FIG. 1 is a block diagram showing a functional configuration of an image forming apparatus according to an embodiment of the present invention.
In addition, arrow A in the same figure shows the gaze direction in FIG.
The image forming apparatus 100 is an image processing apparatus including, for example, a copying machine and a multifunction peripheral, and includes an optical apparatus 102 including optical elements such as a semiconductor laser and a polygon mirror, photosensitive drums 104a, 106a, 108a, 110a, charging Image forming unit 112 including charging units 104b, 106b, 108b, and 110b, developing units (developing units) 104c, 106c, 108c, and 110c, and a transfer unit 122 including an intermediate transfer belt 114 and the like. The

The optical device 102 deflects a light beam (laser beam) L emitted from a surface-emitting type semiconductor laser light source (corresponding to a light source) by a polygon mirror 102c and makes it incident on an fθ lens 102b.
The number of light beams L corresponding to each color of cyan (hereinafter referred to as “C”), magenta (hereinafter referred to as “M”), yellow (hereinafter referred to as “Y”), and black (hereinafter referred to as “K”). After being generated and passing through the fθ lens 102b, it is reflected by the reflection mirror 102a.
The WTL lens 102d shapes the light beam L, then deflects the light beam L toward the reflection mirror 102e, reflects the light beam L to the reflection mirror 102f, and forms the light beam L used for exposure as the photosensitive drums 104a and 106a. , 108a, 110a.

The irradiation of the light beam L onto the photosensitive drums 104a, 106a, 108a, and 110a is performed using a plurality of optical elements as described above. Therefore, timing synchronization is performed in the main scanning direction and the sub-scanning direction. Yes.
In the image forming apparatus 100, hereinafter, the main scanning direction is defined as the scanning direction of the light beam L, the sub-scanning direction is a direction orthogonal to the main scanning direction, and the photosensitive drums 104a, 106a, 108a, It is defined as the rotating direction of 110a.
The photosensitive drum 104 includes a photoconductive layer including at least a charge generation layer and a charge transport layer on a conductive drum such as aluminum.
The photoconductive layer is disposed corresponding to each of the photosensitive drums 104a, 106a, 108a, and 110a, and is charged with a surface charge by chargers 104b, 106b, 108b, and 110b including a corotron, a scorotron, or a charging roller. Is granted.

The electrostatic charges imparted on the photosensitive drums 104a, 106a, 108a, 110a by the respective chargers 104b, 106b, 108b, 110b are imagewise exposed by the light beam L to form an electrostatic latent image.
The electrostatic latent images formed on the photosensitive drums 104a, 106a, 108a, and 110a are developed by developing units 104c, 106c, 108c, and 110c including a developing sleeve, a developer supply roller, a regulating blade, and the like. Is formed.
The developer carried on the photosensitive drums 104a, 106a, 108a, and 110a is transferred onto the intermediate transfer belt 114 that moves in the direction of arrow B by the conveying rollers 114a, 114b, and 114c.
The intermediate transfer belt 114 is conveyed to the secondary transfer unit while carrying C, M, Y, and K developers.

The secondary transfer unit includes a secondary transfer belt 118 and conveying rollers 118a and 118b.
The secondary transfer belt 118 is transported in the direction of arrow C in the figure by transport rollers 118a and 118b.
An image receiving material (recording medium) 124 such as high-quality paper (paper) or a plastic sheet is supplied to the secondary transfer portion from an image receiving material accommodating portion 128 such as a paper feeding cassette by a conveying roller 126.
The secondary transfer unit applies a secondary transfer bias to transfer the multicolor developer image carried on the intermediate transfer belt 114 onto the image receiving material 124 held by suction on the secondary transfer belt 118.
The image receiving material 124 is supplied to the fixing device 120 along with the conveyance of the secondary transfer belt 118.

The fixing device 120 includes a fixing member 130 such as a fixing roller including silicone rubber, fluorine rubber, and the like, pressurizes and heats the image receiving material 124 and the multicolor developer image, and forms the printed material 132 as the image forming apparatus 100. To the outside.
The intermediate transfer belt 114 after transferring the multicolor developer image is supplied to the next image forming process after the transfer residual developer is removed by the cleaning unit 116 including a cleaning blade.
A sub-scanning deviation detecting device (not shown because it is well known) is provided near the end point in the main scanning direction of each of the photosensitive drums 104a, 106a, 108a, 110a, and detects a deviation in the sub-scanning direction. ing.

FIG. 2 is a diagram illustrating a planar configuration in which the optical device 102 of the image forming apparatus 100 illustrated in FIG. 1 is referred to from the line-of-sight direction indicated by arrow A in FIG.
In FIG. 2, the photosensitive drum 104a on which an electrostatic latent image is formed, which cannot be referred to from the line of sight indicated by arrow A in FIG.
As shown in FIG. 2, the optical device 102 includes a driver 206, a VCSEL controller (hereinafter referred to as “GAVD”) 200, a drive current calculation unit (drive current control unit) 204, and an A / D conversion unit 202. , A coupling optical element 210, a light separation means 212, a total reflection mirror 214, a second condenser lens 216, and a photoelectric conversion element 218.
The VCSEL controller 200 is an application specific integrated circuit (ASIC), receives a control signal from a CPU (not shown) that controls image formation of the image forming apparatus 100, and performs drive control of the VCSEL 208. Command.

In addition, the GAVD 200 issues a factory adjustment signal, an initialization signal, a line APC (Auto Power Control) signal for the line APC, an inter-paper APC signal for the inter-paper APC, etc. in response to a command from the CPU. To do.
Further, the line APC is a control for correcting the light amount of the laser beam at every timing when the laser beam is scanned in the main scanning direction while the image forming apparatus 100 is operating and printing on the printed matter (recording paper). is there.
Inter-paper APC is a control for correcting the light amount of laser light by a method different from that for line APC between a plurality of printed sheets that are being continuously printed (printed between sheets).

Specifically, the inter-paper APC is, as shown in FIG. 3, for example, when the intermediate transfer belt moves in the transport direction B, the laser light L is exposed to form a toner image for the paper P. When the body drum K is scanned and then irradiated onto the next sheet P ′, the light quantity of the laser beam L is shown at an interval indicated by INT until the light beam L scans the photosensitive drum K. This is a control for performing correction.
Further, the process control APC is a light amount adjustment performed during process control for adjusting the image forming capability of the image forming apparatus 100, and the scanning APC is a temperature above a certain level within the apparatus of the image forming apparatus 100. This is a light amount adjustment that is executed when a change is indicated or after continuous printing of a certain number or more.

The driver 206 supplies a drive current to the VCSEL 208.
Specifically, the driver 206 receives the control signal from the GAVD 200 and supplies the drive current corresponding to the control signal to the VCSEL 208 to drive the VCSEL 208.
Then, the driven VCSEL 208 generates laser light L.
In this embodiment, 40 laser beams L from the VCSEL 208 are emitted corresponding to 40 channels, but the number of emitted laser beams L is not particularly limited.
The laser light L is collimated by the coupling optical element 210 and then enters the half mirror 212.
The half mirror 212 is formed by dielectric multilayer coating or the like.

The half mirror 212 functions as a separating unit. The incident laser light L is converted into monitor light (monitor beam, first laser light) for measuring the light amount and scanning light for scanning the photosensitive member. (Scanning beam, second laser beam).
The scanning beam is deflected by the polygon mirror 102c, passes through the fθ lens 102b, and is irradiated onto the photosensitive drum 104a.
Note that a synchronization detection device 220 including a photodiode (PD) is disposed in the vicinity of the scanning start position of the photosensitive drum 104a.
The synchronization detection device 220 detects the scanning beam and issues a synchronization signal.
The synchronization signal is a signal that gives timing for various controls including the first light quantity correction.
The monitor beam is reflected by the total reflection mirror 214 to the second condenser lens 216, passes through the second condenser lens 216, and is reflected by the photoelectric conversion element 218 such as a photodiode.

The photoelectric conversion element 218 functions as a photoelectric conversion unit and outputs a monitor voltage Vpd corresponding to the light amount of the monitor beam, and the A / D conversion unit 202 converts the monitor signal into a monitor signal corresponding to the monitor voltage Vpd.
Then, the monitor signal is transmitted to the drive current calculation unit 204.
The drive current calculation unit 204 generates, for example, VCSEL control data based on the light amount value of the laser beam indicated by the input monitor signal.
The generated VCSEL control data is used for driving current control by the driver 206.
Therefore, the drive current calculation unit 204 outputs the generated VCSEL control data to the driver 206.

The A / D conversion unit 202 and the drive current calculation unit 204 may be configured as separate modules or may be configured integrally.
In the case of an integrated configuration, for example, a microcontroller including a ROM, a RAM, and the like that store various control values used for processing can be considered.

FIG. 4 is a block diagram showing a configuration for driving the VCSEL 208.
As shown in FIG. 4, in order to drive the VCSEL 208, the image forming apparatus 100 includes a CPU 400, a synchronization detection device 220, a GAVD 200, a driver 206, a VCSEL 208, a microcontroller 401, an APC control unit 402, And a photoelectric conversion element 218.
The GAVD 200 receives a control signal from the CPU 400, and starts factory setting adjustment and initialization setting of the VCSEL 208.
In parallel with this, the synchronization detection device 220 starts detecting the laser beam.
The APC control unit 402 includes an A / D conversion unit 202, a drive current calculation unit 204, and an IF (interface) control unit 403.

The microcontroller 401 includes a calculation unit 411 and a memory 412 including a ROM area and a RAM area.
The memory 412 stores initial values of various control values used by the drive current calculation unit 204.
Further, the ROM area of the memory 412 stores factory setting data and the like, and the RAM area is used as a register memory for storing values necessary for the area.
The microcontroller 401 receives a command from the GAVD 200 via the IF control unit 403 of the APC control unit 402.
Then, the calculation unit 411 calculates the initial value setting using the factory setting data stored in the memory 412 and the light amount of the laser beam in response to the received command.

The microcontroller 401 sets the register memory 421 included in the drive current calculation unit 204 via the IF control unit 403.
The drive current calculation unit 402 includes a register memory 421, a DEV calculation unit 422, a SW calculation unit 423, and a TH calculation unit 424.
The register memory 421 includes a ch1 target value register 701_1 to ch40 target value register 701_40, a ch1DEV register 705_1 to ch40DEV register 705_40, an SW register 805, and a ch1TH register 1100_1 to a ch1TH register 1100_40, which will be described later.
That is, at the time of initial startup, the initial setting by the microcontroller 401 for the ch1 target value register 701_1 to ch40 target value register 701_40, the ch1DEV register 705_1 to ch40DEV register 705_40, the SW register 805, and the ch1TH register 1100_1 to ch1TH register 1100_40. Value is set.

The DEV calculation unit 422 functions as a first calculation unit, and for each laser beam (i), a current correction value DEV for each beam (laser beam) based on the monitor signal output from the A / D conversion unit 202. (I) is calculated.
The beam-specific current correction value DEV (i) indicates a correction value for correcting the current for controlling the amount of light for each laser beam.
The SW calculation unit 423 functions as a second calculation unit, and a common supply current that is a current supplied to all the laser beams based on the beam-specific current correction value DEV (i) for each laser beam. The value (drive current value common to all laser beams) Isw is calculated.
The TH calculation unit 423 functions as a third calculation unit, and is supplied as a threshold current value for each beam for each laser beam (i) based on the monitor signal or the like output from the A / D conversion unit 202. A current value Ith (i) is calculated.

Note that the VCSEL control data includes a beam-specific current correction value DEV (i), a common supply current value SW, a common cooperative current correction value SHD, and a beam-specific threshold current value TH (i).
The calculated beam current correction value DEV (i), common supply current value SW, and beam threshold current value TH (i) are updated and stored in the register memory 421.
The VCSEL control data stored in the register memory 421 is used for light intensity control of the VCSEL 208 by the continuous operation of the VCSEL and the environmental operation of the image forming apparatus 100.
The calculation method and the SHD switching method by the DEV calculation unit 422, the SW calculation unit 423, and the TH calculation unit 424 will be described later.

The VCSEL control data calculated by the APC control unit 402 is sent to the GAVD 200.
As the first VCSEL control data, the initial setting current value set by the microcontroller 401 is input to the driver 206 together with the lighting signal of each channel.
The driver 206 performs PWM conversion on the input initial set current value to set a drive current, and supplies a current at the set drive current level to the channel specified by the channel lighting signal.

The VCSEL 208 driven by the supplied current generates laser light.
The generated laser light of each channel is fed back via the photoelectric conversion element 218 in order to control the light amount of the laser light.
Based on the fed back monitor signal, the drive current calculation unit 204 calculates an appropriate common supply current value Isw, beam-specific current correction value DEV (i), and beam-specific threshold current value Ith (i).

FIG. 5 is a graph showing output characteristics (hereinafter referred to as IL characteristics) of laser light output from the VCSEL 208 in the image forming apparatus 100 of this embodiment.
In this embodiment, the VCSEL 208 is composed of a 40ch semiconductor laser element.
The graph shown in FIG. 5 shows the amount of light output according to the current supplied to each semiconductor laser element.
Each semiconductor laser element has a threshold current Ith (i) at which laser oscillation starts.
The semiconductor laser elements have different levels of output L corresponding to the drive current level I corresponding to the respective element characteristics.

For this reason, the drive current Iη for each semiconductor laser element to output the same laser beam light amount is different by the value ΔI even at the initial setting.
The initial drive current value Isw (i) indicates the probe current value for the channel i registered in the ROM area of the memory 412 based on the factory measurement before shipment.
The initial drive current value Isw (i) is used when initializing the semiconductor laser element.
In this embodiment, i represents each channel (ch) of the laser light of the VCSEL 208, and takes a value of i = 1 to 40 in this embodiment.

FIG. 6 is a diagram showing a table structure for storing initial values for controlling the VCSEL 200 in the ROM area of the microcontroller 401.
In the ROM area, a channel number 502, a monitor voltage (also referred to as “initial monitor voltage”) Vpd 504 at the time of light emission with a prescribed light amount, and an initialization current Isw_A 506 are stored in association with each other.
In addition, initial values of various control values of the VCSEL 200 are registered for each channel 502 assigned to the semiconductor laser element.

The initial monitor voltage Vpdi 504 is a monitor voltage of the photoelectric conversion element 218 set at the time of factory shipment.
The initialization current Isw_A 506 is an average value of the initial drive current values Isw (i) set for the respective semiconductor elements.
The initialization current Isw_A 506 is assumed to be a current for giving a monitor light quantity at the time of light quantity control.
The initial values of various control values stored in these ROM areas are used for calculation by the drive current calculation unit 204 in the APC control unit 402.

FIG. 7 is a diagram showing an internal configuration of the DEV calculation unit 422 included in the drive current calculation unit 204 shown in FIG.
As shown in FIG. 7, the DEV operation unit 422 shown in FIG. 4 includes ch1 target value registers 701_1 to ch40 target value registers 701_40, a selector 702, a subtractor 703, an adder 704, and ch1 DEV registers 705_1 to ch40DEV. A register 705_40, a selector 706, an enable signal generation unit 707, an APC mode control unit 708, a timing generation unit 709, and a multiplier 710 are provided.
The ch1 target value register 701_1 to ch40 target value register 701_40 and the ch1 DEV register 705_1 to ch40DEV register 705_40 are in the register memory unit 421, respectively, but are illustrated in FIG.

The ch1 target value registers 701_1 to ch40 target value registers 701_40 hold predetermined APC target values for each channel.
In the image forming apparatus 100 of this embodiment, a channel is assigned to each semiconductor laser element of the VCSEL 208.
This is because the monitor signal output from the A / D converter 202 when obtaining the same power on the image plane has a value of the monitor signal when the same image plane light quantity is obtained due to the characteristics of the optical system or the like. This is because each channel may be different.
The values set in the ch1 target value registers 701_1 to ch40 target value registers 701_40 are calculated and set by the microcontroller 401 based on the values stored in the ROM 412 in the microcontroller 401.

The APC mode control unit 708 controls the APC control mode.
The APC control mode will be described later.
The timing generation unit 709 generates a channel designation signal (APC_CH) that specifies a VCSEL channel to perform APC, generates a lighting timing (LDON) of the VCSEL 208, generates a sampling timing (AD_SMP) of the A / D conversion unit 202, which will be described later. The ch1DEV register 705_1 to ch40DEV register 705_40, the update timing (CTL_EN) of the SW register and the ch1TH register to the ch40TH register, and the signal APC_TGT indicating whether the control target is DEV and SW or TH are generated.
The selector 702 selects one of the APC target values of each channel held in the ch1 target value register 701_1 to ch40 target value register 701_40 according to the APC_CH generated by the timing generation unit 709, and sends it to the subtractor 703. Output.

The subtracter 703 subtracts the monitor signal corresponding to the light amount of the monitor beam of each channel, which is input from the A / D converter 202, from the APC target value of each channel input from the selector 702. This subtracted value is set as a target difference value.
Multiplier 710 outputs data obtained by multiplying the target difference value, which is the output value of subtractor 703, by a gain, to adder 704.
The adder 704 outputs data obtained by adding the data output from the multiplier 710 and the data output from the selector 706 to the ch1DEV register 705_1 to ch40DEV register 705_40.

The enable signal generation unit 707 includes an APC mode signal (APC_MODE) generated by the APC mode control unit 708, an APC control target (APC_TGT) generated by the timing generation unit 709, an APC channel (APC_CH), and a register update timing (CTL_EN). ), A write enable signal is output to the corresponding ch1DEV register 705_1 to ch40DEV register 705_40.
The ch1DEV registers 705_1 to ch40DEV registers 705_40 hold the output values output from the adder 704 and output them as beam-specific current correction values DEV (1) to DEV (40).
The output value is updated at the timing when the write enable signal is input from the enable signal generation unit 707.

The selector 706 outputs the output value stored in the ch1DEV register 705_1 to ch40DEV register 705_40 to the adder 704 in accordance with APC_CH generated by the timing generation unit 709.
When the DEV calculation unit 422 has the above-described configuration, when the monitor signal (indicating the light amount of the monitor beam) input from the A / D conversion unit 202 of each channel of the VCSEL 208 is larger than the target value of each channel. The feedback control is applied so as to decrease the beam-specific current correction value DEV of the corresponding channel, and when it is small, the feedback control is applied so that the beam-specific current correction value DEV data of the corresponding channel is increased.
For this reason, the light quantity of the laser beam output for each semiconductor laser of the VCSEL 200 is controlled to be a target value.

FIG. 8 is a diagram showing an internal configuration of the TH calculation unit 424 included in the drive current calculation unit 204 shown in FIG.
As shown in FIG. 8, the TH calculation unit 424 shown in FIG. 4 includes a ch1 target value register 701_1 to ch40 target value register 701_40, a selector 1702, a subtracter 1703, an adder 1704, and a ch1TH register 1705_1 to ch40TH register. 1705_40, a selector 1706, an enable signal generator 1707, a multiplier 1710, a multiplier 1711, a shading data switching signal generator 1713, a shading register (SHD register) 1714, a multiplier 1712, and a selector 1715. .
Note that the ch1 target value register 701_1 to ch40 target value register 701_40, the ch1TH register 705_1 to ch40TH register 705_40, and the shading register 1714 are in the register memory unit 421, but are shown in FIG.

The selector 1702 selects one of the APC target values of each channel held in the ch1 target value register 701_1 to ch40 target value register 701_40 according to the APC_CH generated by the timing generation unit 709, and supplies it to the multiplier 1711. Output.
The multiplier 1711 multiplies the input value by the ratio (SHD2 / SHD1) of the correction value (SHD2) when performing TH control for the normal APC operation (SHD1), and outputs the result to the subtracter 1703.
The subtracter 1703 subtracts the monitor signal corresponding to the light amount of the monitor beam of each channel, which is input from the A / D converter 202, from the APC target value of each channel input from the selector 1702. This subtracted value is set as a target difference value.
The multiplier 1710 outputs data obtained by multiplying the target difference value, which is the output value of the subtractor 1703, by a gain to the adder 1704.

The adder 1704 outputs data obtained by adding the output from the multiplier 1710 and the output of the selector 1706 to the ch1TH register 1705_1 to the ch40TH register 1705_40.
The enable signal generation unit 1707 includes an APC mode signal (APC_MODE) generated by the APC mode control unit 708, an APC control target (APC_TGT) generated by the timing generation unit 709, an APC channel (APC_CH), and a register update timing (CTL_EN). ), The write enable signal is output to the corresponding ch1TH register 1705_1 to ch40TH register 1705_40.
The ch1TH registers 1705_1 to ch40TH registers 1705_40 hold the output values output from the adder 1704 and output them as beam-specific current correction values TH (1) to TH (40). The output value is updated at the timing when the write enable signal is input from the enable signal generation unit 1707.

The selector 1706 outputs the output points stored in the ch1TH register 1705_1 to the ch40TH register 1705_40 to the adder 1704 according to APC_CH generated by the timing generation unit 709.
The shading data switching signal generation unit 1713 receives the signal APC_TGT output from the timing generation unit 709 as an input signal, sets SHD_SEL to a high (High) level at a timing when the control target becomes TH, and otherwise outputs a low ( (Low) level.
The SHD register 1714 is a register that is arranged in the register memory 421 and holds correction data for the total supply current when performing normal APC, and is set at the time of initial setting.
The multiplier 1712 multiplies the input data by the ratio (SHD2 / SHD1) of the correction value (SHD2) when performing TH control for the normal APC operation (SHD1), and outputs the result to the selector 1715.

As a result, the SHD data output from the selector 1715 is the data set in the SHD register 1714 when normal APC control (DEV, SW control) is performed, and the SHD register 1714 when TH control is performed. The data set to (SHD2 / SHD1) is output.
When the TH calculation unit 424 has the above-described configuration, the monitor signal (indicating the amount of light of the monitor beam) input from the A / D conversion unit 202 of each channel of the VCSEL 208 is larger than the target value of each channel. The feedback control is applied so as to decrease the beam-specific current correction value DEV of the corresponding channel, and when it is small, the feedback control is applied so that the beam-specific current correction value DEV data of the corresponding channel is increased.
For this reason, the light quantity of the laser beam output for each semiconductor laser of the VCSEL 200 is controlled to be a target value.

FIG. 9 is a diagram illustrating a configuration of the SW calculation unit 423 included in the drive current calculation unit 204.
As shown in FIG. 9, the SW calculation unit 423 shown in FIG. 4 includes an average value calculation unit 801, a target value register 802, a subtracter 803, an adder 804, an SW register 805, and an enable signal generation unit 806. And a multiplier 807.
The SW calculation unit 423 performs a process of correcting the common supply current value Isw in the inter-paper APC mode.
That is, there is a possibility that all the laser beams of the VCSEL 208 cannot be output with a target light amount only by correcting with the beam-specific current correction value DEV (i) data by the DEV calculation unit 422.
Accordingly, the common supply current Isw is corrected so that all the laser beams fall within a range that can be corrected by the beam-specific current correction value DEV (i) data.

The average value calculation unit 801 calculates the average value of DEV1 to DEV40 input from the DEV calculation unit 422. The calculated average value is output to the subtracter 803.
A target value register 802 holds a target value of a predetermined DEV average value.
The SW calculation unit 423 controls the value of the common supply current Isw by outputting data SW so that the DEV average value becomes a value determined by the target value register 802.
The subtracter 803 subtracts the target value held by the target value register 802 from the average value input from the average value calculation unit 801.
A value obtained by subtracting the target value from the input average value is defined as an average difference value.
The multiplier 807 outputs data obtained by multiplying the average difference value output from the subtracter 803 by the gain, and outputs the data to the adder 804.
The adder 804 inputs data obtained by adding the data input from the multiplier 807 and the data output from the SW register 805 to the SW register 805.

The enable signal generation unit 806 includes an update timing (CTL_EN) output from the timing generation unit 709, a control target control signal (APC_TGT), an APC control mode (APC_MODE) output from the APC mode generation unit 708, and an APC channel. It is determined whether to permit writing based on (APC_CH).
When the enable signal generation unit 806 determines to permit writing, the enable signal generation unit 806 outputs a write enable signal to the SW register 805.
The SW register 805 holds the data output from the adder 804 at the timing when the write enable signal output from the enable signal generation unit 806 becomes valid, and outputs it as common supply setting data SW.
With this configuration, the common supply current value Isw is increased when the average value of DEV (i) is larger than the target value, and the common supply current value Isw is decreased when the average value of DEV (i) is smaller than the target value. It will be.

The image forming apparatus 100 of this embodiment is configured to calculate the common supply current value Isw by feeding back the average value of the beam-specific current correction DEV (i).
However, the average value of the maximum and minimum values of the beam-specific current correction values DEV (i) may be used as the calculation of the common supply current value Isw instead of the average value of the beam-specific current correction values DEV (i). Good.
This increases the probability that appropriate control is performed even when only one channel or only a few of the VCSEL channels are abnormal.
The driver 206 shown in FIG. 4 has a current value based on a threshold current Ith (i) that is initially set in the register memory 421 and the like, a common supply current value Isw, and a beam-specific current correction value DEV (i) that is different for each channel. Then, each channel of the VCSEL is driven.

FIG. 10 is a block diagram showing a detailed internal configuration of the driver 206 shown in FIG.
The driver 206 illustrated in FIG. 4 functions as a control unit, and includes a common supply current unit 206d and a common supply current correction unit 206e as illustrated in FIG.
In the example shown in FIG. 10, each code is distinguished from 1ch to 40ch by adding a suffix.
The driver 206 also includes correction value setting units 206a1 to 206a40 and threshold current generation units 206b1 to 206b40 for each channel (LDi, i = 1, 2, 3,..., 40) of the VCSEL 208 that emits laser light. , And current adders 206c1 to 206c40.
The common current supply unit 206d generates a common supply current Isw according to the input common supply current setting data SW.

The common supply current correction unit 206e outputs a current value (SHD * Isw) obtained by correcting the common supply current Isw according to the common supply current Isw and the common supply current correction data SHD.
The correction value setting units 206a1 to 206a40 output a current value (SHD * DEV (i) * Isw) obtained by correcting the supplied common supply correction current (SHD * Isw) with the beam-specific current correction value DEV (i).
The correction value setting units 206a1 to 206a40 can correct the current value within the range of 68% to 132% with respect to the corrected common supply current (SHD * Isw).
That is, by controlling the corrected common supply current (SHD * Isw) so that the average value of the beam-specific current correction values DEVi becomes 100%, the beam-specific current correction value DEV (i) is out of the correction range. Can be deterred.

The threshold current generators 206b1 to 206b40 generate a threshold current Ith (i) according to TH (i) for each channel of the VCSEL 208.
The current adding units 206c1 to 206c40 add the threshold current Ith (i) corresponding to each channel generated by the threshold current generating units 206b1 to 206b40 to the current corrected for each channel, and each of the VCSELs 208 A current for driving the channel is output and supplied to each channel of the VCSEL 208.
In this embodiment, since the driver 206 has the above-described configuration, a drive current of SHD * DEV (i) * Isw + Ith (i) is applied to the semiconductor element LDi (i is an integer of 1 to 40) of each channel. Can supply.

FIG. 11 is a diagram illustrating input / output signals of the APC mode control unit 708 shown in FIG.
The APC mode control unit 708 receives a reset signal (reset_n), an APC enable signal (apc_enable), a write_ready signal, and an apc_fgate signal as input signals, and outputs bd_en and APC_MODE as output signals.
The APC mode control unit 708 controls the APC mode based on the input signal.
The reset signal (reset_n) is a signal input from the CPU 400 as a signal for initializing the APC mode control unit 708.
The APC enable signal (apc_enable) is a signal input from the CPU 400 as a signal indicating whether or not APC can be executed.

The write_ready signal is input from the GAVD 200 as a signal indicating whether writing preparation is completed (main scanning synchronization processing is completed).
The apc_fgate signal is input from the CPU 400 as a signal indicating whether or not it is the sheet interval timing.
The apc_fgate signal is input at a low level in the case of a paper interval timing, and is input as a high level in other cases.

FIG. 12 is a diagram showing a mode transition of the APC mode control unit 708 shown in FIGS. 7 and 11.
In any mode, the APC mode control unit 708 transitions to the init mode when the input reset signal (reset_n) is at a low level.
The APC mode control unit 708 also shifts to the init mode when the apc_enable signal becomes low level.
When the APC mode signal of the APC mode control unit 708 is the init mode and the input APC enable signal (apc_enable) becomes high level, the APC mode shifts to the mode 0 mode.

Next, after the APC mode of the APC mode control unit 708 shifts to the mode 0 mode, the APC mode control unit 708 shifts to the hold mode after the designated number of APC control processes are completed.
The designated number of times of this APC control processing is set in advance in the register memory 421 in the drive current calculation unit 204 by the microcontroller 401.
When the APC mode of the APC mode control unit 708 shifts to the hold mode, the APC mode control unit 708 notifies the GAVD 200 of the output signal (bd_en) as a high level.
After the BD synchronization processing is completed in the GAVD 200, the GAVD 200 inputs the write_ready signal to the APC mode control unit 708 at a high level.
Then, the APC mode control unit 708 is set to a mode for performing APC between sheets.

Thereafter, when the APC mode of the APC mode control unit 708 is the mode1 mode, the mode shifts to the mode2 mode when the apc_fgate signal is input as a high level.
The mode 2 mode is a mode for performing line APC.
When the APC mode is the mode 2 mode and the apc_fgate signal is input as a low level, the mode 1 mode is again entered.
As described above, the APC mode control unit 708 switches between the mode 1 mode and the mode 2 mode in accordance with the switching between the high level and the low level of the apc_fgate signal.
Then, the APC mode control unit 708 outputs the above-described APC mode as an APC_MODE signal to the timing generation unit 709, the SW calculation unit, the TH calculation unit, and the DEV calculation unit, respectively.

FIG. 13 shows the timing of signals generated by the timing generator 709, enable signal generator 707, enable signal generator 1707, enable signal generator 806, and shading data switching signal generator 1713 when the APC_MODE signal is in mode 0 mode. It is the figure which showed the chart.
The APC_CH signal in FIG. 13 is a signal that generates timing for performing processing of each channel of ch1 to ch40.
The hatched rectangular portion in the figure is the timing for performing TH control, and this portion indicates the TH channel.
The timing generation unit 709 generates APC_CH signals for the number of cycles designated by the microcontroller, with ch1 to ch40 as one cycle.

Thereby, APC control of each channel for the designated period is performed.
Then, the timing generation unit 709 generates a lighting timing signal (LDON) for each channel of the VCSEL 200 according to the APC_CH signal to be generated, and outputs it to the GAVD 2100.
At the same time, the timing generation unit 709 generates a sampling timing signal (AD_SMP) according to the generated APC_CH signal and outputs the sampling timing signal (AD_SMP) to the A / D conversion unit 202.
Thereafter, the timing generation unit 709 generates a timing signal (CTL_EN) for the drive current calculation unit 204 to update the register in accordance with the result of the processing performed by the output signal, and the enable signal generation unit 707 and the enable signal 806 are generated. Output to.

  Then, the enable signal generation unit 707 registers the channel specified according to the input APC mode control signal (APC_MODE), register update timing (CTL_EN), channel designation signal (APC_CH), and APC control target signal (APC_TGT). The ch1DEV register 705_1 to the ch40DEV register 705_40 are updated by generating a write enable signal (REG_DEV_ch1_en to REG_DEV_ch40_en) that instructs to update (ch1DEV register to ch40DEV register).

  Similarly, the enable signal generation unit 1707 includes a channel designated according to the input APC mode control signal (APC_MODE), register update timing signal (CTL_EN), channel designation signal (APC_CH), and APC control target signal (APC_TGT). The write enable signals (REG_TH_ch1_en to REG_TH_ch40_en) for instructing the update of the registers (ch1TH register to ch40THV register) are generated to update the ch1TH registers 705_1 to ch40TH register 705_40.

The enable signal generation unit 806 generates a write enable signal (REG_sw_en) that instructs to update the SW register 805 in accordance with the input APC mode (APC_MODE), register update timing (CTL_EN), and channel designation signal (APC_CH).
Specifically, in the case of APC_MODE = mode 0 mode, the write enable signal (REG_sw_en) is generated to be valid when the register update timing signal (CTL_EN) becomes high level during APC_CH = ch40. .
As a result, control is performed to update the common supply current value Isw after the DEV registers of all channels ch1 to ch40 are updated.
The shading data switching signal generation unit 1713 outputs a high level when the APC control target signal (APC_TGT) indicates a period during which TH control is performed by APC control.

FIG. 14 is a diagram illustrating a timing chart of signals generated by the timing generation unit 709, the enable signal generation unit 707, and the enable signal generation unit 806 when the APC_MODE signal is in the mode 1 mode or the mode 2 mode.
In the example shown in FIG. 14, the light quantity correction control is performed by lighting the VCSEL 200 outside the image area immediately before the line clear signal (LCLR) output at the start of the main scanning by the VCSEL 200.
In addition, a timing signal for performing APC control for two channels per scan by main scanning is shown.
That is, signals for two channels are generated with a channel designation signal (APC_CH) per scan.

The procedure from when the channel designation signal (APC_CH) is issued to when the enable signal is generated is the same as the procedure in the mode 0 mode shown in FIG.
When there is a margin in timing, the number of APC channels controlled per scan may be increased.
In addition, the update of the SW register 805 in which the SW is stored affects the amount of laser light of all the channels of the VCSEL.
For this reason, if the SW is changed during image formation, the image density changes abruptly.
Therefore, in the mode 2 mode in which line APC is performed, the enable signal generation unit 806 can be configured not to generate a signal for updating so as not to control Isw.

This setting will be described later.
Similarly, a change in the TH value appears as a disturbance to the DEV control, so that the image density may change abruptly.
Therefore, the enable signal generation unit 1707 may not generate a signal for updating so that TH control is not performed in the mode 2 mode.
This setting will be described later.
In the above setting, the enable signal generation unit 806 receives the register update timing signal (CTL_EN), the APC mode signal (APC_MODE), the APC control target signal (APC_TGT), and the channel designation signal (APC_CH).

When the APC mode signal (APC_MODE) is in mode 1 mode, the APC control target signal (APC_TGT) is at low level, and the channel designation signal (APC_CH) is at ch40, the register update timing signal (CTL_EN) is enabled at high level. Output signal at high level.
If the APC mode signal (APC_MODE) is in the mode 2 mode, the enable signal generation unit 806 always outputs the enable signal as a low level.
Similarly, the enable signal generation unit 1707 receives a register update timing signal (CTL_EN), an APC mode signal (APC_MODE), an APC control target signal (APC_TGT), and a channel designation signal (APC_CH).

If the APC mode signal (APC_MODE) is in the mode 1 mode, the APC control target signal (APC_TGT) is at the high level, and the register update timing signal (CTL_EN) is at the high level, the channel enable signal indicated by the channel designation signal (APC_CH) Is output at a high level.
If the APC mode signal (APC_MODE) is in the mode 2 mode, the enable signal generation unit 1707 always outputs the enable signal as a low level.

FIGS. 15 to 17 show whether SW, DEV, and TH enable signal generators 707, 806, and 1707 generate SW, DEV, and TH enable signals in each mode according to the APC_MODE signal. It is explanatory drawing which sets.
The control target setting unit 1501 has information on whether SW, DEV, and TH are to be controlled in each mode (whether enable signals are generated) or not (whether enable signals are generated). Each of the enable signal generation units 707, 806, and 1707 confirms the current mode with the APC_MODE signal, and then confirms the control target setting unit 1501, and if the current mode is a control target, A signal is generated, and if it is not a control target, no signal is generated.
The control target setting of each mode of the control target setting unit 1501 can be set and changed from the CPU 400.

For example, as in the above setting example, in the mode 2 mode, when SW and TH are not to be controlled, the CPU 400 sets the mode 2 mode column of the controlled object setting unit 1501 as shown in FIG.
The control target setting unit 1501 may change the control target in accordance with the specifications of the image forming apparatus 100.
For example, in the case of an image quality-oriented model that needs to suppress the density unevenness of the printed image to the utmost limit, the control target of the mode 2 mode during image formation is set not to be a control target as shown in FIG. Thus, since APC is not performed at all during image formation, the VCSEL is turned on with a fixed current, the amount of light is constant, and density unevenness of the printed image does not occur.

In addition, since the time between papers is shortened in a model that emphasizes the printing speed, there is a possibility that the amount of light varies due to insufficient APC time if all APCs of SW, DEV, and TH are performed between papers. is there.
Therefore, by setting the control target of the mode 1 mode during the paper interval not to be all the control objects as shown in FIG. 17, only DEV and TH are performed during the paper interval. The amount of light can be sufficiently stabilized even during this time.

FIG. 18 is a block diagram for explaining that the timing generation unit 709 sets whether or not to turn on the LDON signal in each mode in accordance with the APC_MODE signal.
The timing generation unit 709 confirms the current mode with the APC_MODE signal, and then confirms the control target setting unit 1501. If the current mode is a control target, the timing generation unit 709 turns on the LDON signal at each timing and sets the VCSEL. If it is turned on and not controlled, the LDON signal remains OFF and the VCSEL is not turned on.
For example, since the control target in the mode 2 mode of the control target setting unit 1501 shown in FIG. 15 is only DEV, lighting for controlling TH is performed. In the timing chart shown in FIG. 14, gray is the timing for performing TH control. Do not turn on the part.
Also, since there is no control target in the mode 2 mode of the control target setting unit 1501 shown in FIG. 16, the LDON signal remains off at all timings, and the VCSEL for APC control is not turned on. .

FIG. 19 shows a block diagram for determining the settling of each control target SW, DEV, and TH and controlling the LDON signal after settling.
The control target shown in FIG. 19 is DEV, but a block for determining the same settling is provided for SW and TH.
The block settling determination unit 1901 functions as a settling determination unit for determining settling. The settling determination unit 1901 is connected to the output of the multiplier 710 in FIG. 7, and the settling determination unit 1901 is connected to the DEV register. In 705, as the next control value, it can be seen how many are added to the current register value.
In addition, it is connected to the CPU 400, and the number of settling determinations and a settling register range (in bit units) for determining that the CPU 400 has settled are set.

In the example shown in FIG. 19, the settling judgment number is 10 times and the settling register range is ± 3 bits.
The settling judgment method by the settling judgment unit 1901 is performed from the output of the multiplier 710, the number of settling judgments, and the settling register range.
Next, settling determination processing by the settling determination unit 1901 will be described.
FIG. 20 is a flowchart showing settling determination processing by the settling determination unit 1901.
First, the settling judgment unit 1901 resets the number of continuous settling to “0” in step (indicated by “S” in FIG. 1), and in step 2, after APC, the DEV register 705 is set as the next control value. Check the number of additions to the current register value.
In step 3, it is determined whether or not the added value is within the settling register range.

For example, when the settling register range is ± 3 bits and the output of the multiplier 710 is 2 bits, it is determined that the settling register range is within the settling register range, and the output of the multiplier 710 is −4 bits. If it is, it is determined that it is out of the set register range and is not set.
If it is determined in step 3 that the value is within the settling register range, “1” is added to the number of continuous settling times in step 4 and the process proceeds to step 5; Is reset to “0”.
In step 5, it is determined whether or not the number of continuous settling has reached the number of settling determinations set by the CPU 400 (10 in this embodiment).
If the number of continuous settling times has not reached the number of settling judgments in step 5, the process returns to step 2 to continue checking the added value of the DEV register.

On the other hand, if the number of continuous settling times reaches the number of settling determinations in step 5, it is determined that the DEV register has been set, and in step 6, the settling determination unit 1901 informs the timing generation unit 709 that the settling has occurred, and the timing generation unit 709. Turns off the LDON signal so as not to turn on the APC for correcting the DEV.
Further, in step 7, the settling determination unit 1901 sends a signal notifying that the settling is also performed to the enable signal generation unit 707, and the enable signal generation unit 707 stops generating the enable signal, fixes the register value, The process ends.
The DEV register has 40 channels, but the settling determination unit 1901 determines the settling frequency for each channel, and sequentially stops the APC lighting for DEV correction from the channel determined to be established.

Also for SW and TH, a settling determination unit for monitoring each multiplier 807 and 1710 is prepared, and settling determination and APC lighting stop are performed.
However, regarding SW, SW is calculated from the value of DEV of 40 ch. Therefore, when the SW is settled, the SW register value is fixed, and for the ch where the DEV register is not settled, APC lighting for DEV correction is performed. to continue.

  In this embodiment, since the setting of the VCSEL drive current controlled by the APC is determined and the lighting for the unnecessary APC after the setting is not performed, the number of times the VCSEL is turned on can be minimized. This makes it possible to minimize degradation of the VCSEL.

  The image forming apparatus according to the present invention can be applied to a copying machine and a multifunction machine.

DESCRIPTION OF SYMBOLS 100: Image forming apparatus 102: Optical apparatus 102c: Polygon mirror 102b: f (theta) lens 102a: Reflection mirror 102d: WTL lens 102e: Reflection mirror 102f: Reflection mirror 104,104a, 106a, 108a, 110a: Photosensitive drum 104b, 106b, 108b, 110b: Charging device (charging device) 104c, 106c, 108c, 110c: Developing device (developing device) 112: Image forming unit Belt 114: Intermediate transfer 114a, 114b, 114c: Conveying roller 116: Cleaning unit 118: Secondary Transfer belt 118a, 118b: Conveying roller 120: Fixing device 122: Transfer unit 124: Image receiving material (recording medium) 126: Conveying roller 128: Image receiving material accommodating unit 130: Fixing member 132 : Printed product 200: VCSEL controller (GAVD) 202: A / D conversion unit 204: Drive current calculation unit (drive current control unit) 206: Driver 208: VCSEL 210: Coupling optical element 212: Light separation means 214: Total reflection mirror 216: Second condenser lens 218: Photoelectric conversion element 212: Half mirror 220: Synchronization detection device 206a1 to 206a40: Correction value setting unit 206b1 to 206b40: Threshold current generation unit 206c1 to 206c40: Current addition unit 206d: Common current supply unit 206e: Common supply current correction unit 400: CPU 401: Microcontroller 402: APC control unit 403: IF (interface) control unit 411: Calculation unit 412: Memory 421: Register memory 422: DEV calculation unit 423: SW calculation unit 424: TH calculation unit 502: ch number 504: monitor voltage (initial monitor voltage) Vpd 506 at the time of light emission of specified light quantity 506: initialization current Isw_A 701_1: ch1 target value register 701_40: ch40 Target value register 702, 706, 1702, 1706, 1715: Selector 703, 803, 1703: Subtractor 704, 804.1704: Adder 705_1: ch1DEV register 705_40: ch40DEV register 707: Enable signal generation unit 708: APC mode control unit 709: Timing generation unit 710, 807, 1710, 1711, 1712: Multiplier 801: Average value calculation unit 802: Target value register 805: SW register 8 6: Enable signal generation unit 1001: Light source unit 1100_40: ch1TH register 1501: Control target setting unit 1705_1, 1100_1: ch1TH register 1705_40: ch40TH register 1707: Enable signal generation unit 1713: Shading data switching signal generation unit 1714: Shading register (SHD) Registers) a1 to c4: Light source L: Light beam (laser beam)

JP 2009-1006 A

Claims (6)

A light source that outputs a plurality of laser beams;
Separating means for separating each of the laser beams output from the light source into a first laser beam for measuring the amount of light and a second laser beam for scanning the photosensitive member;
Photoelectric conversion means for outputting a voltage corresponding to the measured light quantity of the first laser beam;
A correction value for each laser beam that controls the amount of light for each laser beam so that the voltage for each laser beam output by the photoelectric conversion means becomes a control target value for each laser beam. First calculating means for calculating;
Second calculation means for calculating a drive current value common to each laser beam based on the correction value for each laser beam for each laser beam;
When driven by a drive current that is α (α is a positive number) times the drive current value calculated by the first calculation unit and the second calculation unit, a photoelectric conversion output is generated for each laser beam of the first calculation unit. Third calculation means for calculating a threshold current value so as to be α times the target value of
Control means for controlling the amount of each laser beam based on the values calculated by the first calculation means, the second calculation means, and the third calculation means,
When the light amount of each laser beam is controlled by the control means, a settling judgment means for judging the settling of each of the first calculation means, the second calculation means, and the third calculation means is provided. Image forming apparatus.   The settling determination unit determines that the difference between the current calculation value and the previous calculation value of the first calculation unit, the second calculation unit, and the third calculation unit is within a preset range as settling, The image forming apparatus according to claim 1, wherein the image forming apparatus is a unit that determines that the case outside the set range is not settling.   The settling determination unit counts the number of times that the difference between the current calculation value and the previous calculation value of the first calculation unit, the second calculation unit, and the third calculation unit is within a preset range. 3. The image forming apparatus according to claim 2, further comprising: means.   4. The image forming apparatus according to claim 3, wherein the settling determination means includes means for determining whether or not the counted value has reached a preset value.   The image forming apparatus according to claim 2, wherein the preset range is set from a control unit that controls the entire image forming apparatus.   The image forming apparatus according to claim 4, wherein the preset value is set from a control unit that controls the entire image forming apparatus.

Images