JP2011086103A - Rfid system, and microcomputer - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To improve security in an RFID system for reading and writing data from/to an RFID tag without contacting the RFID tag. <P>SOLUTION: The RFID system includes a reader/writer (5) for reading and writing information from/to an RFID tag and a microcomputer (4) for controlling operations of the reader/writer (5), wherein the reader/writer (5) is built into the microcomputer (4) and connected to a CPU (11) of the microcomputer by bus. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to an RFID system and a microcomputer that read and write information of an RFID tag wirelessly and in a contactless manner.

  An RFID (Radio Frequency IDentification) system is a system that reads and writes data in a memory built in a tag in a non-contact manner using wireless communication.

FIG. 12 is a schematic configuration diagram illustrating an example of a conventional RFID system.
The RFID system 200 in FIG. 12 includes a host computer 201, a control microcomputer 202, an RFID reader / writer unit (hereinafter also referred to as R / W unit) 203, and an RFID tag 204. Such an RFID system 200 is used as, for example, an entrance / exit management system, an automatic ticket gate system, and a system for reading and writing (updating) monetary data in a prepaid card.

  In the RFID system 200, a host computer 201 is communicably connected to a plurality of control microcomputers 202 via a communication line (for example, a communication line such as a LAN: Local Area Network). 202 is communicably connected to a computer (not shown) having 202. The host computer 201 has a function of accumulating data received from the control microcomputer 202. The host computer 201 stores various applications. For example, the host computer 201 executes the application based on a request from the control microcomputer 202 and transmits an execution result to the control microcomputer 202. Alternatively, the host computer 201 executes a predetermined application and transmits a command (command) to the control microcomputer 202 in order to cause the R / W unit 203 and the control microcomputer 202 to rewrite information of the RFID tag 204.

The control microcomputer 202 is configured to control the operation of the R / W unit 203 and is communicably connected to the R / W unit 203 via a communication line.
The R / W unit 203 operates based on a command from the control microcomputer 202. Specifically, a command for instructing reading / writing of data is transmitted to the RFID tag 204 wirelessly. And the response transmitted from the RFID tag 204 according to the command is received. For example, a response indicating that writing has been completed and data read from the memory of the RFID tag 204 are received as a response.

  In the RFID tag 204, a power source for operating itself is generated from the radiated radio wave from the R / W unit 203. The RFID tag 204 operates by its power source and demodulates the signal received from the R / W unit 203. The RFID tag 204 reads or writes data in its own memory in accordance with a command included in the demodulated signal.

FIG. 13 is a schematic configuration diagram showing an example of the configuration of the control microcomputer 202.
The control microcomputer 202 includes a connector 210, a CPU 211, a clock circuit 212, a ROM 213, a real-time clock circuit 214, a RAM 215, an RS232C conversion circuit 216, and an RS232C connector 217.

The ROM 213, real-time clock circuit 214, RAM 215, and RS232C conversion circuit 216 are connected to the CPU 211 via a bus.
The connector 210 is a connector that connects the R / W unit 203 and the control microcomputer 202 so that they can communicate with each other.

The CPU 211 executes various processes by executing programs stored in the ROM 213.
The clock circuit 212 generates a clock signal (CLK) based on data from the CPU 211 and supplies it to the R / W unit 203.

The ROM 213 stores various programs executed by the CPU 211.
The real time clock circuit 214 generates data representing the actual time and supplies it to the CPU 211.

The RAM 215 is a memory that temporarily stores calculation results of the CPU 211 and the like.
The RS232C conversion circuit 216 and the RS232C connector 217 are a type of connection interface that connects the control microcomputer 202 and an external device (not shown). Specifically, the data is converted to serial.

  The control microcomputer 202 and the R / W unit 203 are connected via a connector 210 with five control lines including GND. The control microcomputer 202 is configured to supply the R / W unit 203 with Vcc, a reset signal (RST), a data signal (I / O), a clock signal (CLK), and the like.

FIG. 14 is a schematic configuration diagram showing an example of the configuration of the R / W unit 203.
The R / W unit 203 includes a baseband processing circuit 221, a reception demodulation circuit 222, a reception amplifier 223, and a transmission modulation circuit 224.

The baseband processing circuit 221 converts digital data (transmission data to the RFID tag 204) input from the CPU 211 into a baseband signal.
The transmission modulation circuit 224 modulates a carrier wave based on the baseband signal generated by the baseband processing circuit 221 to generate a radio signal and transmits it. The wireless signal is transmitted to the RFID tag 204 via an antenna (not shown).

The reception amplifier 223 amplifies the reception signal received from the RFID tag 204. The amplified signal is input to the reception demodulation circuit 222.
The reception demodulation circuit 222 demodulates the amplified signal (the reception signal from the RFID tag 204) input from the reception amplifier 223 and inputs the demodulated signal to the baseband processing circuit 221.

The baseband processing circuit 221 extracts data included in the demodulated signal from the demodulated signal input from the reception demodulating circuit 222 and inputs the data to the CPU 211.
Such an RFID system is described in Patent Documents 1 and 2, for example.

JP 2009-10597 A JP-A-9-297825

  Incidentally, the RFID system 200 as described above (as shown in FIGS. 12 to 14) includes a type in which the R / W unit 203 encrypts data and transmits it to the RFID tag 204. This is to prevent data leakage due to eavesdropping and alteration of data in the RFID tag memory. Specifically, the R / W unit 203 sets a secure key (electronic key) based on a command from the control microcomputer 202, and data input from the CPU 211 based on the secure key (transmission data to the RFID tag 204) ) Is encrypted.

  However, conventionally, communication between the control microcomputer 202 and the R / W unit 203 is not encrypted, and there is a possibility that data may be wiretapped between the control microcomputer 202 and the R / W unit 203. On the other hand, an encryption key for decrypting data may be decrypted by reverse engineering of the R / W unit 203. Actually, there is a situation in which the chip of the R / W unit 203 is analyzed using an optical microscope or image recognition software, the circuit arrangement is determined, and the encryption algorithm is inferred from the circuit arrangement.

  The present invention has been made in view of these problems, and an object of the present invention is to further enhance security in an RFID system that reads and writes data without contact with an RFID tag.

The present invention made to achieve the above object is
A reader / writer device that includes an antenna, and performs at least one of reading and writing of information with an RFID tag that stores information readable and writable wirelessly via the antenna;
A memory for storing a control program for controlling the operation of the reader / writer device, and a CPU for controlling the operation of the reader / writer device by reading out and executing the control program stored in the memory; Equipped with a microcomputer;
An RFID system comprising:
In the RFID system, the reader / writer device is built in the microcomputer and connected to the CPU by a bus.

  The gist of the present invention is that the reader / writer device and the microcomputer are configured as one chip. Specifically, it is assumed that the reader / writer device is built in a microcomputer. In other words, the microcomputer itself has a reader / writer function.

  In the RFID system of this aspect, analysis of communication data between the reader / writer device and the CPU is performed when the reader / writer device and the CPU (microcomputer) are connected via a communication line or a connector. It becomes much more difficult than For example, assuming a configuration in which the reader / writer device is configured as an LSI and connected to a CPU, in this case, signals are exchanged via a signal line having a width of μm. In order to analyze the signal between the reader / writer device and the CPU, it is necessary to monitor the voltage on the signal line. However, it is not practical to manufacture or obtain a probe or the like for detecting such a voltage on the signal line, and in the configuration of the present invention, signal analysis is practically impossible.

For these reasons, according to the present invention, the possibility of wiretapping of data can be remarkably suppressed, and security can be improved.
In the present invention,
The reader / writer device includes a receiving circuit that receives a radio signal from the RFID tag via the antenna,
The memory stores a demodulation program that is executed by the CPU and that causes the CPU to execute demodulation processing for demodulating a radio signal received by the receiving circuit.
The CPU is configured to execute the demodulation process based on the demodulation program.

In other words, the demodulation processing of the received signal received from the RFID tag is configured to be realized by the CPU processing (on software).
In particular, a demodulation program for causing the CPU to perform demodulation processing is preferably stored in a flash memory.

  The flash memory is configured to store binary data of 1 or 0 by electric charge. In view of this point, the data (program) stored in the flash memory is analyzed by analysis of the flash memory (for example, a method of specifying and analyzing the circuit arrangement by an action such as cutting a chip). It is impossible to do.

According to the present invention as described above, the contents (logic) of the demodulation process are not easily deciphered, and the security can be further improved.
In the present invention,
The memory is a program executed by the CPU, and stores a baseband processing program for causing the CPU to execute baseband processing for generating a baseband signal from data to be transmitted to the RFID tag. ,
The CPU is configured to execute the baseband processing based on the baseband processing program,
The reader / writer device includes a modulation circuit that modulates a carrier wave based on a baseband signal generated by baseband processing executed by the CPU and sends the modulated signal to the antenna.

  As described above, the memory in which the baseband processing program is stored is preferably a flash memory. According to this, similarly, the content (logic) of the baseband process becomes difficult to be decoded, and the security can be further improved.

The present invention also provides:
A host computer communicably connected to the microcomputer via a communication line and configured to send a command to the microcomputer;
The RFID tag stores identification information unique to the RFID tag,
The control microcomputer transmits the identification information read from the RFID tag to the host computer,
The host computer includes a host-side memory that stores an encryption key for encrypting the command,
The command is encrypted using both the encryption key read from the host-side memory and the identification information received from the control microcomputer, and is transmitted to the control microcomputer.
Further, the control microcomputer stores the same information as the encryption key stored in the host-side memory, and receives a command received from the host computer from the information and the identification information read from the RFID tag. It is configured to decrypt.

  The present invention can be utilized as, for example, an entrance / exit management system, an automatic ticket gate system, a system for reading / writing (updating) monetary data in a prepaid card, and the like.

For example, in the case of an automatic ticket gate system, it can be assumed that a microcomputer is built in a ticket gate and a host computer is installed at a predetermined center.
The microcomputer reads the information of the user registered in the tag, the information of the charged amount, the information of the boarding / exiting station, etc. from the tag held over the ticket gate, and hosts the read information. Send to computer. The host computer determines from the information whether or not to allow the ticket gate to pass. For example, the fare is calculated from the information of the boarding / exiting station, and it is determined whether or not an amount equal to or more than the fare is charged. In addition, a command is sent to the microcomputer to the effect that the fare amount should be deducted (reduced) from the amount charged in the tag. Based on the command, the microcomputer rewrites the amount information (charged amount information) in the tag to information after the fare is reduced.

In such an RFID system, since personal information and money information are handled, higher security is required.
In this regard, in the present invention, a command from the host computer to the microcomputer is encrypted twice based on both the identification information unique to the RFID tag stored in the RFID tag and the encryption key stored in the host computer. Therefore, information leakage can be suppressed at a higher level. Note that transmission data from the microcomputer to the host computer may be double-encrypted by the same method.

Next, in another aspect of the present invention, the microcomputer includes:
A reader / writer device that includes an antenna, and performs at least one of reading and writing of information with an RFID tag that stores information readable and writable wirelessly via the antenna;
A memory for storing a control program for controlling the operation of the reader / writer device;
A CPU configured to be connected to at least the reader / writer device via a bus, and to control the operation of the reader / writer device by reading out and executing a control program stored in the memory;
It has.

Moreover, such a microcomputer of the present invention includes:
A receiving circuit for receiving a radio signal from the RFID tag via the antenna;
The memory stores a demodulation program that is executed by the CPU and that causes the CPU to execute demodulation processing for demodulating a radio signal received by the receiving circuit.
The CPU may be configured to execute the demodulation process based on the demodulation program.

In the microcomputer of the present invention,
The memory is a program executed by the CPU, and stores a baseband processing program for causing the CPU to execute baseband processing for generating a baseband signal from data to be transmitted to the RFID tag. ,
The CPU is configured to execute the baseband processing based on the baseband processing program,
The reader / writer device may include a modulation circuit that modulates a carrier wave based on a baseband signal generated by baseband processing executed by the CPU and sends the modulated signal to the antenna.

In the microcomputer of the present invention, the memory may be a flash memory.
According to such a microcomputer of the present invention, the RFID system as described above can be realized, and the same effect as the RFID system can be obtained.

1 is a schematic configuration diagram of an RFID system 1 to which the present invention is applied. 2 is a schematic configuration diagram of a control microcomputer 4. FIG. It is the schematic which shows the structure of R / W5, and the function of CPU11. 2 is a schematic configuration diagram of a one-chip microcomputer 7. FIG. 2 is a schematic diagram of a circuit configuration of a one-chip microcomputer 7. FIG. FIG. 6 is a diagram illustrating a demodulation process using a timer circuit 32. It is a figure explaining the effect | action of the demodulation process using the timer circuit. It is a figure which shows the aspect of the exchange of data between the one-chip microcomputer 7 and the host computer 2, and the encryption of data. It is a figure which shows the aspect of the exchange of data between the one-chip microcomputer 7 and the RFID tag 6, and the encryption of data. It is a conceptual diagram of the encryption communication in this embodiment. It is a conceptual diagram of the communication aspect in 2nd Embodiment. It is a figure which shows an example of a structure of the conventional RFID system. It is a figure which shows the structure of the microcomputer in the conventional RFID system. It is a figure showing an example of composition of conventional R / W unit 203.

Embodiments of the present invention will be described below with reference to the drawings.
[First Embodiment]
FIG. 1 is a schematic configuration diagram of an RFID system to which the present invention is applied.

The RFID system 1 shown in FIG. 1 is mainly composed of a host computer 2, a control microcomputer 4 (one-chip microcomputer 7), and an RFID tag 6.
The one-chip microcomputer 7 includes a control microcomputer 4, an application 3 executed in the control microcomputer 4, and an RFID reader / writer (hereinafter also referred to as R / W) 5 in a single chip.

The application 3 is specifically a secure-related application (for example, an application for encryption).
In the RFID system 1, the host computer 2 is communicably connected to a plurality of one-chip microcomputers 7 via a communication line (for example, a communication line such as a LAN: Local Area Network). It is communicably connected to a computer (not shown) having the chip microcomputer 7). The host computer 2 has a function of accumulating data received from the one-chip microcomputer 7. Various applications are stored. For example, the application is executed based on a request from the one-chip microcomputer 7, and the execution result is transmitted to the one-chip microcomputer 7.

The communication principle of the RFID system 1 is as follows.
First, the R / W 5 includes an antenna (described later), and transmits a radio signal including a command to the RFID tag 6 from the antenna.

The RFID tag 6 receives a radio signal from the R / W 5 via an antenna (not shown) provided in the RFID tag 6.
In the RFID tag 6, an electromagnetically induced electromotive force is generated by the resonance action of the antenna. Then, the circuit is activated by the electromotive force, and processing according to the command from the R / W 5 is executed. Data representing the processing result is transmitted to the R / W 5 via the antenna of the RFID tag 6 by load modulation.

When a signal from the RFID tag 6 is received via the antenna at the R / W 5, the received signal is demodulated. Then, data included in the demodulated signal is extracted.
The extracted data is transmitted to the control microcomputer 4.

FIG. 2 is a schematic configuration diagram of the control microcomputer 4.
The control microcomputer 4 includes a CPU 11, a clock circuit 12, a flash memory 13, a real-time clock circuit 14, a RAM 15, an RS232C conversion circuit 16, and an RS232C connector 17. The flash memory 13 and the RAM 15 are nonvolatile semiconductor memories.

The flash memory 13, the real time clock circuit 14, the RAM 15, and the RS232C conversion circuit 16 are connected to the CPU 11 by a bus.
The CPU 11 operates according to various programs stored in the flash memory 13 and executes various processes.

The clock circuit 12 generates a clock signal (CLK) based on data from the CPU 11 and supplies it to the R / W 5.
The flash memory 13 stores various programs executed by the CPU 11.

The real time clock circuit 14 generates data representing the actual time and supplies it to the CPU 11.
The RAM 15 is a memory that temporarily stores calculation results of the CPU 11 and the like.

  The RS232C conversion circuit 16 and the RS232C connector 17 are a kind of connection interface that connects the control microcomputer 4 and an external device (not shown). Specifically, the data is converted to serial.

  Here, the R / W 5 is configured to be supplied with Vcc as an operation power supply, a reset signal (RST), a data signal (I / O), and a clock signal (CLK) from the control microcomputer 4.

FIG. 3 is a schematic diagram showing the configuration of the R / W 5 and the function of the CPU 11.
The R / W 5 includes a transmission modulation circuit 23 and a reception amplifier 24.
The CPU 11 is configured to execute a reception demodulation process 21, a baseband process 22, and the like based on a program stored in the flash memory 13 (see FIG. 2). The flash memory 13 stores a demodulation program for causing the CPU 11 to execute the reception demodulation processing 21, a baseband processing program for causing the CPU 11 to execute the baseband processing 22, and the like.

In the baseband processing, transmission data (digital data) to the RFID tag 6 is converted into a baseband signal. The baseband signal is transmitted to R / W5.
In R / W5, the transmission modulation circuit 23 modulates the carrier wave based on the baseband signal to generate a radio signal, and the radio signal is transmitted to the RFID tag 6 via the antenna. That is, a radio signal on which transmission data to the RFID tag 6 is superimposed is transmitted.

The reception amplifier 24 amplifies the reception signal received from the RFID tag 6 and outputs the amplified signal to the CPU 11.
The CPU 11 executes reception demodulation processing, and demodulates the amplified signal (received signal from the RFID tag 6) input from the reception amplifier 24 of the R / W 5. Further, the baseband processing 22 extracts data contained in the demodulated signal from the demodulated signal after demodulation.

FIG. 4 is a schematic configuration diagram of the one-chip microcomputer 7.
The one-chip microcomputer 7 has the control microcomputer 4 described above. Further, it includes an oscillation circuit 33, a transmission amplifier circuit 34, an amplifier circuit 35, an envelope detection circuit 36, an antenna 37, and a switch 38.

  The oscillation circuit 33 generates a clock signal for the control microcomputer 4 to operate. Specifically, the clock signal generated by the oscillation circuit 33 is input to the control microcomputer 4. The control microcomputer 4 operates based on the clock signal input from the oscillation circuit 33.

  The clock signal generated by the oscillation circuit 33 is also input to the transmission amplifier circuit 34 and used for the operation of the transmission amplifier circuit 34. Note that, by configuring so that the clock signal generated by the oscillation circuit 33 is also used for the operation of the transmission amplifier circuit 34, it is possible to reduce the processing load and to reduce the overall software cost. Specifically, the operation clock of the control microcomputer 4 and the operation clock of the transmission amplifier circuit 34 coincide with each other, and it becomes easy to synchronize. For example, it is not necessary to execute special processing (special processing for synchronization) due to different operation clocks, and the software configuration and processing content can be simplified.

  The transmission amplifier circuit 34 modulates the carrier wave (superimposes the transmission data on the carrier wave) based on the transmission data input from the control microcomputer 4, amplifies the signal, and sends the modulated and amplified signal to the antenna 37. Specifically, the transmission amplifier circuit 34 performs amplitude modulation of a carrier wave in accordance with a bit string of transmission data. Here, the transmission data encoding method when transmitting the transmission data from the control microcomputer 4 to the transmission amplifier circuit 34 may be any method such as Manchester or NRZ. Manchester changes the signal from “high level → low level” when “0”, and changes the signal from “low level → high level” when “1” to distinguish between “0” and “1”. It is a method. NRZ is a method for distinguishing between “0” and “1” by outputting a “low level” signal when “0” and outputting a “high level” signal when “1”.

  The antenna 37 transmits a radio signal including transmission data input from the transmission amplifier circuit 34 to the RFID tag 6. The antenna 37 receives a radio signal transmitted from the RFID tag 6. The radio signal transmitted from the RFID tag 6 is a signal that has been amplitude-modulated in accordance with transmission data from the RFID tag 6 to the one-chip microcomputer 7. More specifically, in the RFID tag 6, amplitude modulation is realized using load modulation. Although not shown, the RFID tag 6 includes a circuit composed of a resistor and a switching element (transistor), and amplitude-modulates the carrier wave by turning on / off the switching element. When the switching element is turned on, a current flows through the resistor, the load increases, and the amplitude of the output signal decreases. That is, the magnitude of the output signal changes depending on the on / off of the switching element.

A received signal (received signal from the RFID tag 6) received by the antenna 37 is input to the envelope detection circuit 36.
The envelope detection circuit 36 is a circuit that demodulates the received signal by detecting the envelope of the received signal from the RFID tag 6. Since the signal transmitted from the RFID tag 6 is amplitude-modulated as described above, the signal transmitted from the RFID tag can be demodulated by envelope detection. That is, it can be demodulated into data representing “0” and “1” based on the magnitude of the amplitude.

The signal detected by the envelope detection circuit 36 is input to the amplification circuit 35.
The amplification circuit 35 amplifies the signal input from the envelope detection circuit 36 and outputs the amplified signal to the control microcomputer 4 side.

  The amplified signal output from the amplifier circuit 35 is directly input to the serial communication circuit 31 of the control microcomputer 4 by switching the switch 38 (for example, a transistor) or input to the serial communication circuit 31 via the timer circuit 32. The

  Here, the switch 38 is switched in accordance with the communication standard. In the case of a communication standard that allows the demodulated signal from the envelope detection circuit 36 to be used as data, the switch 38 is connected to the terminal 39 side. In this case, the signal from the amplifier circuit 35 is directly input to the serial communication circuit 31. This method can be used when data of “0” and “1” is demodulated by envelope detection by the envelope detection circuit 36 as described above.

  When the communication standard is a standard including a subcarrier (in other words, when the signal detected by the envelope detection circuit 36 is a signal modulated according to data), the switch 38 is connected to the terminal 40 side. In this case, the signal from the amplifier circuit 35 is demodulated using the timer circuit 32 and then input to the serial communication circuit 31. Demodulation by the timer circuit 32 will be described later with reference to FIGS.

  FIG. 5 is a schematic diagram of a circuit configuration of the one-chip microcomputer 7. In FIG. 5, the control microcomputer 4 and the specific circuit configuration of the oscillation circuit 33 are not shown. In the present embodiment, it is assumed that the circuit shown in FIG. 5 includes a discrete semiconductor (individual component).

The transmission amplifier circuit 34 includes a resistor 42, a capacitor 62, coils 81 and 82, and a transistor 83.
A signal from the oscillation circuit 33 is input to the transmission amplifier circuit 34 via the capacitor 61. The capacitor 61 is connected to the base terminal of the transistor 83. A resistor 43 is connected between the base terminal of the transistor 83 and GND.

  The emitter terminal of the transistor 83 is connected to GND, and the collector terminal is connected to one end side of each of the coil 81, the coil 82, and the capacitor 62. The other end sides of the coil 81 and the capacitor 62 are connected to each other.

The transmission data is input to the transmission amplifier circuit 34 via the resistor 41.
The antenna 37 is formed integrally with resonance capacitors 65 and 66. Then, it is connected to the transmission amplifier circuit 34 via the capacitor 64. Further, in addition to the capacitor 64, the envelope detection circuit 36 is connected via the capacitor 63.

The envelope detection circuit 36 includes a diode 86, resistors 44, 45 and 46, and a capacitor 69.
The anode of the diode 86 is connected to the antenna 37 side, and the cathode is connected to one end side of the resistors 45 and 46. The other end side of the resistor 46 is connected to GND. The other end of the resistor 45 is connected to one end of the capacitor 69, and the other end of the capacitor 69 is connected to GND.

  That is, in the envelope detection circuit 36, the input signal is passed through the diode 86, and the output from the diode 86 is input to the series circuit of the resistor 45 and the capacitor 69. By appropriately setting the time constants of the resistor 45 and the capacitor 69, a signal having a waveform close to the envelope of the input signal can be obtained as an output signal.

  The amplifier circuit 35 includes resistors 47, 48, 49, and 50, a capacitor 71, and a transistor 84. The output side of the envelope detection circuit 36 and the amplifier circuit 35 are connected via a capacitor 68. A capacitor 67 is connected to a path (power supply line) between the envelope detection circuit 36 and the amplifier circuit 35. The capacitor 67 is a decoupling capacitor and has functions such as supplying an instantaneous current, lowering the impedance of the power supply line, and preventing external noise.

  In the present embodiment, the amplifier circuit 35 is provided in multiple stages. Specifically, an amplifier circuit 35 a including resistors 51, 52, 53, 54, a capacitor 72, and a transistor 85 is provided as an amplifier circuit having a configuration similar to that of the amplifier circuit 35. The output side of the amplifier circuit 35 and the input side of the amplifier circuit 35 a are connected via a capacitor 70.

The signals amplified by the amplifier circuits 35 and 35a are input to the control microcomputer 4 (see FIG. 4).
6 and 7 are diagrams illustrating demodulation processing using the timer circuit 32 of the control microcomputer 4.

  As shown in FIG. 6, it is assumed that the control microcomputer 4 includes a preset timer circuit 91 and a one-shot timer circuit 92 as the timer circuit 32. The preset timer circuit 91 has a built-in timer circuit 90 that counts up or down according to an input pulse (period measurement pulse). In the present embodiment, the timer circuit 90 is configured to count down from an initial value as will be described later with reference to FIG. The preset timer circuit 91 is configured to output a pulse when the count value of the timer circuit 90 reaches zero.

The output of the preset timer circuit 91 is input to the preset timer circuit 91 itself and to the one-shot timer circuit 92.
The preset timer circuit 91 outputs a pulse when the count value of the built-in timer circuit 90 becomes zero.

  The one-shot timer circuit 92 includes a relay, and is configured such that when a trigger is input, the relay is turned on for a certain time, and when the certain time has elapsed, the relay is turned off. In the present embodiment, the one-shot timer circuit 92 is configured such that when a pulse from the preset timer circuit 91 is input, the relay is turned on for a predetermined time (a high level signal is output).

  The preset timer circuit 91 includes a period measurement pulse for measuring the period of the input signal (see the second stage in FIG. 6), a reception signal from the RFID tag 6 (the second stage input signal in FIG. 6), and Is entered. The received signal is a signal composed of a pulse having a period A and a pulse having a period B as shown in the second stage of FIG. It is assumed that the period A represents “1” and the period B represents “0”.

  Under such circumstances, the preset timer circuit 91 and the one-shot timer circuit 92 demodulate the input signal composed of the pulse of the period A and the pulse of the period B as will be described later with reference to FIG.

  As shown in FIG. 7, the timer circuit 90 is a circuit that can count down from the initial value to 0 as described above. Specifically, when the edge of the input signal (see the second stage in FIG. 6) is detected, the timer circuit 90 resets the count value to the initial value and starts counting down from the initial value. Note that the timer circuit 90 performs a counting operation in accordance with the period measurement pulse described above.

  Such a timer circuit 90 can count down to the count value 0 when the cycle of the input signal is the cycle A, and counts down to the count value 0 when the cycle of the input signal is the cycle B. Before, the count value is reset to the initial value based on the edge of the input signal.

  On the other hand, the timer circuit 90 is configured to be reset to the initial value also by the pulse output of the preset timer circuit 91. That is, as described above, the output of the preset timer circuit 91 is input to the preset timer circuit 91 itself. When the pulse output from the preset timer circuit 91 is input to the preset timer circuit 91, the timer circuit The count value of 90 is reset to the initial value (see FIG. 7).

The operation of such a circuit configuration will be described.
When the cycle of the input signal (see the second stage in FIG. 6) is cycle A, the timer circuit 90 can count down to 0, so that the count value of the timer circuit 90 becomes 0. At that time, the preset timer circuit 91 Outputs a pulse. As a result, the one-shot timer circuit 92 outputs a high level signal for a predetermined time. In the period in which the period of the input signal is the period A, pulses are periodically output from the preset timer circuit 91 in this way, and a high-level signal (represents “1”) from the one-shot timer circuit 92 accordingly. Data) is continuously output (see FIG. 7).

  On the other hand, when the cycle of the input signal is cycle B, the timer circuit 90 cannot count down to the count value 0, and therefore no pulse is output from the preset timer circuit 91. Therefore, during the period in which the cycle of the input signal is cycle B, the output signal from the one-shot timer circuit 92 remains at a low level. The low-level signal from the one-shot timer circuit 92 can be recognized as data representing “0”.

In this way, the input signal as shown in the second stage of FIG. 6 is demodulated using the preset timer circuit 91 and the one-shot timer circuit 92.
FIG. 8 is a diagram showing a mode of data exchange and data encryption between the one-chip microcomputer 7 and the host computer 2.

The RFID tag 6 stores identification information unique to the RFID tag 6 (hereinafter also referred to as UID).
When the RFID tag 6 is held over the one-chip microcomputer 7, an inquiry from the one-chip microcomputer 7 is received by the RFID 6, and a UID is transmitted from the RFID tag 6 to the one-chip microcomputer 7 in response to the inquiry. The UID is also transmitted from the one-chip microcomputer 7 to the host computer.

  The one-chip microcomputer 7 stores a command encryption key 102. This command encryption key 102 is the same as the command encryption key 112 stored in the host computer 2.

  When the RFID tag 6 is held over the one-chip microcomputer 7 and a UID is transmitted from the RFID tag 6 to the one-chip microcomputer 7, the UID is input to the SAFER process 101 in the one-chip microcomputer 7. A command encryption key 102 is also input to the SAFER process 101. In the SAFER process 101, an initial value is generated from the UID of the RFID tag 6 and the command encryption key 102. The initial value is input to the linear feedback shift register 103.

  The linear feedback shift register 103 generates an M-sequence random number from the initial value. The linear feedback shift register 103 may be configured by hardware or software.

The output of the linear feedback shift register 103 is input to XOR processes 105 and 106.
In the XOR processing 105, the command is determined based on the input from the linear feedback shift register 103 and the command from the host computer 2 (this command is encrypted by the UID and the command encryption key 112). It is designed to be decrypted.

  The decrypted command is input to the process 104. In the process 104, the contents of the command from the host computer 2 are analyzed, and a predetermined process instructed by the command is executed. As processing instructed by the command, for example, processing such as transmitting predetermined data to the RFID 6 (updating data in the memory of the RFID tag 6) can be considered. The data transmitted to the RFID tag 6 is encrypted again in the process 104 and transmitted to the RFID tag 6. Further, the execution result in the process 104 (the execution result of the process instructed by the command) is input to the XOR process 106.

  In the XOR process 106, the execution result is encrypted based on the execution result from the process 104 and the input from the linear feedback shift register 103. The encrypted execution result is transmitted to the host computer 2 (inputted to the XOR process 115 of the host computer 2).

  The SAFER process 101, the XOR processes 105 and 106, and the process 104 are incorporated in the one-chip microcomputer 7 as the application 3 (see FIG. 1). That is, as already described, the one-chip microcomputer 7 is configured by a single chip including the application microcomputer 3 (particularly, a secure-related application) in addition to the control microcomputer 4 and the R / W 5.

  In the host computer 2, the UID of the RFID tag 6 and the command encryption key 112 are input to the SAFER process 111. In the SAFER process 111, an initial value is generated from the UID of the RFID tag 6 and the command encryption key 112. The initial value is input to the linear feedback shift register 113.

  The linear feedback shift register 113 generates an M-sequence random number from the initial value. The linear feedback shift register 113 may be configured by hardware or software.

The output of the linear feedback shift register 113 is input to XOR processes 114 and 115.
For example, a command (command) to the one-chip microcomputer 7 is input from the application 116 to the XOR process 114 as an application process result. In the XOR process 114, the command is encrypted based on the input from the linear feedback shift register 113 and the command from the application 116. The encrypted command is transmitted to the one-chip microcomputer 7.

  In the XOR processing 115, based on the execution result input from the one-chip microcomputer 7 (the execution result corresponding to the command is encrypted) and the input from the linear feedback shift register 113, the one-chip microcomputer 7 The execution result input from is decoded. The decrypted execution result is input to the application 116 and used for processing in the application 116.

  In the application 116, predetermined application processing is executed based on various types of information such as execution result information (execution result information corresponding to a command in the one-chip microcomputer 7) input from the XOR processing 115. Based on the result of the application process, for example, a command is input to the XOR process 114.

  As described above, in this embodiment, the UID unique to the RFID tag 6 and the common command encryption key (specifically, the command encryption key 102, 112), encryption / decryption of communication between the one-chip microcomputer 7 and the host computer 2 is realized.

FIG. 9 is a diagram showing a mode of data exchange and data encryption between the RFID 6 and the one-chip microcomputer 7.
The RFID tag 6 includes a management data area 121, a random number generation circuit 122, an XOR circuit 123, a comparison circuit 124, and a user data area 125. The management data area 121 and the user data area 125 are areas in the memory (provided in the memory).

  The management data area 121 stores identification information (UID) unique to the RFID tag 6. The UID is a 64-bit code. The management data area 121 also stores a tag release key for changing the access level (changing access permission / denial). The tag release key is a 32-bit code. The tag release key is input to the comparison circuit 124.

The random number generation circuit 122 is a circuit that generates a random number, and the generated random number is input to the XOR circuit 123.
When the RFID tag 6 is held over the one-chip microcomputer 7, an inquiry from the one-chip microcomputer 7 is received by the RFID 6, and a UID is transmitted from the RFID tag 6 to the one-chip microcomputer 7 in response to the inquiry. In addition, a random number is generated by the random number generation circuit 122, and the random number is input to the XOR circuit 123 and transmitted to the one-chip microcomputer 7. The random number is input to the XOR process 133 in the one-chip microcomputer 7.

  The one-chip microcomputer 7 is provided with a flash memory 131 (for example, the flash memory 13 in FIG. 2) that stores a user setting release key set by the user. The user setting release key is a 32-bit code. Further, the one-chip microcomputer 7 is provided with an application 138 that executes various processes.

  When the one-chip microcomputer 7 receives a UID from the RFID tag 6, the UID and a user setting release key stored in the flash memory 131 are input to the SAFER process 132.

  In the SAFER process 132, a tag release key is calculated from the UID and the user setting release key. Hereinafter, the tag release key calculated by the SAFER process 132 is referred to as a first temporary tag release key. The first temporary tag release key is input to the XOR process 133.

In addition to the first temporary tag release key calculated by the SAFER process 132, the random number generated by the random number generation circuit of the RFID tag 6 is input to the XOR process 133.
The processing result of the XOR processing 133 (the XOR operation (exclusive OR operation) result based on the first temporary tag release key and the random number) is transmitted to the RFID tag 6 and input to the XOR circuit 123 of the RFID tag 6. The The XOR circuit 123 calculates a tag release key from the processing result of the XOR processing 133 of the one-chip microcomputer 7 and the random number input from the random number generation circuit 122. Hereinafter, the tag release key calculated by the XOR circuit 123 is referred to as a second temporary tag release key. The second temporary tag release key is input to the comparison circuit 124.

In addition to the input of the second temporary tag release key from the XOR circuit 123, the comparison circuit 124 also receives the tag release key stored in the management data area 121. Then, the comparison circuit 124 compares whether or not both match. As a result of the comparison by the comparison circuit 124, if the second temporary tag release key and the tag release key stored in the management data area 121 match, Access to the user data area 125 is permitted. That is, the user data area 125 is released, and reading and writing are free.

On the other hand, if the two tag release keys do not match as a result of the comparison by the comparison circuit 124, access to the user data area 125 is not permitted.
Data access to the user data area 125 when access to the user data area 125 is permitted will be described.

  As described above, when the RFID tag 6 is held over the one-chip microcomputer 7, the UID is transmitted from the RFID tag 6 to the one-chip microcomputer 7, and the UID is also input to the SAFER process 134 in the one-chip microcomputer 7. A user setting release key stored in the flash memory 131 is also input to the SAFER process 134.

  In the SAFER process 134, encrypted data (hereinafter referred to as first encrypted data) is generated based on the UID and the user setting release key. The first encrypted data is input to the SAFER process 135. Address data from the application 138 is input to the SAFER process 135 in addition to the first encrypted data from the previous SAFER process 134. The address data is information indicating the address of the user data area 125 and indicating the storage destination of the data to be stored.

  In the SAFER process 135, further encrypted data (hereinafter referred to as second encrypted data) is generated from the first encrypted data and the address data. In other words, the second encrypted data is obtained by further (doublely) encrypting the first encrypted data with the address data. The second encrypted data is input to the XOR processes 136 and 137.

  Data for writing to the user data area 125 of the RFID tag 6 is also input to the XOR process 136 from the application 138. In the XOR process 136, the data from the application 138 is encrypted with the second encrypted data input from the SAFER process 135. Then, the encrypted data is transmitted to the RFID tag 6 and written in the user data area 125.

  When reading data from the RFID tag 6, the read data is input to the XOR process 137. In the XOR process 137, the data read from the user data area 125 is restored based on the data read from the user data area 125 of the RFID tag 6 and the second encrypted data input from the SAFER process 135. Is done. The restored data is input to the application 138.

Thus, encryption / decryption of communication data is realized in communication between the RFID tag 6 and the one-chip microcomputer 7 (R / W5).
As described above, in the RFID system 1 according to the present embodiment, first, the R / W 5 having a function of reading and writing information of the RFID tag 6 and the control microcomputer 4 that controls the operation of the R / W 5 are one chip. It is configured as. In other words, the R / W 5 is incorporated into the control microcomputer 4 and formed into one chip. The control microcomputer 4 and the R / W 5 are connected by a bus. In the present specification, the one-chip configuration is referred to as a one-chip microcomputer 7.

  According to such a configuration, the confidentiality of communication data between the control microcomputer 4 and the R / W 5 can be improved. That is, it is unrealistic for a third party to analyze the signal on the circuit, so that the possibility that the third party analyzes the communication data between the control microcomputer 4 and the R / W 5 is reduced. Can do. For this reason, safety (security) can be further improved. In the present embodiment, in the communication between the one-chip microcomputer 7 and the RFID tag 6 (communication between the R / W 5 and the RFID tag 6), the demodulation process (from the RFID tag 6) on the one-chip microcomputer 7 side is performed. (Demodulation processing of received signal) can be realized by software. In the one-chip microcomputer 7, processing for encrypting / decrypting communication data with the host computer 2 and communication data with the RFID tag 6 is executed.

  For example, in the present embodiment, as described above (see also FIG. 10), the one-chip microcomputer 7 and the host computer 2 hold a common command encryption key (command encryption keys 102 and 112). Thus, encryption / decryption of communication data is realized between the one-chip microcomputer 7 and the host computer 2.

In the present embodiment, safety (security) is further improved by such encryption.
In the one-chip microcomputer 7, the processing program is stored in the flash memory 13 (or the RAM 15) in the one-chip microcomputer 7 (control microcomputer 4), and analysis is impossible. . In other words, the flash memory 13 and the RAM 15 are memories that hold information in the state of charge, and it is virtually impossible to analyze the state of charge, thus reducing the possibility of analyzing the contents of the program. Be able to. For this reason, safety (security) is further improved.
[Second Embodiment]
Next, a second embodiment of the present invention will be described.

The second embodiment is different from the first embodiment in the communication mode between the one-chip microcomputer 7 and the host computer 2. A conceptual diagram of the communication mode is shown in FIG.
In FIG. 11, the one-chip microcomputer 7 has a secure-related application and executes the application (performs encryption or the like), which is the same idea as the first embodiment.

The second embodiment is different from the first embodiment in that an application (program) is constructed in an object-oriented manner and the processing content is made into a black box.
According to the second embodiment as described above, it becomes more difficult to analyze the contents of the program, and security can be further enhanced.

As mentioned above, although one Embodiment of this invention was described, this invention is not limited to the said embodiment, A various form can be taken within the technical scope of this invention.
For example, in the above embodiment, the R / W 5 may be configured as an LSI. The R / W 5 may be built in the control microcomputer 4 as in the above-described embodiment and may be configured as a single chip, but communication between the R / W 5 and the control microcomputer 4 is encrypted. As long as it is done, the R / W 5 may be provided outside the control microcomputer 4.

For example, in the above-described embodiment, whether various functions are realized by hardware or software can be selected as appropriate.
In the RFID system 1 of the above embodiment, the configuration including the host computer 2 has been described. However, the present invention can be applied to a configuration including only the one-chip microcomputer 7 and the RFID tag 6.

  The RFID system 1 of the above embodiment can be applied to various systems such as an entrance / exit management system, an automatic ticket gate system, and a system for reading and writing (updating) monetary data in a prepaid card.

DESCRIPTION OF SYMBOLS 1 ... RFID system, 2 ... Host computer, 3 ... Application, 4 ... Control microcomputer, 5 ... Reader / writer apparatus, 6 ... RFID tag, 7 ... One-chip microcomputer, 11 ... CPU, 12 ... Clock circuit, 13 ... Flash memory , 14 ... Real time clock circuit, 15 ... RAM, 16 ... RS232C conversion circuit, 17 ... RS232C connector, 21 ... Reception demodulation processing, 22 ... Baseband processing, 23 ... Transmission modulation circuit, 24 ... Reception amplifier, 31 ... Serial communication circuit 32 ... Timer circuit 33 ... Oscillator circuit 34 ... Transmission amplifier circuit 35 ... Amplifier circuit 36 ... Envelope detector circuit 37 ... Antenna

Claims (9)

A reader / writer device that includes an antenna, and performs at least one of reading and writing of information with an RFID tag that stores information readable and writable wirelessly via the antenna;
A memory for storing a control program for controlling the operation of the reader / writer device, and a CPU for controlling the operation of the reader / writer device by reading out and executing the control program stored in the memory; Equipped with a microcomputer;
An RFID system comprising:
An RFID system, wherein the reader / writer device is built in the microcomputer and connected to the CPU by a bus. The RFID system according to claim 1, wherein
The reader / writer device includes a receiving circuit that receives a radio signal from the RFID tag via the antenna,
The memory stores a demodulation program that is executed by the CPU and that causes the CPU to execute demodulation processing for demodulating a radio signal received by the receiving circuit.
The RFID system, wherein the CPU is configured to execute the demodulation process based on the demodulation program. The RFID system according to claim 1 or 2,
The memory is a program executed by the CPU, and stores a baseband processing program for causing the CPU to execute baseband processing for generating a baseband signal from data to be transmitted to the RFID tag. ,
The CPU is configured to execute the baseband processing based on the baseband processing program,
The reader / writer device includes a modulation circuit that modulates a carrier wave based on a baseband signal generated by baseband processing executed by the CPU and sends the modulated signal to the antenna. RFID system. The RFID system according to any one of claims 1 to 3,
The RFID system according to claim 1, wherein the memory is a flash memory. The RFID system according to any one of claims 1 to 4,
A host computer communicably connected to the microcomputer via a communication line and configured to send a command to the microcomputer;
The RFID tag stores identification information unique to the RFID tag,
The control microcomputer transmits the identification information read from the RFID tag to the host computer,
The host computer includes a host-side memory that stores an encryption key for encrypting the command,
The command is encrypted using both the encryption key read from the host-side memory and the identification information received from the control microcomputer, and is transmitted to the control microcomputer.
Further, the control microcomputer stores the same information as the encryption key stored in the host-side memory, and receives a command received from the host computer from the information and the identification information read from the RFID tag. An RFID system configured to decrypt. A reader / writer device that includes an antenna, and performs at least one of reading and writing of information with an RFID tag that stores information readable and writable wirelessly via the antenna;
A memory for storing a control program for controlling the operation of the reader / writer device;
A CPU configured to be connected to at least the reader / writer device via a bus, and to control the operation of the reader / writer device by reading out and executing a control program stored in the memory;
A microcomputer comprising: The microcomputer according to claim 6.
A receiving circuit for receiving a radio signal from the RFID tag via the antenna;
The memory stores a demodulation program that is executed by the CPU and that causes the CPU to execute demodulation processing for demodulating a radio signal received by the receiving circuit.
The microcomputer is configured to execute the demodulation processing based on the demodulation program. The microcomputer according to claim 6 or 7,
The memory is a program executed by the CPU, and stores a baseband processing program for causing the CPU to execute baseband processing for generating a baseband signal from data to be transmitted to the RFID tag. ,
The CPU is configured to execute the baseband processing based on the baseband processing program,
The reader / writer device includes a modulation circuit that modulates a carrier wave based on a baseband signal generated by baseband processing executed by the CPU and sends the modulated signal to the antenna. Microcomputer. The microcomputer according to any one of claims 5 to 8,
The microcomputer is a flash memory.

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