JP2011082567A - Solid-state imaging device, and camera - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To prevent color mixture by utilizing arrangement of a capacitor region formed separately from a floating diffusion region. <P>SOLUTION: This solid-state imaging device includes: a photoelectric conversion portion; a floating diffusion portion for retaining charge generated in the photoelectric conversion portion; a charge retaining portion for retaining the charge generated in the photoelectric conversion portion; a first transfer portion for transferring the charge of the photoelectric conversion portion to the floating diffusion portion; a second transfer portion for transferring the charge of the charge retaining portion to the floating diffusion portion; and an output portion for outputting a signal in response to the charge retained by the floating diffusion portion. When a photoelectric conversion portion region including the photoelectric conversion portion is nearly square in the layout of respective pixels, a charge retaining portion region including the charge retaining portion is arranged on one side of the square, and an output portion region including the output portion is arranged on other side intersecting that side in the square. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a solid-state imaging device and a camera.

  In recent years, a CMOS area sensor in which a photodiode and a MOS transistor are integrated on a single chip is used as a solid-state imaging device. Compared with a CCD, a CMOS area sensor has advantages such as lower power consumption, lower drive power, and higher speed. In a general CMOS area sensor, each pixel has a photodiode, a floating diffusion (floating diffusion, hereinafter abbreviated as FD) area, and a charge transferred from the photodiode to the FD area. A plurality of pixels each having a transfer transistor for resetting and a reset transistor for resetting the FD region to a predetermined potential are formed in a matrix shape.

  And the technique regarding the CMOS area sensor which expanded the dynamic range is disclosed (for example, refer nonpatent literature 1). In the CMOS area sensor in Non-Patent Document 1, in each pixel, a capacitor region having a capacity larger than that of the FD is further formed, and one terminal of the capacitor region is connected to the FD via a switch. The other terminal is connected to the ground. As a result, when the charge overflows from the photodiode due to strong light (when it overflows), the overflowed charge is retained in the capacitor area, so that a signal can be output according to the amount of the overflowed charge. And the dynamic range is expanded.

Shigetoshi Sugawa, 5 others, "A 100db Dynamic Range CMOS Image Sensor Using a lateral Overflow Integration Capacitor", ISSCC 2005 / SESSION19 / IMAGES / 19.4, DIGEST OF TECHNICAL PAPERS, 2005 IEEE International Solid-State Circuit Conference, February 8, 2005 , P352-353,603

  However, it is a problem in the CMOS area sensor that color mixing with adjacent pixels occurs regardless of the presence or absence of the dynamic range expansion function described above. FIGS. 8A and 8B are diagrams illustrating a mechanism of color mixture generation according to a conventional pixel layout. In FIG. 8A, the transfer unit 502 and the MOS unit 503 are disposed below the photodiode 501. If pixels having such a layout are arranged, color mixing may be unavoidable even if an element isolation region is provided between the pixels. In the case of FIG. 8A, the distance between the photodiodes of each pixel is longer than that in the left-right direction because the MOS portion 503 is arranged in the up-down direction. However, in the left-right direction, as shown in FIG. 8A, for example, the photodiode 501 and the photodiode 504 are arranged with only the element isolation region interposed therebetween. As a result, there is a problem in that charge generated by photoelectric conversion in a deep layer portion of silicon leaks, or light that is incident obliquely and reflected by an aluminum layer or the like enters an adjacent photodiode, thereby causing color mixing.

  Further, as shown in FIG. 8B, a transfer portion 512 and a floating diffusion region 513 are provided on the right side of the photodiode 511, and a MOS portion is provided on the lower side of the photodiode 511. With such a layout, the distance between the photodiode 511 and the photodiode 521 of the pixel adjacent to the right side is larger than that in FIG. 8A, but the distance between the floating diffusion region 513 and the photodiode 521 is short. There is a problem in that charges leak to the diffusion region 513 and color mixing occurs.

  Further, in the layout of Non-Patent Document 1 described above, it is necessary to make a capacitor region large, so depending on the arrangement, the color mixing problem is greatly affected.

  The present invention has been made in view of such a problem, and an object of the present invention is to prevent color mixing by utilizing an arrangement of a capacitor region provided separately from a floating diffusion region.

  Therefore, the present invention relates to a photoelectric conversion unit, a floating diffusion unit that holds charges generated in the photoelectric conversion unit, a charge holding unit that holds charges generated in the photoelectric conversion unit, and a charge of the photoelectric conversion unit. According to the first transfer unit for transferring to the floating diffusion unit, the second transfer unit for transferring the charge of the charge holding unit to the floating diffusion unit, and the charge held by the floating diffusion unit A solid-state imaging device having a plurality of pixels including an output unit that outputs a signal, and in the layout of each pixel, when the photoelectric conversion unit region including the photoelectric conversion unit is substantially square, the charge retention A charge holding portion region including a portion is provided on one side of the square, and an output portion region including the output portion intersects the side in the square. That is provided on the other one side.

  According to the present invention, it is possible to prevent color mixing by utilizing the arrangement of a capacitor region (charge holding unit) provided separately from the floating diffusion region.

It is a figure which shows an example of the circuit structure of each pixel of the solid-state imaging device in this embodiment, and the schematic example of a layout structure. 2 is a timing chart illustrating an operation example of a pixel circuit of the solid-state imaging device illustrated in FIG. It is a figure which shows the more detailed layout example of the layout outline shown in FIG.1 (b). It is a figure which shows the more detailed layout example of the layout outline shown in FIG.1 (b) different from FIG. FIG. 5 is a diagram showing a more detailed layout example of the layout outline shown in FIG. It is a block diagram which shows the case where the solid-state imaging device of each embodiment mentioned above is applied to a "still camera". It is a block diagram which shows the case where the solid-state imaging device of each embodiment mentioned above is applied to a "video camera." It is a figure which shows the mechanism of color mixture generation according to the conventional pixel layout.

The preferred embodiments of the present invention will be described below with reference to the drawings.
(First embodiment)
First, the solid-state imaging device (CMOS area sensor) in the first embodiment of the present invention will be described. FIG. 1A is a diagram illustrating an example of a circuit configuration of each pixel of the solid-state imaging device according to the present embodiment. FIG. 1B is a diagram illustrating a schematic example of the layout configuration of each pixel of the solid-state imaging device according to the present embodiment.

First, the circuit configuration of each pixel will be described with reference to FIG.
As shown in FIG. 1A, each pixel of the solid-state imaging device of this embodiment includes a photodiode 10, a first transfer MOS transistor 11, a reset MOS transistor 12, a second transfer MOS transistor 13, and the like. , A charge holding unit (capacitor) 14, a source follower MOS transistor 15, and a selection MOS transistor 16. Each pixel of the solid-state imaging device is arranged in a two-dimensional matrix of a plurality of rows and a plurality of columns.

  The photodiode 10 accumulates charges generated by incident light. The photodiode 10 is connected to an FD (floating diffusion; floating diffusion) 17 through the first transfer MOS transistor 11. The FD 17 has a layout configuration that also serves as the drain terminal of the first transfer MOS transistor 11, and can hold charges transferred from the photodiode 10 via the first transfer MOS transistor 11. The FD 17 is connected to the drain terminal of the reset MOS transistor 12, the gate terminal of the source follower MOS transistor 15, and the drain terminal of the second transfer MOS transistor 13.

  The source terminal of the second transfer MOS transistor 13 is connected to the ground via the charge holding unit 14. The source terminals of the reset MOS transistor 12 and the source follower MOS transistor 15 are connected to, for example, a power supply line that supplies a power supply voltage VDD. The drain terminal of the source follower MOS transistor 15 is connected to the source terminal of the selection MOS transistor 16 and outputs a signal that changes in accordance with the amount of charge transferred to the FD 17. The circuit configuration illustrated in FIG. 1A described above is the same as the configuration of each pixel of the solid-state imaging device described in the related art (Non-Patent Document 1).

  The first transfer MOS transistor 11, the reset MOS transistor 12, the second transfer MOS transistor 13, and the selection MOS transistor 16 are on / off controlled by control signals supplied to the gate terminals, respectively. The first transfer MOS transistor 11, the reset MOS transistor 12, the second transfer MOS transistor 13, and the selection MOS transistor 16 are turned on (conductive) when a high-level control signal is supplied to the gate terminal. When a low-level control signal is supplied to the gate terminal, it is turned off (cut off).

  Specifically, as shown in FIG. 1A, the control signal TX is supplied to the gate terminal of the first transfer MOS transistor 11, and the control signal TX is supplied to the gate terminal of the second transfer MOS transistor 13. SW is supplied, a control signal SEL is supplied to the gate terminal of the selection MOS transistor 16, and a control signal RES is supplied to the gate terminal of the reset MOS transistor 12.

  Here, the control signal TX is a control signal for transferring charges accumulated by photoelectric conversion in the photodiode 10 to the FD 17. The control signal SW is a control signal for connecting the FD 17 and the charge holding unit 14. The control signal SEL is a control signal for selecting a pixel. The control signal RES is a control signal for resetting the potential of the FD 17 to a power supply voltage VDD (for example, + 5V).

  Next, an operation example of the pixel circuit of the solid-state imaging device shown in FIG. FIG. 2 is a timing chart illustrating an operation example of the pixel circuit of the solid-state imaging device illustrated in FIG. As shown in FIG. 2, when the control signals RES, SEL, TX, and SW are supplied, the pixel in FIG. 1 outputs the charge photoelectrically converted by the photodiode 10 as a pixel signal for a period corresponding to the control. To do.

  First, when the control signals SW and SEL are turned on and other control signals are turned off, the control signal RES is turned on at time t1, thereby resetting the potentials of the FD 17 and the charge holding unit 14 to the power supply potential VDD. Is done. At time t2, the control signal RES is turned off to complete the reset operation.

  Next, at time t3, the control signal SEL is turned off. As a result, charge accumulation starts in the photodiode 10. Since the control signal SW is on during this accumulation, for example, when the photodiode 10 overflows due to strong light and the charge overflows to the FD 17, the charge is stored in the FD 17 and the charge holding. Accumulated in both units 14.

  Next, a pixel signal reading process corresponding to the charge photoelectrically converted by the photodiode 10 is performed. Specifically, at time t4, the control signal SW is turned off and the control signal SEL is turned on. Thereby, the connection between the FD 17 and the charge holding unit 14 is disconnected.

  Next, at time t5, the control signal RES is turned on. Thereby, for example, even if charges are accumulated in the FD 17 due to overflow of the photodiode 10, the potential of the FD 17 is reset to the power supply potential VDD. Since the second transfer MOS transistor 13 is turned off by turning off the control signal SW, the charge holding unit 14 is not reset. In other words, if there is an overflowed charge, the charge holding unit 14 keeps holding it. The control signal RES is turned off after a certain period from time t5 (time earlier than time t6 below).

  Next, at time t6, when the control signal TX is turned on, the first transfer MOS transistor 11 is turned on, and the charge accumulated in the photodiode 10 is transferred to the FD17. As a result, the output signal of the source follower MOS transistor 15 transferred to the FD 17 and corresponding to the held charge is output as a pixel signal.

  Next, a pixel signal reading process corresponding to the overflowed charge for expanding the dynamic range is performed. If no overflow occurs in the photodiode 10, no charge is held in the charge holding unit 14, but here, a description will be made on the assumption that the charge overflowed by the overflow is held in the charge holding unit 14.

  Specifically, the control signal SW is turned on at time t7, and the control signal TX is turned on at time t8, so that the charge overflowed by the overflow held in the charge holding unit 14 and held in the FD17. Are added together. As a result, an output signal of the source follower MOS transistor 15 corresponding to the added charge is output as a pixel signal. Next, when the control signal RES is turned on at time t9, the potentials of the FD 17 and the charge holding unit 14 are reset to the power supply potential VDD.

  As described above, with the circuit configuration of FIG. 1A, the pixel signal can be output based on the overflowed charge amount held in the charge holding unit 14, so that the dynamic range can be expanded. The charge holding unit 14 preferably has a larger capacity than the FD 17. For this reason, the charge holding unit 14 has the next largest area in the layout of each circuit element of the pixel after the photodiode 10.

  Next, a layout example of the circuit shown in FIG. 1A will be described with reference to FIG. The layout example of this embodiment shown in FIG. 1B is a layout that can reduce color mixing with adjacent pixels (mixed signal in the case of a monochrome CMOS area sensor), and shows the features of this embodiment. It is. Note that reference numerals 101 to 103 in FIG. 1A correspond to reference numerals 101 to 103 in FIG. That is, the photodiode region 101 is a layout region including the photodiode 10, the capacitor region 102 is a layout region including the charge holding unit 14, and the MOS region 103 includes the reset MOS transistor 12 and the source follower MOS transistor. 15 and a selection MOS transistor 16. Although details will be described later, the MOS portion region 103 may include the second transfer MOS transistor 13 in some cases.

  The gate region 11 a is a gate region that constitutes the gate terminal of the first transfer MOS transistor 11. The FD region 104 is a region constituting the FD 17 and a region constituting the drain terminal of the first transfer MOS transistor 11.

  The layout shown in FIG. 1B described above is characterized in that when the photodiode region 101 is a square (which may be a substantially square), the capacitor region 102 is arranged on one side of the square, and the rectangular region The MOS portion region 103 is arranged on the other side (side intersecting with the one side). In addition, the capacitor region 102 and the MOS portion region 103 are preferably equal in length or longer than the corresponding one side of the photodiode region 101. Further, in the capacitor region 102, an n-type region or the like may be formed in the silicon substrate to secure the capacitance. However, preferably, the conductive region such as the n-type region is not formed in the silicon substrate. A capacitor is formed on the oxide film.

  Here, a method for forming the capacitor region 102 will be described. In order to form a capacitor in the capacitor region 102, for example, a MOS capacitor or a two-layer POL (poly) capacitor can be considered. In particular, in this embodiment, it is not necessary to form a diffusion layer on the silicon substrate, and it is configured by forming two polysilicon layers with a dielectric film sandwiched between an oxide film and a LOCOS (Local Oxidation of Silicon). A two-layer POL capacity is preferred. Thereby, it is possible to prevent charges from adjacent pixels that cause color mixing from passing through the silicon substrate in the capacitor region 102.

  A MOS capacitor is also preferably formed in a part of the capacitor region 102. The MOS capacitor is a capacitor formed by forming a diffusion layer on a silicon substrate, forming a dielectric film on the diffusion layer, and forming a polysilicon layer thereon.

  It is also possible to form the MOS capacitor and the two-layer POL capacitor in the same region, thereby increasing the capacitance of the charge holding portion 14 formed in the capacitor region 102. Therefore, a configuration example in which the MOS capacitor and the two-layer POL capacitor are formed in the same region will be described below.

  First, a diffusion layer is formed by doping (adding) an n-type impurity in the surface region of the P well. A capacitance (junction capacitance) is formed between the diffusion layer, which is an n-type region (region containing n-type impurities), and a P-well, which is a p-type region (region containing p-type impurities), and can accumulate charges. It is.

  A first dielectric film is formed on the diffusion layer. When the element is separated around the diffusion layer by an insulating layer such as LOCOS (Local Oxidation of Silicon), the first dielectric film may be formed on the insulating layer.

  The first polysilicon layer is formed on the first dielectric film. The first polysilicon layer is connected to the power supply potential VDD or the ground potential. Next, a second dielectric film is formed on the first polysilicon layer. The second polysilicon layer is formed on the second dielectric film.

  As described above, in the present embodiment, the first capacitor is formed by the diffusion layer that is the n-type region and the P-well that is the p-type region. In addition, a second capacitor is formed by the diffusion layer that is the n-type region, the first polysilicon layer, and the first dielectric film. Further, a third capacitor is formed by the first polysilicon layer, the second polysilicon layer, and the second dielectric film. That is, in order to form these first to third capacitors, a P well, a diffusion layer, a first dielectric film, a first polysilicon layer, a second dielectric film, and a second polysilicon layer Are stacked.

  Note that the first polysilicon layer and the second polysilicon layer have conductivity by doping (adding) impurities. The first polysilicon layer and the second polysilicon layer are not necessarily made of polysilicon as long as they are conductive materials. Further, the first and second dielectric films described above are, for example, a laminate of a SiO2 film and a SiN2 film. In addition, the first and second dielectric films have a larger capacitance (capacitance) as the thickness is smaller. Therefore, it is preferable to reduce the thickness of the first and second dielectric films as long as the insulation of the first and second dielectric films is not broken or deteriorated by the applied voltage.

  Further, when a diffusion layer (n-type region) is formed in a silicon substrate, it is not formed around the side opposite to the boundary with the adjacent pixel (the left side in FIG. 1B). , A structure resistant to color mixing can be obtained. The extent to which the diffusion layer (n-type region) is formed with respect to the side opposite to the boundary is determined by the balance between the specifications for preventing color mixing and the specifications for the capacity required for the charge holding unit 14.

  By adopting the layout as described above, the capacitor region 102 or the MOS portion region 103 is always arranged between the photodiode regions 101 of pixels adjacent vertically and horizontally. That is, the photodiode region 101 that is the target of mixed color charge intrusion is arranged away from the photodiode regions 101 of other adjacent pixels. In addition, the FD region 104 that is the target of the mixed color charge intrusion is also distant from the photodiode region 101 and the FD region 104 of other pixels. The capacitor region 102 has a structure that is resistant to color mixing as described above, and the MOS region 103 can cause the drain portion to absorb charges that cause color mixing. As described above, the arrangement of the capacitor region 102 provided separately from the FD region 104 can be utilized to reduce the color mixture as compared with the conventional case.

  In addition, an efficient layout is realized by making one side of the photodiode region 101 that needs the most area and the one side of the capacitor region 102 that needs the second area the same length. Yes. In addition, by arranging the FD region 104 between the photodiode region 101 and the capacitor region 102, it can be said that the FD region 104 is efficiently arranged according to the charge transfer path indicated by the arrow in FIG.

Next, a more detailed layout example of the layout outline shown in FIG.
FIG. 3 is a diagram showing a more detailed layout example of the layout outline shown in FIG. As shown in FIG. 3, the MOS part region 103 includes four gate regions. From the right, the gate region SEL including the gate terminal of the selection MOS transistor 16 and the gate region SF including the gate terminal of the source follower MOS transistor 15 are formed. A gate region RES including the gate terminal of the reset MOS transistor 12 and a gate region SW including the gate terminal of the second transfer MOS transistor 13 are disposed. The control signals SEL, RES, and SW described above are input to the gate regions SEL, RES, and SW.

  The left region of the gate region SEL is a drain region that constitutes the drain terminal of the selection MOS transistor 16, and a contact 305 is disposed to output a pixel signal to the outside. A region between the gate region SF and the gate region RES is a source region that shares the source terminals of the source follower MOS transistor 15 and the reset MOS transistor 12, and is a contact for connecting to a power supply line that supplies the power supply potential VDD. 304 is arranged.

  A region between the gate region RES and the gate region SW is a drain region sharing the drain terminals of the reset MOS transistor 12 and the second transfer MOS transistor 13, and a contact 303 for connecting to the FD region 104 is disposed. Has been. A region on the right side of the gate region SW is a source region that constitutes a source terminal of the second transfer MOS transistor 13, and a contact 302 for connecting to the capacitor region 102 is disposed. In addition, a contact 301 for connecting to the contact 303 is disposed in the FD region 104.

  As shown in FIG. 3, by providing a drain region that shares the drain terminals of the reset MOS transistor 12 and the second transfer MOS transistor 13, it is possible to prevent the capacity of the FD 17 from becoming too large. The capacity of the FD 17 requires an appropriate capacity. If the capacity is too large, the gain at the time of reading the charge deteriorates and the noise ratio deteriorates. Therefore, by sharing two drain regions among the drain regions of the first transfer MOS transistor 11, the reset MOS transistor 12, and the second transfer MOS transistor 13 that affect the capacitance of the FD 17, for example, described later. As shown in FIG. 5, the capacitance of the FD 17 is suppressed as compared with the case where the drain regions of the first transfer MOS transistor 11, the reset MOS transistor 12, and the second transfer MOS transistor 13 are formed as one.

  Next, a layout example different from FIG. 3 will be described. FIG. 4 is a diagram showing a more detailed layout example of the schematic layout shown in FIG. 1B, which is different from FIG. 4 differs from FIG. 3 in that the gate region SW is formed between the FD region 104 and the capacitor region 102 without forming the gate region SW in the MOS portion region 103. In FIG. 4, contacts 404 and 403 are the same as the contacts 305 and 304 in FIG.

  The contact 402 is disposed in the drain region including the drain terminal of the reset MOS transistor 12 and is a contact for connecting to the contact 401 of the FD region 104. The FD region 401 is also a drain region including the drain terminals of the first transfer MOS transistor 11 and the second transfer MOS transistor 13. In other words, in FIG. 4, the drain regions of the first transfer MOS transistor 11 and the second transfer MOS transistor 13 are made common to prevent the capacitance of the FD 17 from becoming too large. Further, the layout arrangement of FIG. 4 has an advantage that the area of each pixel can be reduced as compared with the layout arrangement of FIG.

  Next, a layout example different from FIG. 4 will be described. FIG. 5 is a diagram showing a more detailed layout example of the schematic layout shown in FIG. 1B, which is different from FIG. 5 is different from FIG. 4 in that the gate region RES of the MOS region 103 is arranged so that the FD region 104 is a drain region and the source region is shared with the source follower MOS transistor 15. . In FIG. 5, contacts 412 and 413 are the same as the contacts 403 and 404 in FIG.

  The contact 411 in FIG. 5 is a contact for connecting to the gate region SF. Further, as shown in FIG. 5, the drain regions of the first transfer MOS transistor 11, the reset MOS transistor 12, and the second transfer MOS transistor 13 are shared. As a result, the capacity of the FD 17 is increased, but the number of wirings can be reduced as compared with the case of FIGS. 3 and 4, so that the wiring density can be reduced. Thereby, a yield can be improved. It should be noted that the layout of FIG. 5 is used to increase the yield by reducing the wiring density in exchange for the increase of the capacity of the FD, or the layout of FIGS. 3 and 4 is used to prevent the increase of the capacity of the FD. It may be used properly according to the needs of the user.

(Other embodiments)
Based on FIG. 6, one embodiment when the solid-state imaging device of each embodiment described above is applied to a still camera will be described in detail.
FIG. 6 is a block diagram showing a case where the solid-state imaging device of each embodiment described above is applied to a “still camera”.
In FIG. 6, reference numeral 1301 denotes a barrier that doubles as a lens protect and a main switch. 1304 is a solid-state imaging device for capturing the subject imaged by the lens 1302 as an image signal, and 1306 is an analog-digital conversion of the image signal output from the solid-state imaging device 1304. An A / D converter to perform.

  A signal processing unit 1307 performs various corrections on the image data output from the A / D converter 1306 and compresses the data. 1308 denotes a solid-state imaging device 1304, an imaging signal processing circuit 1305, and an A / D. A timing generator that outputs various timing signals to the D converter 1306 and the signal processor 1307, 1309 is an overall control / arithmetic unit that controls various calculations and the entire still video camera, and 1310 is image data. Is a memory unit for temporarily storing data, 1311 is an interface unit for recording or reading data on a recording medium, and 1312 is a detachable semiconductor memory for recording or reading image data. Reference numeral 1313 denotes an interface unit for communicating with an external computer or the like.

Next, the operation of the still video camera at the time of shooting in the above configuration will be described.
When the barrier 1301 is opened, the main power supply is turned on, then the control system power supply is turned on, and the power supply of the imaging system circuit such as the A / D converter 1306 is turned on.
Then, in order to control the exposure amount, the overall control / arithmetic unit 1309 opens the aperture 1303, and the signal output from the solid-state imaging device 1304 is converted by the A / D converter 1306 and then sent to the signal processing unit 1307. Entered.
Based on the data, the exposure control is performed by the overall control / calculation unit 1309.
The brightness is determined based on the result of the photometry, and the overall control / calculation unit 1309 controls the aperture according to the result.

Based on the signal output from the solid-state imaging device 1304, the high-frequency component is extracted and the distance to the subject is calculated by the overall control / calculation unit 1309. Thereafter, the lens is driven to determine whether or not it is in focus. When it is determined that the lens is not in focus, the lens is driven again to perform distance measurement.
Then, after the in-focus state is confirmed, the main exposure starts.
When the exposure is completed, the image signal output from the solid-state imaging device 1304 is A / D converted by the A / D converter 1306, passes through the signal processing unit 1307, and is written in the memory unit by the overall control / calculation unit 1309.

  Thereafter, the data stored in the memory unit 1310 is recorded on a removable recording medium 1312 such as a semiconductor memory through the recording medium control I / F unit under the control of the overall control / arithmetic unit 1309. Further, the image may be processed by directly inputting to a computer or the like through the external I / F unit 1313.

Next, based on FIG. 7, an example when the solid-state imaging device of each embodiment described above is applied to a video camera will be described in detail.
FIG. 7 is a block diagram showing a case where the solid-state imaging device of each embodiment described above is applied to a “video camera”. In FIG. 7, reference numeral 1401 denotes a photographing lens, which includes a focus lens 1401A for performing focus adjustment, a zoom lens 1401B for performing a zoom operation, and an imaging lens 1401C.

  1402 is a stop, 1403 is a solid-state image sensor that photoelectrically converts an object image formed on the imaging surface into an electrical image signal, and 1404 is an image signal output from the solid-state image sensor 3. Is a sample hold circuit (S / H circuit) that further amplifies the level and outputs a video signal.

  Reference numeral 1405 denotes a process circuit that performs predetermined processing such as gamma correction, color separation, and blanking processing on the video signal output from the sample hold circuit 1404, and outputs a luminance signal Y and a chroma signal C. The chroma signal C output from the process circuit 1405 is subjected to white balance and color balance correction by a color signal correction circuit 1421 and is output as color difference signals RY and BY.

  In addition, the luminance signal Y output from the process circuit 1405 and the color difference signals RY and BY output from the color signal correction circuit 1421 are modulated by an encoder circuit (ENC circuit) 1424 to be a standard television signal. Is output as Then, it is supplied to a video recorder (not shown) or an electronic viewfinder such as a monitor EVF (electric view finder).

  Reference numeral 1406 denotes an iris control circuit which controls the iris driving circuit 1407 based on the video signal supplied from the sample hold circuit 1404, and sets the aperture of the diaphragm 1402 so that the level of the video signal becomes a predetermined value. The ig meter is automatically controlled to be controlled.

Reference numerals 1413 and 1414 denote different band-limited bandpass filters (BPFs) for extracting high-frequency components necessary for performing focus detection from the video signal output from the sample hold circuit 1404. The signals output from the first bandpass filter 1413 (BPF1) and the second bandpass filter 1414 (BPF2) are gated by the gate circuit 1415 and the focus gate frame signal, respectively, and the peak value is detected by the peak detection circuit 1416. It is detected and held and input to the logic control circuit 1417.
This signal is called a focus voltage, and the focus is adjusted by this focus voltage.

  Reference numeral 1418 denotes a focus encoder that detects the moving position of the focus lens 1401A, 1419 denotes a zoom encoder that detects the focal length of the zoom lens 1401B, and 1420 denotes an iris encoder that detects the opening amount of the aperture 1402. The detection values of these encoders are supplied to a logic control circuit 1417 that performs system control.

  The logic control circuit 1417 performs focus detection on the subject based on a video signal corresponding to the set focus detection area, and performs focus adjustment. That is, the high-frequency component peak value information supplied from each of the bandpass filters 1413 and 1414 is taken in, and the focus driving circuit 1409 is driven to the focus motor 1410 to drive the focus lens 1401A to the position where the peak value of the high-frequency component is maximized. Control signals such as a rotation direction, a rotation speed, and rotation / stop are supplied and controlled.

  The embodiment of the present invention has been described in detail with reference to the drawings. However, the specific configuration is not limited to this embodiment, and includes designs and the like that do not depart from the gist of the present invention.

10 Photodiode 11 First transfer MOS transistor 12 Reset MOS transistor 13 Second transfer MOS transistor 14 Charge holding unit (capacitor)
15 Source follower MOS transistor 16 Select MOS transistor 101 Photodiode region 102 Capacitor region 103 MOS part region 104 FD region 11a Gate region

Claims (11)

A photoelectric conversion unit;
A floating diffusion section for holding charges generated in the photoelectric conversion section;
A charge holding unit for holding charges generated in the photoelectric conversion unit;
A first transfer unit for transferring charges of the photoelectric conversion unit to the floating diffusion unit;
A second transfer unit for transferring the charge of the charge holding unit to the floating diffusion unit;
An output unit that outputs a signal corresponding to the charge held in the floating diffusion unit;
A solid-state imaging device having a plurality of pixels including:
In the layout of each pixel, when the photoelectric conversion unit region including the photoelectric conversion unit is substantially square, the charge holding unit region including the charge holding unit is provided on one side of the square and includes the output unit. The partial area is a solid-state imaging device provided on the other side intersecting the side in the square.   The solid-state imaging device according to claim 1, wherein the output unit region further includes a reset unit that resets the floating diffusion unit.   The solid-state imaging device according to claim 1, wherein the output unit region includes the second transfer unit.   3. The solid-state imaging device according to claim 1, wherein drain regions of the first transfer unit and the second transfer unit are shared with the floating diffusion unit.   3. The solid according to claim 2, wherein a drain region of the first transfer unit and the second transfer unit is shared with the floating diffusion unit, and a drain region of the reset unit is further shared with the floating diffusion unit. Imaging device.   The solid-state imaging device according to claim 2, wherein a drain region of the second transfer unit and the reset unit is shared.   The charge holding unit region provided on one side of the substantially rectangular side of the photoelectric conversion unit region has a side longer than the one side, and the output unit region provided on the other side of the square intersecting the side is the other side. The solid-state imaging device according to claim 1, having a side longer than one side.   The solid-state imaging device according to claim 1, wherein the charge holding unit includes polysilicon.   The solid-state imaging device according to claim 8, wherein the charge holding unit is a capacitor made of a MOS.   The solid-state imaging device according to claim 8, wherein the charge holding unit is a capacitor made of two-layer polysilicon. A solid-state imaging device according to any one of claims 1 to 10,
A signal processing unit for processing a signal from the solid-state imaging device;
Having a camera.

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