JP2011081700A - Semiconductor device and multiprocessor system - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To dispense with an external terminal that corresponds to an IPL bus by enabling writing of initial program using a bus for coded data. <P>SOLUTION: A semiconductor device (210) is formed by including a memory (102) which can store a program, a CPU (101) capable of executing a program stored in the memory, and first external terminals (EX_D, EX_CS, EX_WE, and EX_OE) coupled with the bus for coded data that can transmit data stream. The semiconductor device (210) is provided with a control circuit (103) capable of controlling an operation to write the initial program into the memory through the first external terminal. The control circuit includes a circuit that generates an address signal for writing the initial program in the memory. Since writing of the initial program using the bus for coded data becomes possible, an IPL bus is not required. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a semiconductor device and a multiprocessor system having a plurality of processors, and more particularly to a direct access technology for a memory included in the semiconductor device or the multiprocessor system.

  A digital still camera is equipped with a processor having still image or moving image shooting, image processing, various media controls, display control functions, and the like necessary for configuring a camera system. In some cases, the above-mentioned processor is used as a master processor, and various slave processors for realizing unique functions under the control of the master processor are mounted. For example, an audio codec for recording and reproducing digital audio, an LCD controller for displaying captured images on a liquid crystal display (LCD), a moving image codec having a digital video encoding and decoding function, and the like are examples of the slave processor. It is said. The slave processor is provided as an SoC (System-on-a-chip) which is an example of a semiconductor device.

  For example, the moving image codec includes an engine for encoding / decoding moving images, a CPU (Central Processing Unit) that controls the operation of the moving image codec, an SRAM (Static Random Access Memory) that can be randomly accessed by the CPU, and the like. . Such a moving image codec is coupled to the master processor via a code data bus or an IPL bus. The code data bus is used to exchange a data stream (serially output digital data) between the moving image codec and the master processor. The IPL bus is used to write an initial program (IPL: Initial Program Loader) from the master processor to the SRAM in the moving image codec. The IPL is a program that is activated first after the system power is turned on, and is stored in a built-in SRAM in the moving image codec. In the moving image codec, the initial program can be changed from the master processor to the SRAM in the moving image codec via the IPL bus.

  Patent documents 1 and 2 can be cited as documents in which technologies related to the present invention are described.

  Japanese Patent Application Laid-Open No. 2004-151561 describes a technique that allows an initial program to be easily changed in a processor system.

  Patent Document 2 describes a multiprocessor system and a slave system activation method that can reduce the number of components with a simple configuration.

JP 2001-216164 A JP 2007-213292 A

  In an SRAM incorporated in a conventional moving image codec, an external terminal corresponding to a code data bus and an external terminal corresponding to an IPL bus are required. The external terminals corresponding to the code data bus include terminals corresponding to signals such as data, a chip select signal, a write enable signal, and an output enable signal. The external terminals corresponding to the IPL bus include terminals corresponding to the address signal, data, chip select signal, write enable signal, and output enable signal. Thus, a large number of external terminals are required in the conventional moving image codec.

  The inventor of the present application examined reducing external terminals in a moving image codec. If the initial data write and data transfer are performed using the code data bus, the IPL bus is not required, and the external terminal corresponding to the bus can be omitted. I found.

  However, since the code data bus is dedicated to digital data output serially from the master processor to the video codec and originally does not require an address signal, transmission of the address signal is considered. Not. For this reason, it is impossible to transmit both the initial program and the write address signal of the program to the SRAM in the moving image codec using the code data bus.

  In Patent Documents 1 and 2, there is no description or suggestion of omitting an external terminal corresponding to an IPL bus by enabling writing of an initial program using a code data bus.

  An object of the present invention is to provide a technique for omitting an external terminal corresponding to an IPL bus by enabling an initial program to be written using a code data bus.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  The following is a brief description of an outline of typical inventions disclosed in the present application.

  That is, a semiconductor device includes a memory capable of storing a program, a CPU capable of executing a program stored in the memory, and a first external terminal coupled to a code data bus capable of transmitting a data stream. It is formed. At this time, the semiconductor device is provided with a control circuit capable of controlling the operation for writing the initial program to the memory via the first external terminal. The control circuit includes a circuit that generates a write address signal for writing the initial program into the memory.

  According to the above configuration, the control circuit controls an operation for writing the initial program to the memory via the first external terminal, and generates a write address signal for writing the initial program to the memory. To do. As a result, the initial program can be written using the code data bus. This eliminates the need for the IPL bus and achieves the omission of external terminals corresponding to the IPL bus.

  The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows.

  That is, by allowing the initial program to be written using the code data bus, an external terminal corresponding to the IPL bus can be omitted.

1 is a block diagram illustrating a configuration example of a moving image codec as an example of a semiconductor device according to the present invention. 1 is a block diagram illustrating an example of the overall configuration of a digital still camera (DSC) as an example of a multiprocessor system according to the present invention. It is a block diagram of a configuration example of a direct access control circuit included in the moving image codec. It is explanatory drawing of the operation mode in the said moving image codec. It is explanatory drawing of the external terminal specification in the said moving image codec. It is a timing diagram of the operation mode transition in the video codec.

1. First, an outline of a typical embodiment of the invention disclosed in the present application will be described. Reference numerals in the drawings referred to in parentheses in the outline description of the representative embodiments merely exemplify what are included in the concept of the components to which the reference numerals are attached.

  [1] A semiconductor device (210) according to a representative embodiment of the present invention includes a memory (102) capable of storing a program, a CPU (101) capable of executing a program stored in the memory, Including a first external terminal (EX_D, EX_CS, EX_WE, EX_OE) coupled to a code data bus capable of transmitting the data stream, and performs processing of the data stream. The semiconductor device (210) includes a control circuit (103) capable of controlling an operation for writing an initial program to the memory via the first external terminal. The control circuit includes a circuit that generates a write address signal for writing the initial program into the memory.

  [2] In the above [1], the memory can be an SRAM.

  [3] In the above [2], the control circuit (103) has a built-in SRAM access mode and a built-in SRAM boot mode. The control circuit (103) writes the initial program to the SRAM by generating an address for writing to the SRAM (102) in the built-in SRAM access mode, and the initial in the SRAM in the built-in SRAM boot mode. The CPU (101) is caused to execute the program.

  [4] In the above [3], the semiconductor device (210) is provided with a second external terminal (RESET) capable of designating a reset state and a third external terminal (MODE0, MODE) for setting an operation mode. be able to. At this time, the built-in SRAM access mode or the built-in SRAM boot mode is designated according to the logic state of the third external terminal when the reset state designated via the second external terminal is released.

  [5] In the above [4], the control circuit (103) selectively selects the direct access module (301) for controlling direct access from the master processor to the SRAM, and the direct access module as the SRAM. And a switching circuit (302) for coupling to the circuit. At this time, the direct access module generates an address for writing to the SRAM while being selectively coupled to the SRAM (102) by the switching circuit in the built-in SRAM access mode.

  [6] In the above [5], the direct access module (301) includes an address generation circuit (301A) that sequentially generates an address for writing to the SRAM (102) and an address for reading from the SRAM. Can be configured.

  [7] In the above [6], the address generation circuit (301A) increments the address for writing to the SRAM (102) and the address for reading from the SRAM with the initial address of the SRAM as an initial value. Can be configured to generate sequentially.

  [8] A multiprocessor system (200) according to a representative embodiment of the present invention includes a master processor (203), a slave processor (210) subordinate to the master processor, the master processor, and the slave processor. And a code data bus that enables exchange of data streams between them. The slave processor includes a memory (102) capable of storing a program, a CPU (101) capable of executing a program stored in the memory, and a first external terminal (EX_D, EX_CS, EX_WE, EX_OE) and a control circuit (103) capable of controlling an operation for writing an initial program from the master processor to the memory via the code data bus and the first external terminal. The control circuit includes a circuit that generates a write address signal for writing the initial program to the memory.

  [9] In the above [8], the memory can be an SRAM.

  [10] In the above [9], the control circuit (103) includes a built-in SRAM access mode and a built-in SRAM boot mode. At this time, the control circuit (103) writes the initial program to the SRAM by generating an address for writing to the SRAM (102) in the built-in SRAM access mode, and stores the internal program in the SRAM in the built-in SRAM boot mode. The CPU (101) is made to execute an initial program.

  [11] In the above [10], the slave processor (210) is provided with a second external terminal (RESET) capable of designating a reset state and a third external terminal (MODE0, 1) for setting an operation mode. be able to. At this time, the built-in SRAM access mode or the built-in SRAM boot mode is designated according to the logic state of the third external terminal when the reset state designated via the second external terminal is released.

  [12] In the above [11], the control circuit (103) selectively selects the direct access module (301) for controlling direct access from the master processor to the SRAM, and the direct access module as the SRAM. And a switching circuit (302) for coupling to the circuit. At this time, the direct access module generates the write address of the SRAM while being selectively coupled to the SRAM (102) by the switching circuit in the built-in SRAM access mode.

  [13] In [12], the direct access module (301) sequentially generates a write address to the SRAM (102) and a read address from the SRAM in the built-in SRAM access mode. (301A) can be included.

  [14] In the above [13], the address generation circuit (301A) increments the address for writing to the SRAM (102) and the address for reading from the SRAM with the initial address of the SRAM as an initial value. Can be configured to generate sequentially.

2. Details of Embodiments Embodiments will be further described in detail.

  FIG. 2 shows an overall configuration example of a digital still camera (DSC) as an example of a multiprocessor system according to the present invention.

  The digital still camera 200 is provided with an image sensor 202 for directly converting light incident through the lens 201 into a pixel value, and can record a captured still image or moving image as digital data. A CCD (Charge Coupled Device) type or a CMOS (Complementary Metal Oxide Semiconductor) type can be applied to the image sensor 202. The output of the image sensor 202 is transmitted to the main processor 203. The digital still camera 200 has an autofocus shutter 215 that is automatically adjusted in focus by an operation of half-pressing a shutter button. The motor of the autofocus shutter 215 is driven by a motor driver 216. The operation of the motor driver 216 is controlled by the main processor 203. The main processor 203 is provided with a flash memory (Flash) 214 and an SDRAM (Synchronous Random Access Memory) 213. A program executed by the main processor 203 is stored in the flash memory 214. In the SDRAM 213, a work area for arithmetic processing performed by the main processor 203 is formed. The main processor 203 includes an audio codec 204 for recording and reproducing digital audio via a sound collecting microphone 205 and a speaker 206, and an LCD controller for displaying a captured image on a liquid crystal display (LCD) 209. 208, a moving picture codec 210 having a digital video encoding / decoding function, and the like. When the main processor 203 is a master processor, the audio codec 204, the LCD controller 208, and the moving image codec 210 are slave processors and are formed as SoC (System-on-a-chip). Further, the main processor 207 can send a digital video signal to the externally connected television device 207. The main processor 207 can be coupled to various memory cards 211 and various devices 212 compliant with the USB (Universal Serial Bus) standard.

  FIG. 1 shows a configuration example of the moving image codec 210.

  The video codec 210 is not particularly limited, but includes a CPU 101, a static random access memory (SRAM) 102, a direct access control circuit (DACC) 103, a ROM 104, a codec engine 105, a code input / output circuit 106, and an image input / output circuit 106. The output circuit 107 is formed on one semiconductor substrate such as a single crystal silicon substrate by a known semiconductor integrated circuit manufacturing technique. CPU 101, codec engine 105, code input / output circuit 106, and image input / output circuit 107 are coupled to internal bus 109. The SRAM 102 and the ROM 104 are coupled to the direct access control circuit 103.

  The SRAM 102 and the ROM 104 store programs executed by the CPU 101. The CPU 101 executes a program stored in the SRAM 102 or the ROM 104 to transfer a program for performing overall operation control of the moving image codec 210 to a mobile RAM (DDR Mobile RAM) 108. The direct access control circuit 103 performs access source switching and boot address control. In switching the access source, the access from the CPU 101 to the SRAM 102 and the access from the main processor 203 to the SRAM 102 can be switched. In the boot address control, the boot area can be switched. By switching the boot area, it is possible to switch between activation from the SRAM 102 and activation from the ROM 104. The codec engine 105 is an engine corresponding to the moving image compression standard H.264 recommended by, for example, ITU-T (International Telecommunication Union Telecommunication Standardization Sector), and encodes or decodes moving images. The code input / output circuit 106 enables input / output of code data to / from the main processor 203. The image input / output circuit 107 allows image data to be input / output to / from the main processor 203. A low power consumption mobile RAM (DDR Mobile RAM) 108 is coupled to the moving image codec 210, and a system program is transferred to the mobile RAM 108 from the main processor 203 via the moving image codec 210.

  FIG. 3 shows a configuration example of the direct access control circuit 103.

  The direct access control circuit 103 includes an SRAM direct access module 301, an access source switching circuit 302, and a boot address control circuit 303.

  The SRAM direct access module 301 includes an address generation circuit 301A that generates an address signal of the SRAM 102, and an access control circuit 301B that performs access from the main processor 203 to the SRAM 102 without the CPU 101. The address generation circuit 301 </ b> A generates an address signal for writing to the SRAM 102. The write address signal is generated sequentially from the top address of the SRAM 102. The address signal generated by the address generation circuit 301A and the control signal from the access control circuit 301B are transmitted to the SRAM 102 via the access source switching circuit 302.

  The boot address control circuit 303 is based on an address signal (Higher order address) output from the CPU 101 when activation (boot) from the SRAM 102 or the ROM 104 is designated by the operation mode control transmitted from the main processor 203. To select the access (boot) area. Although not particularly limited, the boot address control circuit 303 includes a path selection circuit 303A and a selection control circuit 303B that forms a signal for controlling the selection operation of the path selection circuit 303A. The selection control circuit 303B is activated when the activation from the SRAM 102 or the ROM 104 is designated by the operation mode control transmitted from the main processor 203, and is accessed based on an address signal (Higher order address) output from the CPU 101. Select an area. For example, when the path on the access source switching circuit 302 side is coupled to the CPU 101 via the path selection circuit 303A, the CPU 101 can access the SRAM 102. When the path on the ROM 104 side is coupled to the CPU 101 via the path selection circuit 303 </ b> A, the CPU 101 can access the ROM 104.

  The moving image codec 210 having the above configuration has a CS space boot mode, a built-in ROM boot mode, a built-in SRAM boot mode, and a built-in SRAM access mode as a plurality of operation modes, for example, as shown in FIG. Each operation mode is designated by the main processor 203. In the CS space boot mode, the program is started from an initial program stored in a ROM or the like arranged outside the moving image codec 210. In the built-in ROM boot mode, the program is started from an initial program stored in the ROM 104. In the built-in SRAM boot mode, the program is started from an initial program stored in the SRAM 102. In the built-in SRAM access mode, the initial program can be written to the SRAM 102.

  Next, external terminal specifications in the video codec 210 shown in FIG. 3 will be described with reference to FIG.

  Examples of external terminals used for setting the operation mode include TEST, MODE0, 1, and RESET. TEST, MODE0, 1 are input-only operation mode setting terminals. RESET is a reset terminal for initializing the entire SoC, and this reset terminal is also an input-only terminal.

  EX_D, EX_CS, EX_WE, and EX_OE can be listed as external terminals coupled to the code data bus that enables the data stream to be exchanged between the main processor 203 and the operation codec 210. EX_D is used for data input / output. EX_CS is an input-only terminal and is used for fetching a chip select signal. EX_WE is an input-only terminal and is used for capturing a write enable signal. EX_OE is an input-only terminal and is used for capturing an output enable signal.

  Note that the moving image codec 210 shown in FIG. 3 does not require an external terminal connected to the IPL bus, as will be described later.

  Next, transition of operation modes in the moving image codec 210 will be described.

  The operation mode in the moving image codec 210 is specified by a logical combination of a plurality of external terminals (TEST, MODE 0, 1, RESET) in the moving image codec 210. This designation is performed by the main processor 203.

  For example, as shown in FIG. 6, the video codec 210 is initialized (reset state) in a state where RESET is asserted to a low (L) level. If TEST and MODE0 are set to low level and MODE1 is set to high level while RESET is negated to high (H) level, the built-in SRAM access mode is designated, and thereby the video codec 210 is reset. A transition is made from the state to the built-in SRAM access mode. In this built-in SRAM access mode, the SRAM direct access module 301 and the SRAM 102 are brought into conduction by the access source switching circuit 302. At this time, EX_CS (chip select) is asserted to a low level, EX_WE (write enable) is asserted to a low level, and EX_OE (output enable) is negated to a high level. The initial program is transmitted via EX_D. In this built-in SRAM access mode, a write address signal to the SRAM 102 is sequentially generated by the address generation circuit 301A, for example, by sequentially incrementing the first address of the SRAM 102 in predetermined address units. As a result, the initial program input via EX_D is sequentially written from the top address of the SRAM 102. In this way, the initial program is transferred from the main processor 203 to the SRAM 102 via the external terminals (EX_D, EX_CS, EX_WE, EX_OE) corresponding to the code data bus.

  Next, the video codec 210 is initialized again in a state where RESET is asserted to a low (L) level (reset state. In this case, the program written in the SRAM 102 is retained), and RESET is high (H ) When TEST is low level and MODE0 and MODE1 are high level in the state negated to the level, the built-in RAM boot mode is designated, so that the video codec 210 is reset from the reset state to the built-in RAM boot mode. Transition to. In this built-in RAM boot mode, the boot address control circuit 303 and the SRAM 102 are brought into conduction by the access source switching circuit 302. At this time, the SRAM 102 is selected as an access (boot) area by selecting a path on the access source switching circuit 302 side based on an address signal (Higher order address) output from the CPU 101. In this state, the CPU 101 reads and executes the initial program in order from the top address of the SRAM 102. By executing this initial program, the CPU 101 receives a system program from the main processor 203 and transfers it to a mobile RAM (DDR Mobile RAM) 108. Then, the CPU 101 executes a system program in the mobile RAM 108 to exchange data streams between the main processor 203 and the moving image codec 210 via the code data bus.

  The address generation circuit 301 generates the read address of the SRAM 102, so that the information stored in the SRAM 102 can be transmitted to the main processor 203 via the code data bus. At this time, EX_OE is asserted instead of EX_WE at the external terminal.

  According to the conventional technology, an IPL bus is provided as a dedicated bus for writing an initial program from the master processor to the SRAM in the moving image codec, and the initial program is transmitted via the IPL bus. Therefore, the conventional video codec has to be provided with various external terminals A, D, CS, WE, and OE as shown in FIG. 5 as external terminals corresponding to the IPL bus.

  On the other hand, according to the configuration shown in FIG. 3, by setting the built-in SRAM access mode, the SRAM direct access module 301 and the SRAM 102 are brought into conduction by the access source switching circuit 302, and the code data is sent from the main processor 203. The initial program is transferred to the SRAM 102 via external terminals (EX_D, EX_CS, EX_WE, EX_OE) corresponding to the bus. That is, since the code data bus for exchanging the data stream between the main processor 203 and the moving picture codec 210 is used for the transmission of the initial program by switching the operation mode, the IPL bus becomes unnecessary. Therefore, it is not necessary to provide various external terminals A, D, CS, WE, and OE for coupling to the IPL bus. Thereby, the number of external terminals of the video codec 210 can be reduced.

  According to this embodiment, the following effects can be obtained.

  (1) As shown in FIG. 6, when TEST and MODE0 are at low level and MODE1 is at high level while RESET is negated to high (H) level, the built-in SRAM access mode is designated. As a result, the moving picture codec 210 transitions from the reset state to the built-in SRAM access mode. In this built-in SRAM access mode, the SRAM direct access module 301 and the SRAM 102 are brought into conduction by the access source switching circuit 302 without the intervention of the CPU 101, and the SRAM direct access module 301 generates an address signal for writing to the SRAM 102 and outputs it to the SRAM 102. Access control is performed. Such writing of the initial program can be completed in a shorter time compared to the case where the CPU is interposed using the IPL bus as in the conventional example, so the time from the writing of the initial program to the start-up is completed. Shortening can be achieved.

  (2) By using the code data bus for exchanging the data stream between the main processor 203 and the moving image codec 210 for the transmission of the initial program by switching the operation mode, the IPL bus becomes unnecessary. Therefore, various external terminals A, D, CS, WE, and OE for coupling to the IPL bus can be omitted. Thereby, the number of external terminals of the video codec 210 can be reduced as compared with the conventional example.

  (3) The direct access control circuit 103 includes a direct access module 301 for controlling direct access from the master processor to the SRAM, and a switching circuit 302 for selectively coupling the direct access module to the SRAM. Can be easily formed.

  (4) The address generation circuit 301A sequentially generates the address for writing to the SRAM 102 from the top address of the SRAM 102. Such address generation is performed in a predetermined address unit with the top address of the SRAM 102 as an initial value. This can be easily realized by performing the increment operation.

  Although the invention made by the present inventor has been specifically described based on the embodiments, it is needless to say that the present invention is not limited thereto and can be variously modified without departing from the gist thereof.

  For example, when an interface such as a code data bus for exchanging data streams is unidirectional, both interfaces such as a code data bus for exchanging data streams are set by setting the built-in SRAM access mode. It is also possible to switch so that it can be transmitted in the opposite direction. If an interface such as a code data bus for exchanging data streams can be transmitted bi-directionally, the address generation circuit 301 generates a read address for the SRAM 102, thereby storing the information stored in the SRAM 102 as a code data bus. Via the main processor 203.

  The data width (32, 16, 8) in the data transmission path in the direct access control circuit (DACC) 103 may be fixed, but the data width may be appropriately changed in conjunction with mode switching.

101 CPU
102 SRAM
103 Direct access control circuit 104 ROM
105 Codec Engine 106 Code Input / Output Circuit 107 Image Input / Output Circuit 108 Mobile RAM
203 main processor 210 moving picture codec 301 SRAM direct access module 301A address generation circuit 301B access control circuit 302 access source switching circuit 303 boot address control circuit 303A path selection circuit 303B selection control circuit

Claims (14)

Memory that can store programs;
A CPU capable of executing a program stored in the memory;
A first external terminal coupled to a code data bus capable of transmitting a data stream,
A semiconductor device capable of processing a data stream captured from the first external terminal via the code data bus,
A control circuit capable of controlling an operation for writing an initial program to the memory via the first external terminal;
The semiconductor device, wherein the control circuit includes a circuit that generates a write address signal for writing the initial program into the memory.   The semiconductor device according to claim 1, wherein the memory is an SRAM.   The control circuit has a built-in SRAM access mode and a built-in SRAM boot mode. In the built-in SRAM access mode, the control circuit writes the initial program to the SRAM by generating an address for writing to the SRAM, and the built-in SRAM boot mode. 3. The semiconductor device according to claim 2, wherein the CPU executes an initial program in the SRAM in a mode. The semiconductor device includes a second external terminal that can specify a reset state;
A third external terminal for setting the operation mode,
4. The built-in SRAM access mode or the built-in SRAM boot mode is designated according to the logic state of the third external terminal when the reset state designated via the second external terminal is released. Semiconductor device. The control circuit includes a direct access module for controlling direct access from the master processor to the SRAM;
A switching circuit for selectively coupling the direct access module to the SRAM,
5. The semiconductor device according to claim 4, wherein the direct access module generates an address for writing to the SRAM while being selectively coupled to the SRAM by the switching circuit in the built-in SRAM access mode.   6. The semiconductor device according to claim 5, wherein the direct access module includes an address generation circuit that sequentially generates a write address to the SRAM and a read address from the SRAM.   The semiconductor device according to claim 6, wherein the address generation circuit sequentially generates an address for writing to the SRAM and an address for reading from the SRAM by an increment operation having an initial value at the top address of the SRAM. A master processor;
A slave processor subordinate to the master processor;
A multi-processor system including a coded data bus that enables exchange of a data stream between the master processor and the slave processor,
The slave processor includes a memory capable of storing a program,
A CPU capable of executing a program stored in the memory;
A first external terminal coupled to the code data bus;
A control circuit capable of controlling an operation for writing an initial program to the memory from the master processor via the code data bus and the first external terminal,
The multiprocessor system, wherein the control circuit includes a circuit that generates a write address signal for writing the initial program into the memory.   9. The multiprocessor system according to claim 8, wherein the memory is an SRAM.   The control circuit includes a built-in SRAM access mode and a built-in SRAM boot mode. In the built-in SRAM access mode, the control circuit writes the initial program to the SRAM by generating an address for writing to the SRAM, and the built-in SRAM boot mode. 10. The multiprocessor system according to claim 9, wherein the CPU executes an initial program in the SRAM. The slave processor includes a second external terminal that can specify a reset state;
A third external terminal for setting the operation mode,
11. The built-in SRAM access mode or the built-in SRAM boot mode is designated according to the logic state of the third external terminal when the reset state designated via the second external terminal is released. Multiprocessor system. The control circuit includes a direct access module for controlling direct access from the master processor to the SRAM;
A switching circuit for selectively coupling the direct access module to the SRAM,
12. The multiprocessor system according to claim 11, wherein the direct access module generates a write address of the SRAM in a state in which the direct access module is selectively coupled to the SRAM by the switching circuit in the built-in SRAM access mode.   13. The multiprocessor system according to claim 12, wherein the direct access module includes an address generation circuit that sequentially generates an address for writing to the SRAM and an address for reading from the SRAM.   14. The multiprocessor system according to claim 13, wherein the address generation circuit sequentially generates an address for writing to the SRAM and an address for reading from the SRAM by an increment operation having the initial address of the SRAM as an initial value.

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