JP2011080938A - Maximum and minimum voltage detection circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a maximum and minimum detection circuit for detecting the maximum value and the minimum value out of a plurality of voltages to be measured, which is switchable while a main circuit during detection of the maximum value and the minimum value is used in common. <P>SOLUTION: The detection circuit includes a constitution for switching and controlling so as to select and connect either of a plurality of operational amplifiers OPA1-OPAn for comparison and output by applying voltages V1-Vn to be measured into one input terminal, respectively, and by applying a voltage input into a control processing unit CONT for detecting and processing the maximum voltage or the minimum voltage into the other input terminal, and a field-effect transistor wherein forward-polarity diodes D12-Dn2 and reverse-polarity diodes D11-Dn1 or a parasitic diode are connected in a direction reverse to a forward direction between output terminals of the operational amplifiers OPA1-OPAn and the control processing unit CONT. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a maximum / minimum voltage detection circuit that detects one or both of a maximum value and a minimum value for DC voltages at a plurality of locations.

  Means are known for measuring voltage values at a plurality of locations in various devices and circuits and controlling each unit in accordance with the result of detecting either one or both of the maximum and minimum values. For example, FIG. 5A shows a conventional maximum value detection circuit, where V1, V2,... Vn are measured voltages, OP1 to OPn are operational amplifiers, DP1 to DPn are forward-connected diodes, and CT is A control processing part is shown. Among the measured voltages V1 to Vn, when the maximum value voltage is, for example, V2, the output voltage of the operational amplifier OP2 is output through the diode DP2, and the other measured voltages are not the maximum value, so the diodes DP1 and DP3 ˜DPn is in a reverse bias state. Accordingly, the voltage V2 among the measured voltages V1 to Vn is input to the control processing unit CT as the maximum value Vmax. FIG. 5B shows a conventional minimum value detection circuit, which differs from the maximum value detection circuit of FIG. 5A in that the operational amplifiers OP1 to OPn are connected with diodes DN1 to DNn in the reverse direction. Therefore, the output signal level of the operational amplifier to which the voltage of the minimum value is input becomes the minimum value, and the output signal level of the other operational amplifier is higher than that, so that the diode is in the reverse bias state, and the control processing unit CT The minimum value Vmin can be detected.

  In addition, a large-capacity power storage device is configured by directly connecting a plurality of electric double layer capacitors, and a maximum voltage detector and a minimum voltage detector for detecting the maximum voltage and the minimum voltage among the terminal voltages of each capacitor are provided. The provided configuration is also known. In the charging process for a plurality of electric double layer capacitors connected in series, the charging voltage of each electric double layer capacitor is detected by a maximum voltage detector. Bypass the charging path for the multilayer capacitor, continue charging other capacitors, and when the voltage detected by the minimum voltage detector reaches or exceeds the upper limit voltage, the entire charging is terminated, and each of the series connection Means have been proposed that allow the capacitor to be charged as much as possible (see, for example, Patent Document 1). Also, a diode is connected to the output terminal of the operational amplifier, the output signal is connected to be input to the inverting input terminal of the operational amplifier, a signal is input to the non-inverting input terminal of the operational amplifier, and the diode is connected in the forward direction. Means for detecting the maximum value by the configuration and detecting the minimum value by the configuration in the reverse direction connection have been proposed (for example, see Patent Document 2).

  A plurality of NMOS transistors are connected in parallel, a comparison voltage is applied to each gate, a power supply voltage is applied to the drain of the common connection, a constant current source is connected to the source of the common connection, and the operational amplifier Connect to the non-inverting input terminal, connect the source of the NMOS transistor to the inverting input terminal of this operational amplifier and connect it to the ground through a constant current source, and connect the source voltage to the drain of the NMOS transistor. The output terminal of the operational amplifier is connected to the gate of the NMOS, the maximum voltage detection circuit for outputting the maximum voltage among the voltages applied to the gates of the NOMS transistors connected in parallel from the operational amplifier, and the plurality of NMOS transistors are PMOS transistors. In addition, a minimum voltage detection circuit having a configuration in which a constant current source is connected to the power supply side has been proposed ( In example, see Patent Document 3).

Japanese Patent Laid-Open No. 2003-244859 JP 2006-340162 A JP 2006-345230 A

  In order to detect a maximum value and a minimum value among a plurality of DC voltages, conventionally, for example, as shown in FIG. 5, a maximum value detection circuit ((A) in FIG. 5) and a minimum value detection circuit ( 5 (B)) needs to be prepared separately, and there are problems such as an increase in mounting area and a problem of cost increase. An object of the present invention is to solve such a conventional problem, and the main parts of the maximum value detection circuit and the minimum value detection circuit are combined, and the maximum value detection and the minimum value detection are performed by switching. It is possible.

  The maximum / minimum voltage detection circuit according to the present invention is a maximum / minimum voltage detection circuit for detecting a maximum value or a minimum value of a plurality of measured voltages, and applies the measured voltages to one input terminal, respectively. Alternatively, a plurality of operational amplifiers that apply a voltage input to the control processing unit that detects and processes the minimum voltage to the other input terminal and performs comparison output, and an output terminal of these operational amplifiers and the control processing unit in order. And a switch that performs switching control so as to selectively connect either the direction polarity diode or the reverse polarity diode.

  In addition, a plurality of operational amplifiers that apply a voltage to be measured to one input terminal, apply a voltage input to the control processing unit for detecting and processing the maximum voltage or the minimum voltage to the other input terminal, and compare and output these, and these Each parasitic diode is connected in series between the output terminal of the operational amplifier and the control processing unit so as to have a reverse polarity, and either one is turned on depending on whether the maximum value is detected or the minimum value is detected. And a field effect transistor which is controlled to be in an off state.

  In addition, a plurality of operational amplifiers that apply a voltage to be measured to one input terminal, apply a voltage input to the control processing unit for detecting and processing the maximum voltage or the minimum voltage to the other input terminal, and compare and output these, and these Each parasitic diode is connected in series between the output terminal of the operational amplifier and the control processing unit so as to have a reverse polarity, and either one is turned on depending on whether the maximum value is detected or the minimum value is detected. And a photo MOS field effect transistor which is controlled to be in an off state.

  A plurality of differential amplifiers that respectively input terminal voltages of a plurality of series-connected batteries or capacitors and an output voltage of the differential amplifier are input to the operational amplifier as the measured voltages.

  As a maximum / minimum voltage detection circuit that detects the maximum value or minimum value voltage among multiple types of measured voltages, the main circuit configuration can be shared for maximum value voltage detection and minimum value voltage detection. The switching has an advantage that the main configuration can be used as it is depending on whether the connection configuration of the diode is switched by a switch or the connection configuration of the parasitic diode of the field effect transistor is switched.

It is explanatory drawing of Example 1 of this invention. It is explanatory drawing of Example 2 of this invention. It is explanatory drawing of Example 3 of this invention. It is explanatory drawing of Example 4 of this invention. It is principal part explanatory drawing of a prior art example.

  The maximum / minimum voltage detection circuit of the present invention applies a voltage to be measured to one input terminal, and applies a voltage input to a control processing unit for detecting and processing the maximum voltage or minimum voltage to the other input terminal. Switching control is performed so that a plurality of operational amplifiers for comparison output and either a forward polarity diode or a reverse polarity diode are selectively connected between the output terminals of these operational amplifiers and the control processing unit. It has a configuration to do.

  FIG. 1 is an explanatory diagram of Embodiment 1 of the present invention. OPA1 to OPAn are operational amplifiers, D11 to Dn1 and D12 to Dn2 are diodes, SW11 to SW1n and SW12 to SWn2 are selection switches, and V1 to Vn are comparison targets. The measurement voltage CONT is a control processing unit that performs detection / selection control of the maximum voltage value Vmax or the minimum voltage value Vmin as indicated by (Vmax / Vmin), and cont1 and cont2 indicate control signals for the selection switches. The selection switches SW11 to SW1n and SW12 to SWn2 can be configured by semiconductor switch elements such as transistors. When detecting the maximum value among the comparative measured voltages V1 to Vn, the selection switches SW11 to SWn1 are turned off by the control signal cont1 from the control processing unit CONT, and the selection switches SW12 to SWn2 are turned on by the control signal cont2. For example, when the magnitude relationship of the measured voltages V1 to Vn is V1 <V2 and V2> V3,...> Vn, the output voltage V2 of the operational amplifier OPA2 is set to the other operational amplifiers OPA1, OPA3. The voltage is applied to the diodes D12, D32 to Dn2 connected to the output terminals of the OPAn to be in a reverse bias state, and the voltage V2 from the operational amplifier OPA2 is input to the control processing unit CONT. Can be detected as When the voltage Vn is the maximum voltage, the voltage Vn is input from the operational amplifier OPAn to the control processing unit CONT via the diode Dn2 and the switch SWn2, and the other diodes D12 to D (n-1) 2 are reverse biased. Thus, the voltage Vn can be detected as the maximum voltage.

  When the minimum value is detected, the selection switches SW11 to SWn1 are turned on by the control signal cont1 from the control processing unit CONT, and the selection switches SW12 to SWn2 are turned off by the control signal cont2. For example, when the magnitude relationship of the comparative measured voltages V1 to Vn is V1> V2 and V2 <V3,... <Vn, the output voltage V2 of the operational amplifier OPA2 is equal to the other operational amplifiers OPA1, OPA3. It is applied to the diodes D12, D32 to Dn2 connected to the output terminals of OPAn to enter reverse bias states, and the voltage V2 from the operational amplifier OPA2 is input to the control processing unit CONT, so that the minimum voltage detection is performed. It can be performed. Accordingly, the maximum value detection and the minimum value detection can be easily switched by merely controlling one of the selection switches SW11 to SWn1 and the selection switches SW12 to SWn2 to be turned off and the other to be turned off.

  If both the selection switches corresponding to the operational amplifier are turned off, the detection of the maximum value or the minimum value by the operational amplifier can be put into a pause state. In other words, it is possible to perform selective pause control of detection action as well as control of selective switching of maximum value detection or minimum value detection. Further, the on / off control of the selection switches SW11 to SWn1 and SW21 to SWn2 can be configured to be selectively controlled by a control means other than the control processing unit CONT that detects the voltage of the maximum value or the minimum value. . The diodes D11 to Dn1 and D12 to Dn2 are connected in series to the operational amplifiers OPA1 to OPAn, respectively. The switches SW11 to SWn1 are connected in series and selectively short-circuit each diode. , SW21 to SWn2, and when the maximum value is detected, the switch is controlled to short-circuit the diodes D11 to Dn1, and when the minimum value is detected, the switch is controlled to short-circuit the diodes D12 to Dn2. It is also possible to do.

  FIG. 2 is an explanatory diagram of Embodiment 2 of the present invention, where the same reference numerals as those in FIG. 1 denote the same names, and FET 11 to FET n1 and FET 12 to FET n2 denote field effect transistors. The field effect transistor has a configuration including a parasitic diode formed by a semiconductor pn junction region, and is illustrated as a diode connected between a source and a drain. Two field effect transistors (hereinafter abbreviated as “FET”) are connected in series to the output terminals of the operational amplifiers OPA1 to OPAn so that the forward polarities of the parasitic diodes are reversed. When the FETs 11 to FETn1 are turned on by the control signal cont1 from the control processing unit CONT and the FETs 12 to FETn2 are turned off by the control signal cont2, diodes having forward polarity in the direction of the control processing unit CONT are connected to the output terminals of the operational amplifiers OPA1 to OPAn. Is equivalent to the case where the selection switches SW12 to SWn2 in FIG. 1 are turned on, and only the output of the operational amplifier to which the maximum values of the comparative measured voltages V1 to Vn are input is controlled. Input to the processing unit CONT, the control processing unit CONT can process the maximum voltage among the comparative measurement voltages V1 to Vn.

  When FET11 to FETn1 are turned off by the control signal cont1 from the control processing unit CONT and FET12 to FETn2 are turned on by the control signal cont2, the output terminals of the respective operational amplifiers OPA1 to OPAn are connected in the reverse polarity to the control processing unit CONT. This is a configuration in which a diode is connected, which corresponds to the case where the selection switches SW11 to SWn1 in FIG. 1 are turned on, and can detect the minimum value of the voltage to be measured. In this case as well, if two FETs connected in series corresponding to the operational amplifier are both turned off, the operational amplifier corresponds to a case where the detection operation of the maximum value or the minimum value is stopped. The control signals cont1 and cont2 can be applied to the gates of the FETs 11 to FETn1 and FET12 to FETn2 from control means other than the control processing unit CONT. The control signals cont1 and cont2 can be applied by a manually operated switch or the like. It is also possible to apply to the gates of FET11 to FETn1, FET12 to FETn2.

  FIG. 3 is an explanatory diagram of Embodiment 3 of the present invention, where the same reference numerals as those in FIG. 1 and FIG. 2 indicate the same names, and photo MOSFETs (PM11 to PMn1, PM12 to PMn2) are used. This photo MOSFET is configured in series so that the polarities of the light emitting diode and the parasitic diodes of the two MOSFETs that are turned on when light from the light emitting diode is incident on the base region are opposite to each other, The case where it has the structure which can perform the switching process with respect to alternating current is shown. In Example 3, only one of the two FETs of each photoMOSFET is used. For example, PM11 and PM12 of the photoMOSFET are respectively similar to the case shown in FIG. Are connected so that their parasitic diodes have opposite polarities. The other photoMOSFETs have the same connection configuration. Therefore, each photo MOSFET (PM11 to PMn1, PM12 to PMn2) can be configured to include a light emitting diode and one MOSFET.

  When detecting the maximum value of the comparative measured voltage, the light emitting diodes of one of the photo MOSFETs (PM11 to PMn1) are turned off, and each parasitic diode is connected to the control processing unit CONT in the forward direction. The light emitting diodes of the photo MOSFETs (PM12 to PMn2) are turned on, and the parasitic diodes are shorted. This corresponds to the state in which FET11 to FETn1 in FIG. 2 are turned on and FET12 to FETn2 are turned off. When detecting the minimum value, the light-emitting diode of one photo MOSFET (PM11 to PMn1) is turned on, the parasitic diode is short-circuited, and the other light-emitting diode of the photo MOSFET (PM12 to PMn2) is turned off. The parasitic diode is connected to the operational amplifiers OPA1 to OPAn in the reverse polarity. This corresponds to the state in which FET11 to FETn1 in FIG. 2 are turned off and FET12 to FETn2 are turned on.

  FIG. 4 is an explanatory diagram of Embodiment 4 of the present invention. The same reference numerals as those in FIGS. 1 to 3 indicate the same parts, DA indicates a differential amplifier, and BAT indicates a battery. A case where the maximum value or the minimum value of the voltage of each unit battery at the time of charging or discharging of the battery BAT connected in series is detected will be described with reference to the case where the embodiment 1 shown in FIG. 1 is applied. The differential amplifier DA can be applied to the configuration shown below. The voltage at both ends of the unit battery is input, output as the voltage of each unit battery, and input to the operational amplifiers OPA1 to OPAn, When the maximum value is detected, the switches SW11 to SWn1 are turned off by the control signal cont1, and the switches SW12 to SWn2 are turned on by the control signal cont2. For example, when charging the battery BAT, when the voltage of any unit battery reaches the maximum allowable charge voltage, the control processing unit CONT controls the charge / discharge control unit (not shown) to stop charging. it can. When the minimum value is detected, the switches SW11 to n1 are turned on by the control signal cont1, and the switches SW12 to SWn2 are turned off by the control signal cont2. As a result, a minimum value detection state is established, and when the voltage of any unit battery reaches the discharge allowable voltage, the control processing unit CONT can control the charge / discharge control unit (not shown) to stop the discharge. .

  The switching configuration of the diodes D11 to Dn1, D12 to Dn2 and the switches SW11 to SWn1, SW12 to SWn2 in the fourth embodiment is replaced with the field effect transistors FET11 to FETn1, FET12 to FETn2 of the second embodiment shown in FIG. The configuration may be replaced with the photo MOSFETs (PM11 to PMn1, PM12 to PMn2) of the third embodiment shown in FIG. The battery BAT can be configured as a series-connected electric double layer capacitor that detects the maximum value of the charging voltage or the minimum value of the discharging voltage corresponding to the unit capacitor in charging and discharging. In these configurations, using a basic configuration including operational amplifiers OPA1 to OPAn, the switches SW11 to SWn1, SW12 to SWn2 in FIG. 1 or the field effect transistors FET11 to FETn1, FET12 to FETn2 in FIG. Either maximum value detection or minimum value detection can be performed by switching control using the photo MOSFETs (PM11 to PMn1, PM12 to PMn2) in FIG.

OPA1 to OPAn Operational Amplifier D11 to Dn1, D12 to Dn2 Diode SW11 to SW1n, SW12 to SWn2 Selection Switch V1 to Vn Comparative Voltage to be Measured CONT Control Processing Unit cont1, cont2 Selection Switch Control Signals FET11 to FETn1, FET12 to FETn2 Field Effect Transistors PM11 to PMn1, PM12 to PMn2 Photo MOSFET
DA differential amplifier BAT battery

Claims (4)

In the maximum / minimum voltage detection circuit that detects the maximum or minimum value of multiple measured voltages,
A plurality of operational amplifiers each applying the voltage to be measured to one input terminal, and applying a voltage input to the control processing unit for detecting and processing the maximum voltage or the minimum voltage to the other input terminal for comparison output; A switch for performing switching control so as to selectively connect either a forward polarity diode or a reverse polarity diode between the output terminals of a plurality of operational amplifiers and the control processing unit; Maximum / minimum voltage detection circuit. In the maximum / minimum voltage detection circuit that detects the maximum or minimum value of multiple measured voltages,
A plurality of operational amplifiers each applying the voltage to be measured to one input terminal, and applying a voltage input to the control processing unit for detecting and processing the maximum voltage or the minimum voltage to the other input terminal for comparison output; Between the output terminals of a plurality of operational amplifiers and the control processing unit, each parasitic diode is connected in series so as to have a reverse polarity, and either one is turned on depending on whether maximum value detection or minimum value detection, A maximum / minimum detection circuit comprising: a field effect transistor that controls the other to be turned off. In the maximum / minimum voltage detection circuit that detects the maximum or minimum value of multiple measured voltages,
A plurality of operational amplifiers each applying the voltage to be measured to one input terminal, and applying a voltage input to the control processing unit for detecting and processing the maximum voltage or the minimum voltage to the other input terminal for comparison output; Between the output terminals of a plurality of operational amplifiers and the control processing unit, each parasitic diode is connected in series so as to have a reverse polarity, and either one is turned on depending on whether maximum value detection or minimum value detection, A maximum / minimum detection circuit comprising a photo-MOS field effect transistor that controls the other to be turned off.   A plurality of differential amplifiers that respectively input terminal voltages of a plurality of series-connected batteries or capacitors, and a configuration in which an output voltage of the differential amplifier is input to the operational amplifier as the measured voltage, respectively. The maximum / minimum detection circuit according to any one of claims 1 to 3.

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