JP2011077409A - Method for manufacturing semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method of manufacturing a semiconductor device, which decreases dependence of temperature of a semiconductor substrate on a pattern density, in heat-processing the semiconductor substrate where multiple patterns with different pattern densities exist. <P>SOLUTION: The method includes: a step of forming a first region having a first pattern density on the semiconductor substrate 1, and a second region having a second pattern density that is smaller than the first pattern density; a step of forming a light transmission film that is composed of a silicon oxide film and silicon nitride film on the first region; and a step of irradiating the semiconductor substrate 1 with light through the light transmission film. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device having a plurality of types of patterns having different pattern densities.

  As devices are miniaturized due to high integration of LSIs, the importance of forming shallow diffusion layer regions with low resistance is increasing. For example, a method of performing heat treatment for impurity activation of diffusion layers by flash lamp annealing is used. Yes.

  In addition, when a region with a high pattern density such as a memory cell portion and a region with a low pattern density such as a logic circuit exist on the same semiconductor substrate, the light absorption rate of the semiconductor substrate during the activation heat treatment is the pattern density. Greatly influenced by. As the pattern width and pattern interval are narrower and the pattern density is larger, the light reflectance of the flash lamp is reduced, the heating efficiency is improved, and the temperature of the semiconductor substrate is increased.

  The pattern density dependency of the heating efficiency is remarkable in the case of a short-time heat treatment such as flash lamp annealing, but is not limited to the flash lamp annealing, for example, in the case of lamp annealing with a heating time of about 1 second. Also happens. In order to reduce the pattern density dependency of the heating efficiency, a method of performing a heat treatment after forming a light transmission film on the pattern is known (for example, Patent Document 1).

JP 2006-278532 A

  The present invention has been made to solve the above-described problems, and in particular, in the heat treatment when a plurality of types of patterns having different pattern densities exist on the same semiconductor substrate, the dependence of the semiconductor substrate temperature on the pattern density. An object of the present invention is to provide a method for manufacturing a semiconductor device capable of reducing the above.

  A method for manufacturing a semiconductor device according to one embodiment of the present invention includes: a first region having a first pattern density on a semiconductor substrate; and a second pattern having a second pattern density lower than the first pattern density. And forming a light transmission film on the first region, and irradiating the semiconductor substrate with light through the light transmission film.

  According to the present invention, there is provided a semiconductor device manufacturing method capable of reducing the pattern density dependency of the temperature of a semiconductor substrate in a heat treatment when a plurality of types of patterns having different pattern densities exist on the same semiconductor substrate. Can be provided.

Sectional drawing which shows the manufacturing method of the semiconductor device which concerns on Example 1 of this invention. Sectional drawing which shows the manufacturing method of the semiconductor device which concerns on Example 1 of this invention. Sectional drawing which shows the manufacturing method of the semiconductor device which concerns on Example 1 of this invention. Sectional drawing which shows the manufacturing method of the semiconductor device which concerns on Example 1 of this invention. Sectional drawing which shows the manufacturing method of the semiconductor device which concerns on Example 1 of this invention. Sectional drawing which shows the manufacturing method of the semiconductor device which concerns on Example 1 of this invention. The characteristic view which shows the light absorption rate of the semiconductor substrate which concerns on Example 1 of this invention. Sectional drawing which shows the manufacturing method of the semiconductor device which concerns on Example 2 of this invention.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

  A method for manufacturing a semiconductor device according to the embodiment will be described using the semiconductor device of FIG. 1 as an example.

  FIG. 1 is a cross-sectional view schematically showing a semiconductor device, which includes a memory cell portion that is a first region A1 and a logic circuit portion that is a second region A2. The memory cell portion that is the first region has a first pattern density, and the logic circuit portion that is the second region has a second pattern density that is lower than the first pattern density. That is, the memory cell portion has a higher pattern density than the logic circuit portion.

  Each of the memory cell portion and the logic circuit portion is formed by repeating a certain pattern, and the pattern density is the number of repeated patterns per unit area.

  The memory cell portion and the logic circuit portion have a gate insulating film 2 made of a silicon oxide film on the semiconductor substrate 1 and a gate electrode 3 made of a polycrystalline silicon film. Further, a sidewall insulating film 4 having a laminated structure of a silicon oxide film and a silicon nitride film and a diffusion layer 5 exist in the semiconductor substrate 1 on the side surfaces of the gate insulating film 2 and the gate electrode 3.

  Hereinafter, with reference to FIGS. 2 to 6, a method of manufacturing the semiconductor device according to this example will be described. As shown in FIG. 2, for example, a silicon oxide film to be the gate insulating film 2 and a polycrystalline silicon film to be the gate electrode 3 are formed on the semiconductor substrate 1. Subsequently, the gate electrode 3 and the gate insulating film 2 are processed. At this time, the memory cell portion is processed so that the pattern density is higher than that of the logic circuit portion.

  Further, as shown in FIG. 3, a sidewall insulating film 4 made of a silicon oxide film and a silicon nitride film is formed on the sidewalls of the gate insulating film 2 and the gate electrode 3. Subsequently, conductive impurities are ion-implanted into the semiconductor substrate 1 using the sidewall insulating film 4 as a mask to form a diffusion layer 5.

  As shown in FIG. 4, after a silicon oxide film 6 having a film thickness of, for example, 100 nm to 150 nm is formed on the entire surface of the semiconductor substrate 1 by the ALD method, the silicon oxide film 6 in the logic circuit portion is peeled off. Further, a silicon oxide film 7 having a thickness of 10 nm is formed on the entire surface of the semiconductor substrate 1 by the ALD method.

  Next, as shown in FIG. 5, a 60 nm-thickness silicon nitride film 8 is formed on the entire surface of the semiconductor substrate 1 by plasma CVD. This silicon nitride film 8 is used as SMT (Stress Memory Technique) which is a kind of process induced strain technology.

  Subsequently, as shown in FIG. 6, heat treatment is performed for defect recovery of the semiconductor substrate 1 by ion implantation and activation of the ion implantation element. For example, after performing lamp annealing for 1 second at a temperature of 1000 ° C. to 1050 ° C. using a lamp installed above the semiconductor substrate 1, flash lamp annealing is performed for 1 millisecond at a temperature of 1200 ° C. to 1300 ° C. Do. Lamp annealing is performed mainly for the purpose of recovering defects, and flash lamp annealing is mainly used for the purpose of activating the ion-implanted element, but either one may be used, or after performing flash lamp annealing first, Annealing may be performed.

  Further, the silicon nitride film 8, the silicon oxide film 7 and the silicon oxide film 6 are peeled to obtain a structure as shown in FIG. Thereafter, an interlayer film and wiring are formed by a known method to complete the semiconductor device.

  In this embodiment, when the heat treatment of FIG. 6 is performed, the silicon oxide film 6, the silicon oxide film 7 and the silicon nitride film 8 are present in the memory cell portion having a high pattern density, and the logic circuit portion having a low pattern density is present. A silicon oxide film 7 and a silicon nitride film 8 are present. That is, the silicon oxide film 6 having a thickness of 100 nm to 150 nm and the silicon oxide film 7 having a thickness of 10 nm exist in the memory cell portion, and the silicon oxide film present in the logic circuit portion is the silicon oxide film 7 having a thickness of 10 nm. Only.

  Therefore, when heat treatment is performed, the memory cell portion is irradiated with light on the surface of the semiconductor substrate 1 through the light transmission film made of the silicon oxide film 6, the silicon oxide film 7, and the silicon nitride film. On the other hand, the logic circuit unit irradiates the surface of the semiconductor substrate 1 with light through a light transmission film composed of the silicon oxide film 7 and the silicon nitride film 8.

  The light absorption rate of the semiconductor substrate 1 in the memory cell portion can be reduced by making the light transmission film in the memory cell portion have a laminated structure of a silicon oxide film and a silicon nitride film having a large film thickness. That is, the pattern density dependence of the semiconductor substrate temperature during the heat treatment can be reduced. The reason is as follows.

  FIG. 7 is a graph showing how the light absorption rate of the semiconductor substrate during the thermal process changes depending on the type and thickness of the film present on the semiconductor substrate. The solid line in FIG. 7 shows the optical absorptance when only the silicon nitride film is formed on the semiconductor substrate and the film thickness of the silicon nitride film is changed, and the broken line shows the silicon oxide film having a thickness of 300 nm on the semiconductor substrate. The light absorptance is shown when a film is formed and the thickness of the silicon nitride film formed on the silicon oxide film is changed.

  That is, the solid line corresponds to the case where the semiconductor substrate is irradiated with light through the silicon nitride film, and the broken line corresponds to the case where the semiconductor substrate is irradiated with light through the silicon oxide film and the silicon nitride film. The two types of samples were subjected to flash lamp annealing with an irradiation time of 2 milliseconds, and the light absorption rate of the semiconductor substrate at that time was obtained by calculation. The horizontal axis represents the thickness of the silicon nitride film, and the vertical axis represents the light absorption rate of the semiconductor substrate. The light absorptance indicates the ratio of the light intensity absorbed by the semiconductor substrate to the light intensity applied to the entire semiconductor device.

  FIG. 7 shows that the light absorptance is lower when the silicon oxide film and the silicon nitride film are present on the semiconductor substrate than when only the silicon nitride film is present on the semiconductor substrate. Further, when the thickness of the silicon nitride film is 40 nm to 90 nm, the effect of reducing the absorption rate is great. This indicates that the temperature rise of the semiconductor substrate can be suppressed.

  Furthermore, although FIG. 7 shows the case where the film thickness of the silicon oxide film is 300 nm, it was found that the same light absorption rate is exhibited when the film thickness of the silicon oxide film is 100 nm to 500 nm. When the thickness of the silicon oxide film was less than 100 nm, the light absorptance indicated by the solid line in which only the silicon nitride film was formed was shown. This is presumably because when the silicon oxide film is thin, light refraction hardly occurs and the light directly reaches the semiconductor substrate.

  As described above, the temperature of the semiconductor substrate during the thermal process is formed by forming the light transmission film made of the silicon oxide film having a film thickness of 100 nm to 500 nm and the silicon nitride film having a film thickness of 40 nm to 90 nm in the memory cell portion having a large pattern density. The rise can be suppressed. Therefore, it is possible to reduce the dependency of the semiconductor substrate temperature on the pattern density.

  In this embodiment, the memory cell portion is a region having a high pattern density, and the logic circuit portion is a region having a low pattern density, but the present invention is not limited thereto, and there are regions having different pattern densities on the same semiconductor substrate. It suffices if there is a step of performing heat treatment on the semiconductor substrate.

  With reference to FIG. 8, a method for manufacturing a semiconductor device according to the second embodiment will be described.

  In the second embodiment, the heat treatment method in FIG. 6 is different from the first embodiment. In the first embodiment, the heat treatment is performed using the lamp existing above the semiconductor substrate 1. In the second embodiment, the heat treatment is performed using the lamp existing below the semiconductor substrate 1.

  As shown in FIG. 8, first, a first heat treatment is performed from the surface side of the semiconductor substrate 1 by flash lamp annealing at a temperature of 1200 to 1300 degrees for 1 millisecond. Thereafter, a second heat treatment is performed from the back side of the semiconductor substrate 1 by lamp annealing for 1 second at a temperature of 1000 to 1050 degrees. By performing heating by lamp annealing from the back side, the light absorption rate is low in the memory cell portion having the light transmissive film made of the silicon oxide film and the silicon nitride film having a large film thickness, and heat dissipation proceeds. Therefore, the temperature rise in the memory cell portion can be suppressed.

  In addition, when heating by flash lamp annealing is performed from the back surface side of the semiconductor substrate 1, the heating time is short and heat is not transmitted to the front surface side of the semiconductor substrate 1. Therefore, heating by flash lamp annealing is performed from the surface side of the semiconductor substrate 1.

  As in the first embodiment, the heat treatment may be performed using only lamp annealing. Furthermore, heating by lamp annealing may be performed first from the back surface side of the semiconductor substrate 1, and then heating by flash lamp annealing may be performed from the front surface side of the semiconductor substrate 1. However, it is preferable to perform the heating by flash lamp annealing first because the heat radiation effect at the next lamp annealing is large.

  The present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the spirit of the present invention.

DESCRIPTION OF SYMBOLS 1 ... Semiconductor substrate 2 ... Gate insulating film 3 ... Gate electrode 4 ... Side wall insulating film 5 ... Diffusion layer 6 ... Silicon oxide film 7 ... Silicon oxide film 8 ... Silicon nitride film A1... First region A2... Second region

Claims (5)

Forming a first region having a first pattern density and a second region having a second pattern density lower than the first pattern density on a semiconductor substrate;
Forming a light transmission film on the first region;
Irradiating the semiconductor substrate with light through the light transmission film;
A method for manufacturing a semiconductor device, comprising: 2. The method of manufacturing a semiconductor device according to claim 1, wherein the light transmission film includes a silicon oxide film and a silicon nitride film.   2. The method of manufacturing a semiconductor device according to claim 1, wherein the first region is a memory cell portion, and the second region is a logic circuit portion.   2. The method of manufacturing a semiconductor device according to claim 1, wherein the step of irradiating the light is performed by either flash lamp annealing or lamp annealing.   The method of manufacturing a semiconductor device according to claim 1, wherein the step of irradiating includes a step of performing from the back side of the semiconductor substrate.

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