JP2011076583A - Power integrity analysis device, method and program - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a power integrity analysis device which can analyze a PDN including a complicated shape of a notch or the like at high speed. <P>SOLUTION: The power integrity analysis device 1 includes: a structure information inputting part 10 for inputting structure information showing the shapes of a power supply layer and a ground layer included in a circuit board of a multilayer structure and their arrangement; a unit cell defining part 11 for dividing the power supply layer and the ground layer into the shape of a grid and defining a three-dimensional area sandwiched by two facing unit surfaces as a unit cell; an equivalent circuit generating part 13 for applying a basic configuration of a unit cell equivalent circuit to each unit cell, determining the values of a ground capacitor and an inductor constituting an equivalent circuit of each unit cell to generate the equivalent circuit of each unit cell on the basis of the size of a unit surface of each unit cell and a distance between unit surfaces, and subsequently connecting equivalent circuits of unit cells adjacent to each other to generate the entire equivalent circuit; and a power integrity calculating part 14 for calculating, when voltage is applied to a prescribed position, a voltage value that is generated at another position. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to an apparatus and method for analyzing power integrity of a circuit board, and a program executable by a computer.

  As semiconductor devices become faster and lower in voltage, it is important to ensure power integrity at the package and board level in which they are mounted. In the detailed power integrity verification, it is necessary to perform a detailed circuit simulation in consideration of a three-dimensional layout of a power distribution network (PDN) in the mounting substrate. When the power / ground layer in the mounting substrate is a unit cell that is regarded as a parallel plate plane, the PDN can be modeled as a simple RLC network using the unit unit cell (see, for example, Non-Patent Document 5).

  FIG. 13 shows a circuit board to be analyzed. A power supply conductor layer (hereinafter referred to as a power supply layer) P and a ground conductor layer (hereinafter referred to as a ground layer) made of ideal parallel flat plates are provided above and below the dielectric substrate 73. FIG. 4 is a perspective view showing a structure example of a circuit board on which G is bonded and a structure of a basic cell 70 in the circuit board. When analyzing the power integrity of the circuit board, as shown in FIG. 13, the circuit board is divided into M × N unit unit cells, and an equivalent circuit model is obtained for each unit unit cell. It has been reported that the RLC network modeled in this way can perform transient analysis efficiently by using an algorithm represented by LIM (Latency Insertion Method; hereinafter referred to as LIM). For example, refer nonpatent literature 2-3.)

JP 2007-066575. Japanese Patent Application Laid-Open No. 2008-177384.

L. D. Smith et al., “Power Plane SPICE Models and Simulated Performance for Materials and Geometries”, IEEE Transactions on Advanced Packaging, Vol. 24, No. 3, pp.277-287, August 2001. J. E. Schutt-Aine, “Latency Insertion Method (LIM) for the Fast Transient Simulation of Large Networks,” IEEE Trans, on Circuits and Systems ”, Vol. 48, No. 1, pp. 81-89, Jan. 2001. Z. Deng et al., “Stability analysis of latency insertion method (LIM)”, in Proceedings of IEEE Topical Meeting on Electrical Performance of Electronic Packaging (EPEP) 2004, pp. 167-170, 2004. T. Watanabe et al., “Parallel-Distributed Time-Domain Circuit Simulation of Power Distribution Networks with Frequency-Dependent Parameters”, in Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC) 2006, January 2006. T. Watanabe et al., “Fast Transient Simulation of Power Distribution Networks Containing Dispersion Based on Parallel-Distributed Leapfrog Algorithm”, IEICE Transactions on Fundamentals of Electronics, Communications, Vol. E90-A, No. 2, pp.388-397 , February 2007. E. Engin et al., “Multilayered finite-difference method (MFDM) for modeling of package and printed circuit board planes”, IEEE Transactions on EMC, Vol. 27, No. 2. 2007. K. Bharath et al., “Signal and Power Integrity Co-Simulation for Multi-layered System on Package Modules”, in Proceedings of IEEE International Symposium on Electromagnetic Compatibility 2007, pp. 1-6, July 2007. Synopsys Corporation, “HSPICE Simulation and Analysis User Guide”, pp.312, June 2006. Yuichi Tanji et al., “Implementation of Linear Circuit Simulator FALCON on Multicore CPU”, IEICE Technical Report, Nonlinear Problem Study Group, NLP2009-58, pp. 77-81, August 2009. K. Kundert, “SPARSE 1.4”, Internet URL: http://sparse.sourceforge.net/, as published in January 2010. E. A. Ege et al., “Multilayered finite difference method (MFDM) for modeling of package and printed circuit board planes”, IEEE Trans. On EMC, Vol.27, No.2, 2007. Takayuki Watanabe, “A Study on Equivalent Circuit Representation of Three-Dimensional Structure and Its Circuit Simulation”, IEICE Technical Report, Nonlinear Problem Study Group, NLP2007-102, pp. 39-44, November 2007.

  However, in a power supply / ground layer on an actual mounting substrate, there are a large number of notches, holes, and slits, and it is difficult to regard it as an ideal parallel plate. As a PDN modeling method including such a complicated shape, a multilayered finite-difference method (hereinafter referred to as M-FDM) has been proposed (for example, see Non-Patent Document 11).

  On the other hand, the circuit structure to which LIM can be applied has a restriction that a ground capacitor must be included in all nodes and an inductor must be included in all branches. An equivalent circuit modeled by M-FDM has this restriction. Does not match.

  An object of the present invention is to solve the above problems and provide a power integrity analysis apparatus and method capable of analyzing a PDN including a complicated shape such as a notch at high speed, and a program executable by a computer. is there.

The power integrity analyzer according to the first invention is:
A structure information input unit for inputting structure information indicating the shape and arrangement of the power supply layer and the ground layer of the circuit board having a multilayer structure including at least one power supply layer and at least one ground layer;
The power supply layer and the ground layer are divided into a lattice shape, and the unit surface of the power supply layer or the ground layer facing each divided unit surface is obtained based on the structure information, and sandwiched between the two unit surfaces facing each other. A unit cell delimiting unit that demarcates a three-dimensional region as a unit cell and obtains a positional relationship between the unit cells;
A basic configuration of a unit cell equivalent circuit expressing the electrical characteristics of the unit cell, a storage unit storing a unit cell equivalent circuit in which a ground capacitor is connected to all nodes and an inductor is connected between all nodes;
The basic configuration of the unit cell equivalent circuit stored in the storage unit is applied to each unit cell defined by the unit cell defining unit, and the unit plane size and unit plane between the unit cells And determining the values of the grounding capacitor and the inductor constituting the equivalent circuit of each unit cell based on the distance of the unit cell to generate the equivalent circuit of each unit cell, and then connecting the equivalent circuits of the unit cells adjacent to each other. Thus, an equivalent circuit generation unit that generates an equivalent circuit of the entire circuit board,
In a power integrity analysis apparatus comprising a power integrity calculation unit that calculates and outputs a voltage value generated at another position of the circuit board when a voltage is applied to a predetermined position of the circuit board.
The equivalent circuit generator is
When there is a position where the thickness between the power supply layer and the ground layer of the circuit board or the thickness between the power supply layer and another power supply layer changes, the node where the thickness changes is Applying the basic configuration of the unit cell equivalent circuit stored in the storage unit so as to correspond to the nodes connecting the basic cells, an equivalent circuit of the entire circuit board is generated,
The thickness between the power supply layer and the ground layer of the circuit board, or the thickness between the power supply layer and another power supply layer is a second thickness that is larger than the first thickness from the first thickness. When there is a position where the thickness changes, at the node where the thickness changes, the equivalent circuit is divided into a plurality of adjacent sub-equivalent circuits and separated. In addition, a current control current source for supplying a current equivalent to the current flowing from the node of the basic cell is added, while a voltage equivalent to the voltage applied to the node of the basic cell is applied to the basic cell of the other sub-equivalent circuit. By adding a voltage control voltage source to be applied, a plurality of sub-equivalent circuits adjacent to each other are related to generate an equivalent circuit of the circuit board.

  In the power integrity analysis apparatus, the equivalent circuit generation unit is configured such that a thickness between the power supply layer and the ground layer of the circuit board or a thickness between the power supply layer and another power supply layer is a first thickness. From the above, when there is a position where the thickness changes to a second thickness larger than the first thickness, it is assumed that the power supply layer is present in the second thickness portion and the thickness does not change. Assuming that the current flowing in the power layer of the first thickness is assumed to be branched into the current flowing from the power layer to the ground layer and the assumed current. The current control current source and the voltage control voltage source are added.

  In the power integrity analysis apparatus, the equivalent circuit generation unit may have a thickness between the power supply layer and the ground layer of the circuit board or a thickness between the power supply layer and another power supply layer. When there is a position where the thickness changes from the thickness to the second thickness that is larger than the first thickness, the second thickness is substantially twice the thickness of the first thickness. When it is assumed that the power supply layer exists in the second thickness portion and the thickness does not change, and is divided into two sub-equivalent circuits each having the first thickness, The current-controlled current source and the voltage-controlled voltage source are added under the condition that two magnetic fields parallel to the surface of the circuit board in the equivalent circuit substantially match the magnetic field when not divided. It is characterized by.

Further, in the power integrity analysis apparatus, the equivalent circuit generation unit, when relating the unit cell equivalent circuits of the first unit cell and the second unit cell adjacent to each other, the unit cell of the first unit cell A current control current source that gives a current equivalent to a current flowing into a boundary with the first unit cell in the unit cell equivalent circuit of the second unit cell to the equivalent circuit;
A voltage control voltage source that applies a voltage equivalent to a voltage applied to a boundary with the second unit cell in the unit cell equivalent circuit of the first unit cell to the unit cell equivalent circuit of the second unit cell. It is characterized by adding.

  Still further, in the power integrity analyzer, the power integrity calculation unit, when a voltage is applied to a predetermined position of the circuit board, the current applied to each node of the equivalent circuit of the entire circuit board and each node. A voltage value generated at another position of the circuit board is calculated and output using a latency insertion method (LIM) that alternately calculates a value of a current flowing between them. .

  Still further, in the power integrity analyzer, the power integrity calculation unit, when a voltage is applied to a predetermined position of the circuit board, the current applied to each node of the equivalent circuit of the entire circuit board and each node. The above circuit board using a simulation program (Simulation Program with Integrated Circuit Emphasis; SPICE) which calculates the value of the current flowing between them by solving a simultaneous equation showing the relationship between each current and each voltage using a numerical integration method A voltage value generated at another position is calculated and output.

  Still further, in the power integrity analysis apparatus, the storage unit is a basic configuration of a unit cell equivalent circuit expressing the electrical characteristics of the unit cell, and a ground capacitor and a ground conductance are connected to all nodes, and between all the nodes. A unit cell equivalent circuit in which an inductor and a resistor are connected to each other is stored.

The power integrity analysis method according to the second invention is:
A power integrity analysis method for analyzing the power integrity of a multilayer circuit board including at least one power supply layer and at least one ground layer by a computer,
The computer has a basic configuration of a unit cell equivalent circuit expressing the electrical characteristics of the unit cell, and stores a unit cell equivalent circuit in which a ground capacitor is connected to all nodes and an inductor is connected between all nodes. Part
The above power integrity analysis method is
Inputting structural information indicating the shape and arrangement of the power supply layer and the ground layer of a multilayer circuit board including at least one power supply layer and at least one ground layer;
The power supply layer and the ground layer are divided into a lattice shape, and the unit surface of the power supply layer or the ground layer facing each divided unit surface is obtained based on the structure information, and sandwiched between the two unit surfaces facing each other. Defining a three-dimensional region as a unit cell and determining a positional relationship of each unit cell;
The basic configuration of the unit cell equivalent circuit stored in the storage unit is applied to each unit cell defined by the unit cell defining unit, and the unit plane size and unit plane between the unit cells And determining the values of the grounding capacitor and the inductor constituting the equivalent circuit of each unit cell based on the distance of the unit cell to generate the equivalent circuit of each unit cell, and then connecting the equivalent circuits of the unit cells adjacent to each other. A step of generating an equivalent circuit of the entire circuit board,
Calculating and outputting a voltage value generated at another position of the circuit board when a voltage is applied to a predetermined position of the circuit board.
The step of generating the equivalent circuit includes:
When there is a position where the thickness between the power supply layer and the ground layer of the circuit board or the thickness between the power supply layer and another power supply layer changes, the node where the thickness changes is Applying the basic configuration of the unit cell equivalent circuit stored in the storage unit so as to correspond to the nodes connecting the basic cells, an equivalent circuit of the entire circuit board is generated,
The thickness between the power supply layer and the ground layer of the circuit board, or the thickness between the power supply layer and another power supply layer is a second thickness that is larger than the first thickness from the first thickness. When there is a position where the thickness changes, at the node where the thickness changes, the equivalent circuit is divided into a plurality of adjacent sub-equivalent circuits and separated. In addition, a current control current source for supplying a current equivalent to the current flowing from the node of the basic cell is added, while a voltage equivalent to the voltage applied to the node of the basic cell is applied to the basic cell of the other sub-equivalent circuit. By adding a voltage control voltage source to be applied, a plurality of sub-equivalent circuits adjacent to each other are related to generate an equivalent circuit of the circuit board.

  In the power integrity analysis method, the step of generating the equivalent circuit includes a step in which a thickness between the power supply layer and the ground layer of the circuit board or a thickness between the power supply layer and another power supply layer is the first. Assuming that when there is a position where the thickness changes from the thickness to the second thickness larger than the first thickness, the power supply layer is present in the second thickness portion and the thickness does not change. And assuming that the current flowing through the first thickness power supply layer is branched from the power supply layer to the ground layer and the assumed current. And adding the current control current source and the voltage control voltage source.

  In the power integrity analysis method, the step of generating the equivalent circuit may be performed by determining whether the thickness between the power supply layer and the ground layer of the circuit board or the thickness between the power supply layer and another power supply layer is the first. When there is a position where the thickness changes from a thickness of 1 to a second thickness greater than the first thickness, the second thickness is substantially twice the thickness of the first thickness. When the power supply layer is present in the second thickness portion and the thickness does not change, and is assumed to be divided into two sub-equivalent circuits each having the first thickness, The current-controlled current source and the voltage-controlled voltage source are added under the condition that two magnetic fields parallel to the surface of the circuit board in each sub-equivalent circuit substantially match the magnetic field when not divided. It is characterized by doing.

Furthermore, in the above power integrity analysis method,
The step of generating the equivalent circuit includes:
When relating the unit cell equivalent circuit of the first unit cell and the second unit cell adjacent to each other, the unit cell equivalent circuit of the second unit cell is connected to the unit cell equivalent circuit of the first unit cell. Adding a current-controlled current source that gives a current equivalent to the current flowing into the boundary with the first unit cell;
A voltage control voltage source that applies a voltage equivalent to a voltage applied to a boundary with the second unit cell in the unit cell equivalent circuit of the first unit cell to the unit cell equivalent circuit of the second unit cell. It is characterized by adding.

Furthermore, in the power integrity analysis method,
In the step of calculating the power integrity, when a voltage is applied to a predetermined position of the circuit board, the current applied to each node of the equivalent circuit of the entire circuit board and the value of the current flowing between the nodes are calculated in time. The voltage value generated at the other position of the circuit board is calculated and output using a latency insertion method (LIM) that alternately calculates.

Furthermore, in the power integrity analysis method,
In the step of calculating the power integrity, when a voltage is applied to a predetermined position of the circuit board, the current applied to each node of the equivalent circuit of the entire circuit board and the value of the current flowing between the nodes are calculated. Voltage values generated at other positions on the circuit board using a simulation program (Simulation Program with Integrated Circuit Emphasis; SPICE) which is calculated by solving simultaneous equations indicating the relationship between each current and each voltage using a numerical integration method Is calculated and output.

Furthermore, in the power integrity analysis method,
The storage unit is a basic configuration of a unit cell equivalent circuit expressing the electrical characteristics of the unit cell, and a unit cell in which a ground capacitor and a ground conductance are connected to all nodes, and an inductor and a resistor are connected between all nodes. An equivalent circuit is stored.

  A program executable by a computer according to the third invention includes the steps of the power integrity analysis method.

  Therefore, according to the power integrity analysis apparatus, method, and program according to the present invention, an equivalent circuit of the entire circuit board in which the ground capacitors are connected to all the nodes and the inductor is connected between all the nodes is generated, Power integrity can be calculated at high speed using a circuit. In particular, the thickness between the power supply layer and the ground layer of the circuit board or the thickness between the power supply layer and another power supply layer is larger than the first thickness from the first thickness. When there is a position where the thickness changes, the equivalent circuit is divided into a plurality of adjacent sub-equivalent circuits at the node where the thickness changes, and the basic cell of one of the sub-equivalent circuits is separated. In contrast, a current control current source for supplying a current equivalent to the current flowing from the node of the basic cell is added to the basic cell of the other sub-equivalent circuit, and equivalent to the voltage applied to the node of the basic cell. By adding a voltage control voltage source for applying a voltage, a plurality of sub-equivalent circuits adjacent to each other can be related to generate an equivalent circuit of the circuit board. As a result, even if there is a notch or the like in the power supply layer, the power integrity of the circuit board can be calculated with higher accuracy and higher speed than in the conventional technique.

It is a block diagram which shows the structure of the power integrity analysis apparatus which concerns on the 1st Embodiment of this invention. (A) is a perspective view which shows the example which divided | segmented the power supply layer and ground layer of the circuit board to be analyzed into a grid | lattice form, (b) looked at the circuit board of the multilayered structure shown to (a) from the BB direction. FIG. (A) is a circuit diagram showing a basic configuration of an equivalent circuit 30 of a unit cell used in the power integrity analyzer of FIG. 1, and (b) is an equivalent circuit 30 formed by cascading two basic configurations of (a). FIG. 2C is a circuit diagram of an equivalent circuit 30-3 in which three basic configurations of FIG. It is a figure which shows the whole equivalent circuit (it consists of three subcircuits) when the equivalent circuit of a unit cell is applied with respect to the circuit board of FIG. FIG. 5 is a diagram illustrating an entire equivalent circuit in which unit cells adjacent to each other are related in FIG. 4. It is a figure which shows the hardware constitutions of the power integrity analysis apparatus of FIG. It is a flowchart which shows the power integrity analysis process performed by the power integrity analysis apparatus of FIG. FIG. 8 is a diagram illustrating an example of a calculation result of the power integrity process in FIG. 7, and is a waveform diagram illustrating an output voltage Vout with respect to an input voltage Vin. It is a circuit diagram which shows the equivalent circuit of the whole circuit board obtained by the power integrity process of FIG. It is a figure explaining the calculation conditions of the Example of FIG. 8, Comprising: It is a perspective view of a circuit board. FIG. 8 is a diagram illustrating an example of an analysis result of the power integrity process in FIG. 7, and is a waveform diagram illustrating an output voltage Vout with respect to an input voltage Vin. It is a circuit diagram which shows the whole equivalent circuit of another example of a circuit board obtained by the power integrity process of FIG. An example of a circuit board that is an analysis target circuit board in which a power supply layer 71 and a ground layer 72 made of ideal parallel plates are bonded to the upper and lower sides of a dielectric substrate 73, and the structure of a basic cell 70 therein. It is a perspective view shown. It is a circuit diagram which shows the three-dimensional equivalent circuit of the basic cell 70 of FIG. (A) is a circuit diagram which shows the circuit of the branch between two nodes at the time of circuit analysis using the latency insertion method (Latency Insertion Method; LIM), (b) is from the node of (a). It is a circuit diagram which shows an electric current outflow and a ground circuit. (A) is a longitudinal cross-sectional view of the multilayer circuit board to be analyzed, and (b) is a circuit diagram showing an equivalent circuit of the multilayer circuit board of (a). (A) is a perspective view showing the structure of a basic cell including three planes 81 (P1) to 83 (P3), and (b) is a multilayered finite-difference method (Multilayered finite-difference method); It is a circuit diagram showing an equivalent circuit of a basic cell according to M-FDM. It is a longitudinal cross-sectional view which shows an example of a circuit board when an intermediate | middle power supply layer also has a notch in the right half. It is a circuit diagram which shows the equivalent circuit of FIG. 18 produced using M-FDM based on a prior art. (A) is a circuit diagram which shows an example of the equivalent circuit created using M-FDM which concerns on a prior art, (b) is an example of the equivalent circuit created using the basic cell model which concerns on this embodiment. FIG. It is a circuit diagram which shows an example of the equivalent circuit created using the modified M-FDM. It is a circuit diagram which shows the equivalent circuit of FIG. 18 created using the basic cell model which concerns on this embodiment. It is a perspective view which shows the structure of the circuit board for defining the variable for connecting three subcircuits of FIG. It is a perspective view of Drawing 23A for explaining an assumption condition used when creating an equivalent circuit concerning this embodiment. It is a circuit diagram of the 1st example of the whole equivalent circuit created by the equivalent circuit creation method using the basic cell concerning this embodiment. It is a circuit diagram of the 2nd example of the whole equivalent circuit created by the equivalent circuit creation method using the basic cell concerning this embodiment. It is a perspective view which shows an example of the PDN circuit board of the analysis object by this embodiment. It is a wave form diagram which shows the input voltage Vin applied to the PDN circuit board of FIG. FIG. 27 is a waveform diagram showing an output voltage Vout obtained by each analysis method when an input voltage Vin is applied to the PDN circuit board of FIG. 26. FIG. 29 is a waveform diagram showing an output voltage Vout obtained by each analysis method when a 10-fold loss resistance is set when the input voltage Vin is applied to the PDN circuit board of FIG. . FIG. 30 is a waveform diagram showing an output voltage Vout obtained by each analysis method in the case of FIG. 29. FIG. 30 is a waveform diagram showing an output voltage Vout obtained by each analysis method in the case of FIG. 29. It is a table | surface which shows CPU time when HSPICE simulation is performed with respect to the equivalent circuit which concerns on a present Example. It is a table | surface which shows CPU time when simulating using the HSPICE simulator and the leapfrog simulator with respect to the equivalent circuit which concerns on a present Example. It is a circuit diagram which shows the method of adding a current control current source and a voltage control voltage source in the equivalent circuit which concerns on the 3rd Embodiment of this invention. (A) is a longitudinal cross-sectional view of the circuit board according to Example 1 of the third embodiment, (b) is a longitudinal cross-sectional view of the circuit board when divided and defined by the basic cell according to the embodiment, (C) is the circuit diagram of the equivalent circuit of the basic cell which concerns on this embodiment with respect to the circuit board of (b), and the whole equivalent circuit when the addition method of a current source and a voltage source is used. (A) is a longitudinal cross-sectional view of the circuit board according to Example 2 of the third embodiment, (b) is a longitudinal cross-sectional view of the circuit board when divided and defined by the basic cell according to the embodiment, (C) is the circuit diagram of the equivalent circuit of the basic cell which concerns on this embodiment with respect to the circuit board of (b), and the whole equivalent circuit when the addition method of a current source and a voltage source is used. (A) is a longitudinal cross-sectional view of the circuit board according to Example 3 of the third embodiment, (b) is a longitudinal cross-sectional view of the circuit board when divided and defined by the basic cell according to the embodiment, (C) is the circuit diagram of the equivalent circuit of the basic cell which concerns on this embodiment with respect to the circuit board of (b), and the whole equivalent circuit when the addition method of a current source and a voltage source is used. FIG. 37 is a circuit diagram showing an equivalent circuit when the equivalent circuit according to the second embodiment of FIG. 36 is analyzed using SPICE. It is a figure which shows the analysis result of FIG. 38, Comprising: It is a wave form diagram which shows the input voltage V1 and output voltage V11, V12. It is a circuit diagram which shows an equivalent circuit when analyzing the equivalent circuit which concerns on Example 3 of FIG. 37 using SPICE. It is a figure which shows the analysis result of FIG. 40, Comprising: It is a wave form diagram which shows the input voltage V1 and output voltage V11, V12.

  Hereinafter, a power integrity analysis apparatus and a power integrity analysis method according to embodiments of the present invention will be described. In addition, in each following embodiment, the same code | symbol is attached | subjected about the same component.

First embodiment.
FIG. 1 is a block diagram showing a configuration of a power integrity analysis apparatus 1 according to the first embodiment of the present invention. The power integrity analysis apparatus 1 according to the present embodiment includes a structure information input unit 10 that inputs structure information of a circuit board to be analyzed. In addition, the power integrity analysis apparatus 1 has a unit cell demarcation unit 11 and an equivalent circuit as a configuration for generating an equivalent circuit of the entire circuit board (hereinafter referred to as an entire equivalent circuit) based on the input structural information. And a generation unit 13. Furthermore, the power integrity analysis apparatus 1 includes a power integrity calculation unit 14 that calculates the power integrity of the circuit board based on the entire equivalent circuit, and a result output unit 15 that outputs the calculation result. Hereinafter, each configuration of the power integrity analysis apparatus 1 will be described.

  The structure information input unit 10 inputs information on the shape and arrangement of the power supply layer and the ground layer included in the circuit board as structure information. The circuit board includes at least one power supply layer and at least one ground layer. The information on the shape of the power supply layer and the ground layer is the coordinate information of notches and holes existing in the power supply layer and the ground layer. The information on the arrangement of the power supply layer and the ground layer is information indicating the distance between each layer of the power supply layer and the ground layer. When the thickness of each layer of the circuit board having a multilayer structure is determined, information indicating the number of power supply layers and ground layers may be used. For example, when the thickness of one layer is d [mm], if information indicating that the first layer, the seventh layer is a ground layer, and the fifth layer is a power supply layer is input, the ground layer (first layer) and the power supply are input. It can be seen that there are three wiring layers between the layer (fifth layer) and the distance can be determined as 3 × d [mm]. The power supply layer (fifth layer) and the ground layer (first layer) The distance from the seventh layer) can be determined to be d [mm].

  The unit cell demarcating unit 11 divides the power supply layer P and the ground layers G1 and G2 into a lattice shape. FIG. 2A is a perspective view showing an example in which the power supply layer P and the ground layers G1 and G2 of the circuit board to be analyzed are divided in a lattice shape. In the example shown in FIG. 2A, a circuit board having a three-layer structure of a ground layer G1, a power supply layer P, and a ground layer G2 is shown. The power supply layer P has a shape in which half is cut out. The unit cell demarcation unit 11 divides the ground layer G1, the power supply layer P, and the ground layer G2 into a lattice shape to form a unit surface. Next, the unit cell demarcation unit 11 obtains the unit surface of the opposing power supply layer P or ground layers G1 and G2 based on the structure information for each of the unit surfaces obtained by the division. Then, the unit cell demarcating unit 11 demarcates a three-dimensional region sandwiched between two opposing unit surfaces as unit cells 30 to 35, and obtains a positional relationship between the unit cells 30 to 35.

FIG. 2B is a side view of the multilayer circuit board shown in FIG. 2A as viewed from the BB direction. Based on the structure information shown in FIG. 2B, a unit surface facing each unit surface is obtained. In FIG. 2B, for example, the unit cells 30 to 36 are defined as follows.
(1) The unit surface 21 and the unit surface 25 face each other, and a three-dimensional region sandwiched between the unit surface 21 and the unit surface 25 is defined as a unit cell 30.
(2) The unit surface 22 and the unit surface 28 face each other, and a three-dimensional region sandwiched between the unit surface 22 and the unit surface 28 is defined as a unit cell 31.
(3) The unit surface 25 and the unit surface 27 face each other, and a three-dimensional region sandwiched between the unit surface 25 and the unit surface 27 is defined as a unit cell 32.
(4) The unit surface 23 and the unit surface 29 face each other, and a three-dimensional region sandwiched between the unit surface 23 and the unit surface 29 is defined as a unit cell 33.
(5) The unit surface 20 and the unit surface 24 face each other, and a three-dimensional region sandwiched between the unit surface 20 and the unit surface 24 is defined as a unit cell 34.
(6) The unit surface 24 and the unit surface 26 face each other, and a three-dimensional region sandwiched between the unit surface 24 and the unit surface 26 is defined as a unit cell 35.

  Here, for example, the unit surface 25 faces the unit surface 27 in addition to the unit surface 21. In a circuit board that operates at a high frequency, a skin effect occurs in which current flows on the surface of the power supply layer P or the ground layers G1 and G2. Therefore, the current flowing on the upper surface of the unit surface 25 and the current flowing on the lower surface do not affect each other, and the upper and lower unit cells 30 and 32 on the unit surface 25 can be handled as electrically independent unit cells. Thus, the unit cell demarcation unit 11 demarcates the unit cells 30 to 35 based on the structure information of the power supply layer P and the ground layers G1 and G2, and the size of each unit cell 30 to 35 (the size of the unit surface). In addition, the positional relationship between the unit cells is obtained and stored in the storage unit 16 together with information on the distance of the opposing surface).

  The equivalent circuit generation unit 12 generates an entire equivalent circuit using an equivalent circuit of the unit cell that represents the electrical characteristics of the unit cell defined by the unit cell defining unit 11. The storage unit 16 stores a basic configuration of a unit cell equivalent circuit.

  FIG. 3A is a circuit diagram showing a basic configuration of an equivalent circuit 30 of a unit cell used in the power integrity analyzer of FIG. As shown in FIG. 3A, the basic configuration of the equivalent circuit of the unit cell is that a ground capacitor (C / 2) and a ground conductance (G / 2) are connected to all nodes, and an inductor L and a resistor are connected between all nodes. R is connected. G = R = 0 may be set when there is substantially no loss or when loss is not considered. A calculation method for obtaining an equivalent circuit of a unit cell is described in detail in Non-Patent Document 12, for example. The basic configuration of the unit cell equivalent circuit shown in FIG. 3A is obtained according to the method described in Non-Patent Document 12.

  FIG. 3B is a circuit diagram of an equivalent circuit 30-2 in which two basic configurations of FIG. 3A are cascade-connected, and FIG. 3C is three basic configurations of FIG. It is a circuit diagram of the equivalent circuit 30-3 formed by cascade connection. As shown in FIG. 3 (b) and FIG. 3 (c), each ground capacitor (C / 2) and each two ground conductances (G / 2) which are adjacent to each other are connected in parallel to each other. C and one ground conductance G.

  The equivalent circuit generating unit 13 applies the basic configuration of the unit cell equivalent circuit stored in the storage unit 16 to each unit cell defined by the unit cell defining unit 11, and the unit surface of each unit cell. Based on the size of the unit cell and the distance between the unit surfaces, the value of the ground capacitor and the inductor constituting the equivalent circuit of each unit cell is determined to generate an equivalent circuit of each unit cell, and then the equivalent of the unit cells adjacent to each other is generated. By connecting the circuits, an equivalent circuit of the entire circuit board is generated. Here, when there is a position where the thickness between the power supply layer and the ground layer of the circuit board or the thickness between the power supply layer and another power supply layer changes, the equivalent circuit generation unit 13 has the thickness. By applying the basic configuration of the unit cell equivalent circuit stored in the storage unit so that the node at which the position changes corresponds to the node connecting each basic cell, an equivalent circuit of the entire circuit board is generated. (FIG. 4). 4 is a circuit diagram of an entire equivalent circuit (comprising three sub-circuits) when an equivalent circuit of a unit cell is applied to the circuit board of FIG. 2, and is a unit cell 30 shown in FIG. It is a circuit diagram which shows the unit cell equivalent circuit of -35 with the positional relationship.

Next, the equivalent circuit generation unit 13, for example, when the power supply layer P is notched as shown in FIG. 2B, the thickness between the power supply layer and the ground layer of the circuit board, or the power supply layer and a thickness of the first thickness d between another supply layer, when there is a position change in the larger second thickness d ₁ than the first thickness d, the thickness change Current at which the equivalent circuit is divided into a plurality of sub-equivalent circuits adjacent to each other and separated from the sub-equivalent circuit, and a current equivalent to the current flowing from the node of the basic cell is supplied to the basic cell of one sub-equivalent circuit. While adding a control current source, by adding a voltage control voltage source that applies a voltage equivalent to the voltage applied to the node of the basic cell to the basic cell of the other sub-equivalent circuit, The sub-equivalent circuits of the An equivalent circuit of the substrate is generated (FIG. 5). Here, the equivalent circuit generation unit 13 has a thickness between the power supply layer and the ground layer of the circuit board or a thickness between the power supply layer and another power supply layer from the first thickness d to the first thickness d. When there is a position that changes to the second thickness d ₁ that is larger than the thickness d of the power source, as described with reference to FIGS. 23A and 23B, the power supply layer exists in the portion of the second thickness d 2. Assuming that the thickness does not change, an assumed current is assumed, and the current flowing in the power supply layer having the first thickness d branches into a current flowing from the power supply layer to the ground layer and an assumed current. The current control current source and the voltage control voltage source are added under the condition of the assumption (see formula (22) described later). Note that, as will be described in detail later, the condition is such that when there is a position where the _first thickness d changes to a second thickness d ₁ that is larger than the first thickness d, the second thickness When d ₁ is substantially twice the thickness of the _first thickness d, the power supply layer is present in the portion of the second thickness d ₁ and the thickness does not change, and the first thickness Assuming that each of the sub-equivalent circuits is divided into two sub-equivalent circuits, the two magnetic fields parallel to the surface of the circuit board in each sub-equivalent circuit substantially coincide with the magnetic fields when not divided (described later). This is the condition (see equation (23)).

  In addition, when the equivalent circuit generation unit 13 associates the unit cell equivalent circuits of the first unit cell and the second unit cell adjacent to each other, the equivalent circuit generation unit 13 adds the second unit cell to the unit cell equivalent circuit of the first unit cell. In the unit cell equivalent circuit of the cell, a current control current source for giving a current equivalent to the current flowing into the boundary with the first unit cell is added, and the unit cell equivalent circuit of the second unit cell is added to the unit cell equivalent circuit of the first unit cell. In the unit cell equivalent circuit, a voltage control voltage source that provides a voltage equivalent to the voltage applied to the boundary with the second unit cell is added (FIG. 5).

  FIG. 5 is a diagram showing an entire equivalent circuit in which the unit cells adjacent to each other in FIG. 4 are related. As shown in FIG. 5, with respect to the unit cell equivalent circuit of the unit cell 31, a voltage control voltage source 40 that applies a voltage equivalent to the voltage V1 applied to the unit cell equivalent circuit of the unit cells 30 adjacent to each other, A voltage control voltage source 41 that provides a voltage equivalent to the voltage V2 applied to the unit cell equivalent circuit of the adjacent unit cell 32 is added. Although the RC circuit based on the voltage control voltage sources 40 and 41 is replaced, this is because the voltage control voltage sources 40 and 41 have a function of forcibly applying a voltage equivalent to the voltages V1 and V2. It is. Further, a current control current source 42 that gives a current equivalent to the current Ia flowing through the unit cell equivalent circuit of the unit cells 31 adjacent to each other is added to the unit cell equivalent circuit of the unit cell 30. Similarly, a current control current source 43 that provides a current equivalent to the current Ia flowing through the unit cell equivalent circuit of the unit cells 31 adjacent to each other is added to the unit cell equivalent circuit of the unit cell 32.

  When a predetermined input voltage (for example, pulse voltage) is applied to a predetermined node (hereinafter referred to as an input node) of the entire equivalent circuit, the power integrity calculation unit 14 is connected to a node (hereinafter referred to as an output) that is different from the input contact. Find the change in the voltage value that occurs at the node). For example, when a voltage is applied to a predetermined position of the circuit board, the power integrity calculation unit 14 calculates the current applied to each node of the equivalent circuit of the entire circuit board and the value of the current flowing between the nodes. By using LIM (Latency Insertion Method), which calculates alternately alternately, the voltage generated at a node on the path from the input node to the output node and the current flowing between the nodes are calculated alternately in time. . The result output unit 15 outputs and displays the time change result of the voltage at the output node calculated by the power integrity calculation unit 14 on a display, for example, or outputs it to a printer for printing. The power integrity calculation unit 14 calculates the value of the current applied to each node of the equivalent circuit of the entire circuit board and the value of the current flowing between the nodes when a voltage is applied to a predetermined position of the circuit board. Using a simulation program (Simulation Program with Integrated Circuit Emphasis; SPICE) that solves simultaneous equations showing the relationship between current and each voltage using numerical integration, voltage values generated at other positions on the circuit board are calculated. You may calculate and output.

  FIG. 6 is a diagram showing a hardware configuration of the power integrity analysis apparatus 1 of FIG. The power integrity analysis apparatus 1 is configured by a computer such as a digital computer to which a CPU 50, a RAM 51, a ROM 52, a communication interface 54, a hard disk memory 55, an operation unit 56, and a display 57 are connected by a data bus 58. When the CPU 50 executes arithmetic processing according to the program 53 written in the ROM 52, the function of the power integrity analysis apparatus 1 described above is realized. Such a program 53 is included in the scope of the present invention. The program can be executed by a computer, and may be provided by being recorded on a recording medium such as a CD-ROM.

  FIG. 7 is a flowchart showing a power integrity analysis process executed by the power integrity analysis apparatus of FIG. First, the power integrity analysis apparatus 1 receives input of structure information of a circuit board to be analyzed (S10). The structure information is information indicating the shape and arrangement of the power supply layer and the ground layer included in the circuit board. The power integrity analysis apparatus 1 may read information on the power supply layer and the ground layer from information on the design drawing of the circuit board.

  The power integrity analysis apparatus 1 defines unit cells based on the input structure information (S12). Specifically, as described above, the power supply layer and the ground layer are divided into a lattice shape, and a three-dimensional region where unit surfaces formed by the division face each other is defined as a unit cell. The power integrity analysis apparatus 1 stores the defined unit cell information and unit cell positional relationship data in the storage unit 16. The power integrity analysis apparatus 1 applies the basic configuration of the unit cell equivalent circuit stored in the storage unit 16 to each defined unit cell, and the unit surface size and the unit surface between the unit cells. And determining the values of the grounding capacitor and the inductor constituting the equivalent circuit of each unit cell based on the distance of the unit cell to generate the equivalent circuit of each unit cell, and then connecting the equivalent circuits of the unit cells adjacent to each other. As a result, an equivalent circuit of the entire circuit board is generated (S16). Here, the basic configuration of the unit cell equivalent circuit stored in the storage unit 16 is read, and the values of the ground capacitor and the inductor included in the read basic configuration are determined based on the size of the unit cell, the material of the circuit board, and the like. The power integrity analysis apparatus 1 associates the unit cell equivalent circuits of the unit cells and generates an entire equivalent circuit of the circuit board (S16).

  The equivalent circuit generation unit 13 associates the unit cell equivalent circuits of the first unit cell and the second unit cell adjacent to each other as follows. That is, a voltage control voltage source that applies a voltage equivalent to the voltage applied to the unit cell equivalent circuit of the first unit cell is added to the unit cell equivalent circuit of the second unit cell. On the contrary, a current control current source for supplying a current equivalent to the current flowing through the unit cell equivalent circuit of the second unit cell is added to the unit cell equivalent circuit of the first unit cell. The equivalent circuit generation unit 13 performs the above processing on all unit cells adjacent to each other, thereby associating unit cell equivalent circuits of all unit cells and generating an entire equivalent circuit.

  The power integrity analyzer 1 calculates the power integrity of the circuit board using the entire equivalent circuit (S18). When a predetermined input voltage (for example, a pulse voltage) is applied to a predetermined input node of the entire equivalent circuit, a time displacement of the voltage generated at the output node of the entire equivalent circuit is obtained. Specifically, the power integrity calculation unit 14 alternately calculates the voltage generated at the nodes on the path from the input node to the output node and the current flowing between the nodes in time using, for example, the LIM, and at the output node. Find the voltage. The power integrity analyzer 1 outputs the power integrity calculation result by displaying it on the display (S20).

  FIG. 8 is a diagram showing an example of the calculation result of the power integrity process of FIG. 7, and is a waveform diagram showing the output voltage Vout with respect to the input voltage Vin. FIG. 9 is a circuit diagram showing an entire equivalent circuit of the circuit board obtained by the power integrity processing of FIG. That is, FIG. 8 shows a time change of the voltage Vout generated at the output node when the pulse voltage Vin is applied to the input node in the entire equivalent circuit shown in FIG. As shown in FIG. 8, it can be seen that when a pulse voltage is applied to the input node, the voltage value of the output node varies. The configuration and operation of the power integrity analysis apparatus 1 according to this embodiment have been described above.

  The power integrity analysis apparatus 1 according to the present embodiment generates a unit cell equivalent circuit that expresses the electrical characteristics of a unit cell using a three-dimensional region sandwiched between opposing unit surfaces as a unit cell. Then, the unit cell equivalent circuits adjacent to each other are related to generate an entire equivalent circuit. In this entire equivalent circuit, since a grounded capacitor is connected to all nodes and an inductor is connected between all nodes, the current applied to the nodes and the value of the current flowing between the nodes are calculated alternately in time. And the power integrity calculation can be performed at high speed.

  FIG. 10 is a perspective view of the circuit board for explaining the calculation conditions of the embodiment of FIG. In this example, the power integrity of the circuit board including the three layers of the ground layer G1, the power supply layer P, and the ground layer G2 was analyzed. Note that the power supply layer P is notched and is half the size of the ground layers G1 and G2. In FIG. 10, the size of each layer is indicated by the number of unit surfaces when each layer is divided into a lattice. The relative dielectric constant of the circuit board was 3.0, the conductor loss was 0.0001 [Ω], and the distance between each layer was 1 [mm]. The power supply layer P and the ground layers G1 and G2 were divided so that the size of the unit surface was 20 [mm] × 20 [mm].

  In such a circuit board, when the input voltage Vin is applied between the ground layer G1 and the power supply layer P, the temporal change of the output voltage Vout appearing in the ground layer G2 at the apex on the diagonal line is represented by the present invention. It was determined by the power integrity analyzer 1. Further, as Comparative Example 1, an equivalent circuit of a circuit board is generated using M-FDM according to the related art, and power integrity analysis is performed using a known SPICE (Simulation Program with Integrated Circuit Emphasis; hereinafter referred to as SPICE). As a comparative example 2, the power integrity was analyzed using SPICE based on the equivalent circuit of the circuit board generated in the same manner as in the present embodiment.

  FIG. 11 is a diagram showing an example of the analysis result of the power integrity process of FIG. 7, and is a waveform diagram showing the output voltage Vout with respect to the input voltage Vin. As shown in FIG. 11, the example of the present invention, the comparative example 1 and the comparative example 2 were able to perform analysis with substantially the same accuracy. Table 1 below is a table showing the time required for the analysis.

  As shown in Table 1, in the example, as shown in Comparative Example 1, the M-FDM according to the related art required 401.7681 (seconds), whereas in the present example, only 0. Analysis was possible at 054 (seconds). Thus, in the example, the processing speed was dramatically improved as compared with the power integrity analysis method using the M-FDM according to the prior art. Even when a unit cell equivalent circuit similar to that of the present embodiment is used, when SPICE is used for calculation of power integrity, a time of 41.074 (seconds) is obtained as shown in Comparative Example 2. In short, it took about 100 times as long as this example.

The analysis by SPICE used in Comparative Example 1 and Comparative Example 2 is a method of solving simultaneous equations of Ax = b (A: circuit matrix, x: unknown vector, B: input vector) for each time step during analysis. . In this embodiment, since it is not necessary to solve such simultaneous equations by using LIM, it is considered that the calculation can be performed at high speed.

  The reason why the comparative example 2 was able to calculate at a higher speed than the comparative example 1 is that the number of nodes included in the equivalent circuit of the circuit board is small, and the modeled circuit matrix has non-zero elements (fill-in). There are few things.

  As described above, according to the present embodiment, a unit cell equivalent circuit expressing the electrical characteristics of a unit cell is generated using a three-dimensional region sandwiched between opposing unit surfaces as a unit cell. The electrical characteristics of the unit cell are expressed by a unit cell equivalent circuit in which a ground capacitor is connected to all nodes and an inductor is connected between all nodes. As a result, in the entire equivalent circuit generated by associating a plurality of unit cell equivalent circuits, the voltage value applied to the node and the current value flowing between the nodes can be calculated alternately, for example, in time, and the power integrity Can be calculated at high speed.

  The power integrity analysis apparatus 1 of this embodiment includes a storage unit 16 that stores the basic configuration of the unit cell equivalent circuit. The equivalent circuit generation unit 13 reads the basic configuration of the unit cell equivalent circuit from the storage unit 16. The unit cell equivalent circuit may be generated by determining the values of the ground capacitor and the inductor constituting the unit cell equivalent circuit based on the size of the unit surface of the unit cell and the distance between the unit surfaces.

  Since the unit cells generated by the unit cell demarcation unit 11 have the same configuration sandwiched between two unit planes, the basic configuration of the unit cell equivalent circuit representing the electrical characteristics is the same. . By storing the basic configuration of the unit cell equivalent circuit in the storage unit 16 in advance, the unit cell equivalent circuit can be generated at high speed.

  In the power integrity analysis apparatus according to the present embodiment, the equivalent circuit generation unit 13 determines the unit of the first unit cell when the unit cell equivalent circuit of the first unit cell and the second unit cell adjacent to each other is related. A current control current source for providing a current equivalent to a current flowing into the boundary with the first unit cell in the unit cell equivalent circuit of the second unit cell is added to the cell equivalent circuit, and the second unit cell of the second unit cell A voltage control voltage source that provides a voltage equivalent to the voltage applied to the boundary with the second unit cell in the unit cell equivalent circuit of the first unit cell may be added to the unit cell equivalent circuit. With this configuration, a plurality of unit cell equivalent circuits can be suitably related.

Second embodiment.
First, the background art of the second embodiment will be described below.

  In recent years, power integrity has become one of the most important issues in the design of high speed analog / digital mixed circuits. In order to verify power integrity, the power distribution network (PDN) must be analyzed to estimate undesirable noise such as ground bounce, delta current (ΔI) noise and simultaneous switching noise (SSN).

  Usually, a printed wiring board (hereinafter referred to as a PCB) or a PDN of a printed wiring package has a multilayer power / ground (P / G) plane pair (hereinafter referred to as a power / ground plane pair, a P / G plane pair). In addition, a plane is designed using a conductor plate. Detailed analysis of the PDN using a full wave electromagnetic simulator gives accurate results. However, this requires enormous CPU time and a large memory capacity. In the case of a PCB or package, the PDN can be modeled as a two-dimensional P / G plane in many cases.

  FIG. 13 shows a circuit board to be analyzed, which is an example of the structure of a circuit board in which a power supply layer 71 and a ground layer 72 made of ideal parallel plates are bonded to the top and bottom of a dielectric substrate 73, and a basic cell 70 therein. It is a perspective view which shows the structure. FIG. 14 is a circuit diagram showing a three-dimensional equivalent circuit of the basic cell 70 of FIG. As is well known, one P / G plane pair can be spatially discretized into a unit cell model as shown in FIGS. Each RLGC parameter of the equivalent circuit of the unit cell is derived by the size and the medium coefficient (see, for example, Non-Patent Document 1). Therefore, if the P / G plane pair is modeled as a large number of concentrated RLC elements instead of the full wave simulator, a conventional simulator such as SPICE can be used. However, it is still difficult to analyze these using SPICE due to the large scale of the PDN circuit.

  On the other hand, the latent insertion method (LIM) is one of fast transient simulation methods based on a leapfrog algorithm (see, for example, Non-Patent Documents 2 and 3). In the LIM simulation, the node voltage vector and the branch current vector are calculated alternately. This is in contrast to the implicit numerical integration used in simulators such as SPICE, which can analyze large RLC circuits very efficiently, and the computational cost of solving simultaneous equations is much lower. For example, in Non-Patent Documents 4 and 5, the inventors have shown that the leapfrog algorithm is suitable for simulation of a PDN equivalent circuit composed of a unit cell model having some frequency-dependent dispersion such as skin effect and dielectric loss.

  As described above, one P / G plane pair can be modeled by this unit cell model. However, an actual PDN usually consists of a multi-layer P / G plane pair with many holes and holes. Since there is electromagnetic coupling in the vertical direction through the holes between the two plane pairs, it is impossible to simply apply the unit cell model to model an actual PDN. In order to overcome this problem, for example, Non-Patent Documents 6 and 7 propose a multilayer finite difference method (M-FDM). M-FDM can model a complex plane pair having holes and holes as a large-scale RLC circuit. These circuits can be solved in the time domain by SPICE, but the calculation speed is slow. Furthermore, since the leapfrog algorithm has a limit in the circuit configuration to be analyzed, it is difficult for the leapfrog algorithm to solve an equivalent circuit generated by M-FDM. In other words, every branch must have an inductor, and every node must be connected to an ungrounded capacitor. An equivalent circuit generated by M-FDM does not satisfy the LIM condition.

  In the present embodiment, an effective modeling method for a power distribution network (PDN) composed of a multilayer P / G plane pair having holes and holes is proposed. In the inventors' method, each independent plane pair coupled in the vertical direction is modeled as a concentrated RLC equivalent circuit composed of unit cell models. At the boundary between holes or between holes, separately modeled circuits are connected by a voltage controlled voltage source (VCVS) and a current controlled current source (CCCS) according to the relationship between the electric field and the magnetic field. As a result, the entire equivalent circuit generated by the inventors' method can be solved without difficulty by the leapfrog algorithm. Furthermore, the equivalent circuit generated by the inventors' method can be solved at a much higher speed than that generated by M-FDM even if SPICE is used.

  Next, LIM, which is one of fast transient circuit simulation methods based on the leapfrog algorithm, will be briefly described below (see, for example, Non-Patent Documents 2 and 3). For example, in Non-Patent Documents 4 and 5, the inventors have already shown that LIM is suitable for simulation of a PDN equivalent circuit composed of a unit cell model. The circuit to be analyzed by LIM requires each branch to have an inductor and each node to have a grounded capacitor.

  FIG. 15A is a circuit diagram showing a circuit of a branch between two nodes when circuit analysis is performed using a latency insertion method (LIM), and FIG. 15B is a circuit diagram of FIG. It is a circuit diagram which shows the electric current outflow from the node of a), and a ground circuit. As shown in FIG. 15A, Kirchhoff's voltage law equation (hereinafter referred to as KVL equation) is expressed by the following equation in the case of a branch composed of a series inductor, resistor, and voltage source. In this specification, the number number of the black brackets in which the mathematical formula is imaged and the formula number of the square brackets in which the mathematical formula is input are used in combination. The formula number is assigned to the last part of the formula using the formula (1) as the formula number (there is also a formula that is not given).

  Here, the superscript n indicates a time index. Next, the branch current is updated as follows:

  Each node has a parallel connection circuit of a capacitor, a conductance, and a current source to the ground (ground) as shown in FIG. Therefore, Kirchhoff's current law equation (hereinafter referred to as KCL equation) is expressed by the following equation.

Here, M _a is the number of branches connected to the node a. Next, the nodal voltage is updated as follows:

  Finally, a transient simulation is performed by alternating “leap frog” updates of branch current and node voltage according to equations (2) and (4) and in alternating half time steps. In order to perform a stable simulation, the size of the time step Δt is determined as follows based on the minimum values of inductance and capacitance in the circuit.

  Next, the multilayer finite difference method will be described below.

  16A is a longitudinal sectional view of the multilayer circuit board to be analyzed, and FIG. 16B is a circuit diagram showing an equivalent circuit of the multilayer circuit board of FIG. 16A. Assuming that a plurality of P / G plane pairs are stacked, as shown in FIG. 16, if there are no holes and holes between the plane pairs, each P / G plane pair is equivalent to a unit cell model. It can be modeled separately as a circuit. This is because a current having a high frequency flows only on the surface of the conductor due to the skin effect. On the other hand, an actual multilayer P / G plane pair typically has many holes and holes. Since electromagnetic coupling exists between the two plane pairs in the vertical direction through holes, it is not possible to simply apply the unit cell model to model an actual PDN. In order to overcome this problem, for example, Non-Patent Documents 6 and 7 propose a multilayer finite difference method (M-FDM). The following briefly describes this M-FDM first, and then points out that there is room for improving the modeling of conductor loss in M-FDM.

  Here, first, modeling of a multi-layer plane pair based on M-FDM will be described below.

  FIG. 17A is a perspective view showing the structure of a basic cell including three planes 81 (P1) to 83 (P3), and FIG. 17B is a multilayered finite-difference method according to the prior art. It is a circuit diagram showing an equivalent circuit of a basic cell by method; hereinafter referred to as M-FDM). M-FDM models a multilayer plane as shown in FIG. In this example, the plane 83 (P3) is selected as the common reference terminal. If the partial self-inductances of the plane 81 (P1) and the plane 82 (P2) are L1 and L2, respectively, a partial mutual inductance L2 is introduced between the plane 81 (P1) and the plane 82 (P2).

  FIG. 18 is a longitudinal sectional view showing an example of the circuit board when the middle power supply layer also has a notch in the right half. In FIG. 18, the dielectric layer 90 is changed from the thickness d and d to the thickness d1 (≈2d) due to the notch (FIGS. 23A and 26 are also shown). The example shown in FIG. 18 cannot be simply modeled by the unit cell model because there is no right half of the intermediate plane. In contrast, the M-FDM can model this as shown in FIG.

  FIG. 19 is a circuit diagram showing the equivalent circuit of FIG. 18 created using the M-FDM according to the prior art. The equivalent circuit of FIG. 19 can be solved by SPICE. However, since the leapfrog algorithm has a limit on the circuit configuration to be analyzed, the leapfrog algorithm is difficult to solve.

  Next, the equivalence between the unit cell model and M-FDM will be described below.

  FIG. 20A is a circuit diagram showing an example of a one-dimensional equivalent circuit created using the M-FDM according to the prior art, and FIG. 20B shows a basic cell model according to this embodiment. It is a circuit diagram which shows an example of the produced one-dimensional equivalent circuit. If there are no holes and holes between the multilayer plane pairs, the equivalent circuit generated by M-FDM should be mathematically equivalent to that of a single unit cell model. For example, as shown in FIG. 20, in a simple one-dimensional case including three planes, an equivalent circuit KVL equation generated by M-FDM is expressed by the following equation.

[Equation 1]
V _an-1 −V _an = (R ₁ + sL ₁ + sL ₂ ) I _an-1 + sL ₂ I _bn-1 (6)
[Equation 2]
V _bn−1 −V _bn = sL ₂ I _an−1 + (R ₂ + sL ₂ ) I _bn−1 (7)

  Here, s = jω. The KCL equation is expressed by the following equation.

[Equation 3]
(G + sC) (V _an −V _bn ) = I _an−1 −I _an (8)
[Equation 4]
(G + sC) V _bn = I _bn−1 −I _bn + I _an−1 −I _an (9)

Assuming that the conductor loss is negligible such as R ₁ = R ₂ = 0, the inventors introduce the following variable changes.

[Equation 5]
V _abn = V _an −V _bn , V _abn−1 = V _an−1 −V _bn−1 (10)
[Equation 6]
I ′ _bn = I _an + I _bn , I ′ _bn−1 = I _an−1 + I _bn−1 (11)

  As a result, equations (6) through (9) can be rewritten as follows:

[Equation 7]
V _abn-1 −V _abn = sL ₁ I _an-1 (12)
[Equation 8]
V _bn−1 −V _bn = sL ₂ I ′ _bn−1 (13)
[Equation 9]
(G + sC) V _abn = I _an−1 −I _an (14)
[Equation 10]
(G + sC) V _bn = I ′ _bn−1 −I ′ _bn (15)

  Actually, the equations (12) to (15) are exactly the same as the KVL and KCL of the equivalent circuit using the unit cell model as shown in FIG. Therefore, if the resistance R is negligible, equivalence can be found between the M-FDM and the unit cell model. However, at high frequencies, conductor losses are usually not negligible. In cases involving conductor losses, FIG. 20 (a) and FIG. 20 (b) are not mathematically equal.

  FIG. 21 is a circuit diagram showing an example of an equivalent circuit created using a modified M-FDM. Therefore, the inventors modify the equivalent circuit based on M-FDM as shown in FIG. 21 in order to correct the conductor loss. In this modification, a mutual resistance is introduced between the plane 81 (P1) and the plane 82 (P2). The KVL equation in FIG. 21 is expressed by the following equation.

[Equation 11]
V _an-1 −V _an = (R ₁ + R ₂ + sL ₁ + sL ₂ ) I _an-1 + (R ₂ + sL ₂ ) I _bn−1
(16)
[Equation 12]
V _bn−1 −V _bn = (R ₂ + sL ₂ ) I _an−1 + (R ₂ + sL ₂ ) I _bn−1 (17)

  If Expressions (10) and (11) are used, Expressions (16) and (17) can be rewritten as the following expression.

[Equation 13]
V _abn-1 −V _abn = (R ₁ + sL ₁ ) I _an-1 (18)
[Formula 14]
V _bn−1 −V _bn = (R ₂ + sL ₂ ) I ′ _bn−1 (19)

  It can be seen that the equations (18) and (19) are equal to the KVL of the equivalent circuit using the unit cell model shown in FIG. If the equivalent circuit of FIG. 21 is analyzed by SPICE, an H element that is a current control voltage source can be used as a mutual resistance. On the other hand, it is difficult for the LIM to solve the equivalent circuit generated by the M-FDM and the modified M-FDM because these methods do not satisfy the LIM condition.

  Next, modeling of a multilayer plane pair suitable for the leapfrog algorithm will be described below. That is, an effective modeling method for a multilayer P / G plane pair having holes and holes is proposed. In the proposed method, each independent plane pair connected in the vertical direction is modeled as a concentrated RLC equivalent circuit composed of unit cell models. For example, in the case of FIG. 18, the planes 81 (P1) and 83 (P3) are connected by the right half of these planes. Therefore, this pair is modeled as an independent equivalent circuit.

  FIG. 22 is a circuit diagram showing the equivalent circuit of FIG. 18 created using the basic cell model according to the present embodiment. Since two plane pairs exist in the left half of these planes, an equivalent circuit of three independent sub-circuits can be obtained as shown in FIG.

  Next, it is necessary to correctly connect the equivalent circuits of the three sub-circuits. For example, Non-Patent Document 6 states that it is difficult to realize interconnection between plane pairs, but considering this problem at an electromagnetic level, it is not difficult to connect them correctly.

  FIG. 23A is a perspective view showing a structure of a circuit board for defining variables for connecting the three sub-circuits of FIG. 22, and FIG. 23B is an assumption condition used when creating an equivalent circuit according to this embodiment. It is a perspective view of FIG. 23A for demonstrating.

First, the voltage, current and magnetic field are defined as shown in FIG. Here, Δx, Δy, and Δz indicate unit cell sizes in the x, y, and z directions, respectively. For example, the relationship between V _z1 and I _z1 is expressed by the following equation.

Here, σ and ε are dielectric loss and dielectric constant, respectively. Next, the vertical currents I _z1 and I _z2 can be approximated according to Ampere's law as in the following approximate expression.

[Equation 15]
I _z1 ≈H _y1 Δy−H _y3 Δy = I _x1 −I _a (21)
[Equation 16]
I _{z2 ≈H y2} Δy−H _y3 Δy = I _x2 −I _a (22)

Here, the magnetic field in the x direction is excluded. As a result, the three equivalent circuits shown in FIG. 22 can be connected as shown in FIG. 24 by the voltage control voltage source (VCVS) and the current control current source (CCCS). As shown in FIG. 23B, the approximate setting conditions of the above formulas (21) and (22) are as follows when the plane 82 (P2) is assumed to extend. This is a condition that the magnetic field H _y3a , the lower magnetic field H _y3b, and the magnetic field H _y3 (FIG. 23A) when the plane 82 (P2) is not extended are substantially the same as the following expression.

[Equation 17]
H _y3 ≒ H _y3a ≒ H _y3b (23)

  FIG. 24 is a circuit diagram of a first example of the entire equivalent circuit created by the equivalent circuit creation method using the basic cell according to this embodiment, and FIG. 25 is an equivalent diagram using the basic cell according to this embodiment. It is a circuit diagram of the 2nd example of the whole equivalent circuit created by the circuit creation method. As shown in FIGS. 24 and 25, in the equivalent circuit of the basic cells adjacent to each other, the voltage control voltage source and the parallel circuit of the current control current source and the GC circuit connected in parallel thereto can be switched. FIG. 18 is a typical example, but the proposed method can model a more complicated configuration without difficulty. Furthermore, the equivalent circuit generated by the method proposed by the inventors can be solved by a leapfrog algorithm such as LIM.

  Next, numerical calculation results of the second embodiment will be described below.

  FIG. 26 is a perspective view showing an example of a PDN circuit board to be analyzed according to the present embodiment. First, in order to verify the effectiveness of the proposed modeling method, the PDN shown in FIG. 26 was simulated. FIG. 27 is a waveform diagram showing the input voltage Vin applied to the PDN circuit board of FIG. The voltage source point of the input voltage Vin was excited with a triangular waveform plotted in FIG. The P / G plane pair is modeled by three different modeling methods: M-FDM, modified M-FDM, and the method proposed above by the inventors. To verify the effectiveness and efficiency of the proposed modeling, the transient responses simulated using Synopsys Star-HSPICE® were compared. All simulations were run on an Intel Core2Duo® 2.33 GHz personal computer with a 32-bit Windows Vista® operating system. HSPICE® uses a constant time step size selected as 3.54 psec from equation (5). The inventors have also set the exact option to 1. In HSPICE (registered trademark), if the accurate option is set to 1, a more detailed simulation can be executed, but the simulation time becomes longer (for example, see Non-Patent Document 8).

The unit cell size and medium coefficient are w = 1.0 mm, d = 0.2 mm, t = 0.02 mm, σ = 5.8 × 10 ⁷ , and ε _r = 4.5. Here, w, t, and d are the width of the unit cell 70, the plane (conductor plate) thickness, and the dielectric thickness, and w> d, which is defined in FIG. The conductor loss R is calculated by the following equation.

  Here, f is a signal frequency. Of course, for example, the frequency-dependent unit cell model proposed in Non-Patent Document 5 can be used, but a frequency-independent model is used for the sake of simplicity. In this simulation, assuming that f = 1 GHz, the conductor loss is R≈0.182Ω.

  FIG. 28 is a waveform diagram showing the output voltage Vout obtained by each analysis method when the input voltage Vin is applied to the PDN circuit board of FIG. That is, FIG. 28 plots the voltage waveform at the output voltage Vout simulated using HSPICE (registered trademark). The waveform of the proposed modeling method is in good agreement with other waveforms. Next, in order to verify the accuracy of modeling of the conductor loss, the conductor loss was intentionally increased 10 times, and after this deformation, the HSPICE® simulation was performed again.

  FIG. 29 is a waveform showing the output voltage Vout obtained by each analysis method when the input voltage Vin is applied to the PDN circuit board of FIG. 26 and the loss resistance is set to 10 times that of FIG. FIG. That is, FIG. 29 is a plot of the voltage waveform at the output voltage Vout. The waveform of the proposed modeling method and the waveform of the modified M-FDM are completely the same, but the waveform of the M-FDM is different from the others for the reasons described above.

  FIG. 32 is a table showing CPU time when HSPICE (registered trademark) simulation is performed on the equivalent circuit according to the present embodiment. It can be seen that the equivalent circuit generated by the proposed method can be solved faster than that generated by the M-FDM and the modified M-FDM because the number of fill-ins is the least in the proposed modeling method. . The reason for the minimum number of fill-ins is that all capacitors are grounded in the proposed equivalent circuit.

  Next, in order to verify the efficiency of the leapfrog algorithm, the transient response of the PDN was simulated. The arrangement is the same as in FIG. 26, but the depth of the plane was changed from 25 mm to 100 mm. The linear circuit simulator of the inventors based on a sparse matrix (sparse matrix) LU decomposition (see, for example, Non-Patent Document 10) of a transient response simulated using a proposed transient circuit simulator based on a leapfrog algorithm And FALCON (see, for example, Non-Patent Document 9) and HSPICE (registered trademark). In this simulation, the HSPICE® simulation was performed by changing the time step option in two steps. The inventors' two simulators were compiled using the MS-Visual C ++ compiler, version 2008. In FALCON and HSPICE (registered trademark) simulation, the number of nodes of the equivalent circuit generated by the proposed modeling method is 76,860.

  30 and 31 are waveform diagrams showing the output voltage Vout obtained by each analysis method in the case of FIG. That is, FIG. 30 is a plot of the voltage waveform at the output voltage Vout. As is apparent from FIGS. 30 and 31, the waveform calculated by the inventors' simulator is in good agreement with HSPICE (registered trademark) in which FALCON and the time step are constant.

  FIG. 33 is a table showing CPU time when the equivalent circuit according to the present embodiment is simulated using the HSPICE simulator and the leapfrog simulator. As can be seen from FIG. 33, our simulators are about 105 and 486 times faster than FALCON and HSPICE®, respectively, with the same time step size. If HSPICE® uses variable time steps, the CPU time is improved, but the simulation accuracy is reduced as shown in FIG.

  As described above, according to the present embodiment, an effective modeling method for a multilayer P / G plane pair having holes and holes has been proposed. From the numerical results, the equivalent circuit generated by the proposed method can be solved at a higher speed than that generated by M-FDM using SPICE. It is also clear that the inventors' modeling method can correctly model conductor losses. Furthermore, the leapfrog algorithm enables 486 times faster than HSPICE (registered trademark) with the same level of accuracy.

Third embodiment.
FIG. 34 is a circuit diagram showing a method of adding a current-controlled current source and a voltage-controlled voltage source by dividing into two sub-circuits in an equivalent circuit according to the third embodiment of the present invention. In FIG. 34, the basic procedure is as follows.
(1) When a node is divided into two sub-circuits, the ground capacitor and the ground conductance G are left at one of the divided nodes.
(2) A current control current source is connected to the node where the ground capacitor C and the ground conductance G remain.
(3) A voltage control voltage source is connected to the node where the ground capacitor C and the ground conductance G disappear.

  FIG. 35A is a longitudinal sectional view of the circuit board according to Example 1 of the third embodiment, and FIG. 35B is a longitudinal section of the circuit board when divided and defined by the basic cell according to the embodiment. FIG. 35C is a diagram illustrating an equivalent circuit of the basic cell equivalent circuit according to the present embodiment and a total equivalent when using a method of adding a current source and a voltage source to the circuit board of FIG. It is a circuit diagram of a circuit. In FIGS. 35 and below, 81 and 83 are ground layers, and 82 and 84 are power supply layers. Reference numeral 90 denotes a dielectric layer. In FIG. 35A, in the left half, the dielectric layer 90 is divided by the thicknesses d by the power supply layers 82 and 84, but in the right half, the total thickness d2 is due to the notch of the power supply layers 82 and 84. (≈3d). When the basic cell is defined by the unit cell defining unit 11 of FIG. 1 on the circuit board of FIG. 35A, the result is as shown in FIG. Here, with respect to the circuit board of FIG. 35 (b), the equivalent circuit generation unit 13 of FIG. 1 applies the equivalent circuit of the basic cell, divides it into sub-circuits, and the current control current source and voltage control voltage source. When the addition is performed, the result is as shown in FIG. In FIG. 35C, in the right half sub-circuit, the GC circuits are combined into one parallel circuit. However, the present invention is not limited to this, and may not be combined.

  FIG. 36A is a longitudinal sectional view of a circuit board according to Example 2 of the third embodiment, and FIG. 36B is a longitudinal section of the circuit board when divided and defined by the basic cell according to the embodiment. FIG. 36C is a diagram illustrating an equivalent circuit of the basic cell equivalent circuit according to the present embodiment, and a total equivalent when using a method of adding a current source and a voltage source to the circuit board of FIG. It is a circuit diagram of a circuit. In FIG. 36A, in the left half, the dielectric layer 90 is divided by thicknesses d and d1 (≈2d) by the power supply layer 82, but in the right half, each thickness is due to the notch of the power supply layer 84. It is divided by d1, d. That is, the two notch positions are coincident on the plane of the circuit board, but are different in depth. When the basic cell is defined by the unit cell defining unit 11 of FIG. 1 on the circuit board of FIG. 36A, it is as shown in FIG. Here, for the circuit board of FIG. 36 (b), the equivalent circuit generation unit 13 of FIG. 1 applies the equivalent circuit of the basic cell, divides it into sub-circuits, and the current control current source and voltage control voltage source. When added, the result is as shown in FIG. In FIG. 36C, in the lower left subcircuit and the upper right subcircuit, the GC circuits are combined into one parallel circuit. However, the present invention is not limited to this and may not be combined.

  FIG. 37A is a longitudinal sectional view of a circuit board according to Example 3 of the third embodiment, and FIG. 37B is a longitudinal section of the circuit board when divided and defined by the basic cell according to the embodiment. FIG. 37 (c) is an equivalent diagram of the entire circuit when using the equivalent circuit of the basic cell according to the present embodiment and the method of adding the current source and voltage source to the circuit board of FIG. 37 (b). It is a circuit diagram of a circuit. In FIG. 37A, as in FIG. 36A, in the left half, the dielectric layer 90 is divided by the thickness d, d1 (≈2d) by the power supply layer 82, but in the right half, The power source layer 84 is divided by the thicknesses d1 and d by the cutouts. That is, the two notch positions are coincident on the plane of the circuit board, but are different in depth. When the basic cell is defined by the unit cell defining unit 11 of FIG. 1 on the circuit board of FIG. 37A, it is as shown in FIG. Here, with respect to the circuit board of FIG. 37 (b), the equivalent circuit generator 13 of FIG. 1 applies the equivalent circuit of the basic cell, divides it into sub-circuits, and the current control current source and the voltage control voltage source When added, the result is as shown in FIG. The third embodiment shown in FIG. 37 is characterized in that the third voltage control voltage source is inserted not in the lower right sub-circuit but in the lower left sub-circuit as compared with the second embodiment shown in FIG. Even if configured in this way, it is equivalent as an equivalent circuit.

  FIG. 38 is a circuit diagram showing an equivalent circuit when the equivalent circuit according to the second embodiment of FIG. 36 is analyzed using SPICE, and FIG. 39 is a diagram showing the analysis result of FIG. It is a wave form diagram which shows the input voltage V1 which consists of a triangular wave signal, and output voltage V11, V12. 40 is a circuit diagram showing an equivalent circuit when the equivalent circuit according to Example 3 of FIG. 37 is analyzed using SPICE, and FIG. 41 is a diagram showing the analysis result of FIG. It is a wave form diagram which shows input voltage V1 which consists of two triangular wave signals, and output voltage V11, V12. As is clear from the comparison between FIG. 39 and FIG. 41, the analysis results of the waveforms are the same, and it was proved that the equivalent circuit of FIG. 36 and the equivalent circuit of FIG. 38 are equivalent.

Modified example.
The power integrity analysis apparatus of the present invention has been described in detail with reference to the embodiment. However, the power integrity analysis apparatus of the present invention is not limited to the above-described embodiment.

  The equivalent circuit shown in the above embodiment is an example, and another model may be adopted as the equivalent circuit. However, the equivalent circuit (basic configuration) of the unit cell needs to have a ground capacitor connected to at least all nodes and have an inductor between all nodes.

  Further, the method of relating the equivalent circuits of the sub-circuits shown in the above-described embodiments is an example, and if the boundary conditions of the unit cells are matched, the association may be performed by another method.

  FIG. 12 is a circuit diagram showing an entire equivalent circuit of another example of the circuit board obtained by the power integrity processing of FIG. For example, it is possible to replace the part of the circuit shown in FIG. 5 and generate the circuit shown in FIG.

  In the above-described embodiment, an example is shown in which the time displacement of the voltage at a predetermined output node is output as the output result of power integrity. However, the voltage displacement that occurs at all the nodes of the entire equivalent circuit of the circuit board is output as the output result. It may be output.

  As described above in detail, according to the power integrity analysis apparatus, method, and program according to the present invention, an equivalent circuit of the entire circuit board in which a ground capacitor is connected to all nodes and an inductor is connected between all nodes is generated. The power integrity calculation can be performed at high speed using the entire equivalent circuit. In particular, the thickness between the power supply layer and the ground layer of the circuit board or the thickness between the power supply layer and another power supply layer is larger than the first thickness from the first thickness. When there is a position where the thickness changes, the equivalent circuit is divided into a plurality of adjacent sub-equivalent circuits at the node where the thickness changes, and the basic cell of one of the sub-equivalent circuits is separated. In contrast, a current control current source for supplying a current equivalent to the current flowing from the node of the basic cell is added to the basic cell of the other sub-equivalent circuit, and equivalent to the voltage applied to the node of the basic cell. By adding a voltage control voltage source for applying a voltage, a plurality of sub-equivalent circuits adjacent to each other can be related to generate an equivalent circuit of the circuit board. Thereby, even if there is a notch or the like in the power supply layer, the power integrity of the circuit board can be calculated with higher accuracy and higher speed than in the conventional technique.

1 ... Power integrity analyzer,
10 ... Structure information input part,
11: Unit cell demarcation part,
13: Equivalent circuit generation unit,
14 ... Power integrity calculator,
15 ... Result output section,
16 ... storage part,
20-29 ... unit surface,
30-35 ... unit cell,
30-2, 30-3 ... equivalent circuit,
40, 41 ... Voltage control voltage source,
42, 43 ... current controlled current source,
50 ... CPU,
51 ... RAM,
52 ... ROM,
53 ... Program,
54. Communication interface,
55. Hard disk memory,
56 ... operation unit,
57 ... Display,
58 ... Bus
70 ... unit cell,
P, 71, 82, 84 ... power supply conductor layer (power supply layer),
G1, G2, 72, 81, 83... Ground conductor layer (ground layer),
73, 90-93 ... dielectric layer,
P1 to P3: Plane.

Claims (15)

A structure information input unit for inputting structure information indicating the shape and arrangement of the power supply layer and the ground layer of the circuit board having a multilayer structure including at least one power supply layer and at least one ground layer;
The power supply layer and the ground layer are divided into a lattice shape, and the unit surface of the power supply layer or the ground layer facing each divided unit surface is obtained based on the structure information, and sandwiched between the two unit surfaces facing each other. A unit cell delimiting unit that demarcates a three-dimensional region as a unit cell and obtains a positional relationship between the unit cells;
A basic configuration of a unit cell equivalent circuit expressing the electrical characteristics of the unit cell, a storage unit storing a unit cell equivalent circuit in which a ground capacitor is connected to all nodes and an inductor is connected between all nodes;
The basic configuration of the unit cell equivalent circuit stored in the storage unit is applied to each unit cell defined by the unit cell defining unit, and the unit plane size and unit plane between the unit cells And determining the values of the grounding capacitor and the inductor constituting the equivalent circuit of each unit cell based on the distance of the unit cell to generate the equivalent circuit of each unit cell, and then connecting the equivalent circuits of the unit cells adjacent to each other. Thus, an equivalent circuit generation unit that generates an equivalent circuit of the entire circuit board,
In a power integrity analysis apparatus comprising a power integrity calculation unit that calculates and outputs a voltage value generated at another position of the circuit board when a voltage is applied to a predetermined position of the circuit board.
The equivalent circuit generator is
When there is a position where the thickness between the power supply layer and the ground layer of the circuit board or the thickness between the power supply layer and another power supply layer changes, the node where the thickness changes is Applying the basic configuration of the unit cell equivalent circuit stored in the storage unit so as to correspond to the nodes connecting the basic cells, an equivalent circuit of the entire circuit board is generated,
The thickness between the power supply layer and the ground layer of the circuit board, or the thickness between the power supply layer and another power supply layer is a second thickness that is larger than the first thickness from the first thickness. When there is a position where the thickness changes, at the node where the thickness changes, the equivalent circuit is divided into a plurality of adjacent sub-equivalent circuits and separated. In addition, a current control current source for supplying a current equivalent to the current flowing from the node of the basic cell is added, while a voltage equivalent to the voltage applied to the node of the basic cell is applied to the basic cell of the other sub-equivalent circuit. A power integrity analysis apparatus characterized in that by adding a voltage control voltage source to be applied, a plurality of adjacent sub-equivalent circuits are related to each other to generate an equivalent circuit of the circuit board.   The equivalent circuit generation unit is configured such that the thickness between the power supply layer and the ground layer of the circuit board or the thickness between the power supply layer and another power supply layer is the first thickness. When there is a position where the thickness changes to a second thickness greater than that, an assumed current is assumed when a power supply layer is present in the second thickness portion and the thickness is assumed not to change. The current control current source and the current control current source under the condition that the current flowing through the power supply layer of the first thickness branches to the current flowing from the power supply layer to the ground layer and the assumed current. The power integrity analysis apparatus according to claim 1, wherein the voltage control voltage source is added.   The equivalent circuit generation unit is configured such that the thickness between the power supply layer and the ground layer of the circuit board or the thickness between the power supply layer and another power supply layer is the first thickness. The second thickness is substantially twice the first thickness when there is a position where the second thickness is greater than the second thickness. When it is assumed that the power supply layer exists in the portion and the thickness does not change and is divided into two sub equivalent circuits each having the first thickness, the surface of the circuit board in each sub equivalent circuit 3. The current-controlled current source and the voltage-controlled voltage source are added under the condition that two parallel magnetic fields substantially match the magnetic field when not divided. Power integrity analyzer. The equivalent circuit generator is
When relating the unit cell equivalent circuit of the first unit cell and the second unit cell adjacent to each other, the unit cell equivalent circuit of the second unit cell is connected to the unit cell equivalent circuit of the first unit cell. Adding a current-controlled current source that gives a current equivalent to the current flowing into the boundary with the first unit cell;
A voltage control voltage source that applies a voltage equivalent to a voltage applied to a boundary with the second unit cell in the unit cell equivalent circuit of the first unit cell to the unit cell equivalent circuit of the second unit cell. The power integrity analysis apparatus according to claim 1, wherein the power integrity analysis apparatus is added.   When the voltage is applied to a predetermined position of the circuit board, the power integrity calculation unit temporally calculates the current applied to each node of the equivalent circuit of the entire circuit board and the current flowing between the nodes. 5. The voltage value generated at another position of the circuit board is calculated and output using a latency insertion method (LIM) that alternately calculates. 5. The power integrity analysis apparatus according to one.   The power integrity calculation unit calculates a current applied to each node of the equivalent circuit of the entire circuit board and a current flowing between the nodes when a voltage is applied to a predetermined position of the circuit board. Calculate the voltage value generated at other positions on the circuit board using a simulation program (Simulation Program with Integrated Circuit Emphasis; SPICE) that solves the simultaneous equations showing the relationship between the voltage and each voltage using the numerical integration method. The power integrity analysis apparatus according to any one of claims 1 to 4, wherein the power integrity analysis apparatus outputs the power integrity analysis apparatus.   The storage unit is a basic configuration of a unit cell equivalent circuit expressing the electrical characteristics of the unit cell, and a unit cell in which a ground capacitor and a ground conductance are connected to all nodes, and an inductor and a resistor are connected between all nodes. The power integrity analyzer according to any one of claims 1 to 6, wherein an equivalent circuit is stored. A power integrity analysis method for analyzing the power integrity of a multilayer circuit board including at least one power supply layer and at least one ground layer by a computer,
The computer has a basic configuration of a unit cell equivalent circuit expressing the electrical characteristics of the unit cell, and stores a unit cell equivalent circuit in which a ground capacitor is connected to all nodes and an inductor is connected between all nodes. Part
The above power integrity analysis method is
Inputting structural information indicating the shape and arrangement of the power supply layer and the ground layer of a multilayer circuit board including at least one power supply layer and at least one ground layer;
The power supply layer and the ground layer are divided into a lattice shape, and the unit surface of the power supply layer or the ground layer facing each divided unit surface is obtained based on the structure information, and sandwiched between the two unit surfaces facing each other. Defining a three-dimensional region as a unit cell and determining a positional relationship of each unit cell;
The basic configuration of the unit cell equivalent circuit stored in the storage unit is applied to each unit cell defined by the unit cell defining unit, and the unit plane size and unit plane between the unit cells And determining the values of the grounding capacitor and the inductor constituting the equivalent circuit of each unit cell based on the distance of the unit cell to generate the equivalent circuit of each unit cell, and then connecting the equivalent circuits of the unit cells adjacent to each other. A step of generating an equivalent circuit of the entire circuit board,
Calculating and outputting a voltage value generated at another position of the circuit board when a voltage is applied to a predetermined position of the circuit board.
The step of generating the equivalent circuit includes:
When there is a position where the thickness between the power supply layer and the ground layer of the circuit board or the thickness between the power supply layer and another power supply layer changes, the node where the thickness changes is Applying the basic configuration of the unit cell equivalent circuit stored in the storage unit so as to correspond to the nodes connecting the basic cells, an equivalent circuit of the entire circuit board is generated,
The thickness between the power supply layer and the ground layer of the circuit board, or the thickness between the power supply layer and another power supply layer is a second thickness that is larger than the first thickness from the first thickness. When there is a position where the thickness changes, at the node where the thickness changes, the equivalent circuit is divided into a plurality of adjacent sub-equivalent circuits and separated. In addition, a current control current source for supplying a current equivalent to the current flowing from the node of the basic cell is added, while a voltage equivalent to the voltage applied to the node of the basic cell is applied to the basic cell of the other sub-equivalent circuit. A power integrity analysis method comprising: adding a voltage control voltage source to be applied, and connecting a plurality of adjacent sub-equivalent circuits together to generate an equivalent circuit of the circuit board.   The step of generating the equivalent circuit includes a step in which the thickness between the power supply layer and the ground layer of the circuit board or the thickness between the power supply layer and another power supply layer is the first thickness. Assuming an assumed current when it is assumed that there is a power supply layer in the second thickness portion and the thickness does not change when there is a position where the second thickness is larger than the thickness of the second thickness. And the current control current under the condition that the current flowing through the power supply layer having the first thickness branches to the current flowing from the power supply layer into the ground layer and the assumed current. 9. The power integrity analysis method according to claim 8, wherein a power source and the voltage control voltage source are added.   The step of generating the equivalent circuit includes a step in which the thickness between the power supply layer and the ground layer of the circuit board or the thickness between the power supply layer and another power supply layer is the first thickness. The second thickness when the second thickness is substantially twice the first thickness when there is a position that changes to a second thickness greater than the second thickness. When it is assumed that the power supply layer is present in this portion and the thickness does not change and is divided into two sub-equivalent circuits each having the first thickness, the circuit board of each sub-equivalent circuit 10. The current control current source and the voltage control voltage source are added under a condition that two magnetic fields parallel to a surface substantially match the magnetic field when not divided. The power integrity analysis method described. The step of generating the equivalent circuit includes:
When relating the unit cell equivalent circuit of the first unit cell and the second unit cell adjacent to each other, the unit cell equivalent circuit of the second unit cell is connected to the unit cell equivalent circuit of the first unit cell. Adding a current-controlled current source that gives a current equivalent to the current flowing into the boundary with the first unit cell;
A voltage control voltage source that applies a voltage equivalent to a voltage applied to a boundary with the second unit cell in the unit cell equivalent circuit of the first unit cell to the unit cell equivalent circuit of the second unit cell. The power integrity analysis method according to any one of claims 8 to 10, wherein the power integrity analysis method is added.   In the step of calculating the power integrity, when a voltage is applied to a predetermined position of the circuit board, the current applied to each node of the equivalent circuit of the entire circuit board and the value of the current flowing between the nodes are calculated in time. 12. A voltage value generated at another position of the circuit board is calculated and output using a latency insertion method (LIM) that alternately calculates the output of the circuit board. The power integrity analysis method according to any one of the above.   In the step of calculating the power integrity, when a voltage is applied to a predetermined position of the circuit board, the current applied to each node of the equivalent circuit of the entire circuit board and the value of the current flowing between the nodes are calculated. Voltage values generated at other positions of the circuit board using a simulation program (Simulation Program with Integrated Circuit Emphasis; SPICE) which is calculated by solving simultaneous equations indicating the relationship between each current and each voltage using a numerical integration method The power integrity analysis method according to any one of claims 8 to 11, wherein the power integrity is calculated and output.   The storage unit is a basic configuration of a unit cell equivalent circuit expressing the electrical characteristics of the unit cell, and a unit cell in which a ground capacitor and a ground conductance are connected to all nodes, and an inductor and a resistor are connected between all nodes. The power integrity analysis method according to claim 8, wherein an equivalent circuit is stored.   A computer-executable program comprising the steps of the power integrity analysis method according to any one of claims 8 to 14.

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