JP2011071530A - Semiconductor storage device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To improve performance of an SRAM circuit in a low power-supplying-voltage condition by constituting an SRAM memory cell with an FD-SOI transistor, and controlling the potential of the lower layer of the embedded oxide film of the SOI transistor constituting a drive transistor. <P>SOLUTION: In the SRAM memory cell constituted by using an FD-SOI transistor, a stable operation of the memory cell is enabled by controlling Vth to increase current by controlling well potential under a BOX layer of a drive transistor. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a semiconductor integrated circuit in which a static memory (SRAM) circuit is integrated on a semiconductor chip. In particular, the present invention relates to a circuit configuration for reducing the operating voltage of an SRAM integrated circuit device.

  FIG. 33 shows a conventional SRAM memory cell circuit. BL and BLB are bit lines, WL is a word line, Vdd is a power supply line, Vss is a ground potential line, 111 and 112 are transfer transistors for accessing memory cells, and 113 and 114 are for holding data in memory cells Drive transistors for driving the storage node, 115 and 116 are load transistors for supplying electric charges to hold memory cell data, and 117 and 118 are storage nodes. Reducing the power supply voltage is the simplest and most effective method to reduce the power consumption of the circuit, but at low power supply voltage, the transistor current decreases, causing problems such as a decrease in operation speed and a decrease in operation stability. There is.

  Patent Document 1 discloses a technique for increasing the current when each transistor is on by connecting the transfer transistor of the SRAM memory cell and the back gate of the drive transistor to the gate. Patent Document 2 discloses a technique in which the back gates of six transistors constituting an SRAM memory cell are connected to the gates to increase the current when each transistor is on. In Patent Document 3, when the back gate of the transfer transistor and the drive transistor of the SRAM memory cell or the SOI (Silicon on Insulator) structure is used, the layer below the buried oxide film is connected to the word line, and the word line is A technique for increasing the currents of drive transistors and transfer transistors in an activated memory cell is disclosed.

  As a representative example of the pass transistor logic circuit described in the twelfth embodiment, Neil H. et al. E. Non-Patent Document 1 by Weste and Kamran Eshraghin.

JP 2000-114399 A JP 2000-353340 A Japanese Patent Laid-Open No. 11-16363 Neil H. E. Weste, Kamran Eslaghin “PRINCIPLE OF CMOS VLSI DESIGN, A System Perspective”, SECOND EDITION, p. 304-307

  The power supply voltage of LSI is decreasing due to low power consumption of LSI (Large Scale Integrated circuit) and miniaturization of transistors in the LSI. For example, in a 130 nm process, an LSI that operates with a power supply voltage of 1.2 V is manufactured. When the power supply voltage is lowered, the operation stability at the time of write / read operation is lowered in the SRAM circuit, and the operation becomes difficult. Further, since the current of the transistors constituting the memory cell is reduced, the operation speed is also reduced. When the driving power, that is, the current of each transistor constituting the memory cell changes, the performance of writing, reading stability, and operation speed changes. Therefore, if the performance of each transistor constituting the memory cell can be appropriately controlled, the performance of each transistor can be improved. In the first and second conventional examples, there is disclosed a technology for realizing low voltage operation by controlling the performance of a transistor by connecting the back gate of an appropriate transistor in the SRAM memory cell to the gate. When a voltage higher than that of the source electrode is applied to the back gate of the n-channel bulk CMOS transistor, the threshold voltage (Vth) of the transistor can be controlled to be low.

  However, if the back gate of a bulk CMOS transistor is applied with a potential of 0.5 V or higher at room temperature and about 0.2 V or higher at high temperature, a large junction current flows at the PN junction portion of the transistor, increasing power consumption. There's a problem. Therefore, in the first and second conventional examples, a circuit with a power supply voltage of 0.2 V or less is effective without an increase in power consumption, but in a circuit with a power supply voltage higher than that, the power consumption due to the junction current increases. Therefore, there is a problem that reduction in power consumption is hindered. In the third conventional example, a configuration in which the Vth of a transistor is controlled using an SOI structure transistor is disclosed. By controlling the potential of the layer under the buried oxide film with the SOI structure, it is possible to control the Vth of the transistor by suppressing an increase in extra current, and thus it is possible to reduce the power supply voltage of the SRAM while suppressing an increase in power consumption. Become. However, since the Vth of the drive transistor and the transfer transistor are simultaneously reduced by the activation of the word line, the Vth of the drive transistor connected to the storage node holding the “H” data is lowered, and the SRAM operates stably. There is a problem of impairing sex. Further, since the capacity of the back gate of the transfer transistor and the driving transistor is added to the word line, there is a problem that the parasitic capacity of the word line increases and the operation speed is lowered.

  The SRAM memory cell is composed of SOI transistors, and by appropriately controlling the potential of the well layer under the buried oxide (BOX) layer of each transistor, the current of each transistor is changed to change each performance of the SRAM. It becomes possible to improve. Since the well layer is electrically insulated from the SOI layer in which the transistor is formed by the BOX layer, excessive leakage current does not increase. Furthermore, if a well contact is appropriately formed, the memory cell area does not increase. In addition, by selectively applying power supplies of two types of voltages to specific nodes in the memory, it is possible to change each transistor current and improve each performance. Further, since the load on the word line is not increased, the operation speed is not lowered.

  According to the present invention, it is possible to reduce the voltage, power consumption, and speed of the SRAM circuit.

1 is a schematic diagram of a circuit configuration of an SRAM memory cell to which the present invention is applied. 1 is a schematic cross-sectional view of a transistor structure used in the present invention. The figure which shows the equivalent circuit of the transistor used by this invention. 1 is a schematic diagram of a layout of an SRAM memory cell to which the present invention is applied. 1 is a cross-sectional view of an SRAM memory cell to which the present invention is applied. Schematic of the process at the time of manufacturing the memory cell to which this invention was applied. 1 is a schematic diagram of a layout of an SRAM memory cell to which the present invention is applied. 1 is a cross-sectional view of an SRAM memory cell to which the present invention is applied. 1 is a schematic diagram of a layout of an SRAM memory cell to which the present invention is applied. The figure showing the layout of a memory cell, and the shape of the diffused layer after manufacture. 1 is a schematic diagram of a circuit configuration of an SRAM memory cell and a word driver to which the present invention is applied. 1 is a schematic diagram of a circuit configuration of an SRAM memory cell to which the present invention is applied. 1 is a schematic diagram of a circuit configuration of an SRAM memory cell to which the present invention is applied. 1 is a schematic diagram of a circuit configuration of an SRAM memory cell to which the present invention is applied. 1 is a schematic diagram of a circuit configuration of an SRAM memory cell to which the present invention is applied. 1 is a schematic diagram of a circuit configuration of an SRAM memory cell to which the present invention is applied. 1 is a schematic diagram of a circuit configuration of an SRAM memory cell to which the present invention is applied. 1 is a schematic diagram of a circuit configuration of an SRAM memory cell to which the present invention is applied. 1 is a schematic diagram of a circuit configuration of an SRAM memory cell to which the present invention is applied. 1 is a schematic diagram of a circuit configuration of an SRAM memory cell to which the present invention is applied. 1 is a schematic diagram of a circuit configuration of an SRAM memory cell and a word driver to which the present invention is applied. 1 is a schematic diagram of a circuit configuration of an SRAM memory cell, a word driver, and a source line control circuit to which the present invention is applied. 1 is a schematic diagram of a circuit configuration of an SRAM memory cell to which the present invention is applied. 1 is a schematic diagram of a layout of an SRAM memory cell to which the present invention is applied. 1 is a schematic diagram of a layout of an SRAM memory cell to which the present invention is applied. 1 is a cross-sectional view of an SRAM memory cell to which the present invention is applied. 1 is a cross-sectional view of an SRAM memory cell to which the present invention is applied. 1 is a schematic diagram of a circuit configuration of an SRAM peripheral circuit to which the present invention is applied. 1 is a schematic diagram of a circuit configuration of an SRAM peripheral circuit to which the present invention is applied. 1 is a schematic diagram of a circuit configuration of an SRAM peripheral circuit to which the present invention is applied. 1 is a schematic diagram of a circuit configuration of an SRAM peripheral circuit to which the present invention is applied. 1 is a schematic diagram of a system LSI equipped with an SRAM to which the present invention is applied. 1 is a schematic diagram of a circuit configuration of a conventional SRAM memory cell. 1 is a schematic diagram of a circuit configuration of a DRAM peripheral circuit to which the present invention is applied. 1 is a schematic diagram of an SRAM macro to which the present invention is applied. The figure showing the voltage relationship of the power supply of SRAM with which this invention was applied.

[Example 1]
FIG. 1 shows a circuit diagram of an SRAM memory cell using the present invention. In FIG. 1, BL and BLB are bit lines, WL is a word line, Vdd is a power supply line, Vss is a ground potential line, 1 and 2 are transfer transistors for accessing the memory cells, and 3 and 4 are memory cell data. Driving transistors for driving the storage node for holding, 5 and 6 are load transistors for supplying charges for holding the memory cell data, and 7 and 8 are storage nodes for storing the data. For example, Vdd is 1.2V, and Vss is 0V. FIG. 2 shows a schematic diagram of a cross section of a transistor used in the circuit of FIG. In FIG. 2, 11 is a gate, 12 is a drain, 13 is a source, 14 is a well layer under the BOX layer, 15 is a support substrate, 16 is a buried oxide film (BOX) layer, and 17 is an element isolation region. This transistor has a fully depleted SOI (FD-SOI) transistor structure, and controls the potential of the well layer to control the back gate potential of the bulk CMOS transistor. It is possible to control Vth. Further, since the well layer is separated from the diffusion layers such as the source and drain of the transistor by a BOX layer which is an insulating film, no current flows between the well and the diffusion layer even if the potential of the well is changed. FIG. 3 shows an equivalent circuit of the transistor structure of FIG. Reference numeral 11 denotes a gate, 12 denotes a drain, 13 denotes a source, and 14 denotes a well. The well is separated from a semiconductor region serving as a back gate by a bulk CMOS transistor by a capacitance. Hereinafter, this well 14 will be referred to as the back gate of the transistor of FIG. In FIG. 1, a transistor having this structure is used.

  In the memory cell of FIG. 33, a read operation in the case where “L” data is stored in the storage node 117 and “H” data is stored in the storage node 118 will be described. When reading is performed, the bit lines BL and BLB are precharged to the “H” potential. When the word line WL becomes “H” potential after the precharge is completed, the transfer transistors 111 and 112 are turned on, and the charge of the bit line BL in “H” is transferred from the transfer transistor 111 to the storage node 117 and the drive transistor 113. When the BL potential reaches a level that can be amplified by the sense amplifier, the sense amplifier connected to the bit line is activated, but the data in the memory cell is amplified. Is output. Here, paying attention to the path through which the charge of the bit line is discharged, the storage node 117 is at 0V which is “L” level immediately before the start of the read operation, but when the read operation is started, the storage node 117 Since the resistance between the BL and Vss is divided by the transfer transistor 111 and the drive transistor 113, the potential of the storage node 117 becomes a positive potential such as 0.3V. Here, when this potential is increased, the conductance of the nMOS transistor whose storage node 117 is connected to the gate is increased, and the conductance of the pMOS transistor whose storage node 117 is connected to the gate is decreased. Thus, the potential of the storage node 118 is lowered. Further, the potential increase of storage node 118 is fed back to storage node 117, and the data stored in the memory cell is destroyed by this repetition. In a normal memory cell, the ratio of the conductance of the driving transistor and that of the transfer transistor is designed to take a large value such as 1.5, and the potential of the storage node 117 rises until the data stored in the memory cell is destroyed. Never do. However, due to the recent miniaturization of the transistor manufacturing process, the variation in transistor performance tends to increase, and a memory cell having a conductance ratio lower than that at the time of design is manufactured, and the operational stability at the time of reading tends to decrease. Further, when the power supply voltage is lowered to reduce power consumption, the logical threshold voltage of the inverter composed of the nMOS transistor and the pMOS transistor whose storage node 117 is connected to the gate is lowered, and feedback for destroying data is provided. This is likely to occur, and this also reduces the operational stability during reading.

  In the circuit of the present invention shown in FIG. 1, the operation similar to that shown in FIG. 33 is performed in consideration of the read operation when “L” data is stored in the storage node 7 and “H” data is stored in the storage node 8. Do. However, since the back gate of the driving transistor 3 is connected to the gate, a so-called forward bias is applied to the driving transistor 3, and the Vth of the driving transistor 3 decreases and the conductance increases. When the cage word line is turned on, the potential rise of the storage node 7 is reduced. Further, the load transistor 6 is in a state in which a forward bias is applied, but the drive transistor 4 has the back gate potential equal to the source potential. Therefore, the inverter composed of the load transistor 6 and the drive transistor 4 Since the logic threshold voltage is higher than that when the load transistor 6 is not forward-biased, even when the potential of the storage node 7 rises, feedback that destroys data is unlikely to occur. As described above, the configuration in which the back gates of the load transistor and the drive transistor are connected to the gate has high operation stability at the time of reading, is resistant to variations, and is suitable for operation at a low voltage. Furthermore, in the present invention, when a potential such as 1.2V is applied in the forward direction when the gate and the back gate are connected, no current flows from the well to the diffusion layer by the insulating film, so that a PN of 0.5V or more Even a high voltage that turns on the junction can be applied without an increase in power consumption.

  FIG. 4 shows a layout diagram of the present memory cell. In FIG. 4, 1 and 2 are transfer transistors, 3 and 4 are drive transistors, 5 and 6 are load transistors, 21 is a contact, 22 is a gate electrode, 23 is a diffusion region, and a range surrounded by a dotted line is one It is a memory cell. The gate and the back gate are connected by a contact whose gate is arranged under the gate electrode between the common drive transistor and load transistor.

  FIG. 5 shows an outline of a cross section when FIG. 4 is cut along AA. In FIG. 5, 21 is a contact, 22 is a gate electrode, 24 is an insulating film, 25 is an SOI layer, 26 is a buried oxide film, 27 is a well layer, 28 is an element isolation layer, and 29 is a support substrate. The SOI layer in which the channel is formed is insulated from the well layer by a buried oxide film. Thus, even when a forward bias in the bulk CMOS transistor is applied to the well layer, no current flows from the well to the source electrode. The gate and the back gate are insulated from other electrodes and connected.

  FIG. 6 shows a schematic diagram in the case of sequentially following the manufacturing process in manufacturing the cross-sectional configuration of FIG. In FIG. 6, 25 is an SOI layer, 26 is a buried oxide film, 27 is a well layer, 28 is an element isolation, 29 is a support substrate, 30 is an insulating film, and 31 is a metal contact. FIG. 6A shows a state after the element isolation region is formed. When an oxide film such as SiO2 is formed on the surface, the state shown in FIG. Here, when the contact hole is formed by etching or the like, the state shown in FIG. A metal material to be a contact material such as tungsten is deposited in the contact hole, and the state shown in FIG. Furthermore, when a gate electrode is formed on this, it will be in the state of FIG.6 (e), and a back gate and a gate electrode will be connected.

In the memory cell of FIG. 33, an operation in the case where “H” data is stored in the storage node 117 and reverse data is written when “L” data is stored in the storage node 118 will be described. The bit line BL is set to “L” level, the bit line BLB is set to “H” level, the word line potential is set to “H” level, and the transfer transistor is turned on. The charge of the storage node 117 is discharged through the transfer transistor 111, and the potential of the storage node 117 drops from the “H” level. When the potential of 117 becomes lower than the logical threshold value of the inverter constituted by the load transistor 116 and the drive transistor 114, the potential of the storage node 118 that has been at the “L” level rises, and feedback between the storage nodes also acts. Thus, new data is written into the memory cell. As described above, in the SRAM memory cell, writing is performed by discharging the charge of the storage node at the “H” level by the transfer transistor. However, since the charge is discharged by the transfer transistor, the charge is supplied from the load transistor at the same time. In order to finish the writing operation, it is necessary to extract the charge more than the transfer transistor supplies the load transistor.
Therefore, when the conductance of the load transistor increases, the time required for writing increases, and when the value exceeds the design value due to variations or the like, writing may not be possible. In order to compensate for these, it is necessary to reduce the conductance of the load transistor or increase the conductance of the transfer transistor.

  In this embodiment, since the back gate of the load transistor is connected to the gate and the conductance is increased, the writing time is delayed as compared with the conventional memory cell. Normally, when performing a read operation, after the memory cell operates, the sense amplifier is activated to amplify the data and output the data to the outside, whereas the write operation changes the data in the memory cell Since the operation ends at that time, it is possible to take a longer time compared to the read operation, and there are many cases where there is no problem with an increase in the write time. Further, when there is a problem that the writing time is delayed, the writing time can be shortened by adopting the structure of the memory cell shown in FIG. In this configuration, the back gate of the driving transistor is connected to the gate as in FIG. 1, so that the stability during reading is improved. At the same time, since the back gate of the load transistor is connected to the source electrode, the conductance of the load transistor is smaller and the writing time is faster than the circuit of FIG.

[Example 2]
FIG. 7 shows a layout diagram of an SRAM memory cell using the present invention. In the following embodiments, the same symbols are used for components that are the same as those in the first embodiment, and only different components are described. The circuit configuration of this memory cell at the transistor level is the same as that in FIG. The memory cell layout of FIG. 7 differs from the configuration of FIG. 4 in that the back gate contacts of the drive transistor and the load transistor are formed below the contacts connecting the gate electrode and the metal layer. As a result, the contact formed between the drive transistor and the load transistor is not necessary, and the memory cell area can be reduced.
In particular, when a memory cell is composed of bulk CMOS transistors, it is necessary to separate the wells of the drive transistor and the load transistor, so that a certain distance is necessary for the well separation between the respective transistors. Since well separation is not required, the distance between the portions can be reduced, and the area can be made smaller than that of a memory cell using a bulk CMOS transistor.

  FIG. 8 shows an outline of a cross section when FIG. 7 is cut along AA. A well layer common to the drive transistor and the load transistor is connected to the gate by a contact formed under a contact connecting the gate and the upper layer. This structure can be manufactured in the same process as in FIG.

[Example 3]
FIG. 9 shows a layout diagram of an SRAM memory cell using the present invention. The transistor level circuit diagram of the memory cell of FIG. 9 is the same as FIG. The difference from the first embodiment is that the gate width (W size) of the drive transistor is equal to the W size of the transfer transistor.
Generally, in the SRAM memory cell, as shown in the first embodiment, the conductance of the drive transistor needs to be larger than the conductance of the transfer transistor in order not to raise the potential of the storage node at the “L” level at the time of reading. . In a memory cell using a bulk CMOS transistor, the conductance is generally adjusted by the W size, and the W size of the driving transistor is designed to be about 1.5 times the W size of the transfer transistor. In this embodiment, since the conductance when the back gate of the drive transistor is connected to the gate and the drive transistor is on is larger than the conductance of the transfer transistor, it is not necessary to adjust the conductance according to the W size. And the transfer transistor W size can be made equal. The greatest advantage of equalizing the W size of the drive transistor and transfer transistor is that the shape of the diffusion layer of the drive transistor and transfer transistor formed in a straight line is long, that is, there is no unevenness at the end of the diffusion layer, and diffusion The shape of the layer edge is a straight line. In the case of the conventional layout, the end of the diffusion layer has an uneven shape bent at a right angle in the layout diagram. FIG. 10A shows the diffusion layer and the gate electrode in the layout state. 32 is a transfer transistor, and 33 is a drive transistor. FIG. 10B shows the shape of the diffusion layer when an LSI is actually manufactured from this layout. A gate electrode is also shown for reference. When the transistor is actually manufactured, the gate electrode has a rounded shape, but is shown in a rectangular shape in this figure for easy understanding. It can be seen that the shape of the diffusion layer actually manufactured has irregularities at the end of the diffusion layer, but unlike the layout diagram, the end of the diffusion layer does not bend at a right angle and has a rounded shape. In such a shape, if the gate electrode moves slightly up and down due to factors such as mask displacement during LSI manufacturing, or if the shape of the diffusion layer edge slightly changes, the gate width is This results in a different value, which causes the performance degradation of the SRAM memory cell. In the layout shown in this embodiment, since the end of the diffusion layer is manufactured in a completely linear shape, unevenness does not easily appear at the end of the diffusion layer, and the gate width is kept at the design value even if the gate electrode moves slightly up and down. Is possible. Therefore, the memory cell of this embodiment is a memory cell that is resistant to manufacturing variations at the time of manufacturing and has little deterioration in performance. In addition, since the memory cell using the conventional bulk CMOS transistor needs to have a W size ratio of the drive transistor and the transfer transistor, the drive transistor W size can be manufactured even if the transfer transistor can be manufactured with the minimum W size. Had to be bigger than that. In this embodiment, since both the drive transistor and the transfer transistor can be made the smallest W-size transistor that can be manufactured, the memory cell area can be made smaller than that of the conventional memory cell.

[Example 4]
FIG. 11 shows a circuit diagram of an SRAM using the present invention. Vddh is a power supply voltage higher than Vddl. For example, when Vddl is 1.0V, Vddh is set to 1.2V. In this embodiment, the circuit configuration is the same as that of the first embodiment, but the “H” level potential of the word line is higher than the “H” level potential of the bit line and the source line potential of the load transistor of the memory cell. Is also at a high potential. When the “H” potential of the word line increases, the conductance of the transfer transistor increases, the memory cell current increases, and the operation speed of the memory cell increases. However, in the conventional memory cell, when the conductance of the transfer transistor is increased, there is a problem that operation stability at the time of reading is lowered. In the memory cell of the present invention, the back gate of the drive transistor is connected to the gate, and the conductance when the drive transistor is on is large. Therefore, the conductance of the transfer transistor that increases as the word line voltage increases. It is possible to suppress a decrease in reading stability due to the influence of the above, and it is possible to maintain a large operational stability during reading. Furthermore, since the conductance of the transfer transistor is large, the writing speed is increased. As described above, the memory cell according to the present invention is a memory cell that can operate at high speed and has high operational stability. In an SRAM circuit, much power is consumed in a circuit for transferring data from a bit line and a memory cell to an input / output circuit existing outside the memory circuit, and a word line and a power supply line (load transistor of the load transistor) in the memory cell. The power consumed by the source line is about 1% of the power consumption of the entire SRAM. Therefore, even if a high voltage is applied to the word line to increase the power consumption in the word line portion, the power consumption of the entire SRAM is not greatly affected.

  In this embodiment, a high voltage is applied to the word line, but only the word driver 41 that drives the word line is actually applied with the high voltage. The word driver is written as an inverter circuit composed of one n-channel type transistor and one p-channel type transistor, but may actually be composed of a NAND circuit or a NOR circuit. Even if the circuit changes, the effect of the present invention does not change. In addition, the back gate of the inverter circuit is connected to the gate, but this is also a configuration that depends on the performance that is important when designing, and a configuration in which the back gate of the inverter circuit is connected to the power supply is also conceivable. The effect is similar.

  As a method of generating the high voltage Vddh, there is a method of increasing the voltage from Vddl by installing a charge pump, a method of generating by stepping down from the high power supply voltage used in the input / output circuit, a high power supply and a low power supply from outside the LSI. Various methods such as a method of supplying two kinds of power sources are conceivable. In the present invention, the effect of improving the performance of the memory cell can be obtained regardless of the method of generating Vddh.

  Furthermore, this embodiment can achieve a high speed of the write operation. However, when a higher speed is required, the “H” level potential of the word line WL is set to the Vdd potential in the circuit of FIG. If the configuration is made higher than this, since the conductance of the load transistor does not increase, it is possible to improve both the stability during reading and the operation speed during writing and reading.

[Example 5]
FIG. 12 shows a circuit diagram of an SRAM using the present invention. Vddh is a power supply voltage higher than Vddl. In this embodiment, the circuit configuration is the same as that of the first embodiment, but the "H" level potential of the word line and the source line of the load transistor of the memory cell The potential is higher than the “H” level potential of the bit line. Compared to the fourth embodiment of FIG. 11, the difference is that the power supply voltage of the inverter for holding data is higher. As a result, the conductance of the drive transistor and the load transistor is increased, and the operation stability at the time of reading is improved. Therefore, in this embodiment, operation stability and high-speed operation are achieved.
In addition, since the conductance of the load transistor is increased, when the writing time becomes a problem, the writing time can be increased by using the circuit shown in FIG. In the circuit of FIG. 15, since the back gate of the load transistor is connected to the source electrode, the forward bias is not applied and the conductance does not increase, so that the writing speed is improved.

  FIG. 36 shows changes in potential when the potential of Vddh is changed depending on the state of the SRAM. In the ACT state, which is a so-called active state in which the memory is accessed, Vddh is at a higher potential than Vddl. In contrast, when the memory cell is in the so-called standby state STBY, Vddh is set to the same potential as Vddl. In an LSI with low power consumption that requires a reduction in leakage current, when the transistor microfabrication technology advances and the manufacturing process generation after 90 nm is reached, it flows through the gate oxide film in addition to the subthreshold current that has been a problem as a leakage current until then. Gate leakage current becomes a problem. Since the gate leakage current decreases by an order of magnitude when the applied voltage decreases by about 0.1 V, it is important to reduce the power supply as much as possible when it is unnecessary. In a circuit where low power consumption is not a problem, the control of the voltage Vddh is not always necessary.

[Example 6]
FIG. 13 shows a circuit diagram of an SRAM memory cell using the present invention. Vddh is a power supply voltage higher than Vddl. In this embodiment, the circuit configuration is the same as that of the first embodiment, but the source line potential of the load transistor of the memory cell is higher than the “H” level potential of the bit line and the word line. Yes. Compared with the fifth embodiment of FIG. 12, the "H" level potential of the word line is lower. In general, in an SRAM circuit, the ratio of power consumed by word lines to the total power consumption is small, but the number of word lines activated simultaneously is large, the number of bit lines activated simultaneously is small, etc. In an SRAM having a circuit configuration, power consumption on a word line may occupy a large proportion of the total power consumption. In this embodiment, since the “H” level potential of the word line is low, the power consumption can be kept low. In addition, because the back gate and gate of the transistor that constitutes the inverter that holds the data in the memory cell are connected and a high voltage is applied to the power supply of the inverter that holds the data, stability during reading Is a high memory cell.
When the writing speed is low, the writing speed can be increased by connecting the back gate of the load transistor to the source electrode.
The control of Vddh can be performed in the same manner as in the fifth embodiment.

[Example 7]
FIG. 16 shows a circuit diagram of an SRAM memory cell using the present invention. In the memory cell shown in FIG. 16, the back gates of all six transistors constituting the memory cell are connected to the gate electrodes of the respective transistors. As a result, the current when turned on is increased, the operation speed is increased, and the operation stability is high. The circuit of FIG. 16 differs from the circuit of FIG. 1 as the first embodiment in that the back gate of the transfer transistor is connected to the gate electrode, and the circuit of this embodiment has a load on the word line of FIG. Bigger than. Therefore, when the same word driver is used, the rise of the word line is delayed, and in order to speed up the rise of the word line, it is necessary to use a word driver having a large size. However, since the memory cell current, which is the current for driving the bit line, is increased, the time required for driving the bit line is shortened. Therefore, when the time for driving the bit line is longer than the time for driving the word line in the operation of the memory, the configuration of the present embodiment becomes faster.

  Also in the circuit configuration of this embodiment, as shown in the first to sixth embodiments, the "H" level potential of the word line WL and the source line potential of the load transistor are set to the "H" level of the bit line. Memory cell configurations higher than the potential are conceivable, and there are similar advantages, such as higher speed and improved operation stability of the memory cells. In order to achieve high speed at the time of writing, a configuration in which the back gate of the load transistor is connected to the source electrode is also conceivable.

  FIG. 17 shows a typical configuration when two types of power supply voltages and the back gate of the load transistor are connected to the source electrode. In this configuration, the conductance of the drive transistor is large due to the application of a high voltage and the back gate bias connected to the gate, and the operation stability at the time of reading is high and the operation speed is high. Further, the transfer transistor also has a large conductance and a high operating speed due to the back gate bias effect connected to the gate. Further, since the conductance of the load transistor does not become too high by connecting the back gate to the source electrode, the writing speed is also increased.

  FIG. 18 shows a circuit in which the “H” level potential of the word line is changed to a higher voltage from FIG. The drive transistor has a sufficiently high conductance due to the effect of a high voltage and a back gate bias connected to the gate. Therefore, even when the conductance of the transfer transistor is increased, the stability during reading is maintained. Further, since the conductance of the transfer transistor is high, the operation speed becomes high.

[Example 7]
FIG. 19 shows a circuit diagram of an SRAM memory cell using the present invention. The memory cell shown in FIG. 19 differs from the circuit of FIG. 1 of the first embodiment in that the back gate of the transfer transistor is connected to the source electrode. With this configuration, Vth of the transfer transistor connected to the storage node in which “H” data is held is lowered, so that the writing speed for performing the operation of lowering the “H” potential to “L” is improved. In addition, since the Vth of the transfer transistor connected to the storage node holding “H” data is lowered, the normal SRAM circuit performs the read operation by precharging the bit line to the power supply voltage. As is used in the above, it is possible to perform a read operation by precharging the voltage to about ½ of the power supply voltage. Here, considering the read operation of the SRAM, the potential of the bit line precharged to “H” through the “L” storage node of the selected memory cell is lowered, and the potential difference from the opposite bit line is designed. The sense amplifier is activated when the value reaches the specified value, and the potential difference is amplified. Here, if the potential of the bit line that should be the “H” potential is lowered through the storage node storing “L” of the memory cell due to the leakage current of the transfer transistor of the memory cell that is not selected, the bit line between the bit lines There is a problem that it takes time until the potential difference is made, and the reading speed is slow, or in the worst case, the reading operation cannot be performed, and this is called bit line offset. This is a problem that occurs when the Vth of the unselected transfer transistor is lowered. In the case of the circuit of the present embodiment, only the transfer transistor on the side holding the “H” data has the Vth lowered, so there is no leakage current to the “L” node and the bit line offset The problem does not occur.

  Also in the circuit configuration of this embodiment, as shown in the first to sixth embodiments, the "H" level potential of the word line WL and the source line potential of the load transistor are set to the "H" level of the bit line. Memory cell configurations higher than the potential are conceivable, and there are similar advantages, such as higher speed and improved operation stability of the memory cells. In order to achieve high speed at the time of writing, a configuration in which the back gate of the load transistor is connected to the source electrode is also conceivable.

  In particular, in the configuration shown in FIG. 20, since the “H” level potential of the word line WL is high, the conductance of the transfer transistor is increased, and not only the write time but also the read time can be shortened. The speed can be improved.

[Example 8]
FIG. 21 shows a circuit diagram of an SRAM using the present invention. FIG. 41 shows a word driver, and shows that a potential lower than Vss, which is Vssl, is output as the “L” potential of the word line WL.
In this circuit configuration, the transfer transistor is always back-biased, and the operation speed is high. However, since the transfer transistor is always in a back-biased state, the leakage current of the transfer transistor is large, and the problem of the bit line offset described in the seventh embodiment occurs, which hinders the read operation. In order to avoid this, by setting the “L” level potential of the word line to a potential lower than the Vss potential, the gate-source potential of the transfer transistor becomes a negative value and the leakage current of the unselected word line is reduced. is doing.

  In the configuration of this embodiment, the deactivated word line potential is set to a potential lower than Vss, but the Vth of the transfer transistor is high, and even if the Vth is lowered by the forward bias, the problem of bit line offset does not occur. In this case, it is not necessary to set the word line potential in the inactivated state lower than Vss, and it is possible to operate at a potential equal to Vss without any problem.

[Example 9]
FIG. 22 shows a circuit diagram of an SRAM using the present invention. In FIG. 22, SL is the source line of the driving transistor in the memory cell, and all the lines in the memory cell having the same word line are connected. MC is an SRAM memory cell, and 42 is a potential control circuit. Also in this embodiment, the transfer transistor in the memory cell is in a state in which a forward bias is applied, the conductance is large, and the operation speed is increased. When the word line is activated, the transistor that functions as a switch in the potential control circuit 42 is turned on, and the potential of SL becomes the Vss potential, so that the memory cell operates normally. When the word line is in an inactive state, the switch in the potential control circuit 42 is turned off, and the potential of SL rises from the Vss potential. Here, due to the resistance, the potential of SL becomes a low potential such as 0.3 V so that data stored in the memory cell is not destroyed. When the potential of SL increases, the potential of the storage node storing “L” in the memory cell increases, so that the source potential of the transfer transistor connected to the storage node storing “L” increases. In addition, since the gate-source voltage of the transfer transistor becomes negative and the back gate-source voltage becomes small, the leakage current of the transfer transistor decreases. Therefore, the leakage current of the inactive transfer transistor is reduced, and the problem of bit line offset that occurs when a forward bias is applied to the transfer transistor is solved. In FIG. 22, the potential control circuit 42 includes an n-channel transistor serving as a power switch and a resistor. In this circuit, the SL potential may be set higher than the Vss potential when not selected so that the data in the memory cell is not damaged. Therefore, a configuration using a diode instead of a resistor is also conceivable. A configuration in which a resistor and a diode are connected in parallel or in series and placed between SL and Vss is also conceivable. Further, a configuration is possible in which the potential of the SL is controlled by using a transistor as a resistor or a diode without using a resistor or a diode. As described above, the potential control circuit 42 may have various configurations. However, since the effect is the same as long as the potential of SL can be controlled to a potential higher than Vss, it is not particularly illustrated here.

[Example 10]
FIG. 23 shows an SRAM memory cell circuit using the present invention. In this embodiment, one memory cell is composed of four transistors. In FIG. 23, reference numerals 51 and 52 denote transfer transistors having a function of accessing a storage node from a bit line and a function of charging the storage node to “H”, and 53 and 54 drive a storage node of “L”. The drive transistors 55 and 56 are storage nodes for storing data, WL is a word line, BL and BLB are bit lines, and Vss is a power supply line of “L”. In this circuit, a data holding operation in the case where “H” data is stored in the storage node 55 and “L” data is stored in the storage node 56 will be described. During the data holding operation, the word line WL and the bit lines BL and BLB are all driven to the “H” potential. Since the transfer transistor 51 has a back gate of “L”, a forward bias is applied, and Vth is lowered. Therefore, a leak current flows from the bit line BL to the storage node 55 through the transfer transistor 51, and the “H” potential of the storage node is maintained. Since the back gate of the drive transistor 53 has the same potential as the source electrode, Vth does not change and the leakage current is small, so that the “H” level of the storage node 55 is maintained. The drive transistor 54 has a back gate potential of “H” and is in a state in which a forward bias is applied. Therefore, Vth is lowered and the “L” level of the storage node 56 can be strongly held. Since the back gate of the transfer transistor 52 is at the “H” level, the leakage current is small and the influence on the “L” level of the storage node 56 is small.
Thus, this memory cell is a memory cell that is stable and has a small leakage current that flows unnecessarily. The layout of this memory cell is shown in FIG.

In FIG. 24, 21 is a contact, 22 is a gate electrode, 23 is a diffusion layer, 51 and 52 are transfer transistors, 53 and 54 are drive transistors, and a dotted line represents one memory cell. FIG. 25 shows a memory cell layout showing a gate electrode, a contact, and a well layer. 57 is a well layer. The wells of the transfer transistor 51 and the drive transistor 53, and the transfer transistor 52 and the drive transistor 54 are integrally formed and connected to the storage node. FIG. 26 shows an outline of a cross-sectional view when this memory cell is cut along the plane AA.
From this, it can be seen that the wells of the transfer transistor 52 and the drive transistor 54 are formed integrally. FIG. 27 shows an outline of a cross-sectional view when the memory cell is cut along the plane BB. A well contact is formed under the gate contact, thereby suppressing an increase in memory cell area due to the well contact. The well layer extends from the bottom of the diffusion layer in the lateral direction to the bottom of the gate electrode of the driving transistor for holding reverse data. As described above, since the memory cell of this embodiment uses as few as four transistors, the area can be reduced to less than two-thirds compared with an SRAM memory cell using six transistors, which improves the area efficiency. Excellent.

[Example 11]
FIG. 34 shows a DRAM memory cell using the present invention. RWL is a read word line, RBL is a read bit line, WWL is a write word line, WBL is a write bit line, 121 is a read access transistor used for reading, 122 is a write access transistor used for writing, and 123 is A drive transistor for storing data. Since a capacity is added to the back gate of the driving transistor, it is not necessary to newly provide a capacity for data storage, and the memory cell area can be reduced. In addition, by connecting the gate and back gate of the access transistor, the Vth of the transistor is lowered only when it is turned on, so that the stored data is not easily broken, and conversely, the memory cell has a high access speed. .

[Example 12]
FIG. 28 shows a circuit diagram of circuit components using the present invention. FIG. 28 shows an inverter circuit, which is a high-speed inverter with little leakage current by connecting the gate and back gate of a transistor constituting the circuit. FIG. 29 shows a circuit diagram of circuit components using the present invention. FIG. 29 shows a NAND circuit, which is a high-speed NAND circuit with little leakage current by connecting the gate and back gate of the transistors constituting the circuit. Further, since the n-channel transistors are stacked in two stages, when this circuit is configured by a bulk CMOS transistor, the source potential of the n-channel transistor connected to the output out is higher than Vss, and the back gate bias Is applied, the current decreases and the speed deteriorates. In this embodiment, since the back gate is connected to the gate, the transistor that is turned on is in a state in which a forward bias is applied and can operate at high speed without a decrease in current. In this embodiment, a NAND circuit having two inputs is described, but the same effect can be obtained even in a NAND circuit having three or more inputs. FIG. 30 shows a circuit diagram of circuit components using the present invention. FIG. 30 shows a NOR circuit, which is a high-speed NOR circuit with little leakage current by connecting the gate and back gate of the transistors constituting the circuit. Further, since the p-channel transistors are stacked in two stages, when this circuit is configured by a bulk CMOS transistor, the source potential of the p-channel transistor connected to the output out is lower than Vdd, and the back gate bias is reduced. Since it is in an applied state, the current decreases and the speed deteriorates. In this embodiment, since the back gate is connected to the gate, the transistor that is turned on is in a state in which a forward bias is applied and can operate at high speed without a decrease in current. In this embodiment, a NOR circuit having two inputs is described, but the same effect can be obtained even in a NOR circuit having three or more inputs. FIG. 31 shows a circuit diagram of circuit components using the present invention. In this embodiment, the signal is transmitted by discharging the potential of the node out precharged to the potential “H” by the signal Pre by turning on in1, in2 or in3. Since the back gate of the n-channel transistor for discharging is connected to the gate, the circuit operates at high speed. In addition, since a forward bias is not applied to a transistor that is not turned on, the leakage current is small, and the out voltage is not lowered unnecessarily, so that a circuit with few malfunctions is obtained.

  In this circuit, one n-channel transistor is arranged between the node out and Vss. However, it is possible to adopt a configuration in which two or more n-channel transistors are arranged in series. In this case, similar to the NAND circuit, the conventional bulk CMOS transistor can be operated at high speed without being affected by the speed reduction due to the back gate bias effect. Similarly, when transistors are connected in series, there is no reduction in speed due to the back gate bias effect. Therefore, in the pass transistor logic circuit, the gate electrode and the back gate electrode are connected in the same way as in the circuit diagrams of FIGS. By using such a transistor, high speed operation is possible.

[Example 13]
FIG. 32 shows an outline of an LSI using the present invention. Currently, an LSI called a system LSI in which a CPU, a work memory having a large capacity, and a circuit having other functions are mounted together is manufactured. In FIG. 32, the CPU is the CPU that is the core of the processor, the CACHE is a cache memory used in the CPU, the RAM is a large-capacity work memory, and the PERI is a circuit having a specific function outside the CPU core. Yes. Since the cache memory needs to operate at the same speed as the CPU core, high speed is required. The work memory needs to have a small area because it needs to have a large capacity. Therefore, the cache memory CACHE is composed of the 6-transistor type memory cell having excellent high speed shown in the first to ninth embodiments, and the work RAM is the 4-transistor type having excellent small area characteristics shown in the tenth embodiment. Thus, it is possible to obtain a system LSI that maintains high performance as a whole.

[Example 14]
FIG. 35 shows the overall configuration of a low power SRAM circuit using the present invention. All the transistors in the circuit of the present embodiment use the transistor having the structure shown in FIG. 2, but in order to prevent the circuit diagram from becoming complicated, it is not the equivalent circuit shown in FIG. A transistor with no capacitor at the gate is used. In FIG. 35, bank0 to bank3 are banks in which memory is simultaneously accessed, Vss_mem, Vdd_wd, Vss_amp, and Vss_peri are power sources whose voltages are controlled to reduce leakage current, and PLVC1 to PLVC4 control the potentials of the above power sources. The circuits, sw1 to sw4, are signals for controlling the PLVC1 to PLVC4 and have a bus configuration. MC represents a memory cell, WA represents a write amplifier, SA represents a sense amplifier, DEC represents a peripheral circuit of a memory other than the amplifier, and PLC represents a circuit for controlling each power source. In the figure, the write amplifier WA is connected to each bit line, although it is partially interrupted for easy viewing. In this embodiment, it is possible to reduce the leakage current when the bank is not accessed by being activated only when the power supply of each bank is accessed. In particular, by using the memory cells shown in the first to tenth embodiments as SRAM memory cells of this circuit, an SRAM circuit configuration excellent in various performances such as high-speed performance, leakage performance, and memory operation stability can be obtained. Become. In particular, if the control of Vddh used in the third and subsequent embodiments is performed in common with the power supply control in each bank, it is possible to configure a high-performance SRAM circuit with less leakage current.

  1, 2, 32, 51, 52, 111, 112 ... transfer transistor, 3, 4, 33, 53, 54, 113, 114 ... drive transistor, 5, 6, 115, 116 ... load transistor, 7, 8, 55 , 56, 117, 118 ... data storage nodes in the memory cells, WL ... word lines, BL, BLB ... bit lines, Vdd ... power supply lines, Vss ... ground potential lines, 11, 22 ... gate electrodes, 12 ... drain electrodes, DESCRIPTION OF SYMBOLS 13 ... Source electrode 14, 27 ... Well, 15, 29 ... Support substrate, 16, 26 ... Embedded oxide film layer, 17, 28 ... Element isolation layer, 21, 31 ... Contact, 23 ... Diffusion layer, 24, 30 ... Insulating film, 25... SOI layer, Vddh... Power line higher than Vddl, Vddl... Power line lower than Vddh, 41... Word driver, 42. SL: source line of drive transistor in memory cell, MC: memory cell, 57: well layer in layout diagram, in, in1, in2, in3: input of logic circuit, out: output of logic circuit, Pre: precharge signal, SOC ... System LSI chip, CPU ... CPU core, CACHE ... Cache memory, RAM ... Work memory, PERI ... Logic circuit outside CPU core in system LSI, RWL ... Read word line, RBL ... Read bit line, WWL ... word line for writing, WBL ... bit line for writing, 121 ... read access transistor, 122 ... write access transistor, 123 ... data storage drive transistor, bank0 to bank3 ... memory bank, Vss_mem, Vdd_wd, Vss_amp, Vs _Peri: voltage controlled power supply, PLVC1 to PLVC4: power supply potential control circuit, sw1 to sw4 ... potential control signal, WA ... write amplifier, SA ... sense amplifier, DEC ... memory peripheral circuit other than amplifier, PLC ... power supply control signal generation Circuit, MS1, MD1, MR1... Component of power supply potential control circuit, ACT... Memory cell access period, STBY.

Claims (23)

In a static memory cell including a plurality of transistors having an FD-SOI structure in which an SOI layer is completely depleted and first and second storage nodes for holding data,
The static memory cell includes a bit line for accessing the memory,
A pair of n-channel transfer transistors respectively connected between the first and second storage nodes;
A pair of n-channel drive transistors having a source electrode connected to a ground potential line;
A semiconductor memory device comprising six transistors including a pair of p-channel load transistors whose source electrodes are connected to a first power supply line having a potential higher than the ground potential of the ground potential line.   In the static memory cell, the gate electrodes of the drive transistor and the load transistor are formed in the same linear direction, and the contact connected to the well layer of the drive transistor is between the drive transistor and the load transistor. 2. The semiconductor memory device according to claim 1, wherein the semiconductor memory device is connected to the gate electrode positioned between and to reach the well layer.   2. The semiconductor memory device according to claim 1, wherein the gate width of each of the drive transistor and the transfer transistor has the same design dimension. In the static memory cell,
The high potential (high) voltage of the word line connected to the gate electrode of the transfer transistor is higher than the high potential (high) voltage of the bit line for accessing the memory cell. The semiconductor memory device according to claim 1. In the static memory cell,
2. A potential of a first power supply line connected to a source electrode of the load transistor is higher than a voltage in a high potential state (high) of a bit line for accessing a memory cell. Semiconductor memory device.   The potential of the first power supply line is controlled to be higher than the potential of the high potential state (high) of the bit line during a period in which the memory circuit is being accessed, and is in a period in which the memory circuit is not being accessed. 2. The semiconductor memory device according to claim 1, wherein the potential of the bit line is controlled to be the same as the voltage of the high potential state (high) of the bit line. In the static memory cell,
The voltage of the high potential state (high) of the word line connected to the gate electrode of the transfer transistor is equal to the potential of the first power supply line connected to the source electrode of the load transistor, and the memory cell is accessed. 2. The semiconductor memory device according to claim 1, wherein the voltage is higher than a voltage of a high potential state (high) of the bit line. In the static memory cell,
2. The semiconductor memory device according to claim 1, wherein the well layer of the load transistor is connected to a gate electrode of the load transistor. In the static memory cell,
9. The semiconductor memory device according to claim 8, wherein the drive transistor to which the gate electrode is connected and the well layer of the load transistor are integrally formed. In the static memory cell,
The gates of the driving transistor and load transistor to which the gate electrode is connected are formed in the same straight line direction, and the contact connected to the well layer formed integrally is the gate electrode and the metal wiring The semiconductor memory device according to claim 9, wherein the semiconductor memory device is formed at a lower position of a contact connecting the two. In the static memory cell,
The high potential (high) voltage of the word line connected to the gate electrode of the transfer transistor is higher than the high potential (high) voltage of the bit line for accessing the memory cell. The semiconductor memory device according to claim 8. In the static memory cell,
2. The semiconductor memory device according to claim 1, wherein the well layer of the load transistor is connected to a first power supply line. In the static memory cell,
The voltage of the high potential state (high) of the word line connected to the gate electrode of the transfer transistor is equal to the potential of the first power supply line connected to the source electrode of the load transistor, and the memory cell is accessed. 13. The semiconductor memory device according to claim 12, wherein the voltage is higher than the voltage of the high potential state (high) of the bit line. In the static memory cell,
2. The semiconductor memory device according to claim 1, wherein the well layer of the transfer transistor is connected to a word line which is a gate electrode of the transfer transistor. In the static memory cell,
15. The potential of the first power supply line connected to the source electrode of the load transistor is higher than the voltage of the high potential state (high) of the bit line for accessing the memory cell. Semiconductor memory device. In the static memory cell,
15. The semiconductor memory device according to claim 14, wherein a well layer of the load transistor is connected to a gate electrode of the load transistor. In the static memory cell,
The voltage of the high potential state (high) of the word line connected to the gate electrode of the transfer transistor;
17. The potential of the first power supply line connected to the source electrode of the load transistor is equal and higher than the voltage of the high potential state (high) of the bit line for accessing the memory cell. The semiconductor memory device described. In the static memory cell,
2. The semiconductor memory device according to claim 1, wherein the well layer of the transfer transistor is connected to a storage node to which a source electrode of the transfer transistor is connected. In the static memory cell,
19. The semiconductor memory device according to claim 18, wherein a well layer of the load transistor is connected to a gate electrode of the load transistor. In the static memory cell,
The high potential (high) voltage of the word line connected to the gate electrode of the transfer transistor is higher than the high potential (high) voltage of the bit line for accessing the memory cell. The semiconductor memory device according to claim 18. In the static memory cell,
2. The semiconductor memory device according to claim 1, wherein the well layer of the transfer transistor is connected to a first power supply line to which a source electrode of the load transistor is connected. In the static memory cell,
22. The semiconductor memory device according to claim 21, wherein the voltage of the low potential state (low) of the word line connected to the gate electrode of the transfer transistor is lower than the ground potential of 0V. In the static memory cell,
The source line SL of the driving transistor is connected between memory cells having a common word line, and the SL is controlled to a ground potential of 0 V while the word line is in a high potential state (high).
22. The semiconductor memory device according to claim 21, wherein said word line is controlled to a voltage higher than a ground potential during a period of a low potential state (low).

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