JP2011071197A - Method of manufacturing semiconductor substrate - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method of manufacturing a semiconductor substrate for highly efficiently manufacturing a semiconductor device using SiC. <P>SOLUTION: The manufacturing method includes preparing a first silicon carbide substrate 11 having a first surface F1 and a first backside B1 opposing to each other and having a single crystal structure, and a second substrate 12 having a second surface F2 and a second backside B2 opposing to each other and having a single crystal structure. The first and second silicon carbide substrates 11, 12 are disposed so that the first and second backsides B1, B2 can be directed in the same direction. After a step of disposition, a connection layer 30 made of metal and bonded to the first and second backsides B1, B2 so as to connect the first and second backsides B1, B2 is formed. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a method for manufacturing a semiconductor substrate, and more particularly to a method for manufacturing a semiconductor substrate including a portion made of silicon carbide (SiC) having a single crystal structure.

  In recent years, SiC substrates are being adopted as semiconductor substrates used for manufacturing semiconductor devices. SiC has a larger band gap than Si (silicon) which is more commonly used. Therefore, a semiconductor device using a SiC substrate has advantages such as high breakdown voltage, low on-resistance, and small deterioration in characteristics under a high temperature environment.

  In order to efficiently manufacture a semiconductor device, a substrate size of a certain level or more is required. According to US Pat. No. 7,314,520 (Patent Document 1), a SiC substrate of 76 mm (3 inches) or more can be manufactured.

US Pat. No. 7,314,520

  The size of the SiC substrate is industrially limited to about 100 mm (4 inches). Therefore, there is a problem that a semiconductor device cannot be efficiently manufactured using a large substrate. In particular, in the case of hexagonal SiC, the above-described problem becomes particularly serious when the characteristics of a plane other than the (0001) plane are used. This will be described below.

  A SiC substrate with few defects is usually manufactured by cutting out from a SiC ingot obtained by (0001) plane growth in which stacking faults are unlikely to occur. For this reason, the SiC substrate having a plane orientation other than the (0001) plane is cut out non-parallel to the growth plane. For this reason, it is difficult to ensure a sufficient size of the substrate, or many portions of the ingot cannot be used effectively. For this reason, it is particularly difficult to efficiently manufacture a semiconductor device using a surface other than the (0001) surface of SiC.

  The present invention has been made in view of the above problems, and an object of the present invention is to provide a semiconductor substrate manufacturing method for efficiently manufacturing a semiconductor device using SiC.

The manufacturing method of the semiconductor substrate of this invention has the following processes.
A first silicon carbide substrate having a first surface and a first back surface facing each other and having a single crystal structure, and having a second surface and a second back surface facing each other and having a single crystal structure And a second silicon carbide substrate having First and second silicon carbide substrates are arranged such that each of the first and second back surfaces faces one direction. After the placing step, a connection layer made of metal is formed which is joined to the first and second back surfaces so as to connect the first and second back surfaces to each other.

  According to this manufacturing method, the first and second silicon carbide substrates are integrated as one semiconductor substrate via the connection layer. This semiconductor substrate includes both the first and second surfaces of each of the first and second silicon carbide substrates as the substrate surface on which the semiconductor device is formed. That is, this semiconductor substrate has a larger substrate surface as compared with the case where either one of the first and second silicon carbide substrates is used alone. Therefore, by using this semiconductor substrate, a semiconductor device using silicon carbide can be efficiently manufactured.

  The first and second silicon carbide substrates are made of a semiconductor, whereas the connection layer is made of a metal that is a substance having a low resistivity. Thereby, a semiconductor substrate including a portion having a resistivity smaller than the resistivity of each of the first and second silicon carbide substrates can be formed.

  Preferably, the metal forming the connection layer is made of at least one metal selected from the group consisting of molybdenum, tantalum, tungsten, niobium, iridium, ruthenium, zirconium, titanium, and nickel.

  Thereby, the heat resistance of a connection layer can be improved to about 2000 degreeC or more. Further, portions of the connection layer facing the first and second silicon carbide substrates are easily silicided, whereby the connection layer is more firmly bonded to the first and second silicon carbide substrates.

  Preferably, the connection layer has a thickness of 50 μm or more and 1 mm or less. When the film thickness is 50 μm or more, the connection layer is difficult to break. Further, when the film thickness is 1 mm or less, the thickness of the semiconductor substrate can be made suitable for a general manufacturing process of a semiconductor device.

  Preferably, the step of forming the connection layer is performed by depositing a metal from one direction.

Thereby, the connection layer can be formed by a vapor deposition method.
Preferably, the step of forming the connection layer is performed by plating a metal from one direction.

Thereby, the connection layer can be formed by a plating method.
Preferably, the step of disposing the first and second silicon carbide substrates is arranged on the metal plate made of metal and positioned in one direction with respect to the first and second silicon carbide substrates. This is performed by placing two silicon carbide substrates. Further, the step of forming the connection layer is performed by melting and solidifying the metal plate.

  Thereby, the connection layer can be formed by a simple method of melting and solidifying the metal plate.

  Preferably, the off angle of the first surface with respect to the {0001} plane of the first silicon carbide substrate is not less than 50 ° and not more than 65 °. The off angle of the second surface with respect to the {0001} plane of the second silicon carbide substrate is not less than 50 ° and not more than 65 °. Thereby, compared with the case where the 1st and 2nd surface is a {0001} plane, channel mobility in the 1st and 2nd surface can be raised.

  Preferably, the angle formed by the off orientation of the first surface and the <1-100> direction of the first silicon carbide substrate is 5 ° or less. The angle formed between the off orientation of the second surface and the <1-100> direction of the second silicon carbide substrate is 5 ° or less. Thereby, compared with the case where the 1st and 2nd surface is a {0001} plane, channel mobility in the 1st and 2nd surface can be raised.

  Preferably, the off angle of the first surface with respect to the {03-38} plane in the <1-100> direction of the first silicon carbide substrate is −3 ° to 5 °. The off angle of the second surface relative to the {03-38} plane in the <1-100> direction of the second silicon carbide substrate is −3 ° to 5 °. Thereby, compared with the case where the 1st and 2nd surface is a {0001} plane, channel mobility in the 1st and 2nd surface can be raised.

  Preferably, the angle formed by the off orientation of the first surface and the <11-20> direction of the first silicon carbide substrate is 5 ° or less. The angle formed between the off orientation of the second surface and the <11-20> direction of the second silicon carbide substrate is 5 ° or less. Thereby, compared with the case where the 1st and 2nd surface is a {0001} plane, channel mobility in the 1st and 2nd surface can be raised.

  As is apparent from the above description, according to the method for manufacturing a semiconductor substrate of the present invention, a method for manufacturing a semiconductor substrate for efficiently manufacturing a semiconductor device using silicon carbide can be provided.

It is a top view which shows roughly the structure of the semiconductor substrate in Embodiment 1 of this invention. It is a schematic sectional drawing in alignment with line II-II of FIG. It is sectional drawing which shows schematically the 1st process of the manufacturing method of the semiconductor substrate in Embodiment 1 of this invention. It is sectional drawing which shows schematically the 2nd process of the manufacturing method of the semiconductor substrate in Embodiment 1 of this invention. It is sectional drawing which shows roughly 1 process of the manufacturing method of the semiconductor substrate in Embodiment 2 of this invention. It is a fragmentary sectional view which shows schematically the structure of the semiconductor device in Embodiment 3 of this invention. It is a schematic flowchart of the manufacturing method of the semiconductor device in Embodiment 3 of this invention. It is a fragmentary sectional view which shows roughly the 1st process of the manufacturing method of the semiconductor device in Embodiment 3 of this invention. It is a fragmentary sectional view which shows schematically the 2nd process of the manufacturing method of the semiconductor device in Embodiment 3 of this invention. It is a fragmentary sectional view which shows roughly the 3rd process of the manufacturing method of the semiconductor device in Embodiment 3 of this invention. It is a fragmentary sectional view which shows schematically the 4th process of the manufacturing method of the semiconductor device in Embodiment 3 of this invention.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.
(Embodiment 1)
1 and 2, semiconductor substrate 80 of the present embodiment includes a plurality of SiC substrates 11 to 19 (silicon carbide substrate) having a single crystal structure and a connection layer 30 made of metal. Connection layer 30 is bonded to the back surfaces of SiC substrates 11 to 19 so as to connect the back surfaces of SiC substrates 11 to 19 (the surface opposite to the surface shown in FIG. 1). The SiC substrates 11 to 19 are fixed to each other by the connection layer 30. Each of SiC substrates 11 to 19 has a surface exposed on the same plane. For example, each of SiC substrates 11 and 12 has surfaces F1 and F2 (FIG. 2). Thereby, semiconductor substrate 80 has a larger surface than each of SiC substrates 11-19. Therefore, when the semiconductor substrate 80 is used, a semiconductor device using SiC can be manufactured more efficiently than when each of the SiC substrates 11 to 19 is used alone.

  Preferably, the crystal structures of SiC substrates 11 and 12 are hexagonal, and more preferably 4H—SiC or 6H—SiC.

  Next, a method for manufacturing the semiconductor substrate 80 will be described. In the following description, only the SiC substrates 11 and 12 among the SiC substrates 11 to 19 may be referred to in order to simplify the description, but the SiC substrates 13 to 19 are also handled in the same manner as the SiC substrates 11 and 12.

  Referring to FIG. 3, first, SiC substrate 11 (first silicon carbide substrate) and SiC substrate 12 (second silicon carbide substrate) having a single crystal structure are prepared. SiC substrate 11 has surface F1 (first surface) and back surface B1 (first back surface) facing each other, and SiC substrate 12 has surface F2 (second surface) and back surface B2 (second surface) facing each other. Back side). Specifically, for example, SiC substrates 11 and 12 are prepared by cutting a SiC ingot grown on the (0001) plane in the hexagonal system along the (03-38) plane. Preferably, the parallelism of SiC substrate 11 is 1 ° or less.

  Next, SiC substrates 11 and 12 are arranged on stage 81 in a processing chamber (not shown) for vapor deposition so that each of back surfaces B1 and B2 is exposed in one direction (downward in FIG. 3). Is done. That is, SiC substrates 11 and 12 are arranged so as to be aligned in plan view.

  Preferably, the above arrangement is performed such that each of back surfaces B1 and B2 is located on the same plane, or each of front surfaces F1 and F2 is located on the same plane.

  Preferably, the shortest distance between SiC substrates 11 and 12 (the shortest distance in the horizontal direction in FIG. 3) is 5 mm or less. Specifically, for example, substrates having the same rectangular shape may be arranged in a matrix with an interval of 5 mm or less.

  In order to install SiC substrates 11 and 12 at equal intervals, for example, a countersink having a size corresponding to SiC substrates 11 and 12 may be formed on stage 81. By placing the SiC substrates 11 and 12 in the countersink, the SiC substrates 11 and 12 can be installed at equal intervals.

Next, the processing chamber is evacuated, so that the pressure in the processing chamber is, for example, 10 ⁻³ Pa. Subsequently, metal is deposited from one direction (downward in FIG. 3). This vapor deposition can be carried out by heating the metal as the vapor deposition source to a melting point or higher by energizing and heating the metal.

  The connection layer 30 is formed by the above vapor deposition. Thus, the semiconductor substrate 80 is manufactured.

  According to the present embodiment, as shown in FIG. 2, SiC substrates 11 and 12 are integrated as one semiconductor substrate 80 via connection layer 30. Semiconductor substrate 80 includes both surfaces F1 and F2 of each of the SiC substrates as a substrate surface on which a semiconductor device such as a transistor is formed. That is, semiconductor substrate 80 has a larger substrate surface as compared to the case where either SiC substrate 11 or 12 is used alone. Therefore, a semiconductor device using SiC can be efficiently manufactured by using the semiconductor substrate 80.

  In addition, SiC substrates 11 and 12 are made of a semiconductor, whereas connection layer 30 is made of a metal that is a substance having a low resistivity. Thereby, a semiconductor substrate including a portion having a resistivity smaller than the resistivity of each of SiC substrates 11 and 12 can be formed. Thereby, for example, the connection layer 30 can be used as an electrode of a semiconductor device.

  Preferably, the metal forming the connection layer 30 is made of at least one metal selected from the group consisting of molybdenum, tantalum, tungsten, niobium, iridium, ruthenium, zirconium, titanium, and nickel. Thereby, the heat resistance of the connection layer 30 can be improved to about 2000 degreeC or more. In addition, since the portion of connection layer 30 facing SiC substrates 11 and 12 can be easily silicided, the connection between connection layer 30 and SiC substrates 11 and 12 can be further strengthened.

  More preferably, the metal forming the connection layer 30 is made of at least one metal selected from the group consisting of molybdenum, titanium, and nickel. Thereby, ohmic connection can be established between connection layer 30 and SiC substrates 11 and 12. Therefore, in the semiconductor device manufactured using the semiconductor substrate 80, the connection layer 30 can be used as an ohmic electrode.

  Preferably, the connection layer 30 has a film thickness of 50 μm or more and 1 mm or less. When the film thickness is 50 μm or more, the connection layer 30 is difficult to break. Further, when the film thickness is 1 mm or less, the thickness of the semiconductor substrate 80 can be set to a thickness suitable for a general manufacturing process of a semiconductor device.

  Preferably, the step of arranging SiC substrates 11 and 12 is performed such that the shortest distance between SiC substrates 11 and 12 is 5 mm or less. Thereby, connection layer 30 can be formed so as to more reliably connect back surface B1 of SiC substrate 11 and back surface B2 of SiC substrate 12.

  In the present embodiment, preferably, the off angle of surface F1 with respect to the {0001} plane of SiC substrate 11 is not less than 50 ° and not more than 65 °, and the off angle of surface F2 with respect to the {0001} plane of SiC substrate 12 is 50 It is not less than 65 ° and not more than 65 °. Thereby, the channel mobility in the surface F1 and F2 can be raised compared with the case where the surfaces F1 and F2 are {0001} planes.

  Preferably, the angle formed between the off orientation of surface F1 and the <1-100> direction of SiC substrate 11 is 5 ° or less, and the off orientation of surface F2 and the <1-100> direction of SiC substrate 12 The formed angle is 5 ° or less. Thereby, the channel mobility in the surface F1 and F2 can be raised more.

  Preferably, the off angle of the surface F1 with respect to the {03-38} plane in the <1-100> direction of the SiC substrate 11 is −3 ° to 5 °, and the {1-100> direction of the SiC substrate 12 is { The off-angle of the surface F2 with respect to the 03-38} plane is −3 ° to 5 °. Thereby, the channel mobility in the surfaces F1 and F2 can be further increased.

  In the above description, the “off angle of the surface F1 with respect to the {03-38} plane in the <1-100> direction” means the normal line of the surface F1 to the projecting plane extending in the <1-100> direction and the <0001> direction. Is an angle formed by the normal projection of the {03-38} plane, and the sign thereof is positive when the orthographic projection approaches parallel to the <1-100> direction. Is negative when approaching parallel to the <0001> direction. The same applies to the “off angle of the surface F2 with respect to the {03-38} plane in the <1-100> direction”.

  Preferably, the angle formed by the off orientation of surface F1 and the <11-20> direction of SiC substrate 11 is 5 ° or less, and the off orientation of surface F2 and the <11-20> direction of SiC substrate 12 The formed angle is 5 ° or less. Thereby, the channel mobility in the surface F1 and F2 can be raised compared with the case where the surfaces F1 and F2 are {0001} planes.

  In this embodiment, the vapor deposition method is used to form the connection layer, but other methods can be used. For example, a sputtering method can also be used. In this case, for example, the atmosphere in the processing chamber is an Ar atmosphere, and the power applied to the sputtering target is 200 to 500 W. A plating method can also be used.

(Embodiment 2)
In the present embodiment, a method for manufacturing semiconductor substrate 80 (FIGS. 1 and 2) by a simpler method than that of the first embodiment will be described. In the following, for simplification of description, only SiC substrates 11 and 12 among SiC substrates 11 to 19 (FIG. 1) may be referred to, but SiC substrates 13 to 19 are also treated in the same manner as SiC substrates 11 and 12. Is called.

  Referring to FIG. 5, metal plate 31 made of the metal described in the first embodiment is arranged in one direction (downward direction in FIG. 5) with respect to SiC substrates 11 and 12. SiC substrates 11 and 12 are placed on metal plate 31 such that metal plate 31 is in contact with each of back surfaces B1 and B2.

  Next, metal plate 31 on which SiC substrates 11 and 12 are placed as described above is put into a heating furnace (not shown). By this heating furnace, the metal plate 31 is heated to a temperature higher than the melting point of the metal. Thereby, the metal plate 31 is melted.

  Next, the temperature in the heating furnace is lowered. As a result, the melt of the metal plate 31 is re-solidified to form the connection layer 30 (FIG. 2). Thus, the semiconductor substrate 80 (FIG. 2) is manufactured.

  Since the configuration other than the above is substantially the same as the configuration of the first embodiment described above, the same or corresponding elements are denoted by the same reference numerals, and description thereof is not repeated.

  Also in the present embodiment, the same effect as in the first embodiment can be obtained. Further, the connection layer 30 can be formed by a simple method of melting and solidifying the metal plate 31.

(Embodiment 3)
Referring to FIG. 6, semiconductor device 100 of the present embodiment is a vertical DiMOSFET (Double Implanted Metal Oxide Semiconductor Field Effect Transistor), and includes substrate 80, buffer layer 121, breakdown voltage holding layer 122, p region 123, It has an n ⁺ region 124, a p ⁺ region 125, an oxide film 126, a source electrode 111, an upper source electrode 127, a gate electrode 110, and a drain electrode 112.

  Substrate 80 has n-type conductivity in the present embodiment, and has growth layer 30 and SiC substrate 11 as described in the first embodiment. The drain electrode 112 is provided on the growth layer 30 so as to sandwich the growth layer 30 with the SiC substrate 11. The buffer layer 121 is provided on the SiC substrate 11 such that the SiC substrate 11 is sandwiched between the buffer layer 121 and the growth layer 30.

Buffer layer 121 has n-type conductivity and has a thickness of 0.5 μm, for example. The concentration of the n-type conductive impurity in the buffer layer 121 is, for example, 5 × 10 ¹⁷ cm ⁻³ .

The breakdown voltage holding layer 122 is formed on the buffer layer 121 and is made of silicon carbide whose conductivity type is n-type. For example, the thickness of the breakdown voltage holding layer 122 is 10 μm, and the concentration of the n-type conductive impurity is 5 × 10 ¹⁵ cm ⁻³ .

On the surface of the breakdown voltage holding layer 122, a plurality of p regions 123 having a p-type conductivity are formed at intervals. An n ⁺ region 124 is formed in the surface layer of the p region 123 inside the p region 123. A p ⁺ region 125 is formed at a position adjacent to the n ⁺ region 124. From the top of the n ⁺ region 124 in one p region 123, the breakdown voltage holding layer 122 exposed between the p region 123 and the two p regions 123, the other p region 123, and the n ⁺ region 124 in the other p region 123 An oxide film 126 is formed so as to extend to. A gate electrode 110 is formed on the oxide film 126. A source electrode 111 is formed on the n ⁺ region 124 and the p ⁺ region 125. An upper source electrode 127 is formed on the source electrode 111.

The maximum value of the nitrogen atom concentration in the region within 10 nm from the interface between the oxide film 126 and the n ⁺ region 124, p ⁺ region 125, p region 123 and the breakdown voltage holding layer 122 as the semiconductor layer is 1 × 10 ²¹ cm ^−3. That's it. Thereby, the mobility of the channel region under the oxide film 126 (part of the p region 123 between the n ⁺ region 124 and the breakdown voltage holding layer 122, which is in contact with the oxide film 126) can be improved. .

  Next, a method for manufacturing the semiconductor device 100 will be described. 8 to 11 show only steps in the vicinity of SiC substrate 11 among SiC substrates 11 to 19 (FIG. 1), similar steps are also performed in the vicinity of each of SiC substrate 12 to SiC substrate 19. It is.

  First, in the substrate preparation step (step S110: FIG. 7), the semiconductor substrate 80 (FIGS. 1 and 2) is prepared. The conductivity type of the semiconductor substrate 80 is n-type.

  Referring to FIG. 8, buffer layer 121 and breakdown voltage holding layer 122 are formed as follows by the epitaxial layer forming step (step S120: FIG. 7).

First, the buffer layer 121 is formed on the surface of the substrate 80. Buffer layer 121 is made of n-type silicon carbide and is, for example, an epitaxial layer having a thickness of 0.5 μm. Further, the concentration of the conductive impurity in the buffer layer 121 is set to 5 × 10 ¹⁷ cm ⁻³ , for example.

Next, the breakdown voltage holding layer 122 is formed on the buffer layer 121. Specifically, a layer made of silicon carbide of n-type conductivity is formed by an epitaxial growth method. The thickness of the breakdown voltage holding layer 122 is, for example, 10 μm. The concentration of the n-type conductive impurity in the breakdown voltage holding layer 122 is, for example, 5 × 10 ¹⁵ cm ⁻³ .

Referring to FIG. 9, p region 123, n ⁺ region 124, and p ⁺ region 125 are formed as follows by the implantation step (step S 130: FIG. 7).

First, an impurity having a p-type conductivity is selectively implanted into a part of the breakdown voltage holding layer 122, whereby the p region 123 is formed. Next, n ⁺ region 124 is formed by selectively injecting n-type conductive impurities into a predetermined region, and p-type conductive impurities having a conductivity type are selectively injected into the predetermined region. As a result, a p ⁺ region 125 is formed. The impurity is selectively implanted using a mask made of an oxide film, for example.

  After such an implantation step, an activation annealing process is performed. For example, annealing is performed in an argon atmosphere at a heating temperature of 1700 ° C. for 30 minutes.

Referring to FIG. 10, a gate insulating film forming step (step S140: FIG. 7) is performed. Specifically, oxide film 126 is formed so as to cover the breakdown voltage holding layer 122, p region 123, n ⁺ region 124, and p ⁺ region 125. This formation may be performed by dry oxidation (thermal oxidation). The dry oxidation conditions are, for example, a heating temperature of 1200 ° C. and a heating time of 30 minutes.

Thereafter, a nitrogen annealing step (step S150) is performed. Specifically, an annealing process is performed in a nitrogen monoxide (NO) atmosphere. For example, the heating temperature is 1100 ° C. and the heating time is 120 minutes. As a result, nitrogen atoms are introduced in the vicinity of the interface between each of the breakdown voltage holding layer 122, the p region 123, the n ⁺ region 124, and the p ⁺ region 125 and the oxide film 126.

  Note that an annealing process using an argon (Ar) gas that is an inert gas may be performed after the annealing process using nitrogen monoxide. The conditions for this treatment are, for example, a heating temperature of 1100 ° C. and a heating time of 60 minutes.

  Referring to FIG. 11, source electrode 111 and drain electrode 112 are formed as follows by the electrode formation step (step S160: FIG. 7).

First, a resist film having a pattern is formed on the oxide film 126 by photolithography. Using this resist film as a mask, portions of oxide film 126 located on n ⁺ region 124 and p ⁺ region 125 are removed by etching. As a result, an opening is formed in the oxide film 126. Next, a conductor film is formed in contact with each of n ⁺ region 124 and p ⁺ region 125 in this opening. Next, by removing the resist film, the portion of the conductor film located on the resist film is removed (lifted off). The conductor film may be a metal film, and is made of nickel (Ni), for example. As a result of this lift-off, the source electrode 111 is formed.

  In addition, it is preferable that the heat processing for alloying is performed here. For example, heat treatment is performed for 2 minutes at a heating temperature of 950 ° C. in an atmosphere of argon (Ar) gas that is an inert gas.

  Referring to FIG. 6 again, upper source electrode 127 is formed on source electrode 111. A drain electrode 112 is formed on the back surface of the substrate 80. Thus, the semiconductor device 100 is obtained.

  Note that a structure in which the conductivity types in this embodiment are switched, that is, a structure in which the p-type and the n-type are replaced can also be used.

  The semiconductor substrate for manufacturing the semiconductor device 100 is not limited to the semiconductor substrate 80 of the first embodiment, and may be a semiconductor substrate obtained by the second embodiment, for example.

  Although a vertical DiMOSFET is illustrated, other semiconductor devices may be manufactured using the semiconductor substrate of the present invention. For example, a RESURF-JFET (Reduced Surface Field-Junction Field Effect Transistor) or a Schottky diode is manufactured. Also good.

(Appendix 1)
The semiconductor substrate of the present invention is manufactured by the following manufacturing method.

  A first silicon carbide substrate having a first surface and a first back surface facing each other and having a single crystal structure, and having a second surface and a second back surface facing each other and having a single crystal structure And a second silicon carbide substrate having First and second silicon carbide substrates are arranged such that each of the first and second back surfaces faces one direction. After the arranging step, a connection layer made of metal joined to the first and second back surfaces so as to connect the first and second back surfaces to each other is formed.

(Appendix 2)
The semiconductor device of the present invention is manufactured using a semiconductor substrate manufactured by the following manufacturing method.

  A first silicon carbide substrate having a first surface and a first back surface facing each other and having a single crystal structure, and having a second surface and a second back surface facing each other and having a single crystal structure And a second silicon carbide substrate having First and second silicon carbide substrates are arranged such that each of the first and second back surfaces faces one direction. After the placing step, a connection layer made of metal is formed which is joined to the first and second back surfaces so as to connect the first and second back surfaces to each other.

  The embodiments and examples disclosed herein are illustrative in all respects and should not be construed as being restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

  The method for manufacturing a semiconductor substrate of the present invention can be particularly advantageously applied to a method for manufacturing a semiconductor substrate including a portion made of silicon carbide having a single crystal structure.

  11 SiC substrate (first silicon carbide substrate), 12 SiC substrate (second silicon carbide substrate), 13 to 19 SiC substrate, 30 connection layer, 80 semiconductor substrate, 81 stage, 100 semiconductor device.

Claims (10)

A first silicon carbide substrate having a first surface and a first back surface facing each other and having a single crystal structure, and having a second surface and a second back surface facing each other and having a single crystal structure Preparing a second silicon carbide substrate having:
Disposing the first and second silicon carbide substrates such that each of the first and second back surfaces faces one direction;
Forming a connection layer made of metal bonded to the first and second back surfaces so as to connect the first and second back surfaces to each other after the arranging step. Production method.   2. The method of manufacturing a semiconductor substrate according to claim 1, wherein the metal is made of at least one metal selected from the group consisting of molybdenum, tantalum, tungsten, niobium, iridium, ruthenium, zirconium, titanium, and nickel.   The method for manufacturing a semiconductor substrate according to claim 1, wherein the connection layer has a thickness of 50 μm or more and 1 mm or less.   The method of manufacturing a semiconductor substrate according to claim 1, wherein the step of forming the connection layer is performed by evaporating the metal from the one direction.   The method of manufacturing a semiconductor substrate according to claim 1, wherein the step of forming the connection layer is performed by plating the metal from the one direction. The step of disposing the first and second silicon carbide substrates includes positioning the first and second silicon carbide substrates on the metal plate located in the one direction with respect to the first and second silicon carbide substrates and made of the metal. And by placing a second silicon carbide substrate,
The method of manufacturing a semiconductor substrate according to claim 1, wherein the step of forming the connection layer is performed by melting and then solidifying the metal plate.   The off angle of the first surface with respect to the {0001} plane of the first silicon carbide substrate is not less than 50 ° and not more than 65 °, and the second surface with respect to the {0001} plane of the second silicon carbide substrate The semiconductor substrate manufacturing method according to claim 1, wherein the off-angle is 50 ° or more and 65 ° or less.   The angle formed by the off orientation of the first surface and the <1-100> direction of the first silicon carbide substrate is 5 ° or less, and the off orientation of the second surface and the second silicon carbide The method for manufacturing a semiconductor substrate according to claim 7, wherein an angle formed by a <1-100> direction of the substrate is 5 ° or less.   The off angle of the first surface with respect to the {03-38} plane in the <1-100> direction of the first silicon carbide substrate is -3 ° or more and 5 ° or less, and the <1-100> direction of the second silicon carbide substrate is < The method for manufacturing a semiconductor substrate according to claim 8, wherein an off angle of the second surface with respect to the {03-38} plane in the 1-100> direction is not less than −3 ° and not more than 5 °.   The angle formed between the off orientation of the first surface and the <11-20> direction of the first silicon carbide substrate is 5 ° or less, and the off orientation of the second surface and the second silicon carbide The method for manufacturing a semiconductor substrate according to claim 7, wherein an angle formed by a <11-20> direction of the substrate is 5 ° or less.

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