JP2011066290A - Semiconductor device, and method of manufacturing the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To keep a breakdown voltage and reduce an on-voltage at the same time, in a high-voltage semiconductor device, in particular, a horizontal IGBT. <P>SOLUTION: In the high-voltage semiconductor device (horizontal IGBT), an N-type drift region 104 and a P-type body region 105 are formed in an SOI layer 103, an N-type emitter region 106 is formed in the body region 105, and an N-type buffer region 115 and a P-type collector region 116 are formed in the drift region 104. A high breakdown voltage is kept by forming the buffer region 115 into a structure comprising a lightly doped part 115a surrounding a heavily doped part 115b. An impurity adjustment region 119 with P-type impurities introduced in the heavily doped part 115b is formed in a collector region 116 side part, and carrier (electron) concentration of the part is reduced, whereby the efficiency of minority carrier injection into the buffer region 115 and the drift region 104 from the collector region 116 is improved, and the on-voltage is reduced. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a semiconductor device in which a high breakdown voltage lateral IGBT (Insulated Gate Bipolar Transistor) is formed on an SOI (Silicon On Insulator) substrate and a manufacturing method thereof.

  In recent years, a semiconductor device in which a low-voltage driving IC circuit and a high breakdown voltage element are combined has been used for various applications. In particular, a high breakdown voltage lateral IGBT is employed in a semiconductor device used in a driving circuit of a plasma display. The normal high breakdown voltage lateral IGBT operates as follows. That is, when 0 V is applied to the emitter electrode, a positive voltage is applied to the collector electrode, and a positive voltage higher than the threshold voltage is applied to the gate electrode, the IGBT is turned on. In the ON state, a channel is formed on the surface of the body region below the gate electrode, and electrons pass through the channel from the emitter electrode and are injected into the drift region. At that time, holes are injected from the collector region into the buffer region and the drift region so as to satisfy the charge neutrality condition. As a result, conductivity modulation occurs in the drift region and the buffer region, and in the IGBT, compared to other semiconductor devices, the on-voltage (the collector-emitter voltage when a predetermined current flows in the saturation region of the IGBT current-voltage characteristics) ) Can be greatly reduced.

At this time, the ON voltage becomes more effective as the efficiency of injection of holes, which are minority carriers from the collector region, into the drift region or the buffer region is higher. This injection efficiency is considered to be roughly proportional to the ratio (Ne / Nb) between the P-type impurity concentration Ne in the collector region and the N-type impurity concentration Nb in the buffer region (reference: Power Semiconductor Devices B.JAYANT BALIGA 1996). This can be improved by reducing the N-type impurity concentration Nb of the buffer region. However, when the N-type impurity concentration in the buffer region is lowered, the remaining time of holes, which are minority carriers injected from the collector region, becomes longer in the drift region and the buffer region when the IGBT is turned off from the on state. . That is, the switching speed is slowed down because the time taken for the holes to disappear due to recombination becomes longer. From the viewpoint of improving the switching speed, in the conventional structure, it is important to suppress the amount of holes injected from the collector region to the buffer region. Therefore, the impurity concentration in the buffer region is a relatively high concentration of 1 × 10 ¹⁷ / cm. It is set to about ³ to 1 × 10 ¹⁹ / cm ³ .

  However, when the gate electrode, the emitter electrode, and the support substrate have the same potential of 0 V, a positive voltage is applied to the collector electrode, and the channel under the gate electrode is off, the buffer region having a high impurity concentration and the low impurity concentration Since equipotential lines tend to concentrate near the boundary with the drift region, increasing the impurity concentration in the buffer region increases the electric field strength in this region, making it difficult to improve the breakdown voltage of the IGBT as a whole. Had. As a technique for improving this, a structure as described in Patent Document 1 has been proposed.

JP-A-8-227999

  However, the device described in Patent Document 1 still has a problem. FIG. 11 is a diagram for explaining the problem. Since the buffer region 115 is usually formed by ion implantation from the surface of the semiconductor layer, the impurity concentration of the buffer layer 115 on the side closer to the surface of the semiconductor layer is higher. FIG. 12B shows an impurity concentration profile in the horizontal direction along the line X-X ′ in FIG. 11. FIG. 12A shows an impurity concentration profile in the depth direction of the Y-Y ′ line in FIG. 11. As shown in FIGS. 12A and 12B, the impurity concentration of the second buffer region 115b at the junction between the collector region 116 and the second buffer region 115b is a region located on the side of the collector region 116 (FIG. 11). The area close to the bottom (point A in FIG. 11) has a lower concentration than the point B). Therefore, the injection efficiency of minority carriers that are injected from the side of the collector region 116 into the buffer layer 115 and diffuse to a certain extent without recombining the buffer layer 115 and contribute to conductivity modulation is lowered. It was still not easy to reduce.

  SUMMARY OF THE INVENTION The present invention solves the above-described conventional problems, and an object of the present invention is to provide a semiconductor device and a manufacturing method thereof that can sufficiently reduce the on-voltage without causing a decrease in breakdown voltage of the high breakdown voltage IGBT. To do.

The semiconductor device of the present invention that solves the above-described conventional problems is as follows.
A semiconductor layer; a first conductivity type body region formed in the semiconductor layer; a second conductivity type drift region formed in the semiconductor layer adjacent to the body region; and a body region surface portion An emitter region of the second conductivity type formed on the control region, and a control electrode portion formed via a gate insulating film over the surface of the body region and the surface of the drift region from the end of the emitter region; A second conductivity type buffer region formed in the drift region opposite to the emitter region across the control electrode portion; a first conductivity type collector region formed in the buffer region surface; and Located in the buffer region on the side of the collector region, and its carrier concentration is substantially the same as the carrier concentration of the buffer region located in the portion in contact with the bottom of the collector region It is characterized in that a Tsu and has regions.

The semiconductor device of the present invention is
A semiconductor layer; a first conductivity type body region formed in the semiconductor layer; a second conductivity type drift region formed in the semiconductor layer adjacent to the body region; and a body region surface portion An emitter region of the second conductivity type formed on the control region, and a control electrode portion formed via a gate insulating film over the surface of the body region and the surface of the drift region from the end of the emitter region; A second conductivity type buffer region formed in the drift region opposite to the emitter region across the control electrode portion; a first conductivity type collector region formed in the buffer region surface; and An impurity adjustment region formed in the buffer region on the side of the collector region, and a portion where the second conductivity type impurity concentration of the buffer region is in contact with the bottom of the collector region rather than the surface thereof And the impurity adjustment region contains the first conductivity type impurity having a concentration not exceeding the second conductivity type impurity concentration in the surface portion of the buffer region located on the side of the collector region. It is what.

  In the above semiconductor device, the value of (the second conductivity type impurity concentration in the surface portion of the buffer region located on the side of the collector region−the first conductivity type impurity concentration included in the impurity adjustment region) is The buffer region may be substantially the same as the second conductivity type impurity concentration in the portion in contact with the bottom of the collector region. With such a configuration, the carrier concentration in the impurity adjustment region and the carrier concentration of the buffer layer located at the portion in contact with the bottom of the collector region can be made substantially the same.

  The buffer region is provided in the first buffer region with a first buffer region having a first average concentration of second conductivity type impurities, and a second average of second conductivity type impurities higher than the first average concentration. It is desirable that the second buffer region has a concentration, and the collector region is provided in the second buffer region.

  The semiconductor layer may be provided on one main surface of the support substrate via an insulating film.

A method of manufacturing a semiconductor device of the present invention for solving the above conventional problem is as follows.
Forming a first conductivity type body region in the semiconductor layer; forming a second conductivity type drift region in the semiconductor layer adjacent to the body region; and forming a second conductivity type on the surface of the body region. A step of forming a two-conductivity type emitter region, and a step of providing a control electrode portion via a gate insulating film formed over the surface of the body region and the surface of the drift region from the end of the emitter region Forming a second conductivity type buffer region in the drift region opposite to the emitter region across the control electrode portion, and forming a first conductivity type collector region on the surface of the buffer region And a step of forming an impurity adjustment region by introducing a first conductivity type impurity into the buffer region located on the side of the collector region.

  In the above semiconductor device manufacturing method, the concentration of the first conductivity type impurity introduced into the buffer region located on the side of the collector region is equal to the concentration of the second conductivity type impurity in the surface portion of the buffer region. It is desirable not to exceed.

  In the semiconductor device manufacturing method of the present invention, more specifically, after the collector region forms a mask layer having an opening on the surface of the buffer region, the surface portion of the buffer region is formed using the mask layer as a mask. The step of introducing the first conductivity type impurity into the buffer region located on the side of the collector region is formed by ion-implanting the first conductivity type impurity to the first collector type using the mask layer as a mask. Impurities are ion-implanted, and the angle of ion implantation relative to the normal of the buffer region surface is larger than the ion implantation for forming the collector region.

  As described above, in the semiconductor device of the present invention, (1) the second conductivity type impurity concentration of the buffer region is smaller in the portion in contact with the bottom of the collector region than in the surface thereof, and in the buffer region located on the side of the collector region Includes a first conductivity type impurity having a concentration not exceeding the second conductivity type impurity concentration in the surface portion of the buffer region, and (2) (second conductivity type impurity concentration in the surface portion of the buffer region − The value of the first conductivity type impurity concentration contained in the buffer region located on the side of the collector region is set to be substantially the same as the second conductivity type impurity concentration of the buffer region in contact with the collector region bottom. That is, (3) the carrier concentration in the buffer region located on the side of the collector region and the carrier concentration in the buffer region located on the portion in contact with the bottom of the collector region. There are those having features that have a structure that has substantially the same. According to this structure, even when the impurity concentration on the surface of the buffer region is high, the injection efficiency of minority carriers injected from the side of the collector region into the buffer region can be improved, and the on-voltage can be reduced.

  The buffer region is provided in the first buffer region with a first buffer region having a first average concentration of the second conductivity type impurity, and has a second average concentration of the second conductivity type impurity higher than the first average concentration. By configuring with the second buffer region, the high breakdown voltage of the semiconductor device can be maintained. In the present invention, not all of the above effects must be exhibited, and any one effect may be exhibited.

Sectional drawing of the high voltage | pressure-resistant lateral IGBT which concerns on 1st Embodiment. FIG. 3 is an enlarged view of the vicinity of a collector region and a buffer region of the high breakdown voltage lateral IGBT according to the first embodiment. (A) And (b) is a figure which shows the carrier concentration profile in the YY 'direction and XX' direction in FIG. 2, respectively. Process sectional drawing which shows the manufacturing method of the high voltage | pressure-resistant lateral IGBT which concerns on 2nd Embodiment of this invention. Process sectional drawing which shows the manufacturing method of the high voltage | pressure-resistant lateral IGBT which concerns on 2nd Embodiment of this invention. Process sectional drawing which shows the manufacturing method of the high voltage | pressure-resistant lateral IGBT which concerns on 2nd Embodiment of this invention. Process sectional drawing which shows the manufacturing method of the high voltage | pressure-resistant lateral IGBT which concerns on 2nd Embodiment of this invention. Process sectional drawing of the collector region and buffer region vicinity of the high voltage | pressure-resistant lateral IGBT which concerns on this invention. Process sectional drawing of the collector region and buffer region vicinity of the high voltage | pressure-resistant lateral IGBT which concerns on this invention. Process sectional drawing of the collector region and buffer region vicinity of the high voltage | pressure-resistant lateral IGBT which concerns on this invention. The enlarged view of the collector region and buffer region vicinity of a high voltage | pressure-resistant lateral IGBT for demonstrating the conventional subject. (A) And (b) is a figure which shows the impurity concentration profile in the YY 'direction and XX' direction in FIG. 11, respectively.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

(Embodiment 1)
FIG. 1 is a cross-sectional view showing the structure of an N-channel lateral IGBT according to the first embodiment of the present invention. In FIG. 1, a support substrate 101 is a substrate serving as a base for forming an N-channel lateral IGBT, and a buried oxide film 102 is formed on the surface thereof. On the buried oxide film 102, an SOI layer 103 (semiconductor layer) made of P-type single crystal silicon is formed. Although the support substrate 101 and the SOI layer 103 are originally individual silicon single crystal substrates, they are bonded together via a buried oxide film 102 having a thickness of about 3 to 10 μm to constitute one SOI substrate. The SOI layer 103 is polished and planarized to a thickness of about 3 to 10 μm from the surface. The specific resistance of the SOI layer 103 is about 1 to 10 Ω · cm.

In the SOI layer 103, a drift region 104 as an N-type impurity region is formed. Further, a body region 105 as a P-type impurity region is formed adjacent to one side of the drift region 104 by ion implantation into the SOI layer 103. The thicknesses of the drift region 104 and the body region 105 are the same as the thickness of the SOI layer 103 in the example of FIG. In the body region 105, an emitter region 106 as a high-concentration N-type impurity region is formed at a depth of about 0.5 μm from the surface. A buffer region 115 is adjacent to the other side of the drift region 104 and is formed in the SOI layer 103 as an N-type impurity region having a higher concentration than the drift region 104. The buffer region 115 includes a first buffer region 115b close to the collector region 116 described below and a second buffer region 115a close to the drift region 104. The depth from the surface of the SOI layer 103 is about 1 μm and 2 μm, respectively. Degree. The average N-type impurity concentration in the second buffer region 115b is set higher than the average N-type impurity concentration in the second buffer region 115b. A collector region 116 is provided as a P-type impurity region at a depth of about 0.5 μm on the surface portion of the SOI layer 103 where the buffer region 115 is formed, and its impurity concentration is as high as about 1 × 10 ²¹ / cm ^3. Concentration.

  An N-type impurity adjustment region 119 is provided in contact with the collector region 116 in a predetermined region located on the side of the P-type collector region 116. The impurity adjustment region 119 may surround a part of the periphery of the side of the collector region 116, or may completely surround the side of the collector region 116 over the entire circumference. The carrier concentration (electrons) in the impurity adjustment region 119 is equal to the carrier concentration (electrons) in the second buffer region 115b in the vicinity including the boundary (PN junction) between the bottom of the collector region 116 and the second buffer region 115b. It is desirable to be adjusted. On the surface of the drift region 104, a LOCOS oxide film 107 is formed to a thickness of about 100 to 1000 nm. A gate oxide film 108 is formed on the drift region 104 and the body region 105 between the emitter region 106 and the end portion of the LOCOS oxide film 107 and is in contact with the LOCOS oxide film 107. A gate electrode 109 for controlling the current flowing through the channel under the gate oxide film 108 is formed from the gate oxide film 108 to the LOCOS oxide film 107 at the end of the emitter region 106.

  Further, an interlayer insulating film 110 is formed on the SOI layer 103 so as to cover the gate electrode 109, the LOCOS oxide film 107, and the like. An emitter electrode 111 is formed on the interlayer insulating film 110, and a part of the emitter electrode 111 is electrically connected in common to the emitter region 106 and the body region 105, and extends further from the gate electrode 109 toward the collector region 116. . A collector electrode 112 is formed on the interlayer insulating film 110 and a part thereof is connected to the collector region 116. Further, an isolation trench 113 filled with an insulating film 114 is provided to electrically isolate other elements adjacent to the IGBT, and surrounds the region of the SOI layer 103 where the normal IGBT is to be formed and its bottom is buried. The oxide film 102 is reached.

  The above is the configuration of the IGBT according to the present invention. The impurity adjustment region 119 will be described in more detail. 2 is an enlarged cross-sectional view of the vicinity of the collector region 116 and the buffer layer 115 of FIG. 1, and FIGS. 3A and 3B are cross-sectional views taken along lines YY ′ and XX ′ in FIG. It is a figure which shows a carrier concentration profile in the state which a density | concentration profile, correctly, the voltage is not applied to at least each electrode 111,112 of IGBT, and is not operating. A region C shown in FIG. 3B is an impurity adjustment region 119, and in regions other than this region, the carrier concentration may be considered to be substantially equal to the impurity concentration. This is because the impurities are normally activated by the heat treatment. 3 (a) and 3 (b), the carrier concentration profile of the N-type buffer region 115 has a two-step shape due to the first buffer region 115a and the second buffer region 115b. The portion corresponds to the second buffer region 115b, and the step portion having a low carrier concentration corresponds to the first buffer region 115a.

2 and 3, the point A is the position where the carrier concentration in the second buffer region 115b is maximized in the vicinity of the junction with the second buffer region 115b at the bottom of the collector region 116, and the point B is the collector region. This is a position where the carrier concentration in the second buffer region 115b is maximized in the vicinity of the junction with the second buffer region 115b at the side portion 116. When the impurity adjustment region 119 is not provided as in the prior art, the carrier concentration at the point B is about 1 × 10 ¹⁸ / cm ³ and the point A is about 8 × 10 ¹⁷ / cm ^{3 as an example} . By forming the impurity adjustment region 119 in a portion adjacent to the collector region 116 in the region 115b, the carrier concentration at the point B is set to about 8 × 10 ¹⁷ / cm ³ which is the same as the carrier concentration at the point A. Can do. Specifically, the impurity adjustment region 119 is formed by introducing a P-type impurity of the opposite conductivity type into the second buffer region 115b and canceling out some of the carriers in this portion. That is, (N-type impurity concentration at the position (point B) where the carrier concentration becomes maximum in the vicinity of the junction between the second buffer region 115b and the collector region 116 on the side of the collector region 116) − (P-type introduced at the point B) The value of (impurity concentration) is close to the N-type impurity concentration at the position (point A) where the carrier concentration becomes maximum in the vicinity of the junction between the second buffer region 115b and the collector region 116 at the bottom of the collector region 116. It is formed by introducing a P-type impurity so as to reach a degree. The carrier concentration at least at point B is desirably 95% to 105% of the carrier concentration at point A. Although it is desirable to do as described above, the present invention is not limited to this. Basically, a P-type impurity having a concentration not exceeding the N-type impurity concentration of the surface portion adjacent to the collector region 116 of the second buffer region 115b. It is possible to introduce a concentration.

  In a semiconductor device such as an IGBT according to the present invention, an appropriate amount of an impurity having a conductivity type opposite to that of this portion is introduced into the second buffer region 115b on the side of the collector region 116 to adjust the concentration of both impurities, thereby adjusting the carrier concentration. As a result, the carrier concentration in the second buffer region 115b on the side surface of the collector region 116 can be reduced as compared with the IGBT having the conventional structure shown in FIGS. The concentration can be the same as that of the second buffer region 115 b at the bottom of the region 116. For this reason, minority carriers (holes) injected from the side of the collector region 116 into the second buffer region 115b and recombined with the carriers (electrons) in the second buffer region 115b can be moderately reduced. Without increasing the conductivity of the first buffer region 115a and the second portion 115b, the amount of minority carriers (holes) to be diffused over a relatively long distance can be increased. That is, the on-voltage can be reduced by increasing the minority carrier injection efficiency from the collector region 116. At the same time, in the present invention, since the first buffer region 115a having a lower impurity concentration is added so as to surround the second buffer region 115b, an effect of preventing the breakdown voltage in the buffer region 115 from being lowered can be obtained. .

(Embodiment 2)
4 to 7 are process cross-sectional views illustrating a method for manufacturing an N-channel lateral IGBT according to the second embodiment of the present invention. The IGBT formed by this manufacturing method corresponds to the IGBT shown in FIG. The manufacturing method will be described below.

  First, in FIG. 4, a support substrate 101 is a substrate serving as a base for forming an N-channel lateral IGBT, and a buried oxide film 102 is formed thereon. A P-type SOI layer 103 is formed on the buried oxide film 102. Although the support substrate 101 and the SOI layer 103 are originally individual silicon single crystal substrates, they are bonded together via a buried oxide film 102 having a thickness of about 3 to 10 μm to constitute one SOI substrate. The SOI layer 103 is polished and planarized to a thickness of about 3 to 10 μm from the surface. At this time, the specific resistance of the SOI layer 103 is about 1 to 10 Ω · cm.

Next, as shown in FIG. 5, in order to form the N-type impurity region constituting the drift region 104, although not shown, it is selectively 3 × 10 ¹² cm ⁻ from the surface of the SOI layer 103 patterned using a resist or the like. ^In order to form about ² × 10 ¹² cm ⁻² in order to form a P-type impurity region constituting the body region 105 adjacent to one side of the drift region 104 using a resist or the like as a mask. Boron is selectively injected. Further, phosphorus of 1 × 10 ¹⁴ cm ⁻² is selectively implanted into the N-type impurity layer constituting the drift region 104 and thermally diffused by performing high-temperature heat treatment at 1200 ° C., and adjacent to the other side of the drift region 104. A first buffer region 115a is formed. Thereafter, phosphorus of about 5 × 10 ¹² cm ⁻² is selectively implanted from the surface of the SOI layer 103 into the buffer region 115 and thermally diffused by high-temperature heat treatment at 1100 ° C., and the first buffer region is formed in the peripheral portion. A second buffer region 115b having a predetermined depth is formed with 115a remaining. At this time, since the shape of the deep portion of the buffer region 115 is maintained almost the original state, this portion becomes the first buffer region 115a.

  Next, a LOCOS oxide film 107 having a thickness of about 100 to 1000 nm is formed on the surface of the drift region 104 formed in the SOI layer 103 by thermal oxidation, and the SOI layer region and the LOCOS oxide film 107 to be the emitter region 106 are formed. A gate oxide film 108 is formed on the drift region 104 and the body region 105 between them to a thickness of about 10 to 50 nm so as to be in contact with the LOCOS oxide film 107 using a thermal oxidation method. A gate electrode 109 made of crystalline silicon is formed. After that, using the gate electrode 109 as a part of the mask, an emitter region 106 is formed by implanting high-concentration N-type impurities such as phosphorus and arsenic into the body region 105.

Further, as shown in FIG. 6, a resist film 117 having an opening in a region to be a collector region is formed on the SOI layer 103, and the surface of the second buffer region 115b is made normal to the surface of the second buffer region 115b using the resist film 117 as a mask. On the other hand, BF ₂ ⁺ of about 3 to 8 × 10 ¹⁵ cm ⁻² is implanted with an ion incident angle of 7 ° or less to form a collector region 116. FIG. 8 is an enlarged view of the buffer region 115 portion showing a state immediately after BF ₂ ⁺ ion implantation. Then, following the BF ₂ ⁺ ion implantation, an oblique ion implantation method using the resist film 117 as a mask is performed at an angle larger than that in the case of the BF ₂ ⁺ ion implantation, for example, 8 at 30 ° with respect to the normal of the SOI layer 103 surface. × 10 ¹² cm ⁻² of BF ₂ ⁺ is implanted into the collector region 116 to form an ion implantation layer to be the impurity adjustment region 119. The impurity adjustment region 119 can be easily formed in the second buffer region 115b in the vicinity of the side of the collector region 116 by ion implantation with such a large tilt angle. FIG. 9 is an enlarged view showing a state immediately after oblique ion implantation. In this ion implantation, BF ₂ ⁺ is implanted beyond the depth of the collector region 116, and it is desirable to set the acceleration energy low enough not to change the carrier concentration of the second buffer region 115b near the bottom of the collector region 116. In this embodiment, as an example, by setting to about 130 keV, implantation can be performed so as not to exceed the depth of the collector region 116.

At this time, the impurity concentration in the depth direction of the second buffer region 115b is, for example, distributed to about 8 × 10 ¹⁷ to 1 × 10 ¹⁸ / cm ³ , and the impurity concentration on the SOI surface is 1 × 10 ¹⁸ / cm ³ , The impurity concentration in the vicinity of the bottom of the collector region 116 is about 8 × 10 ¹⁷ / cm ³ . The impurity concentration of the first buffer region 115a is about 1 × 10 ¹⁶ / cm ³ (bottom surface) to 5 × 10 ¹⁶ / cm ³ (SOI layer surface), and the second buffer near the region where the collector region 116 is formed. The region 115b has a higher concentration than the first buffer region 115a.

Thereafter, the resist film 117 is removed, and annealing is performed at a relatively low temperature of 800 ° C. to 900 ° C. As a result, (N-type impurity concentration at the position (point B) where the carrier concentration becomes maximum in the vicinity of the junction between the second buffer region 115b and the collector region 116 on the side of the collector region 116) − (P-type introduced at the point B) The value of (impurity concentration) is about 8 × 10, which is about the same as the N-type impurity concentration at the position (point A) where the carrier concentration is maximum in the vicinity of the junction between the second buffer region 115b and the collector region 116 at the bottom of the collector region It can be about ¹⁷ / cm ³ . The impurity adjustment region forming ion implantation is preferably set so that the carrier concentration at least at point B is 95% to 105% of the carrier concentration at point A. After the annealing, the collector region 116 has a high impurity concentration of about 1 × 10 ²¹ / cm ³ and an impurity depth of about 0.5 μm. FIG. 10 is an enlarged view showing a state after annealing.

  Next, as shown in FIG. 7, an interlayer insulating film 110 made of a silicon oxide film, a silicon nitride film, or a laminated film thereof is formed on the SOI layer 103 so as to cover the gate electrode 109, the LOCOS oxide film 107, and the like. Then, after etching the isolation trench 113 for electrically isolating other IGBTs adjacent to the IGBT shown in FIG. 7, such as low voltage drive circuit elements, the interlayer insulating film 110 and the SOI layer 103 are etched in the vertical direction, An insulating film 114 such as TEOS or BPSG is filled in the isolation trench 113 by CVD. In addition, a metal electrode is formed on the interlayer insulating film 110, and an emitter electrode 111, a part of which is electrically connected to the emitter region 106 and the body region 105, is formed. Further, a metal electrode is formed on the interlayer insulating film 110. The collector electrode 112 is formed so that a part thereof is connected to the collector region 116.

  According to the present embodiment configured as described above, since the impurity adjustment region 119 for adjusting the impurity concentration of the second buffer region 115b on the side of the collector region 116 is formed, A in FIG. Since the value of (N-type impurity concentration−P-type impurity concentration) at the point can be made substantially the same as the N-type impurity concentration at the B point, the collector region is the same as in the first embodiment. Since the minority carrier injection efficiency from 116 to the buffer region increases at the junction of the side of the collector region 116 and the second buffer region 115b, the on-voltage can be reduced without causing a decrease in breakdown voltage. .

  Furthermore, in the present embodiment, the resist pattern used in the process of forming the impurity adjustment region 119 is the same as the resist pattern used in the collector region 116, so that it is not necessary to consider mask misalignment between the collector region 116 and the impurity adjustment region 119. It is possible to control the relative position with higher accuracy. In the above embodiment, the N-channel lateral IGBT has been described as an example. However, the present invention is not limited to this, and can also be applied to a P-channel lateral IGBT.

  The semiconductor device and the semiconductor manufacturing method according to the present invention include not only a single high-voltage semiconductor device such as an IGBT but also a semiconductor integrated circuit in which a low-voltage drive semiconductor integrated circuit and a high-voltage semiconductor element are integrated on the same substrate. Useful for devices.

101 support substrate 102 buried oxide film 103 SOI layer 104 drift region 105 body region 106 emitter region 107 LOCOS oxide film 108 gate oxide film 109 gate electrode 110 interlayer insulating film 111 emitter electrode 112 collector electrode 113 isolation trench 114, 118 insulating film 115 buffer Region 115a First buffer region 115b Second buffer region 116 Collector region 117 Resist film 119 Impurity adjustment region

Claims (9)

A semiconductor layer;
A first conductivity type body region formed in the semiconductor layer;
A drift region of a second conductivity type formed adjacent to the body region in the semiconductor layer;
A second conductivity type emitter region formed on the surface of the body region;
A control electrode portion formed through a gate insulating film over the surface of the body region and the surface of the drift region from the end of the emitter region;
A buffer region of a second conductivity type formed in the drift region opposite to the emitter region across the control electrode portion;
A first conductivity type collector region formed on the surface of the buffer region;
A region located in the buffer region on the side of the collector region and having a carrier concentration that is substantially the same as the carrier concentration of the buffer region located in a portion in contact with the bottom of the collector region. A semiconductor device characterized by the above. A semiconductor layer;
A first conductivity type body region formed in the semiconductor layer;
A drift region of a second conductivity type formed adjacent to the body region in the semiconductor layer;
A second conductivity type emitter region formed on the surface of the body region;
A control electrode portion formed through a gate insulating film over the surface of the body region and the surface of the drift region from the end of the emitter region;
A buffer region of a second conductivity type formed in the drift region opposite to the emitter region across the control electrode portion;
A first conductivity type collector region formed on the surface of the buffer region;
An impurity adjustment region formed in the buffer region on the side of the collector region,
The second conductivity type impurity concentration of the buffer region is smaller at the portion in contact with the bottom of the collector region than at the surface thereof,
The semiconductor device according to claim 1, wherein the impurity adjustment region includes a first conductivity type impurity having a concentration not exceeding the second conductivity type impurity concentration in a surface portion of the buffer region located on the side of the collector region.   The value of (the second conductivity type impurity concentration in the surface portion of the buffer region located on the side of the collector region−the first conductivity type impurity concentration included in the impurity adjustment region) is the collector region of the buffer region. 3. The semiconductor device according to claim 2, wherein the concentration is substantially the same as the second conductivity type impurity concentration in a portion in contact with the bottom.   4. The semiconductor device according to claim 2, wherein a carrier concentration in the impurity adjustment region is substantially the same as a carrier concentration in the buffer layer located in a portion in contact with the bottom of the collector region.   The buffer region is provided in the first buffer region with a first average concentration of a second conductivity type impurity and a second average concentration of a second conductivity type impurity higher than the first average concentration. The semiconductor device according to claim 1, wherein the collector region is provided in the second buffer region.   The semiconductor device according to claim 1, wherein the semiconductor layer is provided on a surface of a support substrate via an insulating film. Forming a first conductivity type body region in the semiconductor layer;
Forming a drift region of a second conductivity type adjacent to the body region in the semiconductor layer;
Forming a second conductivity type emitter region on the surface of the body region; and a gate insulating film formed on the surface of the body region and on the surface of the drift region from the end of the emitter region. Providing a control electrode part via,
Forming a second conductivity type buffer region in the drift region opposite to the emitter region across the control electrode portion;
Forming a first conductivity type collector region on the surface of the buffer region;
And a step of forming an impurity adjustment region by introducing a first conductivity type impurity into the buffer region located on the side of the collector region.   The concentration of the first conductivity type impurity introduced into the buffer region located on the side of the collector region does not exceed the concentration of the second conductivity type impurity in the surface portion of the buffer region. 8. A method for producing a semiconductor device according to 7.   The collector region is formed by forming a mask layer having an opening on the surface of the buffer region, and then ion-implanting a first conductivity type impurity into the surface portion of the buffer region using the mask layer as a mask, The step of introducing the first conductivity type impurity into the buffer region located on the side of the collector region is performed by ion-implanting the first conductivity type impurity using the mask layer as a mask. 9. The method of manufacturing a semiconductor device according to claim 7, wherein an ion implantation angle with respect to a normal line is larger than an ion implantation for forming the collector region.

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