JP2011065976A - Induction heating cooker - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an induction heating cooker increasing accuracy in adjustment of the power for heating by controlling the switching frequency of an inverter. <P>SOLUTION: A base clock generation unit 34 outputs a base clock signal of a frequency according to a timer counted value. An inverter driving pulse generation unit 25 multiplies the base clock signals to generate drive pulse signals VG1-VG4 for driving respective transistors 18-21 of the inverter 3 based on a multiplied clock signal, thereby increasing the resolution of the switching frequency of the inverter 3. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to an induction heating cooker that performs cooking by induction heating of a load on a cooking appliance such as a pan.

  The induction heating cooker has advantages such as safety and temperature control function without using fire, and is rapidly spreading as an IH cooking heater incorporated in a system kitchen. By the way, since the cooking pot etc. which are heating objects are made with various materials, it is calculated | required that an induction heating cooking appliance can heat all those materials efficiently. For this reason, in addition to heating a high-permeability pan such as an iron pan, an induction heating cooker has been devised that can also heat a low-permeability pan such as an aluminum pan (for example, Patent Document 1, 2).

  However, when heating an aluminum pan, there are the following problems in adjusting the heating power. That is, when heating the aluminum pan, the Q value, which is the sharpness of the change in the resonance current when the frequency of the high-frequency current supplied to the resonance circuit is changed, is higher than when heating the iron pan. Value. When the value of Q is high, the resonance current changes greatly due to a slight change in the switching frequency of the inverter, and the heating power also changes greatly, so that accurate adjustment becomes difficult.

  In Patent Document 3, in order to improve this problem, first, the switching frequency of the inverter is varied to roughly adjust the input power, and then the DC voltage supplied to the inverter is finely adjusted to target the input power. Techniques for matching values are disclosed. According to this thing, the heating electric power (input electric power) at the time of heating an aluminum pan can be adjusted accurately.

JP 2001-160484 A JP 2006-140088 A JP 2006-351371 A

  However, in the configuration described in Patent Document 3, since it is necessary to perform two types of control, frequency control and voltage control, there is a problem that the control content becomes complicated. Therefore, it is conceivable to increase the resolution of the switching frequency and improve the adjustment accuracy of the heating power to the aluminum pan only by controlling the frequency.

  In an induction heating cooker, a drive signal for driving a switching element of an inverter is often generated using, for example, a drive signal generation circuit that generates a drive signal for controlling a three-phase motor built in a microcomputer. Since many microcomputers equipped with such a drive signal generation circuit can perform high-speed calculations, many of them are expensive.

  Now, such a drive signal generation circuit mounted on a microcomputer generates a drive signal having a frequency corresponding to the count value of a dedicated waveform generation counter. Therefore, in order to increase the frequency resolution of the drive signal, the operating frequency (timer frequency) of the waveform generation counter may be increased. However, since the control target is originally a motor, the timer frequency of this type of drive signal generation circuit is often low. Therefore, it has been difficult to increase the resolution of the switching frequency of the drive signal for driving the switching element of the inverter in the induction heating cooker.

  This invention is made | formed in view of the said situation, The objective is to provide the induction heating cooking appliance which can improve the adjustment precision of the heating electric power by control of the switching frequency of an inverter.

  In order to achieve the above object, an induction heating cooker of the present invention includes a DC power supply circuit, a resonance circuit including an induction heating coil and a resonance capacitor for induction heating of an object to be heated, and a plurality of switching elements. Comprising: an inverter that converts a DC voltage output from the DC power supply circuit into a high-frequency voltage and supplies the high-frequency voltage to the resonance circuit; and a control unit that controls a switching operation of the inverter. A clock signal generation circuit that divides a clock signal to generate a base clock signal, a multiplication circuit that generates a multiplied clock signal by multiplying the base clock signal, and the plurality of switching elements based on the multiplied clock signal, respectively And a drive signal generation circuit that generates a plurality of drive signals for driving.

  If comprised in this way, the drive signal for driving the switching element of an inverter will be produced | generated based on the multiplied clock signal which multiplied the base clock signal. That is, the frequency of the drive signal is determined according to the frequency of the base clock signal and the multiplication number of the multiplication circuit. The base clock signal is generated by dividing the reference clock signal. For this reason, the frequency of the base clock signal is changed by adjusting the number of reference clock signals required to generate one period. In this case, the number of reference clock signals for one cycle increases as the frequency of the base clock signal decreases. An increase in the number of reference clock signals for one cycle of the base clock signal leads to an increase in the frequency resolution of the drive signal generated based on the base clock signal. In the above configuration, since the drive signal is generated based on the multiplied clock signal obtained by multiplying the base clock signal, the frequency of the base clock signal can be lowered as the multiplication number of the multiplication circuit is increased, and the drive signal is correspondingly increased. It is possible to increase the frequency resolution.

  According to the present invention, since the frequency resolution of a plurality of drive signals for driving the plurality of switching elements of the inverter can be increased, the adjustment accuracy of the heating power by controlling the switching frequency of the inverter can be improved.

The electrical block diagram of the induction heating cooking appliance which shows the 1st Embodiment of this invention Block diagram showing the configuration of the inverter drive pulse generator Block diagram showing one configuration example of the multiplier circuit The figure which shows one structural example of a waveform generation circuit The figure which shows the waveform of each part of the waveform generation circuit The figure which shows one structural example of a dead time variable circuit The figure which shows the waveform of each part of the dead time variable circuit Fig. 7 equivalent when the dead time length is changed The figure which shows the waveform of each part at the time of driving an inverter FIG. 2 equivalent view showing the second embodiment of the present invention 6 equivalent diagram 7 equivalent diagram Equivalent to FIG. FIG. 2 equivalent view showing the third embodiment of the present invention FIG. 1 equivalent view showing a fourth embodiment of the present invention 2 equivalent diagram 3 equivalent figure

(First embodiment)
Hereinafter, a first embodiment of the present invention will be described with reference to FIGS.
FIG. 1 schematically shows the electrical configuration of an induction heating cooker. An induction heating cooker 1 shown in FIG. 1 includes a DC power supply circuit 2, an inverter 3, a resonance circuit 4, a control circuit 5, a gate control circuit 6, and the like. The full-wave rectifier circuit 7 constitutes a DC power supply circuit 2 together with a smoothing capacitor 8, and its AC input terminal has a 200 V single-phase AC power supply 11 via AC power supply lines L 1 and L 2 and a noise filter 10. It is connected to the.

  The positive side DC output terminal of the full-wave rectifier circuit 7 is connected to one terminal of the capacitor 8 via the reactor 12 and the diode 13. The negative DC output terminal of the full-wave rectifier circuit 7 is connected to the other terminal of the capacitor 8. The NPN transistor 14 forms a chopper circuit 15 together with the reactor 12 and the diode 13. The collector of the transistor 14 is connected to the interconnection point of the reactor 12 and the diode 13, and the emitter is connected to the negative DC output terminal of the full-wave rectifier circuit 7. DC power supply lines 16 and 17 are connected to both terminals of the capacitor 8.

  The inverter 3 converts the DC voltage VDC output from the DC power supply circuit 2 into a high frequency voltage by the switching operation, and supplies it to the resonance circuit 4. The inverter 3 includes a first half bridge circuit (corresponding to an arm) in which the first and second transistors 18 and 19 are connected in series between the DC power supply lines 16 and 17, and the third and fourth transistors 20 and 21. Is a full bridge type inverter circuit composed of a second half bridge circuit (corresponding to an arm) connected in series.

  The first to fourth transistors 18 to 21 correspond to switching elements, and are, for example, IGBTs. In these first to fourth transistors 18 to 21, free wheel diodes 18 a to 21 a are connected between the collector and the emitter, respectively. The resonance circuit 4 is connected between a node N1 which is an interconnection point of the first transistor 18 and the second transistor 19 and a node N2 which is an interconnection point of the third transistor 20 and the fourth transistor 21. It is connected. Further, snubber capacitors 22 and 23 for reducing switching loss are connected between the nodes N1 and N2 and the DC power supply line 17.

  The first and second transistors 18 and 19 are operated alternately so that when one is on, the other is off. The third and fourth transistors 20 and 21 are also operated alternately so that when one is on, the other is off. The on / off operation of each of the transistors 18 to 21 is controlled by the gate control circuit 6. The gate control circuit 6 includes an inverter drive pulse generator 25 and a driver 26.

  The resonance circuit 4 includes an induction heating coil 27, first and second resonance capacitors 28 and 29, and a relay switch 30. For example, an induction heating coil 27 for heating a heated object 31 that is a pan and a first resonance capacitor 28 are connected in series between nodes N1 and N2. A series circuit of a second resonance capacitor 29 and a relay switch 30 is connected in parallel to the first resonance capacitor 28. The relay switch 30 is provided to switch the resonance frequency by switching the connection state of the resonance capacitors 28 and 29. In this embodiment, the number of turns of the induction heating coil 27 is set to 60 turns.

  When the relay switch 30 is off, the induction heating coil 27 and the first resonance capacitor 28 constitute a series resonance circuit. The capacity of the first resonance capacitor 28 is set so that the resonance frequency when heating the aluminum pan (object to be heated) in this state is about 80 kHz. On the other hand, when the relay switch 30 is on, the resonance capacitors 28 and 29 are connected in parallel to each other, and the capacitance and the induction heating coil 27 constitute a series resonance circuit. The parallel capacitances of the resonant capacitors 28 and 29 are set so that the resonant frequency when heating the iron pan (object to be heated) in that state is about 20 kHz. In this case, the capacity of the first resonant capacitor 28 is determined so as to satisfy the condition when the relay switch 30 is in the off state first, and the second condition is satisfied so that the condition when the relay switch 30 is in the on state is satisfied later. The capacity of the resonant capacitor 29 is determined.

  The control circuit 5 is constituted by, for example, a 32-bit microcomputer (reference clock = 40 MHz). The control circuit 5 includes an input power control unit 32, a load determination unit 33, and a base clock generation unit 34 as functions realized by the software.

  The input voltage detection circuit 35 detects an AC input voltage between the AC power supply lines L 1 and L 2 and gives the detected value to the input power control unit 32. The input current detection circuit 36 detects an AC input current via the current transformer 37 and gives the detected value to the input power control unit 32 and the load determination unit 33. The inverter current detection circuit 38 detects the current flowing through the inverter 3 via the current transformer 39 and supplies the detected value to the load determination unit 33.

  The power factor improving unit 40 is a base for driving the transistor 14 based on the detection values of the input voltage detection circuit 35 and the input current detection circuit 36 so that the waveform of the AC input current follows the waveform of the AC input voltage. Generate a signal. This base signal is given to the base of the transistor 14 via the driver 41. Thus, the chopper circuit 15 applies the set DC voltage VDC between the DC power supply lines 16 and 17 and acts as a power factor improving chopper.

  In the control circuit 5, the load determination unit 33 (corresponding to the material determination unit) is configured to detect the object 31 to be heated from the AC input current detected by the input current detection circuit 36 and the inverter current detected by the inverter current detection circuit 38. Determine the material. The load determination unit 33 gives a determination signal indicating the determination result of the material to the base clock generation unit 34. When determining that the material of the article to be heated 31 is aluminum, the load determination unit 33 turns off the relay switch 30 via the relay switching circuit 42. Moreover, the load determination part 33 turns ON the relay switch 30 via the relay switching circuit 42, when it determines with the material of the to-be-heated material 31 being iron.

  The power (heating power) consumed by the induction heating coil 27 is controlled by the input power control unit 32. The input power control unit 32 is a circuit that controls the power consumed by the induction heating coil 27 so as to match the target power value instructed from the outside. Since the current flowing through the induction heating coil 27 is a high-frequency current, it is not easy to detect the heating power. Therefore, in this embodiment, instead of directly controlling the power consumed by the induction heating coil 27, control is performed to match the input power of the DC power supply circuit 2 with the input power target value calculated based on the target power value. Do. As a result of the control, the power consumption (heating power) of the induction heating coil 27 is made to coincide with the target power value.

  That is, the input power control unit 32 calculates the input power from the AC input voltage detected by the input voltage detection circuit 35 and the AC input current detected by the input current detection circuit 36. The input power control unit 32 provides the base clock generation unit 34 with a frequency command that instructs the target value of the heating frequency (frequency of the inverter current IQ) so that the calculated input power becomes equal to the input power target value.

  The base clock generation unit 34 (corresponding to a clock signal generation circuit) includes, for example, a timer. The base clock generation unit 34 is given a reference clock (for example, 40 MHz) of the microcomputer. The base clock generator 34 counts this reference clock with a timer, and generates a base clock signal having a frequency corresponding to the count value. That is, the base clock generation unit 34 generates a base clock signal by dividing the reference clock (corresponding to the reference clock signal). The base clock generation unit 34 determines the frequency of the base clock signal based on the frequency command given from the input power control unit 32 and taking into account the determination result of the load determination unit 33. The base clock signal is output from, for example, a general-purpose I / O port of a microcomputer and is supplied to the inverter drive pulse generator 25.

  In the gate control circuit 6, the inverter drive pulse generator 25 generates drive pulse signals VG 1 to VG 4 for driving the transistors 18 to 21 of the inverter 3 using the base clock signal supplied from the control circuit 5 ( Details will be described later). The drive pulse signals VG1 to VG4 are supplied to the gates of the transistors 18 to 21 of the inverter 3 through the driver 26, respectively. In the present embodiment, the control means 9 is composed of the control circuit 5 and the gate control circuit 6.

  FIG. 2 is a block diagram illustrating a configuration of the inverter drive pulse generation unit 25. The inverter drive pulse generation unit 25 includes a multiplication circuit 43, a waveform generation circuit 44, and a dead time variable circuit 45. The multiplier circuit 43 generates a multiplied clock signal obtained by multiplying the base clock signal supplied from the control circuit 5 (64 times). The waveform generation circuit 44 generates drive pulse signals VG1 'to VG4' based on the multiplied clock signal supplied from the multiplication circuit 43. The dead time variable circuit 45 changes the rising timing of the drive pulse signals VG1 ′ to VG4 ′ generated by the waveform generation circuit 44, and serves as drive pulse signals VG1 to VG4 for turning on / off the transistors 18 to 21 of the inverter 3. Output.

  FIG. 3 shows a configuration example of the multiplier circuit 43. The multiplication circuit 43 shown in FIG. 3 includes a phase comparator 46, an LPF 47, a VCO 48, an inverter 49, and a frequency divider 50. The phase comparator 46 outputs a voltage signal corresponding to the phase difference between the base clock signal and the output signal of the frequency divider 50. The output of the phase comparator 46 is smoothed through an LPF 47 (low-pass filter) and then supplied to the VCO 48.

  The VCO 48 (voltage controlled oscillator) outputs a signal having a frequency corresponding to the voltage value of a given voltage signal. The output of the VCO 48 is supplied to the frequency divider 50 via the inverter 49 and is output as a multiplied clock signal. The frequency divider 50 divides the multiplied clock signal by 1/64 and outputs it. With such a configuration, the multiplier circuit 43 generates a multiplied clock signal that is synchronized with the base clock signal and has a frequency that is 64 times that of the base clock signal.

  FIG. 4 shows a configuration example of the waveform generation circuit 44, and FIG. 5 shows signal waveforms at various parts in the waveform generation circuit 44. The waveform generation circuit 44 (corresponding to the drive signal generation circuit) shown in FIG. 4 includes a counter 51, OR circuits 52 and 53, an AND circuit 54, a NAND circuit 55, a NOR circuit 56, and inverters 57 and 58. The counter 51 counts in synchronization with the falling edge of the multiplied clock signal (see FIG. 5A) applied to the CK terminal. The counter 51 outputs a signal (see (b) to (d) in FIG. 5) indicating a count value (3-bit binary data) from the QA terminal, the QB terminal, and the QC terminal.

  The output signals from the QA terminal and QB terminal of the counter 51 are given to the input terminals of the OR circuit 52, respectively. The output signal of the OR circuit 52 (see FIG. 5E) is applied to one input terminal of the AND circuit 54, one input terminal of the NAND circuit 55, and the input terminal of the inverter 57. The output signal of the inverter 57 (see (f) of FIG. 5) is applied to one input terminal of the OR circuit 53 and one input terminal of the NOR circuit 56.

  The output signal from the QC terminal of the counter 51 is given to the input terminal of the inverter 58. The output signal of the inverter 58 (see (g) of FIG. 5) is obtained by using the other input terminal of the AND circuit 54, the other input terminal of the NAND circuit 55, the other input terminal of the OR circuit 53, and the other input of the NOR circuit 56. Given to the terminal. With such a configuration, drive pulse signals VG1 'and VG2' are output from the OR circuit 53 and the NOR circuit 56, respectively (see (h) and (i) of FIG. 5). Further, drive pulse signals VG3 'and VG4' are output from the AND circuit 54 and the NAND circuit 55, respectively (see (j) and (k) in FIG. 5).

  As shown in FIG. 5, the period (switching period) of the drive pulse signals VG1 'to VG4' is eight times the period of the multiplied clock signal. That is, the switching frequency of each of the transistors 18 to 21 in the inverter 3 is 1/8 of the frequency of the multiplied clock signal and 8 times the frequency of the base clock signal. Further, as shown in FIG. 5 (h), the drive pulse signal VG1 ′ turns on the first transistor 18 during the 5/8 cycle of the switching cycle and turns off during the remaining 3/8 cycle. It is supposed to be in a state. As shown in (j) of FIG. 5, the drive pulse signal VG3 ′ turns on the third transistor 20 during the 3/8 cycle of the switching period and turns off during the remaining 5/8 period. It is supposed to be. The timing for turning on the third transistor 20 is delayed by 1/8 cycle from the timing for turning on the first transistor 18.

  The drive pulse signals VG2 'and VG4' have waveforms having opposite polarities to those of the drive pulse signals VG1 'and VG3', respectively. That is, the drive pulse signal VG2 ′ causes the second transistor 19 to operate in the opposite direction to the first transistor 18, and the drive pulse signal VG4 ′ causes the fourth transistor 21 to operate as the third transistor. The operation opposite to that of 20 is performed.

  FIG. 6 shows an example of the configuration of the dead time variable circuit 45, and FIGS. 7 and 8 show signal waveforms of respective parts of the dead time variable circuit 45. The dead time variable circuit 45 shown in FIG. 6 is changed so as to delay only the rising timing of the input drive pulse signal VG1 'and output as the drive pulse signal VG1. Although not shown, the same configuration as that of the present circuit is provided corresponding to the drive pulse signals VG2 'to VG4'.

  The dead time variable circuit 45 shown in FIG. 6 includes resistors 59 and 60, capacitors 61 and 62, a diode 63, Schmitt trigger type inverters 64 and 65, and a transistor 66. The input terminal of the drive pulse signal VG 1 ′ is connected to the ground line 67 through the resistor 59 and the capacitor 61. A series circuit of a diode 63 and a resistor 60 is connected in parallel with the resistor 59. The diode 63 is provided such that the cathode is on the input terminal side. A capacitor 62 and a transistor 66 are connected in series between a node N3, which is an interconnection point between the resistor 59 and the capacitor 61, and the ground line 67.

  The transistor 66 includes a base-emitter resistance and a base resistance, and a switching signal output from the control circuit 5 is supplied to the base. The control circuit 5 switches the switching signal to an H level (a level at which the transistor 66 can be sufficiently turned on) or an L level (a level at which the transistor 66 can be sufficiently turned off). The signal at node N3 is output as drive pulse signal VG1 through inverters 64 and 65.

  Since the transistor 66 is turned off when the switching signal is at the L level, only the capacitor 61 is connected between the node N3 and the ground line 67. On the other hand, since the transistor 66 is turned on when the switching signal is at the H level, the capacitors 61 and 62 are connected in parallel between the node N3 and the ground line 67. In the present embodiment, the capacity of the capacitor 62 is set to about twice the capacity of the capacitor 61. Further, the resistance value of the resistor 59 is set to about 10 times the resistance value of the resistor 60.

  According to such a configuration, when the switching signal is at the L level, the capacitor 61 is charged via the resistor 59 when the drive pulse signal VG1 ′ (see FIG. 7A) rises (time t0). Therefore, the rise of the signal at the node N3 becomes gentle (see FIG. 7B). On the other hand, when the drive pulse signal VG1 ′ falls (time t1), the charge of the capacitor 61 is discharged through the resistor 60 and the diode 63 having a resistance value sufficiently smaller than that of the resistor 59, so that the signal at the node N3 Falls sharply (see FIG. 7B). By passing the slowly rising signal generated in this way through the inverters 64 and 65, the driving pulse signal VG1 (see FIG. 7C) with the rising timing delayed by the time T1 is generated.

  When the switching signal is at the H level, the capacitors 61 and 62 are charged via the resistor 59 when the drive pulse signal VG1 ′ (see FIG. 8A) rises (time t0). The rise of the signal at the node N3 is very gradual (see FIG. 8B). On the other hand, when the drive pulse signal VG1 ′ falls (time t1), the fall of the signal at the node N3 becomes steep, as in the case where the switching signal is at the L level (FIG. 8 (( b)). The drive pulse signal VG1 in which the rising timing is delayed by a time T2 longer than the time T1 by passing the very slowly rising signal thus generated through the inverters 64 and 65 (see FIG. 8C). Is generated.

  In this way, by delaying the rising timing of the drive pulse signals VG1 to VG4, the dead time when the first and second transistors 18 and 19 are both turned off, and the third and fourth transistors 20 and 21 are In any case, a dead time for turning off is provided. The length of the dead time can be switched in two steps according to the level of the switching signal given from the control circuit 5. The control circuit 5 outputs an L level switching signal when the input power is greater than or equal to a predetermined value, and outputs an H level switching signal when the input power is less than the predetermined value. Therefore, the length of the dead time is shortened if the input power is equal to or greater than a predetermined value, and is increased if the input power is less than the predetermined value.

Next, the operation of this embodiment will be described.
When a signal (not shown) indicating the start of heating is input from the outside, the load determination unit 33 determines the type (material) of the object to be heated 31. In making this determination, the load determination unit 33 turns on the relay switch 30. The input power control unit 32 instructs the base clock generation unit 34 to set, for example, 25 kHz as a target value for the heating frequency of the inverter 3. In this state, the detection value of the inverter current detection circuit 38 when the inverter 3 is driven is read. When the material of the object to be heated 31 is aluminum, the inductance of the induction heating coil 27 becomes a small value because of the low magnetic permeability. For this reason, the resonance frequency of the resonance circuit 4 is a value greatly deviated from 25 kHz (for example, 50 kHz). In this case, only a small current flows through the induction heating coil 27.

  On the other hand, when the material of the article to be heated 31 is iron-based, the resonance frequency is about 20 kHz. Since the heating frequency 25 kHz is very close to the value, a larger current flows through the induction heating coil 27 than in the case of an aluminum-based material. Therefore, it can be determined from the magnitude of the current flowing through the induction heating coil 27 whether the material of the article to be heated 31 is iron-based or aluminum-based. In addition, instead of the magnitude of the current flowing through the induction heating coil 27, it can be determined from the magnitude of the input power obtained by the input power control unit 32. In this case, the value of the input power is small in the aluminum system and larger in the iron material.

  After determining the material of the object to be heated 31, the relay switch 30 of the resonance circuit 4 is switched according to the material. When the material is aluminum, the relay switch 30 is turned off to set the resonance frequency to about 80 kHz. If the material is iron, the relay switch 30 is turned on to set the resonance frequency to about 20 kHz.

  The input power control unit 32 gives the target value of the heating frequency to the base clock generation unit 34 so that the calculated input power becomes equal to the set input power set by the user. The base clock generation unit 34 outputs a base clock signal having a frequency 1/32 of the instructed heating frequency to the inverter drive pulse generation unit 25. In this embodiment, since the target value of the heating frequency when the material is aluminum is about 80 kHz to about 90 kHz, the base clock signal in that case is about 2.5 kHz to about 2.8 kHz. Further, since the target value of the heating frequency when the material is iron-based is about 25 kHz to about 35 kHz, the base clock signal in that case is about 0.78 kHz to about 1.09 kHz.

  The inverter drive pulse generator 25 generates drive pulse signals VG1 to VG4 for turning on / off the transistors 18 to 21 so that a high-frequency current that matches the instructed heating frequency flows through the induction heating coil 27. These drive pulse signals VG1 to VG4 are applied to the gates of the transistors 18 to 21 through the driver 26, respectively.

  The operation of inverter 3 when drive pulse signals VG1 to VG4 are applied in this way will be described with reference to FIG. FIG. 9 shows waveforms of respective parts in the inverter 3, where (a) is the inverter current IQ, (b) is the high-frequency voltage VQ output from the inverter 3, and (c) to (f) are drive pulse signals VG1 to VG4. Indicates. Here, the case where the material of the article to be heated 31 is aluminum is described.

  When the first transistor 18 and the fourth transistor 21 are turned on, the current IQ (+) is supplied to the induction heating coil 27 through the path of the first transistor 18, the induction heating coil 27, the first resonance capacitor 28, and the fourth transistor 21. ) Flows, and the first resonant capacitor 28 is charged. Subsequently, the fourth transistor 21 is turned off and the third transistor 20 is turned on. During this period, a dead time during which both the third and fourth transistors 20 and 21 are turned off is provided. Short circuit is prevented. After the fourth transistor 21 is turned off and the snubber capacitor 23 is charged during this dead time, a delay occurs in the path of the first transistor 18, the induction heating coil 27, the first resonant capacitor 28, and the free wheel diode 20a. Current flows.

  When the third transistor 20 is turned on, a current IQ (−) flows to the induction heating coil 27 through the path of the first resonant capacitor 28, the induction heating coil 27, the free wheeling diode 18a and the third transistor 20, The current IQ (+) flows through the induction heating coil 27 through the path of the first resonance capacitor 28, the free wheel diode 20a, the first transistor 18 and the induction heating coil 27, and then the first resonance capacitor 28, the induction heating coil. 27, resonance occurs in which the current IQ (−) flows through the induction heating coil 27 through the path of the free wheel diode 18a and the third transistor 20. Then, the third transistor 20 is turned off and the fourth transistor 21 is turned on, but there is also a dead time between them. After the third transistor 20 is turned off and the snubber capacitor 23 is charged during this dead time, the path of the first resonant capacitor 28, the induction heating coil 27, the freewheel diode 18a, the capacitor 8 and the freewheel diode 21a. Delay current flows at.

  When the fourth transistor 21 is turned on, a current IQ (+) flows through the induction heating coil 27 through the path of the first transistor 18, the induction heating coil 27, the first resonant capacitor 28, and the fourth transistor 21, and 1 resonant capacitor 28 is charged. Subsequently, the first transistor 18 is turned off and the second transistor 19 is turned on, and there is also a dead time during this period. After the first transistor 18 is turned off and the snubber capacitor 22 is charged during this dead time, a delay occurs in the path of the induction heating coil 27, the first resonant capacitor 28, the fourth transistor 21 and the free wheel diode 19a. Current flows.

  When the second transistor 19 is turned on, a current IQ (−) flows through the induction heating coil 27 through the path of the first resonant capacitor 28, the induction heating coil 27, the second transistor 19 and the free wheel diode 21a. Subsequently, a current IQ (+) flows through the induction heating coil 27 through the path of the first resonance capacitor 28, the fourth transistor 21, the free wheel diode 19a, and the induction heating coil 27, and then the first resonance capacitor 28, A resonance occurs in which the current IQ (−) flows through the induction heating coil 27 through the path of the induction heating coil 27, the second transistor 19, and the free wheel diode 21a. Then, the second transistor 19 is turned off and the first transistor 18 is turned on, and there is also a dead time between them. After the second transistor 19 is turned off and the snubber capacitor 22 is charged during this dead time, the path of the first resonant capacitor 28, the induction heating coil 27, the freewheel diode 18a, the capacitor 8 and the freewheel diode 21a. Delay current flows at.

  By repeating the above operation, as shown in FIG. 9, the high frequency voltage VQ output from the inverter 3 becomes twice the switching frequency of each of the transistors 18 to 21, and the inverter current IQ flowing through the induction heating coil 27 is switched. The frequency is four times the frequency. In this embodiment, the switching frequency at the time of 2 kW heating of the aluminum-based material pan is set to 22 kHz. Thereby, the frequency of the inverter current IQ is 88 kHz, which is four times the switching frequency. When the material of the object to be heated 31 is iron-based, except that the first and second resonance capacitors 28 and 29 are connected in parallel in the resonance circuit 4 and the target value of the heating frequency is different. For example, the inverter 3 operates in the same manner as in the case where the above-described material is aluminum.

  Power control (heating power control) for matching the input power with the set input power is performed by changing the switching frequency of the inverter 3. This switching frequency is changed in the base clock generation unit 34 of the control circuit 5 according to the count number of the timer. One count of this timer is 0.025 μs when the reference clock is 40 MHz. Therefore, when the switching frequency is varied in the range of 20 kHz to 22.5 kHz, that is, when the frequency of the base clock signal is varied in the range of 2.5 kHz to 2.8 kHz, the timer count is in the range of 16000 to 14285. It will be changed in the range of (count number = 1715). Therefore, the switching frequency of the inverter 3 can be changed in units of about 1.5 Hz (= 2.5 kHz / 1715).

As described above, according to the present embodiment, the following effects can be obtained.
The base clock generation unit 34 in the control circuit 5 includes a timer built in the microcomputer, and outputs a base clock signal having a frequency corresponding to the count value of the timer. The inverter drive pulse generator 25 includes a multiplication circuit 43 that multiplies the base clock signal, and generates drive pulse signals VG1 to VG4 having a frequency that is eight times the frequency of the base clock signal. The transistors 18 to 21 of the inverter 3 are driven by the drive pulse signals VG1 to VG4. As a result, the switching frequency of the inverter 3 can be changed in units of about 1.5 Hz according to the timer count in the base clock generation unit 34.

  As described above, since the resolution of the switching frequency can be increased as compared with the conventional one, switching power control (heating power control) when the material of the object to be heated 31 is aluminum, which was difficult in the prior art, is switched. It can be performed with accuracy only by frequency control, and the control content of power control can be simplified. Further, since it is not necessary to control the DC voltage VDC for power control, the chopper circuit 15, the power factor correction unit 40, and the driver 41 do not need to have a voltage variable function. Accordingly, since it is possible to use those configurations having only a power factor improvement function, it is possible to obtain an effect of increasing the number of options for parts.

  It is possible to easily change the resolution of the switching frequency simply by changing the multiplication number in the multiplication circuit 43. If the multiplication number of the multiplication circuit 43 is increased, the frequency of the base clock signal can be lowered. That is, the control circuit 5 can be configured by a relatively inexpensive microcomputer that operates with a low reference clock (for example, an 8-bit microcomputer with a reference clock of 20 MHz). As a result, power consumption in the microcomputer is reduced, and the burden on the power supply circuit that supplies power to the control circuit 5 can be reduced.

  The base clock signal generated by the base clock generation unit 34 is a square wave signal (a signal with a duty of 50%) generated based on the count value of the timer. For this reason, it is not necessary to configure the control circuit 5 using a microcomputer having a function of generating a special output waveform (for example, a function of generating a PWM signal for three-phase motor control). Therefore, it is possible to use a relatively inexpensive microcomputer having a standard function.

  A dead time variable circuit 45 is provided, and the rising timing of the drive pulse signals VG1 to VG4 can be changed in two stages. That is, the length of the dead time of each arm of the inverter 3 can be changed in two stages. When the resonance current of the resonance circuit 4 becomes small, the time for which the snubber capacitors 22 and 23 are charged becomes long. Therefore, when the resonance current is small, that is, when the input power is small, the dead time is lengthened, and when the resonance current is large, that is, when the input power is large, the dead time is shortened to reduce the switching loss due to the snubber voltage. Can be reduced.

  The dead time variable circuit 45 generates the drive pulse signals VG1 to VG4 by delaying only the rising timing of the drive pulse signals VG1 'to VG4'. In this way, the dead time during which the arm switching elements are simultaneously turned off can be set reliably, and the time is not set unnecessarily long. Thus, since the dead time does not become longer than necessary, it is possible to prevent a problem that the desired power cannot be obtained due to setting the dead time too long.

(Second Embodiment)
Hereinafter, a second embodiment in which the configuration for generating the drive pulse signals VG1 to VG4 is partially changed with respect to the first embodiment will be described with reference to FIGS.
In the present embodiment, an inverter drive pulse generation unit 71 shown in FIG. 10 is used instead of the inverter drive pulse generation unit 25 shown in FIG. The inverter drive pulse generation unit 71 is provided with a multiplication circuit 72 instead of the multiplication circuit 43, a new division circuit 73, and a dead time variable circuit with respect to the inverter drive pulse generation unit 25. The difference is that a dead time variable circuit 74 is provided instead of 45.

  The multiplication circuit 72 has substantially the same configuration as the multiplication circuit 43 shown in FIG. 3, but the multiplication number is different. The multiplier circuit 72 generates a multiplied clock signal obtained by multiplying the base clock signal supplied from the control circuit 5 by 128 times. The multiplier circuit 72 can be configured, for example, by changing the frequency division number of the frequency divider 50 in the multiplier circuit 43 from 64 to 128. Note that the multiplication number of the multiplication circuit 72 can be appropriately changed as long as it is a value larger than the multiplication number of the multiplication circuit 43 such as 258, for example.

  The frequency divider 73 divides the output signal of the frequency multiplier 72 by half (divided by 2). The output signal of the frequency dividing circuit 73 is given to the waveform generating circuit 44 as a frequency divided clock signal. This frequency-divided clock signal is obtained by multiplying the base clock signal by 64 times (128/2 times), and is the same as the multiplied clock signal in the first embodiment. The frequency divider 73 outputs the input signal with a frequency halved without changing the duty of the input signal. When the multiplication number of the multiplication circuit 72 is other than 128, the division ratio of the division circuit 73 is changed so that the frequency of the divided clock signal is the same as the frequency of the multiplied clock signal in the first embodiment. do it. The dead time variable circuit 74 changes the rising timing of the drive pulse signals VG1 'to VG4' in synchronization with the multiplied clock signal output from the multiplier circuit 72, and outputs it as drive pulse signals VG1 to VG4.

  FIG. 11 shows an example of the configuration of the dead time variable circuit 74, and FIGS. 12 and 13 show signal waveforms at various parts of the dead time variable circuit 74. The dead time variable circuit 74 shown in FIG. 11 changes so as to delay only the rising timing of the input drive pulse signal VG1 'and outputs it as the drive pulse signal VG1. Although not shown, the same configuration as that of the present circuit is provided corresponding to the drive pulse signals VG2 'to VG4'.

  The dead time variable circuit 74 includes a two-stage shift register 77 composed of flip-flops 75 and 76, buffers 78 and 79, and an AND circuit 80. The shift register 77 uses the multiplied clock signal provided from the multiplication circuit 72 as an operation clock. That is, a multiplied clock signal (operation clock signal) is supplied to the clock terminals CK of the flip-flops 75 and 76. Note that the shift register 77 is not limited to two stages, and the number of stages can be appropriately changed according to the required dead time.

  The input terminal of the drive pulse signal VG 1 ′ is connected to the input terminal D of the flip-flop 75 and one input terminal of the AND circuit 80. The output terminal Q of the flip-flop 75 is connected to the input terminal of the buffer 78. The output terminal Q of the flip-flop 76 is connected to the input terminal of the buffer 79. Buffers 78 and 79 are tristate buffers. The buffer 78 outputs an input signal when an L level signal is applied to the gate terminal, and puts the output terminal in a high impedance state when an H level signal is applied. The buffer 79 outputs an input signal when an H level signal is applied to the gate terminal, and puts the output terminal in a high impedance state when an L level signal is applied.

  A switching signal is given to each gate terminal of the buffers 78 and 79. This switching signal is the same as the switching signal of the first embodiment, and is output from the control circuit 5. The output terminals of the buffers 78 and 79 are connected in common and are connected to the other input terminal of the AND circuit 80. The output terminal of the AND circuit 80 is an output terminal for the drive pulse signal VG1.

  According to such a configuration, when the switching signal is at the L level, the output signal of the flip-flop 75 is given to the other input terminal of the AND circuit 80. As shown in FIGS. 12A to 12C, the output signal of the flip-flop 75 is obtained by delaying the drive pulse signal VG1 'by one cycle of the operation clock signal. A logical product of the output signal of the flip-flop 75 and the drive pulse signal VG1 'is output as the drive pulse signal VG1 (see FIG. 12D). The rise timing of the drive pulse signal VG1 is delayed by one clock compared with the rise timing of the drive pulse signal VG1 '. On the other hand, the fall timing of the drive pulse signal VG1 is the same as the fall timing of the drive pulse signal VG1 '.

  When the switching signal is at the H level, the output signal of the flip-flop 76 is given to the other input terminal of the AND circuit 80. As shown in FIGS. 13A to 13C, the output signal of the flip-flop 76 is obtained by delaying the drive pulse signal VG1 'by two cycles of the operation clock signal. A logical product of the output signal of the flip-flop 76 and the drive pulse signal VG1 'is output as the drive pulse signal VG1 (see FIG. 13D). The rise timing of the drive pulse signal VG1 is delayed by two clocks compared to the rise timing of the drive pulse signal VG1 '. On the other hand, the fall timing of the drive pulse signal VG1 is the same as the fall timing of the drive pulse signal VG1 '.

According to the above configuration, the following effects can be obtained.
The dead time variable circuit 45 of the first embodiment is configured to set the dead time using a time constant related to the charging operation to the capacitors 61 and 62. For this reason, there is a possibility that the dead time may fluctuate due to variations in the capacitance of the capacitors 61 and 62 and the resistance value of the resistor 59, fluctuation due to their temperature and aging, and the like.
On the other hand, the dead time variable circuit 74 of the present embodiment uses the shift register 77 that operates in synchronization with the multiplied clock signal as described above, and sets the dead time in synchronization with the multiplied clock signal (operation clock). It is a configuration. For this reason, the dead time can be accurately set to a desired time, and the problem that the dead time fluctuates due to the accuracy of component constants, temperature characteristics, aging deterioration, and the like does not occur.

  The frequency divider 73 and the dead time variable circuit 74 are configured as digital circuits. The waveform generation circuit 44 is also configured as a digital circuit. This makes it possible to configure these circuits with gate arrays, FPGAs (Field Programmable Gate Arrays), PLDs (Programmable Logic Devices), etc., simplifying the circuit configuration and reducing the board area and the number of components. The effect is obtained. Since the circuit configuration excluding a part of the multiplier circuit 72 (LPF 47, capacitor, resistor, etc. constituting the VCO 48) is also a digital circuit, if the circuit configuration is incorporated in a gate array or the like, each of the above-described effects can be obtained. Will increase.

  The dead time variable circuit 74 can easily change the length of the dead time in units of one cycle of the multiplied clock signal by changing the number of stages of the shift register 77. The length of the dead time can also be changed by changing the frequency of the multiplied clock signal supplied to the dead time variable circuit 74. The frequency of the multiplied clock signal can be changed by changing the multiplication number of the multiplication circuit 72, for example. However, in that case, it is necessary to change the frequency dividing number of the frequency dividing circuit 73 in accordance with the change of the multiplication number.

(Third embodiment)
Hereinafter, a third embodiment in which the configuration for generating the drive pulse signals VG1 to VG4 is partially changed with respect to the first embodiment will be described with reference to FIG.
In the present embodiment, an inverter drive pulse generator 91 shown in FIG. 14 is used instead of the inverter drive pulse generator 25 shown in FIG. The inverter drive pulse generation unit 91 includes a multiplier circuit 92 in addition to the inverter drive pulse generation unit 25 shown in FIG. 2, and a dead time variable circuit 93 instead of the dead time variable circuit 45. Is different.

  A multiplier circuit 92 (corresponding to a clock multiplier circuit) generates an operation clock signal obtained by multiplying the multiplied clock signal supplied from the multiplier circuit 43 by a factor of two. The multiplier circuit 92 can be configured, for example, by changing the frequency dividing number of the frequency divider 50 in the multiplier circuit 43 shown in FIG. Note that the multiplication number of the multiplication circuit 92 can be appropriately changed according to the length of the required dead time.

  The dead time variable circuit 93 has the same configuration as the dead time variable circuit 74 of the second embodiment. The dead time variable circuit 93 changes the rising timing of the drive pulse signals VG1 'to VG4' in synchronization with the operation clock signal output from the multiplier circuit 92, and outputs the drive pulse signals VG1 to VG4. Even with such a configuration, the same operations and effects as those of the second embodiment can be obtained.

(Fourth embodiment)
Hereinafter, a fourth embodiment of the present invention will be described with reference to FIGS.
15 to 17 correspond to FIGS. 1 to 3 in the first embodiment, and the same or corresponding components as those in FIGS. 1 to 3 are denoted by the same reference numerals and description thereof is omitted. To do. The induction heating cooker 101 of this embodiment shown in FIG. 15 is different from the induction heating cooker 1 of the first embodiment shown in FIG. 1 in that the inverter drive pulse generator 25, the input voltage detection circuit 35, and the inverter current detection. The difference is that an inverter drive pulse generator 102, an input voltage detection circuit 103, and an inverter current detection circuit 104 are provided instead of the circuit 38.

  The input voltage detection circuit 103 (corresponding to the input voltage detection means) performs full-wave rectification and smoothing of the AC voltage (input voltage) between the AC power supply lines L1 and L2, and the input voltage detection signal Vd1 obtained by dividing the smoothed output. Is output as the detected value of the input voltage. The inverter current detection circuit 104 (corresponding to the inverter current detection means) detects the current flowing through the inverter 3 as a voltage through the current transformer 39, and rectifies and smooths the detected voltage with full-wave rectification and divides the smoothed output. The pressed inverter current detection signal Vd2 is output as the detected value of the inverter current. The inverter drive pulse generation unit 102 is supplied with detection signals Vd1 and Vd2 from the input voltage detection circuit 103 and the inverter current detection circuit 104.

  When the inverter drive pulse generator 102 detects that one of the value of the input voltage and the value of the inverter current has risen beyond the first abnormal value based on the detection signals Vd1 and Vd2, the drive pulse signal VG1 When the frequency of VG4 is set higher than the set value and it is detected that one of the frequencies exceeds the second abnormal value, the output of the drive pulse signals VG1 to VG4 is stopped (prohibited) ( Details will be described later).

  In the present embodiment, the abnormal values of the input voltage and the inverter current are determined as follows. That is, the induction heating cooker 101 is a 200V device. For this reason, for example, 220V is set as the first abnormal value of the input voltage, and 240V is set as the second abnormal value. The rated current (instantaneous value) of the first to fourth transistors 18 to 21 constituting the inverter 3 is generally about 120A. Therefore, 90A is the first abnormal value of the inverter current, and 100A is the second abnormal value. Note that these abnormal values are not limited to the above values, but may be changed as appropriate according to the ratings of the devices and parts.

  FIG. 16 shows the configuration of the inverter drive pulse generator 102. The inverter drive pulse generation unit 102 further includes an output control circuit 105 and a multiplication number switching circuit 106 in addition to the inverter drive pulse generation unit 25 shown in FIG. 2, and a multiplication circuit 107 instead of the multiplication circuit 43. It is different from the point of having.

  The output control circuit 105 (corresponding to the output stop means) is composed of comparators 108 and 109 and a gate circuit 110. The inverting input terminal of the comparator 108 is supplied with the input voltage detection signal Vd1. A threshold voltage Vt1H (first threshold value) is applied to the non-inverting input terminal of the comparator 108. An inverter current detection signal Vd2 is applied to the inverting input terminal of the comparator 109. A threshold voltage Vt2H (first threshold value) is applied to the non-inverting input terminal of the comparator 109.

  The gate circuit 110 is provided corresponding to each of the drive pulse signals VG1 to VG4, but here, only the one corresponding to the drive pulse signal VG1 is illustrated and described. The gate circuit 110 calculates and outputs a logical product of the signals given to the three input terminals. The drive pulse signal VG1 and the output signals Sa and Sb of the comparators 108 and 109 are supplied to the three input terminals of the gate circuit 110, respectively. The output terminal of the gate circuit 110 is an output terminal for the drive pulse signal VG1.

  The multiplication number switching circuit 106 (corresponding to the multiplication number switching means) is composed of comparators 111 and 112 and a gate circuit 113. An input voltage detection signal Vd1 is given to the inverting input terminal of the comparator 111. A threshold voltage Vt1L (second threshold) lower than the threshold voltage Vt1H is applied to the non-inverting input terminal of the comparator 111. An inverter current detection signal Vd2 is given to the inverting input terminal of the comparator 112. A threshold voltage Vt2L (second threshold) lower than the threshold voltage Vt2H is applied to the non-inverting input terminal of the comparator 112. The gate circuit 113 calculates and outputs the logical product of the signals given to the two input terminals. Output signals Sc and Sd of the comparators 111 and 112 are supplied to two input terminals of the gate circuit 113. The output signal Se of the gate circuit 113 is given to the multiplier circuit 107.

  In the present embodiment, the threshold voltages Vt1H, Vt2H, Vt1L, and Vt2L are set to the following values. That is, the threshold voltage Vt1H is set to a value equal to the voltage value of the input voltage detection signal Vd1 output when the input voltage is 240V. The threshold voltage Vt1L is set to a value equal to the voltage value of the input voltage detection signal Vd1 output when the input voltage is 220V. The threshold voltage Vt2H is set to a value equal to the voltage value of the inverter current detection signal Vd2 output when the inverter current is 100A. The threshold voltage Vt2L is set to a value equal to the voltage value of the inverter current detection signal Vd2 output when the inverter current is 90A.

  FIG. 17 shows a configuration example of the multiplier circuit 107. The multiplication circuit 107 shown in FIG. 17 is different from the multiplication circuit 43 shown in FIG. 3 in that a frequency divider 114 is provided instead of the frequency divider 50. The frequency divider 114 is supplied with the output signal Se from the multiplication number switching circuit 106. The frequency divider 114 switches the frequency division ratio according to the logic level of the output signal Se. Specifically, the frequency divider 114 sets the frequency division ratio to 1/64 when the output signal Se is at a high level. Thereby, the multiplication number of the multiplication circuit 107 becomes 64 times as usual. On the other hand, when the output signal Se is at a low level, the frequency divider 114 sets the frequency division ratio to 1/128, which is larger than usual. Thereby, the multiplication number of the multiplication circuit 107 becomes 128 times larger than usual. Note that the frequency divider 114 is often constituted by a binary counter, for example. In this case, the output of the counter used for frequency division output may be switched so as to obtain a desired frequency division ratio according to the logic level of the output signal Se.

Next, the operation and effect of the above configuration will be described.
When the input voltage between the AC power supply lines L1 and L2 is less than 220V and the inverter current flowing through the inverter 3 is less than 90A, the output signals Sa and Sb of the comparators 108 and 109 are all at the high level. Become. Therefore, the gate circuit 110 is in a state (output permission state) in which the input drive pulse signals VG1 to VG4 are output as they are. Further, the output signals Sc and Sd of the comparators 111 and 112 are both at a high level. For this reason, the output signal Se of the gate circuit 113 becomes a high level, the multiplication number of the multiplication circuit 107 becomes 64 times as usual, and the frequencies of the output drive pulse signals VG1 to VG4 become the set values.

  Subsequently, when the input voltage rises to 220 V or higher, the output signal Sc of the comparator 111 turns to the low level. For this reason, the output signal Se of the gate circuit 113 is changed to the low level and is changed to the multiplication number 128 times of the multiplication circuit 107. Thereby, the frequency of the output drive pulse signals VG1 to VG4 becomes higher than the set value. This state is continued until the input voltage becomes less than 220V or becomes 240V or more.

  Further, when the inverter current increases to 90 A or more, the output signal Sd of the comparator 112 turns to the low level. For this reason, the output signal Se of the gate circuit 113 is changed to the low level, and the same state as that when the input voltage is increased to 220 V or higher is obtained. This state is continued until the inverter current becomes less than 90A or 100A or more. In this way, by changing the frequency of the drive pulse signals VG1 to VG4 to be higher than the set value, the input power (heating power) is reduced.

  Subsequently, when the input voltage further increases to 240 V or more, the output signal Sa of the comparator 108 turns to the low level. For this reason, a low level signal (a signal fixed to 0V) is output from the gate circuit 110 (output prohibited state). Further, when the inverter current further increases to 100 A or more, the output signal Sb of the comparator 109 turns to the low level. For this reason, a low level signal is output from the gate circuit 110 (output prohibited state). When the low level signal is output from the gate circuit 110 in this way, the first to fourth transistors 18 to 21 are immediately turned off, and the drive of the inverter 3 is stopped.

  As described above, the inverter drive pulse generation unit 102 of the present embodiment is configured so that the input voltage between the AC power supply lines L1 and L2 rises to the second abnormal value (240V) or more, or the inverter that flows to the inverter 3 An output control circuit 105 is provided to stop the output of the drive pulse signals VG1 to VG4 when the current rises to the second abnormal value (100A) or more. According to such a configuration, for example, when the input voltage suddenly increases due to the influence of a lightning surge or the voltage fluctuation of the AC power supply 11, or so-called pan removal, pan-shifting, pan-floating, etc., the induction heating coil 27 The first to fourth transistors 18 to 21 are immediately turned off and the drive of the inverter 3 is stopped. Therefore, it is possible to prevent a situation in which the input power is suddenly increased due to the increase of the input voltage or the inductance of the induction heating coil 27 and the first to fourth transistors 18 to 21 are broken.

  Moreover, the change of the input power accompanying the increase of the input voltage or the change of the inductance becomes even more rapid when an object having a high Q value such as an aluminum pan is used as the article to be heated 31. Since the inverter drive pulse generator 102 of this embodiment stops (prohibits) the output of the inverter drive pulse signals VG1 to VG4 immediately after detecting an abnormality in the input voltage or inverter current, it follows the sudden change in input power. Thus, the drive of the inverter 3 can be stopped.

  When the drive of the inverter 3 is stopped, a certain amount of time is required until the drive of the inverter 3 is restarted thereafter because the load determination needs to be performed again. For this reason, in the present embodiment, the first to fourth transistors 18 to 21 are protected in the following manner with respect to an increase in input power that does not immediately cause a failure of the inverter 3.

  That is, the inverter drive pulse generation unit 102 multiplies the multiplication circuit 107 when the input voltage rises above the first abnormal value (220V) or when the inverter current rises above the first abnormal value (90A). A multiplication number switching circuit 106 for increasing the number than usual is provided. According to such a configuration, when the input voltage and the inverter current rise to such an extent that the first to fourth transistors 18 to 21 do not fail immediately, the frequencies of the drive pulse signals VG1 to VG4 are set. It becomes higher than the value and the input power is reduced. Therefore, the first to fourth transistors 18 to 21 can be protected without stopping the driving of the inverter 3.

  The output control circuit 105 includes comparators 108 and 109 and a gate circuit 110 interposed in the output path of the drive pulse signals VG1 to VG4. The multiplication number switching circuit 106 includes comparators 111 and 112 and a gate circuit 113. That is, the output control circuit 105 and the multiplication number switching circuit 106 are configured as digital circuits. As a result, these circuits can be configured by ASIC (Application Specific Integrated Circuit), FPGA, PLD, etc., and the circuit configuration can be simplified, and effects such as reduction of the board area and the number of parts can be obtained.

(Other embodiments)
The present invention is not limited to the embodiments described above and illustrated in the drawings, and the following modifications or expansions are possible.
The drive pulse signals VG1 to VG4 are not limited to the waveforms shown in the above embodiments. That is, the drive system of the inverter 3 is not limited to the system that can suffice the switching frequency shown in the above embodiments to be 1/4 of the frequency of the resonance current. For example, the switching frequency may be a half of the resonance current frequency. Moreover, the system which makes the switching frequency the same as a resonant current may be sufficient. Furthermore, it is good also as a structure which can switch these systems. In that case, when heating the heated object 31 made of an aluminum material that requires heating at a high frequency, the switching frequency is driven by a method that can be lower than the frequency of the resonance current, and the iron-based material is driven. When heating the object to be heated 31 that can be heated with sufficiently high efficiency even at a low frequency of about 20 kHz, such as a material, it may be configured to be driven by a method in which the switching frequency is the same as the frequency of the resonance current.
When the material of the article to be heated 31 is iron-based, the multiplication number of the multiplication circuit 43 is decreased. When the material of the object to be heated 31 is aluminum-based, the multiplication number of the multiplication circuit 43 is increased. You may comprise. In this case, if the frequency of the drive clock signals VG1 to VG4 output from the inverter drive pulse generator 25, that is, the switching frequency of the inverter 3 is not changed, the frequency of the base clock signal is changed according to the change of the multiplication number. Good.

When the material of the object to be heated 31 is a material having high magnetic permeability such as iron, the heating frequency control range may be wide, for example, 20 kHz to 100 kHz. In this case, the ratio between the minimum value and the maximum value of the frequency within the control range is 5. On the other hand, the dynamic range of voltage-frequency conversion of the VCO 48 of the multiplier circuit 43 is usually about 2 to 3. For this reason, if the multiplication number (frequency division ratio of the frequency divider 50) is fixed, the frequency control range cannot be realized. In order to solve such a problem, when the iron-based material to be heated 31 is heated, the frequency dividing ratio of the frequency divider 50 of the multiplier circuit 43 may be changed midway. In that case, the heating operation may be temporarily stopped when the frequency division ratio is switched. If it does so, since the drive frequency of the inverter 3 will not change rapidly during heating operation, the failure of the inverter 3 can be prevented beforehand.
In the second embodiment, instead of the configuration in which the frequency dividing ratio of the frequency divider 50 is changed in the middle, the frequency dividing ratio of the frequency dividing circuit 73 may be changed in the middle. Alternatively, in the high frequency range, the multiplied clock signal is supplied to the waveform generating circuit 44 without passing through the divider circuit 73, and in the low frequency range, the divided clock signal obtained by dividing the multiplied clock signal by the divider circuit 73 is waveform-generated. A configuration may be applied to the circuit 44. If each structure mentioned above is employ | adopted, it will become possible to take the control range of a heating frequency widely.

The control circuit 5 only needs to have a function as the base clock generation unit 34 that generates the base clock signal by dividing the reference clock, and may be configured by a DSP (Digital Signal Processor), for example. If the inverter drive pulse generator 25 outputs drive pulse signals VG1 to VG4 that are higher than the base clock signal, preferably at least twice the frequency of the base clock signal, the multiplication number of the multiplier circuit 43 can be changed as appropriate. It is. That is, the multiplier circuit 43 may be any circuit that multiplies the base clock signal by n times (n is an integer). Further, the multiplication circuits 43, 72, and 92 are not limited to the circuit configuration shown in FIG.
The waveform generation circuit 44 only needs to generate the drive pulse signals VG1 ′ to VG4 ′ based on the multiplied clock signal, and is not limited to the circuit configuration shown in FIG.
The dead time variable circuit 45 is not limited to the circuit configuration of FIG. 6 as long as it changes the rising timing of the drive pulse signals VG1 ′ to VG4 ′ and outputs the drive pulse signals VG1 to VG4. The dead time variable circuits 74 and 93 are not limited to the circuit configuration of FIG. 11 as long as the dead time is set by an operation synchronized with the multiplied clock signal. For example, a counter that counts the multiplied clock signal may be provided, and the drive pulse signals VG1 to VG4 in which the dead time is set may be generated using the output signal of the counter and the drive pulse signals VG1 ′ to VG4 ′. Further, the dead time variable circuit may be capable of switching the dead time in three or more stages, or may be one having no dead time switching function. Furthermore, the dead time variable circuit may be provided as necessary.

  In the fourth embodiment, the gate circuit 110 of the output control circuit 105 is provided corresponding to each of the drive pulse signals VG1 to VG4. That is, the output control circuit 105 simultaneously stops driving the first and third transistors 18 and 20 constituting the upper arm of the inverter 3 and the second and fourth transistors 19 and 21 constituting the lower arm. It was. In such a configuration in which the upper and lower arms are simultaneously stopped, the resonance state in the inverter 3 is suddenly stopped, and abnormal noise may be generated from the pan or the like immediately after the upper and lower arms are stopped. As a countermeasure, the gate circuit 110 of the output control circuit 105 may be provided corresponding to only the drive pulse signals VG1 and VG3. With this configuration, the output control circuit 105 stops only the output of the drive pulse signals VG1 and VG3 for driving the first and third transistors 18 and 20 constituting the upper arm of the inverter 3. Become. Thereby, immediately after only the upper arm is stopped, the minimum resonance state is maintained in the inverter 3, so that the generation of the abnormal noise can be prevented. Further, in such a configuration, the inverter 3 is controlled so that the lower arm is stopped after a predetermined period (for example, about a half cycle of the AC power supply cycle) after the upper arm is stopped and the resonance state is sufficiently attenuated. That's fine.

The output control circuit 105 may include only one of the comparators 108 and 109. That is, the output control circuit 105 may be configured to detect only one of the input voltage abnormality and the inverter current abnormality and stop the output of the drive pulse signals VG1 to VG4. Further, the multiplication number switching circuit 106 may include only one of the comparators 111 and 112. That is, the multiplication number switching circuit 106 may be configured to detect only one of the abnormality of the input voltage or the abnormality of the inverter current and change the multiplication number of the multiplication circuit 107.
The multiplication number switching circuit 106 may be provided as necessary.
The output control circuit 105 may be configured to stop the output of the drive pulse signals VG1 to VG4 in response to an abnormality in the input voltage or the inverter current, and is not limited to the circuit configuration in FIG. The multiplication number switching circuit 106 may be configured to switch the multiplication number of the multiplication circuit 107 in accordance with an abnormality in the input voltage or the inverter current, and is not limited to the circuit configuration in FIG.

  In the drawings, 1 and 101 are induction heating cookers, 2 is a DC power supply circuit, 3 is an inverter, 4 is a resonance circuit, 9 is control means, 18 to 21 are first to fourth transistors (switching elements), and 27 is Induction heating coil, 28 and 29 are resonance capacitors, 31 is an object to be heated, 33 is a load determination unit (material determination unit), 34 is a base clock generation unit (clock signal generation circuit), 43, 72 and 107 are multiplication circuits, 44 is a waveform generation circuit (drive signal generation circuit), 45, 74, and 93 are dead time variable circuits, 73 is a frequency divider, 77 is a shift register, 92 is a multiplier (clock multiplier), and 103 is an input voltage detector. (Input voltage detection means), 104 is an inverter current detection circuit (inverter current detection means), 105 is an output control circuit (output stop means), 106 is a multiplication number switching circuit (multiplication number cut-off) Means), 110 denotes a gate circuit.

Claims (15)

A DC power supply circuit;
A resonance circuit including an induction heating coil and a resonance capacitor for induction heating of an object to be heated;
An inverter that includes a plurality of switching elements, and converts the DC voltage output from the DC power supply circuit into a high-frequency voltage and supplies the high-frequency voltage to the resonance circuit;
Control means for controlling the switching operation of the inverter,
The control means includes
A clock signal generation circuit that divides a reference clock signal to generate a base clock signal;
A multiplier circuit for generating a multiplied clock signal obtained by multiplying the base clock signal;
An induction heating cooker, comprising: a drive signal generation circuit that generates a plurality of drive signals for driving the plurality of switching elements based on the multiplied clock signal. The induction heating cooker according to claim 1,
The induction heating cooker, wherein the clock signal generation circuit is constituted by a microcomputer. The induction heating cooker according to claim 1 or 2,
The induction heating cooker, wherein the base clock signal is a signal having a duty of 50%. In the induction heating cooker according to any one of claims 1 to 3,
The inverter includes an arm having two switching elements connected in series,
Induction heating cooking characterized by comprising a dead time variable circuit for changing the plurality of drive signals so that the dead time during which the two switching elements of the arm are simultaneously turned off becomes longer as the input power is smaller vessel. The induction heating cooker according to claim 4,
The induction heating cooker, wherein the dead time variable circuit sets the dead time by an operation synchronized with the multiplied clock signal. The induction heating cooker according to claim 5,
The variable dead time circuit includes a shift register that operates in synchronization with the multiplied clock signal, and the dead time is set using a signal obtained by delaying the drive signal through the shift register. Induction heating cooker. The induction heating cooker according to claim 6,
A frequency dividing circuit for frequency-dividing the multiplied clock signal;
The drive signal generation circuit generates the drive signal using an output signal of the frequency divider circuit,
The induction cooker, wherein the shift register uses the multiplied clock signal as an operation clock. The induction heating cooker according to claim 6,
A clock multiplication circuit for multiplying the multiplied clock signal;
The drive signal generation circuit generates the drive signal using the multiplied clock signal,
The shift register uses an output signal of the clock multiplication circuit as an operation clock. In the induction heating cooker according to any one of claims 4 to 8,
The induction heating cooking device, wherein the dead time variable circuit sets a dead time by changing a rising timing of the drive signal. The induction heating cooker according to any one of claims 1 to 9,
Comprising a material judging means for judging the material of the object to be heated;
An induction heating cooker characterized in that when the material determining means determines that the material of the object to be heated is a low magnetic permeability metal, the multiplication number of the multiplication circuit is increased. In the induction heating cooker according to any one of claims 1 to 10,
Input voltage detection means for detecting an input voltage input to the DC power supply circuit and outputting the detected value;
An induction heating cooker comprising: output stop means for stopping output of the drive signal when the detected value is equal to or greater than a first threshold value. The induction heating cooker according to any one of claims 1 to 11,
Inverter current detection means for detecting the inverter current flowing through the inverter and outputting the detected value;
An induction heating cooker comprising: output stop means for stopping output of a drive signal when the detected value is equal to or greater than a first threshold value. The induction heating cooker according to claim 11 or 12,
The induction heating cooker characterized in that the output stop means includes a gate circuit provided in an output path of the drive signal. The induction heating cooker according to any one of claims 11 to 13,
An induction heating cooker comprising a multiplication number switching means for increasing a multiplication number of the multiplication circuit when the detected value is equal to or higher than a second threshold value lower than the first threshold value. . In the induction heating cooker according to any one of claims 11 to 14,
The inverter includes an arm having two switching elements connected in series,
The induction heating cooker, wherein the drive stop means stops only the output of the drive signal for driving the upper arm of the arms.

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