JP2011065972A - Electric discharge lamp lighting device and luminaire employing the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an electric discharge lamp lighting device which reliably performs detection of end of life and detection of a load short circuit, suppresses stress to a resonance circuit to improve safety, and miniaturizes a coil of the resonance circuit. <P>SOLUTION: The electric discharge lamp lighting device including a feedback control circuit varying an operating frequency of a driving signal by detecting a lighting condition of an electric discharge lamp la for feedback to a drive control circuit, has: a detecting circuit for detecting voltage applied to the electric discharge lamp la to generate a detecting signal; a first decision unit (comparator CP1) for input of the detecting signal to determine that the detecting signal is abnormal when it is over a first value Vref1; a second decision unit (comparator CP2) for input of the detecting signal to determine that the detecting signal is abnormal when it is below a second value Vref2 (<Vref1); and a mask (AND gate G1) invalidating results of decision of the first decision unit during any time from immediately after staring of an inverter to termination of starting control. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a discharge lamp lighting device for lighting a discharge lamp at high frequency and a lighting fixture using the same.

(Conventional example 1)
Conventionally, a discharge lamp lighting device (Japanese Patent Laid-Open No. 10-189278) as shown in FIG. 17 has been proposed. In this lighting device, a DC voltage supplied from a DC power supply 10 is converted into high-frequency power by an inverter circuit 11 and supplied to a discharge lamp la. Specifically, a series circuit of switching elements Q1 and Q2 made of a power MOSFET is connected to the DC power source 10, and a discharge lamp la is connected to both ends of the switching element Q2 via a coupling capacitor C2 and a resonance inductor L1. Yes. A resonance and starting capacitor C3 is connected in parallel to the discharge lamp la.

  The gates of the switching elements Q1, Q2 are connected to the control circuit 13. The control circuit 13 incorporates a high frequency oscillation circuit and controls the oscillation frequency. When the switching elements Q1, Q2 are alternately turned on by the control circuit 13, high-frequency power is supplied to the discharge lamp la.

  A detection circuit 12 that detects a lamp voltage is connected to the discharge lamp la. The detection circuit 12 detects the lamp voltage of the discharge lamp la, and if this lamp voltage is a normal lamp voltage that does not exceed a predetermined voltage (abnormal voltage), it is an abnormal lamp voltage that is higher than a predetermined voltage such as H output or the end of lamp life. Is a signal output of L output.

  The output from the detection circuit 12 is connected to the negative input terminal of the comparator CP through the resistor R7. In addition, a voltage obtained by dividing the voltage of the DC power supply 10 by the resistors R9 and R10 is applied to the negative input terminal of the comparator CP, and a capacitor C5 is connected in parallel with the resistor R10. A reference voltage obtained by dividing the voltage of the DC power supply 10 by resistors R6 and R8 is applied to the + input terminal of the comparator CP. The output of the comparator CP is input to the control circuit 13.

  When the output of the comparator CP is L, the control circuit 13 is controlled with, for example, an oscillation frequency of 50 kHz, and when it is H, the control circuit 13 is controlled with an oscillation frequency of 100 kHz, for example. The oscillation frequency is set to be higher than the resonance frequency at the time of lighting. The oscillation frequency is 50 kHz and the full power is in the full lighting state. The oscillation frequency of 100 kHz is the power saving state (about 30% with respect to the full power full lighting state). Brightness).

  FIG. 18 shows operation waveforms of each part of the circuit of FIG. In the figure, (a) is the output (H / L) from the detection circuit 12, (b) is the voltage at the negative input terminal of the comparator CP (voltage of the capacitor C5), and (c) is the output (H / L) of the comparator CP. ) And (d) are control states.

  At the time of power-on, when the lamp voltage is normal, as shown in FIG. 18A, the output of the detection circuit 12 is H, and the voltage at the negative input terminal of the comparator CP is moderated while the capacitor C5 is charged. To rise. Initially, as shown in FIG. 18C, the output of the comparator CP is H, and oscillates at an oscillation frequency of 100 kHz. This also serves as preheating for extending the lamp life. After that, when the voltage at the negative input terminal of the comparator CP exceeds the reference voltage at the positive input terminal, the output of the comparator CP is inverted as shown in FIG. .

  On the other hand, in the case of an abnormal lamp voltage such as the end of life of the discharge lamp la, first, the same operation as that of the normal lamp is performed. However, when the detection circuit 12 detects the abnormal voltage, as shown in FIG. When the output of 12 becomes L and the capacitor C5 is discharged and becomes equal to or lower than the reference voltage, the output of the comparator CP becomes H and the power saving state is entered. However, when the power saving state is entered, the lamp voltage decreases, the output of the detection circuit 12 becomes H again, the capacitor C5 is charged, and when the reference voltage is exceeded, the output of the comparator CP is inverted and the 50 kHz normal lighting is performed. Become. Thereafter, by repeating charging / discharging with the time constants of the resistor R7 and the capacitor C5, the operation of repeating the power saving mode and the normal lighting brightness is performed to alert the user that the discharge lamp la is about to be replaced. .

(Conventional example 2)
Further, a discharge lamp lighting device (Japanese Patent Laid-Open No. 2001-267090) equipped with a feedback circuit as shown in FIG. 19 has been proposed. 20 is a DC power supply, 21 is an inverter circuit, 22 is a resonant load circuit, 23 is a feedback circuit, 24 is an error amplifier, 25 is an oscillation circuit, and 26 is a control power supply circuit. The control power supply circuit 26 includes a step-down resistor R11, a smoothing capacitor C6, and a constant voltage diode ZD1, and generates a control power supply voltage Vcc from the DC power supply 20. The control power supply voltage Vcc serves as a drive power supply for the oscillation circuit 25 formed of an integrated circuit, and serves as a drive power supply for the operational amplifier OP1 of the error amplifier 24 in the feedback circuit 23. Further, the voltage is divided by the resistors R12 and R13, and the reference voltage is supplied to the non-inverting input terminal of the operational amplifier OP1.

  Since the configuration of the resonant load circuit 22 is the same as that of the conventional example 1, the feedback circuit 23 having a different configuration will be described. The feedback circuit 23 includes a detection resistor R17 that detects a high-frequency current flowing through the discharge lamp la, an integration circuit that includes a resistor R16 that integrates a high-frequency voltage detected by the detection resistor R17, and a capacitor C7, and a capacitor C7 for integration. An operational amplifier OP1 is provided as a feedback impedance. The high frequency voltage generated in the detection resistor R17 is averaged by the resistor R16 of the feedback circuit 23 and the capacitor C7, and the averaged DC voltage is applied to the inverting input terminal of the operational amplifier OP1 of the error amplifier 24.

  The oscillation frequency of the oscillation circuit 25 is originally set by the time constant of the capacitor C8 and the resistor R15, but when the output voltage of the operational amplifier OP1 changes, the current flowing out of the oscillation circuit 25 via the diode D2 and the resistor R14 changes. Accordingly, when viewed from the oscillation circuit 25, the resistance value of the resistor R15 is equivalent to being variably controlled, and therefore the oscillation frequency is variably controlled. The oscillation frequency of the oscillation circuit 25 is controlled so that the voltage at the connection point of the resistor R16 and the capacitor C7, that is, the average value of the high-frequency voltage between the terminals of the detection resistor R17 is equal to the reference voltage of the non-inverting input terminal of the operational amplifier OP1. .

  The lamp power of the discharge lamp la is represented by the product of the average value of the high-frequency current flowing through the detection resistor R17 and the DC voltage of the DC power source 20. Therefore, if the voltage of the DC power supply 20 is constant, the average value of the inter-terminal high-frequency voltage of the detection resistor R17 that is proportional to the average value of the high-frequency current flowing through the detection resistor R17 is controlled to be equal to the reference voltage. The lamp voltage of the discharge lamp la tries to maintain a constant value.

Japanese Patent Laid-Open No. 10-189278 JP 2001-267090 A

  However, when a detection circuit 12 that detects a rise in lamp voltage with a single detection threshold as in Conventional Example 1 and a lighting device having a feedback circuit 23 as in Conventional Example 2 are combined, a load short circuit occurs. Sometimes the following problems can occur:

  Since the lamp voltage and the lamp power are reduced when the load is short-circuited, the lamp voltage does not exceed a predetermined voltage, and an abnormal voltage cannot be detected by the detection circuit as in Conventional Example 1. For this reason, the inverter circuit continues to operate. Further, when the lamp power is reduced, the feedback circuit as in Conventional Example 2 is operated, and in order to keep the lamp power constant, the oscillation frequency of the inverter circuit is lowered to operate in a direction approaching the resonance point of the LC resonance curve. As a result, an excessive current flows through the resonance circuit, and in the worst case, the coil is destroyed. In order to prevent destruction, it is necessary to select a large coil with high direct current superposition characteristics, which is disadvantageous in terms of space and cost.

  The present invention has been made in view of the above reasons, and its purpose is to reliably carry out end-of-life detection and load short-circuit detection, suppress stress on the resonance circuit, improve safety, and improve the resonance circuit. An object of the present invention is to provide a discharge lamp lighting device capable of reducing the size of the coil.

  In order to solve the above-described problem, the discharge lamp lighting device according to claim 1 includes a DC power source (chopper unit 1) and a switching element Q1, which is turned on and off at a high frequency connected to the DC power source, as shown in FIG. An inverter circuit 2 that outputs a high-frequency power source using Q2 and a discharge lamp la that is a load are connected, a resonance inductor L1 and a resonance capacitor C3 are connected, and a high-frequency power source that is output from the inverter circuit 2 is applied Drive control circuit (control unit 3 and driver) for setting the operating frequency of the drive signal for turning on and off the resonant load circuit 5 and the switching elements Q1 and Q2 provided in the inverter circuit 2 and performing preheating and start control immediately after the inverter is started Part 4) and a state in which the operating state of the drive signal is varied by detecting the lighting state of the discharge lamp la and feeding back to the drive control circuit. A discharge lamp lighting device provided with a feedback control circuit (control unit 3 and current detection resistor R4), which detects a voltage applied to the discharge lamp la and generates a detection signal (resistors R1 to R3, diode D1) , Capacitor C4), a first determination unit (comparator CP1) for determining an abnormality by inputting a detection signal and exceeding the first value Vref1, and a second value smaller than the first value Vref1 by inputting the detection signal A second determination unit (comparator CP2) that determines an abnormality by falling below Vref2, and a mask unit (AND gate) that invalidates the determination result of the first determination unit for an arbitrary time from the start of the inverter to the end of start control G1).

  A second aspect of the present invention is a lighting fixture in which the discharge lamp lighting device according to the first aspect is housed in a fixture casing (FIG. 16).

  According to the present invention, when the lamp voltage becomes an abnormal voltage at the end of the life of the discharge lamp, the inverter circuit is stopped by the first determination unit to prevent the abnormal voltage and the stress applied to the circuit components is reduced. There is an inhibitory effect. Further, by controlling the abnormality detection result by the first determination unit to be effective only in the lighting mode, there is an effect that it is possible to prevent malfunction of the detection circuit due to high voltage application at the start. Further, when the lamp voltage is reduced when the load is short-circuited, the second determination unit stops the inverter circuit to prevent an excessive current from flowing to the resonance circuit, and suppresses the stress applied to the circuit components. effective.

It is a circuit diagram of Embodiment 1 of the present invention. It is a timing chart which shows operation | movement of Embodiment 1 of this invention. It is a timing chart which shows operation | movement of the one modification of Embodiment 1 of this invention. It is a timing chart which shows operation | movement of the other modification of Embodiment 1 of this invention. It is a circuit diagram of Embodiment 2 of the present invention. It is a timing chart which shows operation | movement of Embodiment 2 of this invention. It is a timing chart which shows operation | movement of Embodiment 3 of this invention. It is operation | movement explanatory drawing of Embodiment 4 of this invention. It is a timing chart which shows operation | movement of Embodiment 4 of this invention. It is operation | movement explanatory drawing of Embodiment 5 of this invention. It is a timing chart which shows operation | movement of Embodiment 5 of this invention. It is a timing chart which shows operation | movement of Embodiment 6 of this invention. It is a circuit diagram of Embodiment 7 of the present invention. It is a circuit diagram of Embodiment 8 of the present invention. It is a timing chart which shows operation | movement of Embodiment 8 of this invention. It is a perspective view which shows the external appearance of the lighting fixture of Embodiment 9 of this invention. FIG. 6 is a circuit diagram of Conventional Example 1. 10 is a timing chart showing the operation of Conventional Example 1. FIG. 10 is a circuit diagram of Conventional Example 2.

(Embodiment 1)
FIG. 1 is a circuit diagram of Embodiment 1 of the present invention. The commercial AC power supply AC is full-wave rectified by the full-wave rectifier DB1, and the pulsating output voltage is converted into a DC voltage smoothed by the chopper unit 1. As the chopper unit 1, a booster type is generally used, but is not limited to this. The smoothed DC voltage output from the chopper unit 1 is converted into a high frequency voltage by the inverter circuit 2 and supplied to the resonant load circuit 5.

  The inverter circuit 2 includes a series circuit of switching elements Q1 and Q2 made of MOSFETs, and operates so that the switching elements Q1 and Q2 are alternately turned on at a high frequency by the output of the driver unit 4. The source current of the switching element Q2 is detected by the current detection resistor R4 and is fed back to the feedback terminal FB of the control unit 3. The control unit 3 incorporates a high-frequency oscillation circuit and variably controls the oscillation frequency so that the average value of the current fed back to the feedback terminal FB is constant.

  The resonant load circuit 5 includes an inductor L1, capacitors C1 to C3, and a discharge lamp la. The resonance frequency at the time of lighting is set to be lower than the oscillation frequency of the inverter circuit 2. The output increases when the oscillation frequency becomes low, and the output decreases when the oscillation frequency becomes high.

  The voltage across the discharge lamp la is divided by the resistors R1 and R2 of the abnormality detection circuit 6 and detected as a voltage Vx. The peak value of the voltage Vx is applied to the parallel circuit of the capacitor C4 and the resistor R3 via the diode D1, and is input as a detection voltage to the + input terminal of the comparator CP1 and the − input terminal of the comparator CP2. The first reference voltage Vref1 is applied to the negative input terminal of the comparator CP1, and the second reference voltage Vref2 is applied to the positive input terminal of the comparator CP2. The relationship between the first reference voltage Vref1 and the second reference voltage Vref2 is Vref2 <Vref1.

  The output of the comparator CP1 is connected to one input of the AND gate G1. The mode signal a output from the control unit 3 is input to the other input of the AND gate G1. The mode signal a is H level output only when the lamp state is the lighting mode. The output of the AND gate G1 is connected to one input of the OR gate G2. The output of the comparator CP2 is connected to the other input of the OR gate G2.

  The output of the OR gate G2 is input to the control unit 3. The control unit 3 operates and stops the inverter circuit 2 according to the output state of the OR gate G2. The actual abnormality detection flow will be described with reference to the timing chart of FIG.

  A description will be given of the end of life detection in FIG. When the lamp voltage rises at the end of the life of the discharge lamp la and Vref1 <Vx at t0, the output of the comparator CP1 changes from L level to H level. Since the lit mode signal a is at the H level, the output of the AND gate G1 is at the H level. The output of the AND gate G1 becomes H level, the output of the comparator CP2 becomes L level, and the output of the OR gate G2 becomes H level.

  The control unit 3 recognizes that the abnormality is detected when the output of the OR gate G2 is at the H level, transmits a signal for stopping the inverter circuit 2 to the driver unit 4, and stops the inverter circuit 2. When the driver unit 4 stops the inverter circuit 2, the chopper unit 1 may be stopped simultaneously.

  A description will be given of when a load short circuit is detected in FIG. When the load impedance decreases due to insulation degradation or the like, the lamp voltage decreases, and when Vx <Vref2 at t1, the output of the comparator CP2 changes from L level to H level. Since the output of the comparator CP1 is L level, the output of the AND gate G1 is L level. Since the output of the AND gate G1 is L level and the output of the comparator CP2 is H level, the output of the OR gate G2 is H level. The subsequent operation is the same as the stop operation at the end of the lifetime.

  As described above, the abnormality detection circuit 6 detects the end of the lamp life or the lamp abnormality, but the AND gate G1 enables the end of lamp life detection only in the lighting mode.

  As the operation after the abnormality is detected, the operations shown in FIGS. 3 and 4 are also possible. In the case of FIG. 3, when an abnormality is detected during lighting at the oscillation frequency f1, the oscillation frequency of the inverter circuit 2 is increased to f2, and the operation is continued at a frequency at which the stress of the components of the inverter circuit 2 and the resonant load circuit 5 is suppressed.

  In the case of FIG. 4, when an abnormality is detected during lighting at the oscillation frequency f1, the inverter circuit 2 is intermittently oscillated several times at the oscillation frequency f3 and then stopped.

  In summary, when the lamp voltage increases and exceeds a certain threshold value, and when the lamp voltage decreases and falls below a certain threshold value, a protective operation is performed to stop the inverter circuit.

  For example, when the high-frequency output voltage rises at the end of the lamp life, the inverter circuit is stopped to prevent component destruction due to high voltage application. Detection is enabled only during lighting, so that the detection operation is prevented from malfunctioning when a high voltage required at start-up is applied.

  In addition, when the high frequency output voltage is extremely reduced due to a load short circuit, the current range of the resonant load circuit can be limited by stopping the inverter circuit, so that the DC superimposition of the inductor L1 of the resonant load circuit can be set low. The coil can be downsized. As a result, there are effects that cost reduction and mounting space can be secured.

(Embodiment 2)
FIG. 5 is a circuit diagram of Embodiment 2 of the present invention. The basic configuration is the same as that of the first embodiment. The difference from the first embodiment is the AND gate G3 and the mode signal b. The output of the comparator CP2 and the mode signal b are input to the input of the AND gate G3.

  FIG. 6 shows a timing chart of the present embodiment. First, the normal state of FIG. When the commercial AC power supply AC is turned on, the mode signal b is output at the H level for a certain time from t2 to t3, and the output of the comparator CP2 becomes valid at the AND gate G3.

  In a normal state during the period from t2 to t3, since Vref2 <Vx <Vref1, the outputs of the comparators CP1 and CP2 are L level, and the outputs of the AND gate G1, the OR gate G2, and the AND gate G3 are also L level. . As a result, the control unit 3 changes the frequency of the inverter circuit 2 from f4 → f5 → f1 every predetermined time, and turns on the discharge lamp la. At the time of transition to the lighting mode, the mode signal a becomes H level, but since the output of the comparator CP1 remains at L level, the output of the OR gate G2 remains at L level and the lighting operation continues.

  Next, a description will be given of when a load short circuit is detected in FIG. When the commercial AC power supply AC is turned on, the mode signal b is output at the H level for a certain time from t2 to t3, and the output of the comparator CP2 becomes valid at the AND gate G3. When a load short circuit is detected, Vx <Vref2 <Vref1, and the output of the comparator CP1 is L level and the output of the comparator CP2 is H level. Since the mode signal b is at H level from t2 to t3, the output of the AND gate G3 is at H level. Since the output of the AND gate G1 is L level and the output of the AND gate G3 is H level, the output of the OR gate G2 is H level. Since the output of the OR gate G2 is at the H level, the control unit 3 recognizes this as an abnormality detection, issues a stop signal for the inverter circuit 2 to the driver unit 4, and continues the stop state of the inverter circuit 2. Although the mode signal b becomes L level at t3, the stopped state continues until the commercial AC power supply AC is turned off.

  For example, if the lamp wire has a ground fault due to an assembly error at the time of construction, the load short circuit is detected immediately after the power is turned on, and the operation of the inverter circuit 2 is stopped. Can suppress the stress. Also, there is an effect that erroneous detection during normal operation can be avoided by invalidating the abnormality detection result by the comparator CP2 after a certain period from when the power is turned on.

(Embodiment 3)
FIG. 7 is a timing chart of the third embodiment of the present invention. The circuit configuration is the same as in the second embodiment. The difference from the second embodiment is the mode signal b. The mode signal b is at the L level until a certain time t6, and the H level is output after the certain time t6. It may be continuously lit up to a certain time t6, and each power ON / OFF state by normal use is also possible.

  First, the normal state of FIG. After the time of continuous lighting or cumulative lighting after a certain time t6 has elapsed since the first power-on, the mode signal b changes from the L level to the H level, and the output of the comparator CP2 becomes valid at the AND gate G3. Since Vref2 <Vx <Vref1 at normal time, the outputs of the comparators CP1 and CP2 are L level, and the outputs of the gates G1, G2, and G3 are also L level. Thereby, normal operation is continued.

  Next, a description will be given of when a load short circuit is detected in FIG. After the time of continuous lighting or cumulative lighting after a certain time t6 has elapsed since the first power-on, the mode signal b changes from the L level to the H level, and the output of the comparator CP2 becomes valid at the AND gate G3. When the load impedance decreases due to insulation degradation or the like, the lamp voltage decreases and when Vx <Vref2 <Vref1 at t7, the output of the comparator CP1 becomes L level and the output of the comparator CP2 becomes H level. As a result, the output of the AND gate G1 becomes L level, the output of the AND gate G3 becomes H level, and the output of the OR gate G2 becomes H level. As a result, the control unit 3 recognizes that the abnormality has been detected, and issues a stop signal for the inverter circuit 2 to the driver unit 4 to stop the inverter circuit 2.

  For example, the load impedance may decrease after a considerable period of time has elapsed since the start of use due to insulation deterioration or the like, but load short-circuit detection is performed until a certain period of time during which insulation deterioration is unlikely to occur (the above-mentioned fixed time t6). By disabling it, it is possible to avoid a stop due to a malfunction of the detection circuit. Needless to say, by using Embodiment 2 together, an unsafe mode due to abnormal attachment during construction can be avoided.

  According to the present embodiment, by controlling the abnormality detection result by the comparator CP2 so that it becomes effective after a certain period from the start of use, it is possible to detect a load short circuit due to insulation deterioration that occurs over time, and The circuit is stopped and an excessive current is prevented from flowing into the resonant load circuit, thereby suppressing the stress applied to the circuit components. Further, by invalidating the abnormality detection result by the comparator CP2 from the start of use to a certain period, there is an effect that it is possible to avoid erroneous detection in a period in which insulation deterioration is unlikely.

(Embodiment 4)
FIG. 8 is an operation explanatory diagram of Embodiment 4 of the present invention. The basic configuration is the same as that of the first embodiment. The difference from the first embodiment is Vref2. The voltage value of Vref2 increases as the cumulative lighting time is measured.

  FIG. 9 shows a timing chart of the present embodiment. When the load voltage decreases due to insulation degradation or the like, the lamp voltage decreases, and when Vx <Vref2 <Vref1 at t8, the output of the comparator CP1 becomes L level, the output of the comparator CP2 becomes H level, and the output of the OR gate G2 becomes H level Become a level. The control unit 3 recognizes that the abnormality has been detected, and issues a stop signal for the inverter circuit 2 to the driver unit 4 to stop the inverter circuit 2.

  As a result, the load short circuit is easily detected by the comparator CP2 as time elapses, and the lamp voltage drop due to insulation deterioration can be detected early even if it is mild during long-term use.

  According to the present embodiment, by increasing the sensitivity of abnormality detection by the comparator CP2 over time, a lamp voltage drop due to insulation deterioration can be detected early even when used for a long time, and the inverter circuit can be This is effective to prevent the excessive current from flowing to the resonance circuit by stopping and to further suppress the stress applied to the circuit components with the passage of time.

(Embodiment 5)
FIG. 10 is an operation explanatory diagram of Embodiment 5 of the present invention. The basic configuration is the same as that of the fourth embodiment. The difference from the fourth embodiment is Vref1. The voltage value of Vref1 decreases as the cumulative lighting time is measured, and the voltage value of Vref2 increases.

  FIG. 11 shows a timing chart of the present embodiment. A description will be given of (a) when the end of life is detected. When the lamp voltage rises at the end of the lamp life and Vref2 <Vref1 <Vx at t9, the output of the comparator CP1 becomes H level, the output of the comparator CP2 becomes L level, and the output of the OR gate G2 becomes H level. The control unit 3 recognizes that the abnormality has been detected, and issues a stop signal for the inverter circuit 2 to the driver unit 4 to stop the inverter circuit 2. Since the same operation as that of the fourth embodiment is performed when the load is short-circuited in FIG.

  As a result, both the end-of-life detection of the comparator CP1 and the load short-circuit detection of the comparator CP2 are likely to be applied as time elapses, and after the long-term use, it is possible to detect the end-of-life and early insulation even if the insulation deterioration is slight. .

  According to the present embodiment, by increasing the detection sensitivity of the comparators CP1 and CP2 over time, an increase in the lamp voltage at the end of the lamp life or a decrease in the lamp voltage due to insulation deterioration is early even if it is mild during long-term use. It is possible to detect the current, and the inverter circuit is stopped to prevent an excessive current from flowing to the resonance circuit, and the stress applied to the circuit components can be further suppressed with aging.

(Embodiment 6)
FIG. 12 is a timing chart according to the sixth embodiment of the present invention. The basic configuration is the same as that of the third embodiment. The difference from the third embodiment is the mode signal b. In the present embodiment, as shown in FIG. 12B, the mode signal b is at the L level for a certain period (for example, 200 ms) after shifting to the lighting mode.

  First, a case where there is no detection mask after the transition to lighting in FIG. The commercial AC power supply AC is turned on at t2, and the oscillation frequency of the inverter circuit 2 changes from f4 (preheating frequency) → f5 (starting frequency) → f1 (lighting frequency). And extremely low. If the lamp impedance rapidly decreases at the time of transition to lighting at t11, when Vx <Vref2 <Vref1 at t12, the output of the comparator CP1 becomes L level and the output of the comparator CP2 becomes H level. As a result, the output of the AND gate G1 becomes L level, the output of the AND gate G3 becomes H level, and the output of the OR gate G2 becomes H level. The control unit 3 recognizes that the abnormality has been detected, and issues a stop signal for the inverter circuit 2 to the driver unit 4 to stop the inverter circuit 2. When the inverter circuit 2 is stopped, the discharge lamp la is extinguished so that the lamp impedance is increased again.

  Thus, when Vref2 <Vx <Vref1 at t13, the output of the comparator CP1 becomes L level, the output of the comparator CP2 becomes L level, the output of the AND gate G1 becomes L level, the output of the AND gate G3 becomes L level, and OR The output of the gate G2 becomes L level. The control unit 3 issues an operation signal for the inverter circuit 2 to the driver unit 4 to operate the inverter circuit 2 again.

  Next, a case where there is a detection mask after the transition to the lighting mode in FIG. During the transition from the start to the lighting mode, the mode signal b is set to L level during the period from t11 to t14, and the detection result of the comparator CP2 is invalidated by the AND gate G3.

  At the time of transition to the lighting mode at t11, the lamp impedance once suddenly decreases but stabilizes with time.

  Between t12 and t13, Vx <Vref2 <Vref1, and the output of the comparator CP1 is L level and the output of the comparator CP2 is H level. During this time, since the mode signal b is L level, the output of the AND gate G1 is L level, the output of the AND gate G3 is L level, and the output of the OR gate G2 is L level.

  At t13, Vref2 <Vx <Vref1, and when the mode signal b changes from L level to H level at t14, the output of the comparator CP1 becomes L level, the output of the comparator CP2 becomes L level, and the output of the AND gate G1 becomes L level. The output of the AND gate G3 becomes L level, and the output of the OR gate G2 becomes L level.

  Therefore, the control unit 3 continues the lighting operation. As a result, even if the lamp impedance rapidly decreases at the time of transition to the lighting mode, the lighting operation can be continued without malfunctioning the load short circuit detection. After the detection mask after the transition to the lighting mode is completed, the detection threshold Vref2 may be operated as shown in the fourth and fifth embodiments.

  According to the present embodiment, by controlling the abnormality detection result by the comparator CP2 to be invalid only for a certain period from the start to the lighting mode transition, even if the lamp impedance suddenly decreases during the lighting mode transition, There is an effect that false detection can be avoided.

(Embodiment 7)
FIG. 13 is a circuit diagram of Embodiment 7 of the present invention. The basic configuration is the same as in the first to sixth embodiments. The difference from the first to sixth embodiments is the microcomputer 7. The detection operation of the first to sixth embodiments is performed by software control of the microcomputer 7. Specifically, the detection voltage may be A / D converted and compared with thresholds corresponding to the reference voltages Vref1 and Vref2. The specific contents of the detection operation are the same as in the first to sixth embodiments, and thus the description thereof is omitted. The eighth embodiment described later may also be realized by software control of the microcomputer 7.

  According to the present embodiment, by realizing the first determination unit and the second determination unit with a microcomputer, it is possible to reduce the number of parts, reduce costs, and secure mounting space.

(Embodiment 8)
FIG. 14 is a circuit diagram of Embodiment 8 of the present invention. The basic configuration is the same as that of the sixth embodiment. The difference from the sixth embodiment is the resistance R5.

  FIG. 15 shows a timing chart of the present embodiment. A description will be given of a load state in FIG. During the preheating and starting period t15 to t17, the mode signal a is set to L level, and the detection result of the comparator CP1 is invalidated by the AND gate G1.

  The mode signal b changes from L level to H level from t15 when the inverter circuit 2 starts oscillating, and the detection result of the comparator CP2 is validated by the AND gate G3.

  If the output of the OR gate G2 is H level during the period from the power ON to the start of oscillation of the inverter circuit 2, the control unit 3 recognizes that the load is in a loaded state, and the output of the OR gate G2 is H during the oscillation of the inverter circuit 2. If it is a level, it shall have two functions of stopping the inverter circuit 2 as abnormality detection.

  During the period from the commercial AC power supply AC is turned on at t2 to t15, the DC voltage VA is input to the resistors R5, the filament of the discharge lamp la, and the voltage Vx divided by the resistors R1 and R2 to the comparators CP1 and CP2.

  From t2 to t15, Vref2 <Vref1 <Vx, and the output of the comparator CP1 is H level and the output of the comparator CP2 is L level. As a result, the output of the AND gate G1 becomes H level, the output of the AND gate G3 becomes L level, and the output of the OR gate G2 becomes H level.

  During this period, the control unit 3 recognizes that the output of the OR gate G2 is at the H level during a period before the oscillation of the inverter circuit 2 from the power ON, and therefore determines that the load is in a load state. As a result, the control unit 3 changes the oscillation frequency of the inverter circuit 2 from f4 → f5 → f1 at regular intervals, and turns on the discharge lamp la.

  In the start-up period from t16 to t17, Vref2 <Vref1 <Vx and the output of the comparator CP1 is H level and the output of the comparator CP2 is L level. However, since the mode signal a is L level during the start-up period, the AND gate The output of G1 is at L level, the output of AND gate G3 is at L level, the output of OR gate G2 is at L level, and no erroneous detection occurs.

  Next, the no-load state in FIG. 15B will be described. Since the filament resistance of the discharge lamp la does not exist from t1 until the commercial AC power supply AC is turned on, the DC voltage VA is not applied to the resistors R1 and R2, and therefore Vx = 0V. As a result, Vx <Vref2 <Vref1, and the output of the comparator CP1 becomes L level and the output of the comparator CP2 becomes H level. During this time, since the mode signal b is L level, the output of the AND gate G1 is L level, the output of the AND gate G3 is L level, and the output of the OR gate G2 is L level.

  During this period, the control unit 3 recognizes that the output of the OR gate G2 is at the L level during the period before the oscillation of the inverter circuit 2 from the time when the power is turned on, and therefore determines that there is no load. As a result, the control unit 3 issues a stop signal for the inverter circuit 2 to the driver unit 4 and continues to stop the inverter circuit 2.

  With the above operation, it is possible to detect the presence or absence of a load by using an abnormality detection comparator.

  According to the present embodiment, the presence / absence of a load is determined between the time the power is turned on and the start of inverter oscillation by supplying a detection signal to the comparators CP1 and CP2 by resistance-dividing the DC voltage through the lamp filament. There is an effect that it can be detected.

(Embodiment 9)
FIG. 16 is a perspective view showing an example of the appearance of a lighting fixture according to Embodiment 9 of the present invention. The lighting fixture 30 includes a housing 31 that houses any of the discharge lamp lighting devices according to the first to eighth embodiments, and a socket 32 for connecting the discharge lamp la to the discharge lamp lighting device. In addition to being used as a single lighting fixture as illustrated in FIG. 16, it may be configured as a lighting system that controls blinking and dimming of a plurality of lighting fixtures.

  A discharge lamp used in a lighting fixture is generally a fluorescent lamp whose discharge tube has a straight tube shape, a ring shape, or a bent shape, but is not limited thereto.

5 Resonant load circuit 6 Abnormality detection circuit CP1 Comparator (first determination unit)
CP2 comparator (second determination unit)
G1 AND gate (mask part)
la Discharge lamp

Claims (2)

DC power supply,
An inverter circuit that outputs a high-frequency power source using a switching element connected to a DC power source and turned on and off at a high frequency;
A resonant load circuit connected to a discharge lamp as a load, having a resonant inductor and a resonant capacitor, to which a high-frequency power output from an inverter circuit is applied;
A drive control circuit that sets an operating frequency of a drive signal for turning on and off a switching element provided in the inverter circuit, performs preheating immediately after the inverter starts, and start control;
A discharge lamp lighting device including a feedback control circuit that detects a lighting state of a discharge lamp and varies an operating frequency of a drive signal by feeding back to the drive control circuit,
A detection circuit that detects a voltage applied to the discharge lamp and generates a detection signal;
A first determination unit that inputs a detection signal and determines an abnormality by exceeding the first value;
A second determination unit that inputs a detection signal and determines abnormality by falling below a second value smaller than the first value;
A discharge lamp lighting device comprising: a mask unit that invalidates a determination result of the first determination unit for an arbitrary period of time from the start of the inverter to the end of the start control. A lighting fixture comprising the discharge lamp lighting device according to claim 1 housed in a fixture housing.

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