JP2011065704A - Nonvolatile semiconductor memory device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a highly reliable nonvolatile semiconductor memory device. <P>SOLUTION: The nonvolatile semiconductor memory device includes a control circuit 3 configured to control a soft program operation for setting data of memory cells MC to a threshold voltage distribution state where an excessive erasing state is eliminated after the data are collectively erased. The control circuit 3 applies a voltage Vspgm to word lines WL when characteristics of the memory cells MC are determined to be in the initial state, and applies voltages Vwld_spgm1 higher than the voltage Vspgm by a predetermined voltage value to dummy word lines WLDD, WLDS. When the characteristics of the memory cells MC are determined to be deteriorated, the control circuit 3 executes a soft program operation by applying a voltage Vspgm to the word lines WL and applying voltages Vwld_spgm2 lower than the voltages Vwld_spgm1 by a predetermined voltage value to the dummy word lines WLDD, WLDS. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a nonvolatile semiconductor memory device, and more particularly to a nonvolatile semiconductor memory device configured using electrically rewritable nonvolatile memory cells.

  A NAND flash memory is known as a nonvolatile semiconductor memory device that can be electrically rewritten and can be highly integrated. In a NAND flash memory, a plurality of memory cells are connected in series so that adjacent memory cells share a source / drain diffusion layer to constitute a NAND cell unit. Both ends of the NAND cell unit are connected to a bit line and a source line via a select gate transistor, respectively. With such a NAND cell unit configuration, the unit cell area is smaller than that of the NOR type and large capacity storage is possible.

  A memory cell of a NAND flash memory has a charge storage layer (floating gate electrode) formed on a semiconductor substrate via a tunnel insulating film, and a control gate electrode stacked thereon via an inter-gate insulating film. The data is stored in a nonvolatile manner according to the charge accumulation state of the floating gate electrode. For example, binary data storage is performed with data “0” being a high threshold voltage state in which electrons are injected into the floating gate electrode and data “1” being a low threshold voltage state in which electrons are emitted from the floating gate electrode. I do. Recently, the threshold voltage distribution to be written is subdivided and multi-value storage such as 4-value and 8-value is also performed.

  The data write operation of the NAND flash memory is performed on a page-by-page basis with the memory cells arranged along the selected word line as one page. Specifically, the write operation is performed as an operation of applying a write voltage to the selected word line and injecting electrons from the cell channel to the floating gate electrode by FN tunneling. In this case, the cell channel potential is controlled in accordance with the write data “0”, “1”.

  That is, in the case of writing “0” data, the voltage Vss is applied to the bit line, and the bit line is transferred to the channel of the selected memory cell through the selection gate transistor that is turned on. At this time, in the selected memory cell, a large electric field is applied between the floating gate electrode and the channel, and electrons are injected into the floating gate electrode. On the other hand, in the case of “1” data write (non-write), the power supply voltage Vdd is applied to the bit line, the cell channel is charged to the voltage Vdd−Vth (Vth is the threshold voltage of the select gate transistor), and then selected. The gate transistor is turned off, and the cell channel is brought into a floating state. At this time, the potential of the cell channel rises due to capacitive coupling with the word line, and electron injection into the floating gate electrode is prohibited.

  In recent years, as the minimum processing size becomes smaller and smaller, the influence of capacitive coupling between floating gate electrodes of adjacent memory cells has increased. This influence may cause undesirable threshold voltage fluctuations (erroneous writing) of the memory cell. In particular, when the memory cell at the end of the NAND cell unit is directly connected to the selection gate transistor, the operation characteristics vary between the memory cell at the end of the NAND cell unit and the other memory cells, and erroneous writing is possible. Increases nature. For this, a system in which a dummy cell not used for data storage is arranged next to the selection gate transistor is effective.

  Also, a method of performing a so-called soft program operation is known in order to eliminate an over-erased state of memory cells after batch erasure (see, for example, Patent Document 1). The soft program operation is important in preventing data change due to capacitive coupling between floating gate electrodes of adjacent memory cells. In particular, it is important as a technique for preventing erroneous writing in a NAND flash memory that has been miniaturized.

JP 2008-305536 A

  An object of the present invention is to provide a highly reliable nonvolatile semiconductor memory device.

  A nonvolatile semiconductor memory device according to an aspect of the present invention includes a NAND cell unit including a memory string formed by connecting a plurality of nonvolatile memory cells in series, and select transistors respectively connected to both ends of the memory string. A memory cell array, a word line connected to a control gate electrode of the nonvolatile memory cell, a bit line connected to a first end of the NAND cell unit, and a second end of the NAND cell unit Control for controlling a soft program operation for setting the first threshold voltage distribution state in which the overerased state is canceled after collectively erasing the data of the source line connected to the unit and the nonvolatile memory cell in a predetermined range A circuit, wherein the control circuit determines that the characteristic of the nonvolatile memory cell is in the first state, The nonvolatile memory cell is connected to the first threshold voltage except for the second word line connected to the nonvolatile memory cell at the end of the NAND cell unit. A first voltage for setting a distributed state is applied, a second voltage higher than the first voltage by a predetermined voltage value is applied to the second word line, the soft program operation is executed, and the nonvolatile memory In the case where it is determined that the characteristic of the volatile memory cell is in the second state, a third voltage equal to or lower than the voltage value of the first voltage is applied to the first word line, and the second word line is The soft program operation is performed by applying a fourth voltage lower than the second voltage by a predetermined voltage value.

  According to the present invention, a highly reliable nonvolatile semiconductor memory device can be provided.

1 is a diagram showing a memory cell array and a control circuit of a nonvolatile semiconductor memory device according to a first embodiment. FIG. It is a figure which shows the threshold voltage distribution of the non-volatile semiconductor memory device which concerns on 1st Embodiment. It is a figure explaining the soft program operation | movement of the non-volatile semiconductor memory device which concerns on 1st Embodiment. It is a figure explaining the problem of the soft program operation | movement of a non-volatile semiconductor memory device. It is a figure explaining the problem of the soft program operation | movement of a non-volatile semiconductor memory device. It is a figure explaining the soft program operation | movement of the non-volatile semiconductor memory device which concerns on 1st Embodiment. It is a figure explaining the soft program operation | movement of the non-volatile semiconductor memory device which concerns on 1st Embodiment. It is a figure explaining the soft program operation | movement of the non-volatile semiconductor memory device which concerns on 1st Embodiment. It is a figure explaining the soft program operation | movement of the non-volatile semiconductor memory device which concerns on 1st Embodiment. It is a figure explaining the soft program operation | movement of the non-volatile semiconductor memory device which concerns on 1st Embodiment. It is a figure explaining the soft program operation | movement of the non-volatile semiconductor memory device which concerns on 2nd Embodiment. It is a flowchart explaining operation | movement of the control circuit which concerns on embodiment. It is a flowchart explaining operation | movement of the control circuit which concerns on embodiment. It is a flowchart explaining operation | movement of the control circuit which concerns on embodiment. It is a flowchart explaining operation | movement of the control circuit which concerns on embodiment.

  Next, embodiments of the present invention will be described in detail with reference to the drawings. In the description of the drawings in the following embodiments, portions having the same configuration are denoted by the same reference numerals and redundant description is omitted. In the following embodiments, the nonvolatile semiconductor memory device will be described as a NAND flash memory using a memory cell having a stacked gate structure. However, this configuration is merely an example, and it goes without saying that the present invention is not limited to this.

(First embodiment)
[Configuration of Nonvolatile Semiconductor Memory Device According to First Embodiment]
The configuration of the nonvolatile semiconductor memory device according to the first embodiment of the present invention will be described below with reference to FIG.

  FIG. 1 is a diagram showing a memory cell array and a control circuit of the NAND flash memory according to the present embodiment. The NAND cell unit 1 of the NAND flash memory is connected in series between the source side select gate transistor STS, the drain side select gate transistor STD, the dummy cell DC connected to each of the select gate transistors STS, STD, and the dummy cell DC. A plurality of memory cells MCn (n = 0 to 63). In the NAND cell unit 1, a plurality of memory cells MCn share a source / drain region with adjacent ones to form a memory string. The memory cell array is configured by providing a plurality of NAND cell units 1 on a matrix.

  The memory cell MC has an N-type source / drain region formed in a P-type well of a silicon substrate, and has a stacked gate structure having a control gate electrode and a floating gate electrode as a charge storage layer. The NAND flash memory changes the amount of charge held in the floating gate electrode by a write operation and an erase operation. Thereby, the threshold voltage of the memory cell MC is changed, and 1-bit or multi-bit data is stored in one memory cell. Here, when the memory cells MC0 and MC63 are directly connected to the selection gate transistors STS and STD, the operation characteristics of the memory cells M0 and M63 at the end of the NAND cell unit 1 and the other memory cells MC are different. It varies. For this reason, dummy cells DC that are not used for normal data holding are provided at the end of the NAND cell unit 1 to make the characteristics of the memory cells MC used for data holding uniform.

  Note that the memory cell array can be configured without providing the dummy cell DC at the end of the NAND cell unit 1. In this case, the memory cells MC0 and MC63 to be provided at the end of the NAND cell unit 1 are also used for storing information. In the following embodiments, description will be made on the assumption that the dummy cell DC is provided at the end of the NAND cell unit 1, but the NAND flash memory according to the present invention is not limited to this. That is, the present invention can be applied to a case where the memory cell MC at the end of the NAND cell unit 1 is used as a data storage cell instead of the dummy cell DC.

  Control gate electrodes of a plurality of memory cells MCn arranged in the X direction in FIG. 1 are commonly connected by a word line WLn (n = 0 to 63). The gate electrodes of the plurality of source side select gate transistors STS are commonly connected by a source side select gate line SGS. The gate electrodes of the plurality of drain side select gate transistors STD are commonly connected by a drain side select gate line SGD. The control gate electrodes of the plurality of dummy cells DC arranged in the X direction in FIG. 1 are commonly connected by a drain side dummy word line WLDD or a source side dummy word line WLDS. In the NAND flash memory, a set of a plurality of NAND cell units 1 sharing a word line WLn constitutes a block.

  A bit line contact BLC is connected to the drain region of the drain side select gate transistor STD. This bit line contact BLC is connected to a bit line BL extending in the Y direction in FIG. The source side select gate transistor STS is connected to a source line SL extending in the X direction in FIG. 1 via a source region. A sense amplifier circuit SA used for cell data read, write, erase, and soft program operations is arranged on one end side of the bit line BL. A row decoder / driver 2 that selectively drives the word lines WL, dummy word lines WLDS, WLDD, and select gate lines SGS, SGD is disposed on one end side of the word lines WL.

  The NAND flash memory is provided with a control circuit 3 for controlling a read operation, a write operation, and an erase operation with respect to the memory cell array and used for a soft program operation described in detail later. The control circuit 3 determines whether the characteristics of the dummy cells DC and the memory cells MC provided in the NAND cell unit 1 are in an initial state, in a deteriorated state, or to what extent they are deteriorated based on various types of information. judge. As an example, the control circuit 3 determines the number of pulses applied during the erase operation, the number of write / erase operations to the NAND flash memory, the number of pulses applied during the write operation, or the number of pulses applied during the soft program operation. Make a decision. Further, the control circuit 3 stores the number of write / erase operations to the NAND flash memory and the number of pulse application times during the write operation and the soft program operation based on the operations of the sense amplifier circuit SA and the row decoder / driver 2. To do.

  Next, the data storage state of the NAND flash memory according to the present embodiment will be described with reference to FIG. FIG. 2 is a diagram showing a threshold voltage distribution of the memory cell MC of the NAND flash memory according to the present embodiment.

  When the memory cell MC of the NAND flash memory stores binary data (1 bit / cell), the threshold voltage distribution of the data is as shown in FIG. A state where the threshold voltage is negative is data “1” (erased state), and a state where the threshold voltage is positive is data “0”. When the memory cell MC of the NAND flash memory stores quaternary data (2 bits / cell), the threshold voltage distribution of the data is as shown in FIG. In this case, four types of threshold voltage distributions (E, A, B, C) are provided from the lower threshold voltage. Four types of data “11”, “01”, “00”, and “10” are assigned to these threshold voltage distributions. Here, the threshold voltage distribution E is a negative threshold voltage state obtained by batch block erase.

  In the data read operation of the NAND flash memory, a read pass voltage Vread that makes a non-selected memory cell conductive regardless of data is applied to the non-selected word line WL in the memory cell array. Note that the read pass voltage Vread applied to each non-selected memory cell may be different. Further, a read pass voltage for conducting the dummy cell DC and the select gate transistors STS and STD is applied to the dummy word lines WLDD and WLDS and the select gate lines SGS and SGD, respectively. The read pass voltage may be different between the dummy cell DC and the select gate transistors STS and STD.

  During the binary data read operation, a voltage (for example, voltage 0 V) between two threshold voltage distributions is applied to the selected word line WL connected to the selected memory cell MC. By applying this voltage, it is detected whether or not a current flows through the NAND cell unit 1, and data reading is executed. On the other hand, during the read operation of quaternary data, the voltage value of the voltage applied to the selected word line WL corresponds to the four threshold voltage distributions of the selected memory cell MC. Voltage AR, BR, or CR. The voltage AR is the lowest voltage, and the voltage value increases in the order of BR and CR. In the four-value data read operation, data read is performed by detecting whether or not a current flows through the NAND cell unit 1 at any of the voltages AR, BR, and CR.

  During the write operation of “0” data, a write voltage Vpgm (for example, 15 V to 20 V) is applied to the selected word line WL. In addition, the voltage Vss is applied to the bit line BL, and the bit line BL is transferred to the channel (hereinafter referred to as “cell channel”) of the selected memory cell MC through the drain side select gate transistor STD that is turned on. At this time, in the selected memory cell MC, a large electric field is applied between the floating gate electrode and the cell channel, and electrons are injected from the cell channel to the floating gate electrode by FN tunneling. In the case of multi-value data storage, a plurality of threshold voltage distributions can be provided by adjusting the number of electrons injected into the floating gate by changing the number of times of application of the write pulse.

  In a “1” data write operation (non-write), the power supply voltage Vdd is applied to the bit line BL, and the bit line BL is transferred to the cell channel of the selected memory cell MC via the drain side select gate transistor STD. After charging the cell channel to the voltage Vdd-Vth (Vth is the threshold voltage of the selection gate transistor), the selection gate transistor is turned off and the cell channel is brought into a floating state. In this case, even if the write voltage Vpgm is applied to the selected word line WL, the potential of the cell channel rises due to capacitive coupling with the selected word line WL, and electrons are not injected into the floating gate electrode. As a result, the memory cell MC holds “1” data.

  The data erasing operation in the NAND flash memory is executed in units of blocks. In the data erasing operation, all word lines WL including the dummy word lines WLDD and WLDS of the selected block are set to 0V, and a positive boosted erasing voltage (for example, 18V to 20V) is applied to the P-type well in which the memory cell array is formed. Done. As a result, a negative threshold voltage state (erased state) in which electrons of the floating gate electrode are emitted in all the memory cells MC of the selected block is obtained. Thereafter, an erase verify operation is performed as necessary. The erase verify operation is performed as an operation for confirming whether or not all memory cells MC of the NAND cell unit 1 have been erased to a negative threshold voltage. Specifically, in the erase verify operation, a predetermined voltage (for example, 0 V) is applied to all the word lines, and it is detected whether or not a current flows through the NAND cell unit 1.

  Next, the soft program operation of the NAND flash memory will be described with reference to FIG. In the above erase operation, the lower limit value control of the threshold voltage distribution is not normally performed. Therefore, the threshold voltage distribution of the memory cell MC after erasing becomes like the threshold voltage distribution EBS shown on the left side of FIG. In this case, the NAND cell unit 1 may include an over-erased memory cell MC. If there is a difference in threshold voltage between the memory cells MC, there is a possibility that data change (erroneous writing) due to capacitive coupling between floating gate electrodes of adjacent memory cells MC may occur in the subsequent operation. Therefore, a soft program operation using a weak write condition, that is, a write voltage Vspgm (for example, 10 V to 15 V) lower than a normal write voltage (for example, 15 V to 20 V) is performed on all memory cells MC and dummy cells DC. Eliminate the erased state. As a result, the threshold voltage distribution of the memory cell MC becomes the threshold voltage distribution EAS shown on the right side of FIG. As a result of the soft program operation, the range of the threshold voltage distribution of the memory cell MC can be narrowed as a whole.

  After this soft program operation, a soft program verify operation is performed. This is performed as an operation for confirming whether the threshold voltage of the predetermined number of memory cells MC or dummy cells DC has exceeded the soft program verify level 1 (voltage Vspv1). When the threshold voltage of the predetermined number of memory cells MC or dummy cells DC exceeds the soft program verify level 1 (voltage Vspv1) shown in FIG. In the soft program operation, if the threshold voltage of the memory cell MC or the dummy cell DC is excessively increased, the erased state and the written state cannot be distinguished. Therefore, when the threshold voltage of the predetermined number of memory cells MC or dummy cells DC exceeds the soft program verify level 2 (voltage Vspv2), a verify failure is set.

  Here, in the soft program operation, if the same soft program voltage Vspgm is applied to all the word lines WL and the dummy word lines WLDD and WLDS, the following problems occur. Next, this problem will be described with reference to FIGS.

  First, a case where the number of write / erase operations of the NAND flash memory is small and the characteristics of the dummy cells DC and the memory cells MC are in the initial state (first state) will be described with reference to FIG. When the number of write / erase operations is small, both the memory cell MC and the dummy cell DC are not deteriorated, and the difference in characteristics is small. Here, in the soft program operation, the same soft program voltage Vspgm (for example, 10 V) is applied to all the word lines WL and the dummy word lines WLDD and WLDS (see FIG. 4A). Further, a drain side selection gate voltage Vsgd (for example, 2.5 V) is applied to the drain side selection gate line SGD, and a source side selection gate voltage Vsgs (for example, 0 V) is applied to the source side selection gate line SGS.

  Here, the selection gate voltages Vsgd and Vsgs are lower than the soft program voltage Vspgm. The dummy cell DC is adjacent to the selection gate transistors STD and STS to which the selection gate voltages Vsgd and Vsgs are applied to the gate electrode. Therefore, in the dummy cell DC, writing by the soft program operation is slower than the normal memory cell MC in which the soft program voltage Vspgm is applied to the adjacent word lines WL. As a result, the threshold voltage value varies between the dummy cell DC and the normal memory cell MC after the soft program operation. That is, as indicated by a solid line (After SPROG) in FIG. 4B, the threshold voltage of the dummy cell DC is lower than the threshold voltage of the normal memory cell MC.

  In this state, when the read operation is executed a plurality of times, the threshold voltage of the memory cell MC and the dummy cell DC rises due to the read disturb (see the broken line (After Read Disturb) in FIG. 4B). At this time, since the threshold value of the dummy cell DC is low, the threshold voltage of the dummy cell DC is easily affected by the read disturb, and the threshold voltage of the dummy cell DC is larger than the threshold voltage of the normal memory cell MC. If the threshold voltage increase of the dummy cell DC is large when read disturb occurs, inter-cell interference occurs between the memory cells MC0 and MC63 adjacent to the dummy cell DC, and the threshold voltages of the memory cells M0 and MC63 are reduced. To rise. As a result, there is a problem that unintended change (erroneous writing) of data in the memory cells M0 and MC63 occurs.

  Next, a case where the write / erase operation of the NAND flash memory is repeated a plurality of times and the dummy cell DC and the memory cell MC are in a deteriorated state (second state) will be described with reference to FIG. When the write / erase operation to the memory cell MC is repeated a plurality of times, the dummy cell DC in the vicinity of the end of the NAND cell unit 1 becomes a normal memory cell MC in the NAND cell unit 1 due to the influence of the selection gate transistors STS and STD. The tunnel insulating film deteriorates faster. When the tunnel insulating film of the dummy cell DC deteriorates, excessive electrons are injected into the floating gate electrode even in the same soft program operation, and the writing speed becomes faster than that of the normal memory cell MC.

  Again, in the soft program operation, as shown in FIG. 5C, the same soft program voltage Vspgm is applied to all the word lines WL and the dummy word lines WLDD and WLDS. When the dummy cell DC is deteriorated, the writing speed is higher than that of the normal memory cell MC. Therefore, as shown in FIG. 5A, the dummy cell DC is set to be higher than the threshold voltage of the normal memory cell MC. The threshold voltage is higher. As a result, as shown in FIG. 5B, in the threshold voltage distribution after the soft program operation, some dummy cells DC are overwritten (OP: overprogrammed state). If the number of dummy cells DC in the overwritten state OP in which the threshold voltage exceeds the soft program verify level 2 (voltage Vspv2) exceeds a predetermined number, the soft program operation cannot be terminated normally. Therefore, there is a problem that a block including the NAND cell unit 1 is determined as a block failure.

  In order to solve these problems, the nonvolatile semiconductor memory device of the present embodiment executes a soft program operation as shown below.

[Operation of Nonvolatile Semiconductor Memory Device According to First Embodiment]
6 and 7 are diagrams for explaining the soft program operation of the NAND flash memory according to the present embodiment. FIG. 6 shows a soft program operation when the number of times of writing / erasing of the NAND flash memory is small and the characteristics of the dummy cell DC and the memory cell MC are in the initial state. FIG. 7 shows a soft program operation in the case where the write / erase operation of the NAND flash memory is repeated a plurality of times and the dummy cells DC and the memory cells MC are in a deteriorated state.

  First, a case where the number of times of writing / erasing of the NAND flash memory is small and the characteristics of the dummy cell DC and the memory cell MC are in an initial state will be described with reference to FIG. In the NAND flash memory according to the present embodiment, the control circuit 3 can determine whether the characteristics of the dummy cells DC and the memory cells MC are in an initial state or in a deteriorated state. The operation of the control circuit 3 will be described in detail later. When the control circuit 3 determines that the characteristics of the dummy cell DC and the memory cell MC are in the initial state, as shown in FIG. 6A, the word line WL connected to the normal memory cell MC includes A soft program voltage Vspgm is applied. The soft program voltage Vspgm is set to 10 V, for example. The dummy word line soft program voltage Vwld_spgm1 is applied to the dummy word lines WLDD and WLDS connected to the dummy cell DC. The dummy word line soft program voltage Vwld_spgm1 is set to a voltage value (for example, 11V) that is higher than the soft program voltage Vspgm (for example, 10V) by a predetermined value when the characteristics of the dummy cell DC and the memory cell MC are in the initial state. The Further, a drain side selection gate voltage Vsgd (for example, 2.5 V) is applied to the drain side selection gate line SGD, and a source side selection gate voltage Vsgs (for example, 0 V) is applied to the source side selection gate line SGS.

  The above voltage value is one example in the soft program operation, and the magnitude relationship between the voltage values of the voltages applied to the word line WL and the dummy word lines WLDD and WLDS only needs to be greater than the voltage Vspgm1. In the NAND flash memory according to the present embodiment, when the characteristics of the dummy cell DC and the memory cell MC are in the initial state, such a voltage is applied to the word line WL to execute the soft program operation. The soft program operation may be an operation in which the soft program voltage application to the word line WL and the dummy word lines WLDD and WLDS is repeated a plurality of times.

  Here, since the selection gate voltages Vsgd and Vsgs are lower than the soft program voltage Vspgm, the writing speed of the dummy cells DC adjacent to the selection gate transistors STD and STS may be reduced. However, the dummy word lines WLDD and WLDS are applied with the dummy word line soft program voltage Vwld_spgm1 higher than the voltage Vspgm. Therefore, the writing speed of the dummy cell DC is almost the same as that of the normal memory cell MC. As a result, the threshold voltage value does not vary between the dummy cell DC and the normal memory cell MC after the soft program operation. That is, as indicated by a solid line (After SPROG) in FIG. 6B, the threshold voltage of the dummy cell DC after the soft program operation and the threshold voltage of the normal memory cell MC are substantially the same value. .

  Next, a case where the write / erase operation of the NAND flash memory is repeated a plurality of times and the dummy cell DC and the memory cell MC are in a deteriorated state will be described with reference to FIG. Even when it is determined by the control circuit 3 that the characteristics of the dummy cell DC and the memory cell MC are in a deteriorated state, the word line WL connected to the normal memory cell MC is not connected to the word line WL as shown in FIG. A soft program voltage Vspgm (for example, 10 V) is applied. The dummy word line soft program voltage Vwld_spgm2 is applied to the dummy word lines WLDD and WLDS connected to the dummy cell DC. The dummy word line soft program voltage Vwld_spgm2 is set to a voltage value (for example, 9 V) lower than the soft program voltage Vspgm by a predetermined value when the dummy cell DC is in a deteriorated state. Further, a drain side selection gate voltage Vsgd (for example, 2.5 V) is applied to the drain side selection gate line SGD, and a source side selection gate voltage Vsgs (for example, 0 V) is applied to the source side selection gate line SGS.

  The above voltage value is one example in the soft program operation, and the magnitude relationship between the voltage values of the voltages applied to the word line WL and the dummy word lines WLDD, WLDS only needs to be smaller than the voltage Vspgm. In the NAND flash memory according to the present embodiment, when the characteristics of the dummy cell DC and the memory cell MC are deteriorated, such a voltage is applied to the word line WL to execute the soft program operation. The soft program operation may be an operation in which the soft program voltage application to the word line WL and the dummy word lines WLDD and WLDS is repeated a plurality of times.

  In the above-described embodiment, the state of the dummy cell DC has been described as the two states of the initial state and the deteriorated state. This can also be divided into a plurality of three or more states depending on the progress of the deterioration state. A case where the dummy cell DC is in a plurality of states will be described with reference to FIGS. 8A to 9. FIG. 8A and FIG. 9 show the voltages applied to the word lines WL and the dummy word lines WLDD and WLDS (corresponding to (a) in each figure) in the soft program operation, and the threshold voltages of the memory cells after the soft program operation. It is a figure (equivalent to (b) of each figure) showing a value. FIG. 8A shows a case where the characteristics of the dummy cell DC are in an initial state, and FIG. 9 shows a case where the characteristics of the dummy cell DC are deteriorated.

  The state shown in FIG. 8B is a case where the write / erase operation of the NAND flash memory is repeated a plurality of times and the dummy cell DC is in a slightly deteriorated state (third state). The state in which the dummy cell DC is slightly deteriorated is an intermediate state in which the dummy cell DC shifts from the initial state to the deteriorated state. In the state where the dummy cell DC is slightly deteriorated (third state), the voltage Vwld_spgm and the voltage Vspgm may be equalized in the magnitude relationship between the voltage values of the voltages applied to the word line WL and the dummy word lines WLDD and WLDS. it can. In this case, a voltage applied to the dummy word lines WLDD and WLDS is set to a voltage Vwld_spgm3.

Here, the voltages applied to the dummy word lines WLDD and WLDS during the soft program operation change as voltage Vwld_spgm1 → voltage Vwld_spgm3 → voltage Vwld_spgm2 as the degradation state of the dummy cell DC progresses (FIG. 8A (a), FIG. 8B). FIG. 9 (a)). Based on the progress of the deterioration state of the dummy cell DC and the memory cell MC, the relationship between the voltage Vspgm applied to the word line WL and the voltage applied to the dummy word lines WLDD and WLDS during the soft program operation is as follows: voltage Vwld_spgm1> voltage Vspgm
Voltage Vwld_spgm3 = voltage Vspgm
Voltage Vwld_spgm2 <voltage Vspgm
It becomes.

  In other words, it can be said that the voltage applied to the dummy word line WLDD during the soft program operation changes as voltage Vwld_spgm1> voltage Vwld_spgm3> voltage Vwld_spgm2 as the write / erase operation of the NAND flash memory is repeated a plurality of times.

  As described above, the dummy cell DC deteriorated by repeated write / erase operations to the NAND flash memory has a higher write speed than the normal memory cell MC. However, as shown in FIG. 7B, in the soft program operation according to the present embodiment, the dummy word line soft program voltage Vwld_spgm2 is set to a voltage lower than the soft program voltage Vspgm in the degradation state of the dummy cell DC. The Further, as shown in FIG. 8B, in the state where the dummy cell DC is slightly deteriorated, the dummy word line soft program voltage Vwld_spgm3 is set to the same level as the soft program voltage Vspgm. Therefore, the writing speed to the dummy cell DC is almost the same as that of the normal memory cell MC. As a result, the threshold voltage value does not vary between the dummy cell DC and the normal memory cell MC after the soft program operation. As shown in FIG. 7A, in the threshold voltage distribution after the soft program operation, cells in an overwritten state (OP: overprogrammed state) do not occur.

[Effect of Nonvolatile Semiconductor Memory Device According to First Embodiment]
The effect of the soft program operation of the NAND flash memory according to the present embodiment will be described with reference to FIGS. 8A to 9.

  As shown in FIGS. 8A (a) and 9 (a), in the NAND flash memory according to the present embodiment, different voltages are applied to the word lines WL and the dummy word lines WLDS, WLDD during the soft program operation. is doing. That is, the soft program voltage Vspgm is applied to the word line WL, and the dummy word line soft program voltages Vwld_spgm1 and Vwld_spgm2 are applied to the dummy word lines WLDS and WLDD. The voltage values of the soft program voltage Vspgm and the dummy word line soft program voltages Vwld_spgm1 and Vwld_spgm2 when the characteristics of the dummy cell DC and the memory cell MC are in the initial state and when the dummy cell DC is in a deteriorated state. The magnitude relationship is changed. As a result, as shown in FIGS. 8A (b) and 9 (b), in the NAND flash memory according to the present embodiment, variations in the threshold voltage between the memory cell MC and the dummy cell DC after the soft program operation are performed. Can be suppressed.

  When the characteristics of the dummy cell DC and the memory cell MC are in the initial state, as shown in FIG. 8A (b), the threshold voltage of the dummy cell DC after the soft program operation and the threshold voltage of the normal memory cell MC Are substantially the same value. When a read operation is performed in this state, the threshold voltage of the memory cell MC and the dummy cell DC rises due to read disturb (see the broken line (After Read Disturb) in FIG. 8A (b)). Here, the threshold voltage increase of the dummy cell DC due to read disturb is the same as the threshold voltage of the normal memory cell MC because the threshold voltage of the dummy cell DC is substantially the same as the threshold voltage of the normal memory cell MC. It is almost equal to the rise of the value voltage. Therefore, even when read disturb occurs, the influence on the memory cells MC0 and MC63 adjacent to the dummy cell DC is reduced, and erroneous writing to the memory cells M0 and MC63 can be prevented.

  Further, even when the dummy cell DC and the memory cell MC are in a deteriorated state, as shown in FIG. 9B, the threshold voltage of the dummy cell DC after the soft program operation and the threshold value of the normal memory cell MC The voltage is substantially the same value. That is, in the threshold voltage distribution after the soft program operation, cells in the over-written state (OP: over-programmed state) do not occur (see the threshold voltage distribution in FIG. 7A). As a result, the number of dummy cells DC and memory cells MC in the overwritten state OP in which the threshold voltage exceeds the soft program verify level 2 (voltage Vspv2) does not exceed the predetermined number, and the soft program operation is normally terminated. Can do. Thus, the NAND flash memory according to the present embodiment can surely execute the soft program operation.

  In addition, when the dummy cell DC and the memory cell MC are in a deteriorated state, the number of times the dummy word line soft program voltage Vwld_spgm2 is added to the dummy word line by setting the dummy word line soft program voltage Vwld_spgm2 to be the same as the soft program voltage Vspgm. Is less than the number of times that the soft program voltage Vspgm is applied to the word line. However, in a deteriorated state, the threshold value of the dummy cell DC exceeds the soft program verify level 2 (voltage Vspv2) just by applying the dummy word line soft program voltage Vwld_spgm2 (= Vspgm) once to the dummy word line. I can not cope with the case.

(Second Embodiment)
[Configuration of Nonvolatile Semiconductor Memory Device According to Second Embodiment]
Next, a non-volatile semiconductor memory device according to a second embodiment of the present invention will be described. Since the configuration of the nonvolatile semiconductor memory device according to the second embodiment is the same as that of the first embodiment, description thereof is omitted. The nonvolatile semiconductor memory device according to the second embodiment is different from the first embodiment in that the voltage value of the soft program voltage Vspgm applied to the word line WL is changed.

[Operation of Nonvolatile Semiconductor Memory Device According to Second Embodiment]
FIG. 10 is a diagram for explaining the soft program operation of the NAND flash memory according to the present embodiment. FIG. 10A shows a voltage application state to the word line WL and the dummy word lines WLDD and WLDS during the soft program operation when the characteristics of the dummy cell DC and the memory cell MC are in the initial state. FIG. 10B shows a voltage application state to the word line WL and the dummy word lines WLDD and WLDS during the soft program operation when the dummy cell DC and the memory cell MC are in a deteriorated state. In the soft program operation according to the present embodiment, the voltage of the soft program voltage Vspgm applied to the word line WL depending on whether the characteristics of the dummy cell DC and the memory cell MC are in the initial state or in the degraded state. The value is changed.

  First, a case where the number of times of writing / erasing of the NAND flash memory is small and the characteristics of the dummy cell DC and the memory cell MC are in an initial state will be described with reference to FIG. When the control circuit 3 determines that the characteristics of the dummy cell DC and the memory cell MC are in the initial state, as shown in FIG. 10A, the word line WL connected to the normal memory cell MC includes A soft program voltage Vspgm is applied. The soft program voltage Vspgm is set to 10 V, for example. The dummy word line soft program voltage Vwld_spgm1 is applied to the dummy word lines WLDD and WLDS connected to the dummy cell DC. The dummy word line soft program voltage Vwld_spgm1 is set to a voltage value (for example, 11 V) higher than the soft program voltage Vspgm by a predetermined value when the characteristics of the dummy cell DC and the memory cell MC are in the initial state. Further, a drain side selection gate voltage Vsgd (for example, 2.5 V) is applied to the drain side selection gate line SGD, and a source side selection gate voltage Vsgs (for example, 0 V) is applied to the source side selection gate line SGS.

  The above voltage value is one example in the soft program operation, and the magnitude relationship between the voltage values of the voltages applied to the word line WL and the dummy word lines WLDD and WLDS only needs to be greater than the voltage Vspgm1. In the NAND flash memory according to the present embodiment, when the characteristics of the dummy cell DC and the memory cell MC are in the initial state, such a voltage is applied to the word line WL to execute the soft program operation.

  Next, a case where the write / erase operation of the NAND flash memory is repeated a plurality of times and the dummy cells DC and the memory cells MC are in a deteriorated state will be described with reference to FIG. When it is determined by the control circuit 3 that the characteristics of the dummy cell DC and the memory cell MC are in a degraded state, as shown in FIG. 10B, the word line WL connected to the normal memory cell MC includes A soft program voltage Vspgm ′ is applied. Here, in the soft program operation in the present embodiment, the voltage value of the soft program voltage applied to the word line WL is changed depending on whether the dummy cell DC and the memory cell MC are in the initial state or in the deteriorated state. Let That is, when the characteristics of the dummy cell DC and the memory cell MC are in a deteriorated state, the voltage value of the soft program voltage Vspgm ′ is lower than the soft program voltage Vspgm in the initial state by a predetermined value (for example, 9 V). Set to.

  The dummy word line soft program voltage Vwld_spgm2 is applied to the dummy word lines WLDD and WLDS connected to the dummy cell DC. The dummy word line soft program voltage Vwld_spgm2 is set to a voltage value (for example, 8 V) lower than the soft program voltage Vspgm ′ by a predetermined value when the dummy cell DC and the memory cell MC are in a deteriorated state. Further, a drain side selection gate voltage Vsgd (for example, 2.5 V) is applied to the drain side selection gate line SGD, and a source side selection gate voltage Vsgs (for example, 0 V) is applied to the source side selection gate line SGS.

  The above voltage value is one example in the soft program operation, and the magnitude relationship between the voltage values of the voltages applied to the word line WL and the dummy word lines WLDD and WLDS only needs to be smaller than the voltage Vspgm ′. In the NAND flash memory according to the present embodiment, when the characteristics of the dummy cell DC and the memory cell MC are deteriorated, such a voltage is applied to the word line WL to execute the soft program operation. Further, the voltage Vwld_spgm2 is smaller than the voltage Vwld_spgm1, and the voltage Vspgm 'is smaller than the voltage Vspgm.

[Effects of Nonvolatile Semiconductor Memory Device According to Second Embodiment]
Also in the NAND flash memory according to the present embodiment, different voltages are applied to the word line WL and the dummy word lines WLDS and WLDD during the soft program operation. The soft program voltage Vspgm and the dummy word line soft program voltages Vwld_spgm1 and Vwld_spgm2 depending on whether the characteristics of the dummy cell DC and the memory cell MC are in the initial state or the dummy cell DC and the memory cell MC are in a deteriorated state. The magnitude relationship of the voltage value is changed. As a result, even in the NAND flash memory according to the present embodiment, variations in threshold voltage between the memory cell MC and the dummy cell DC after the soft program operation can be suppressed.

  Here, if the write / erase operation to the NAND flash memory is repeated a plurality of times, not only the dummy cell DC but also the normal memory cell MC deteriorates. That is, the tunnel insulating film of the memory cell MC also deteriorates as the write / erase operation is repeated, and the write speed is increased. When the voltage value of the soft program voltage Vspgm is set to the same value when the characteristics of the memory cell MC are in the initial state and when the memory cell MC is in a deteriorated state, a part of the memory cells in the soft program operation There is a possibility that the MC becomes overwritten (OP: overprogrammed). If the number of memory cells MC in the overwritten state OP in which the threshold voltage exceeds the soft program verify level 2 (voltage Vspv2) exceeds a predetermined number, the soft program operation cannot be terminated normally.

  However, in the NAND flash memory according to the present embodiment, as shown in FIG. 10, the soft program voltage Vspgm 'applied to the word line is set to a voltage lower than the soft program voltage Vspgm. Therefore, the writing speed to the memory cell MC in the deteriorated state is suppressed, and a cell in an overwritten state (OP: overprogrammed state) does not occur. As a result, the number of dummy cells DC and memory cells MC in the overwritten state OP in which the threshold voltage exceeds the soft program verify level 2 (voltage Vspv2) does not exceed the predetermined number, and the soft program operation is normally terminated. Can do. Thus, the NAND flash memory according to the present embodiment can surely execute the soft program operation.

  Similarly to the first embodiment, there may exist a state (third state) in which the write / erase operation of the NAND flash memory is repeated a plurality of times and the dummy cells DC are slightly deteriorated. Also in this case, as in the first embodiment, the voltage Vwld_spgm1> the voltage Vwld_spgm3> the voltage Vwld_spgm2.

  The NAND flash memory according to the embodiment of the present invention has been described above. In this NAND flash memory, the soft program voltage Vspgm applied to the word line and the dummy word line soft program voltage Vwld_spgm1 depending on whether the characteristics of the dummy cell DC and the memory cell MC are in the initial state or in the degraded state. , Vwld_spgm2 is changed in voltage magnitude relationship. The control circuit 3 determines whether the characteristics of the dummy cell DC and the memory cell MC are in an initial state or in a deteriorated state. Hereinafter, the determination operation of the characteristics of the dummy cell DC and the memory cell MC by the control circuit 3 will be described. Here, the determination operation by the control circuit 3 described below can be applied to both the first and second embodiments.

[Determination Operation 1 by Control Circuit 3]
FIG. 11 is a flowchart for explaining the operation of the control circuit 3 during the soft program operation of the NAND flash memory according to the present embodiment.

  The soft program operation of the NAND flash memory according to the first and second embodiments is executed following the erase operation. Here, as described above, in erasing data, the control gate voltage of the memory cell MC is set to 0 V, and a high voltage erase pulse is applied to the well in which the memory cell MC is formed. Thereby, electrons are emitted from the floating gate electrode to the semiconductor substrate through the tunnel insulating film, and the threshold voltage of the memory cell MC is shifted in the negative direction. The application of the erase pulse is executed a plurality of times while increasing the voltage value. The control circuit 3 can determine the characteristics of the dummy cell DC and the memory cell MC based on the number of times of application of the erase pulse. Hereinafter, a description will be given with reference to FIG.

  During the erase operation of the NAND flash memory, the erase pulse voltage applied to the well is applied a plurality of times while being increased by a predetermined voltage value. (Step S11). Thereafter, it is confirmed that the erase operation is completed by a verify operation for checking whether or not the erase is completed. At this time, the control circuit 3 detects how many times the erase pulse has been applied (step S12). The control circuit 3 compares the number of erase pulses applied during the erase operation with a preset determination value (step S13).

  Here, in the dummy cell DC and the memory cell MC, the tunnel insulating film deteriorates every time the operation of the NAND flash memory is repeated. In the dummy cell DC and the memory cell MC, as the tunnel insulating film deteriorates, the speed of the erase operation for emitting electrons from the floating gate electrode becomes slower. Therefore, as the dummy cell DC and the memory cell MC deteriorate, the number of times of pulse application necessary for the erase operation increases. The control circuit 3 compares the number of times of erasing pulse application during the erasing operation with the determination value.

  The control circuit determines the states of the dummy cells DC and the memory cells MC based on the number of erase pulses applied during the erase operation and the determination value (step S14). For example, when the number of times of application of the erase pulse during the erase operation exceeds a predetermined value, the control circuit 3 determines that the dummy cell DC and the memory cell MC are in a deteriorated state, while applying the erase pulse during the erase operation. When the number of times is equal to or less than the predetermined value, the control circuit 3 determines that the dummy cell DC and the memory cell MC are in the initial state. The control circuit 3 has a plurality of determination values, and can determine a plurality of states such as an initial state, a slightly deteriorated state, and a deteriorated state by comparison with the determination values.

  The sense amplifier circuit SA and the row decoder / driver 2 execute the voltage application method of the above-described embodiment based on the determination result of the control circuit 3. The determination operation based on the number of reset pulse applications directly detects the number of reset pulse applications at the time of the reset operation, and thus does not require the control circuit 3 to hold the number of reset pulse applications. In this case, it is not necessary to provide an area for storing information in the control circuit 3, and the NAND flash memory can have a simpler configuration.

[Determination Operation 2 by Control Circuit 3]
FIG. 12 is a flowchart for explaining the operation of the control circuit 3 during the soft program operation of the NAND flash memory according to the present embodiment. FIG. 12 shows a case where the control circuit 3 executes a determination operation based on the number of write / erase operations to the NAND flash memory.

  In this case, each time a write / erase operation is performed on the NAND flash memory, information that the write / erase operation has been performed is sent from the sense amplifier circuit SA and the row decoder / driver 2 into the control circuit 3. It is done. Based on this information, the control circuit 3 stores the number of times the write / erase operation to the NAND flash memory has been executed. The control circuit 3 can determine the characteristics of the dummy cell DC and the memory cell MC based on the number of write / erase operations to the NAND flash memory. Hereinafter, a description will be given with reference to FIG.

  When the determination operation by the control circuit 3 is started, the control circuit 3 acquires information on the number of write / erase operations to the NAND flash memory from the internal storage area (step S21). Here, the information on the number of write / erase operations indicates how many times the program / erase operations have been executed in the past for the block on which the soft program operation is executed. The control circuit 3 compares the number of write / erase operations to the NAND flash memory with a preset determination value (step S22).

  As described above, in the dummy cell DC and the memory cell MC, the tunnel insulating film deteriorates every time the write / erase operation of the NAND flash memory is repeated. The control circuit 3 determines the states of the dummy cells DC and the memory cells MC based on the number of write / erase operations of the NAND flash memory and the determination value (step S23).

  For example, the control circuit 3 determines that the dummy cell DC and the memory cell MC are in a degraded state when the number of write / erase operations to the NAND flash memory exceeds a predetermined value. On the other hand, the control circuit 3 determines that the dummy cell DC and the memory cell MC are in the initial state when the number of write / erase operations to the NAND flash memory is equal to or less than a predetermined value. The control circuit 3 has a plurality of determination values, and can determine a plurality of states such as an initial state, a slightly deteriorated state, and a deteriorated state by comparison with the determination values. The sense amplifier circuit SA and the row decoder / driver 2 execute the voltage application method of the above-described embodiment based on the determination result of the control circuit 3.

[Determination Operation 3 by Control Circuit 3]
FIG. 13 is a flowchart for explaining the operation of the control circuit 3 during the soft program operation of the NAND flash memory according to the present embodiment. FIG. 13 shows a case where the control circuit 3 executes the determination operation based on the number of pulse application times during the write operation to the NAND flash memory.

  During the data write operation, a write voltage (for example, 15V to 20V) is applied to the selected word line WL. Further, the voltage Vss is applied to the channel of the selected memory cell MC. As a result, a large electric field is applied between the floating gate electrode of the selected memory cell MC and the cell channel, and electrons are injected from the cell channel into the floating gate electrode. The application of the write pulse is executed a plurality of times while increasing the voltage value. When this write operation is executed, information on how many times the write pulse has been applied is sent from the sense amplifier circuit SA and the row decoder / driver 2 to the control circuit 3. Based on this information, the control circuit 3 stores the number of pulse applications during the write operation. The control circuit 3 can determine the characteristics of the dummy cell DC and the memory cell MC based on the number of pulse applications during the write operation. Hereinafter, a description will be given with reference to FIG.

  When the determination operation by the control circuit 3 is started, the control circuit 3 acquires information on the number of pulse applications during the write operation from the internal storage area (step S31). Here, the information on the number of times of pulse application at the time of the write operation represents the number of times of pulse application at the time when the previous write operation was executed for the block where the soft program operation is executed. The control circuit 3 compares the number of pulse applications during the write operation with a preset determination value (step S32).

  As described above, in the dummy cell DC and the memory cell MC, the speed of the write operation for injecting electrons into the floating gate electrode increases as the tunnel insulating film deteriorates. Therefore, as the dummy cell DC and the memory cell MC deteriorate, the number of pulse applications necessary for the write operation decreases. The control circuit 3 determines the state of the dummy cell DC and the memory cell MC based on the number of pulse applications during the write operation and the determination value (step S33).

  For example, the control circuit 3 determines that the dummy cell DC and the memory cell MC are in a deteriorated state when the number of pulse applications during the write operation is less than a predetermined value. On the other hand, the control circuit 3 determines that the dummy cell DC and the memory cell MC are in the initial state when the number of pulse applications during the write operation is equal to or greater than a predetermined value. The control circuit 3 has a plurality of determination values, and can determine a plurality of states such as an initial state, a slightly deteriorated state, and a deteriorated state by comparison with the determination values. The sense amplifier circuit SA and the row decoder / driver 2 execute the voltage application method of the above-described embodiment based on the determination result of the control circuit 3.

[Determination Operation 4 by Control Circuit 3]
FIG. 14 is a flowchart for explaining the operation of the control circuit 3 during the soft program operation of the NAND flash memory according to the present embodiment. FIG. 14 shows a case where the control circuit 3 executes the determination operation based on the number of pulse applications during the soft program operation to the NAND flash memory.

  Similar to the write operation, the pulse is applied a plurality of times while increasing the voltage value of the soft program voltage during the soft program operation. When this soft program operation is executed, information on how many times the soft program pulse has been applied is sent from the sense amplifier circuit SA and the row decoder / driver 2 to the control circuit 3. Based on this information, the control circuit 3 stores the number of pulse applications during the soft program operation. For example, the control circuit 3 can determine the characteristics of the dummy cell DC and the memory cell MC based on the number of pulse application times during the soft program operation. Hereinafter, a description will be given with reference to FIG.

  When the determination operation by the control circuit 3 is started, the control circuit 3 acquires information about the number of pulse applications during the soft program operation from the internal storage area (step S41). Here, the information on the number of times of pulse application during the soft program operation represents the number of times of pulse application when the previous soft program operation was executed for the block in which the soft program operation is executed. The control circuit 3 compares the number of pulse applications during the soft program operation with a preset determination value (step S42).

  As described above, in the dummy cell DC and the memory cell MC, the speed of the write operation for injecting electrons into the floating gate electrode increases as the tunnel insulating film deteriorates. Therefore, as the dummy cell DC and the memory cell MC deteriorate, the number of pulse applications necessary for the soft program operation decreases. The control circuit 3 determines the states of the dummy cells DC and the memory cells MC based on the number of pulse applications during the soft program operation and the determination value (step S43).

  The control circuit 3 determines that the dummy cell DC and the memory cell MC are in a deteriorated state when the number of pulse applications during the soft program operation is less than a predetermined value. On the other hand, the control circuit 3 determines that the dummy cell DC and the memory cell MC are in the initial state when the number of pulse applications during the soft program operation is equal to or greater than a predetermined value. The control circuit 3 has a plurality of determination values, and can determine a plurality of states such as an initial state, a slightly deteriorated state, and a deteriorated state by comparison with the determination values. The sense amplifier circuit SA and the row decoder / driver 2 execute the voltage application method of the above-described embodiment based on the determination result of the control circuit 3.

  The cell characteristic determination operation by the control circuit 3 has been described above. Here, in the NAND flash memory, the determination operation of the control circuit 3 may be any one of the above-described operations, or a plurality of determination operations may be combined.

[Others]
As mentioned above, although embodiment of this invention was described, this invention is not limited to these, A various change, addition, a combination, etc. are possible in the range which does not deviate from the meaning of invention. For example, the memory cell array can be configured without providing the dummy cell DC at the end of the NAND cell unit 1. In this case, in the description of the embodiment, the dummy cells DC are the memory cells MC0 and MC63, and the dummy word lines WLDD and WLDS are used so that the dummy cells DC are not provided.

  The number of memory cells MCn connected in series between the select transistors STD and STS may be plural (power of 2), and the number is not limited to 64. The data stored in the memory cell has been described as being binary data or quaternary data, but this may be data of other values (for example, 8-value data).

  Further, even when the dummy cell DC is arranged only on the drain side selection gate line SGD side or only on the source side selection gate line SGS side of the NAND cell unit 1, the embodiment of the present invention can be applied. Further, not only one dummy cell DC is provided at the end of the NAND cell unit 1, but also two or more dummy cells DC may be provided. In this case, the embodiment of the present invention may be applied only to the dummy cells DC adjacent to the drain side selection gate line SGD and the source side selection gate line SGS, or the embodiment of the present invention is applied to all dummy cells DC. You may do it.

  DESCRIPTION OF SYMBOLS 1 ... NAND cell unit, 2 ... Row decoder / driver, 3 ... Control circuit, MC ... Memory cell, WL ... Word line, BL ... Bit line, SL ... Source STS ... Source side select gate line, SGS ... Source side select gate line, STD ... Drain side select gate transistor, SGD ... Drain side select gate line, DC ... Dummy cell, WLDS ..Source side dummy word line WLDD... Drain side dummy word line.

Claims (6)

A memory cell array formed by arranging a memory string formed by connecting a plurality of nonvolatile memory cells in series, and NAND cell units each including a selection transistor connected to both ends of the memory string;
A word line connected to a control gate electrode of the nonvolatile memory cell;
A bit line connected to a first end of the NAND cell unit;
A source line connected to a second end of the NAND cell unit;
A control circuit for controlling a soft program operation for setting the first threshold voltage distribution state in which the over-erased state is canceled after collectively erasing data of the nonvolatile memory cells in a predetermined range,
The control circuit includes:
In the case where it is determined that the characteristics of the nonvolatile memory cell are in the first state,
The non-volatile memory cell is connected to the first threshold voltage on a first word line excluding a second word line connected to the non-volatile memory cell at the end of the NAND cell unit among the word lines. Apply a first voltage to set the distribution state,
Applying a second voltage higher than the first voltage by a predetermined voltage value to the second word line to execute the soft program operation;
In the case where it is determined that the characteristics of the nonvolatile memory cell are in the second state,
Applying a third voltage equal to or lower than the voltage value of the first voltage to the first word line;
The nonvolatile semiconductor memory device, wherein the soft program operation is executed by applying a fourth voltage lower than the second voltage by a predetermined voltage value to the second word line.   The nonvolatile semiconductor memory device according to claim 1, wherein the fourth voltage is a voltage lower than the third voltage by a predetermined voltage value.   The nonvolatile semiconductor memory device according to claim 1, wherein the third voltage is a voltage lower than the first voltage by a predetermined voltage value. The nonvolatile memory cell provided at the end of the NAND cell unit among the nonvolatile memory cells is a dummy cell that is not used for data storage,
4. The nonvolatile semiconductor memory device according to claim 1, wherein the second word line is a dummy word line connected to a control gate electrode of the dummy cell. The control circuit applies a pulse voltage to the semiconductor substrate on which the nonvolatile memory cells are formed, and controls an erase operation for collectively erasing data of the nonvolatile memory cells in a predetermined range,
5. The control circuit according to claim 1, wherein the control circuit determines whether the characteristic of the nonvolatile memory cell is in a first state or a second state based on the number of pulse applications during the erasing operation. The nonvolatile semiconductor memory device according to any one of the above. The control circuit selects one of the nonvolatile memory cells as a selected memory cell, applies a pulse voltage to a selected word line connected to the selected memory cell, and writes data to the selected memory cell. A write operation and a pulse voltage is applied to the semiconductor substrate on which the nonvolatile memory cell is formed to control an erase operation for collectively erasing data of the nonvolatile memory cell in a predetermined range,
The control circuit determines whether a characteristic of the nonvolatile memory cell is in a first state or a second state based on the number of times the write operation or the erase operation is performed. The nonvolatile semiconductor memory device according to any one of 1 to 4.

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