JP2011065353A - Parallel processing system control device, method and program - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a parallel processing system control device for controlling a parallel processing system, which conceals a difference between respective processors and respective shared memories of the parallel processing system and which controls in an unified manner the parallel processing system from an application program. <P>SOLUTION: The parallel processing system control device includes: a common command conversion-memory management part, an individual execution control part, memory management information, and an individual execution control registration part, for analyzing a common command not depending on a specific processor, specifying each processor executing each partial processing of the application program 40, specifying a shared memory storing a buffer for input/output data of each partial processing, specifying an address for accessing the buffer for the input/output data from each processor, converting the common command into a processor individual command that is different for each processor, and performing execution control of the parallel processing system. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a control apparatus for controlling a parallel processing system including a plurality of different types of processors and a plurality of shared memories, a method thereof, and a program thereof.

  In order to achieve high performance with low power consumption, devices with strict restrictions on power consumption, such as embedded systems, differ in CPU (Central Processing Unit), DSP (Digital Signal Processor), dedicated processor, reconfigurable processor, dedicated accelerator, etc. Including a processor, each process in one application is assigned to a processor having the optimum power performance.

  Here, as a method of executing and controlling one application in a processing apparatus including a plurality of different processors, there are the following methods.

  The first method is to embed a control procedure unique to each processor in an application program. An application is divided into several partial processes, and each partial process is assigned to a processor such as a CPU, a DSP, a dedicated processor, a reconfigurable processor, or a dedicated accelerator. When data transfer is required between the partial processes, a shared memory or a dedicated buffer between processors is used. The entire process is generally controlled by the CPU, and each processor startup, stop, data input, and other processes are performed by calling an execution control procedure specific to each processor from the application program by means such as a function call. Do.

  The second method is an interpreter method used in servers and the like including different models. Each different processor executes an interpretation program called an interpreter of a common language (for example, Java (registered trademark)). A program written in a common language is executed by each different processor as the interpreter interprets it. In this method, the entire application is described in a common language, and each partial process is assigned to a different processor for execution.

  The third method is applied to peripheral devices such as I / O, and conceals the unique characteristics of each peripheral device with a device driver. For example, in the case of a peripheral device that functions as a file system, different I / O devices can be accessed from an application program by a unified procedure provided by a device driver.

  In order to execute one application in a processing apparatus including a plurality of different processors, data transfer between the plurality of processors is required. There are the following methods for transferring data between a plurality of processors.

  The first method is performed via a shared memory, which secures a data area to be transferred to a shared memory accessible from a plurality of processors, and writes and receives data to be transferred by the sending processor in the data area. The data processor transfers data by reading data from the data area.

  The second method uses a memory management processor that can access the local memory of each processor in common. The sending processor writes the data to be transferred to the local processor. The receiving processor notifies the memory management processor of the address of the sending processor and the data area in its local memory. The memory management processor reads data from the address of the designated processor and local memory, writes the data to the local memory of the receiving processor, and notifies the receiving processor of the address of the data area into which the data has been written. The receiving processor performs data transfer by reading data from the address notified from the memory management processor.

  Techniques conforming to these methods are disclosed in the following documents.

JP 2007-328415 A JP 2007-148746 A Japanese Patent Laid-Open No. 02-039262 JP-A-62-028860 JP 2006-350622 A Japanese Patent No. 3087477 Japanese Patent Application Laid-Open No. 08-179953 JP 09-106352 A Japanese Patent Laid-Open No. 11-282692 Japanese Patent No. 4021534 JP 05-282257 A

COMPUTER ARCHITECTURE: A Quantitative Approach, Fourth Edition, J. L. Hennessy, D. A. Patterson, pp205-237, Fig. 4.8, Fig. 4.19 Published 2007

  However, the above method has several problems as follows.

  The first problem relates to the methods of Patent Literature 3, Patent Literature 4, Patent Literature 5, Patent Literature 6, and Patent Literature 10. In a method in which a CPU or the like calls a specific execution control procedure from an application program by means of a function call or the like according to each processor, the application program changes when the configuration of the device changes according to changes in the required specifications and performance of the application. Etc. software also needed to be changed accordingly.

  The second problem relates to the methods of Patent Document 1, Patent Document 7, Patent Document 8, and Patent Document 9. In the interpreter method, the difference between different processors can be concealed by the interpreter, but the interpreter method is executed while interpreting the application code at any time, so the execution speed becomes very slow, and in order to achieve the required performance However, it was difficult to apply to devices with strong restrictions such as built-in due to power and cost.

  The third problem relates to the technique of Patent Document 2. The method of concealing the device-specific characteristics with the device driver means that it is difficult to support a programmable processor. For devices such as DSPs, dedicated processors, and reconfigurable processors whose functions change greatly according to the program, and processors whose functions change according to parameter settings even for dedicated accelerators, they are unified as device drivers It is difficult to predefine a typical control procedure.

  The fourth problem relates to the technique of Non-Patent Document 1. In the method using shared memory for data transfer between processors, when the number of processors is large, the scale of hardware for allowing each processor to uniformly access the shared memory area becomes very large. This is difficult to apply in embedded applications where power consumption is severely restricted.

  The fifth problem relates to the technique of Patent Document 11. In the method of providing a memory management processor that can access the local memory of each processor for data transfer between the processors, the memory management processor performs the data transfer between the local memory of the sending processor and the receiving processor each time the data is transferred between the processors. When data copy to a local memory is required and there are many data transfers between processors, there is a problem that the performance is greatly reduced by data copy.

  The present invention has been made in view of the above problems, and is an apparatus for controlling a parallel processing system including a plurality of different types of processors and a plurality of shared memories, a method thereof, and a program thereof. An object of the present invention is to provide an apparatus, a method thereof, and a program thereof that can conceal differences, abstract the functions of different processors, and can control each processor uniformly from a high-level application program, and have high execution efficiency.

  According to the present invention, there is provided a parallel processing system control device for controlling a parallel processing system including a plurality of processors of different types and a plurality of shared memories. A plurality of common commands respectively corresponding to each of the plurality of partial processes included in the application program, and independent of the type of each processor included in the parallel processing system, and the input / output data handled by each processor A processor that executes each partial process is determined by receiving a request for execution of a plurality of common commands independent of the common memory included in the parallel processing system and analyzing each common command. The input / output data buffers handled by each processor are A common command conversion / memory management unit that determines a shared memory and converts each common command into a processor individual command that is an individual command corresponding to the determined processor, and each of the plurality of processors A plurality of individual execution control units for performing control for causing the corresponding processor to execute the partial processing specified by the processor individual command, a function for controlling access to each of the plurality of shared memories, and the plurality of shared A memory management information holding unit for holding memory management information including an address conversion table for each of the plurality of processors accessing the processor on an address map unique to the processor; and the common command conversion / memory management unit Used to determine the processor to perform the partial processing performed Information, information used for conversion of the common command to the processor individual command performed by the common command conversion / memory management unit, commands, functions, and functions used by the processor control performed by the individual execution control unit A process management table group in which information including an identifier is generated is generated, the process management table group is registered in the common command conversion / memory management unit and the individual execution control unit, and the process management table group is managed. There is provided a parallel processing system control device comprising an individual execution control registration unit that generates and manages the memory management information.

  In addition, according to the present invention, there is provided a parallel processing system control method performed by a parallel processing system control device for controlling a parallel processing system including a plurality of processors of different types and a plurality of shared memories. When the memory management unit receives an execution request for an application program, the execution request is a plurality of common commands each corresponding to each of a plurality of partial processes included in the application program, and is sent to the parallel processing system. Received as multiple common command execution requests that do not depend on the type of each processor included, and do not depend on which common memory the input / output data buffer handled by each processor is located in the parallel processing system. Execute each partial process by analyzing each common command Determining a shared memory in which a buffer of input / output data handled by each processor is arranged, and converting each common command into a processor individual command that is an individual command corresponding to the determined processor; Each of a plurality of individual execution control units corresponding to each of the plurality of processors performs control for causing the corresponding processor to execute the partial processing specified by the processor individual command; and memory management A function for controlling access to each of the plurality of shared memories, and an address conversion table for each of the plurality of processors to access the plurality of shared memories on an address map unique to the processor; A step of holding memory management information including: and an individual execution control registration unit Information used for determining the processor that executes the partial processing performed by the common command conversion / memory management unit, conversion of the common command performed by the common command conversion / memory management unit into the processor individual command Generating a process management table group in which information including information used for processing, information used in the control of the processor performed by the individual execution control unit, information including a function, and an identifier is described, and the process management table group is used as the common A parallel processing system control comprising: registering in a command conversion / memory management unit and the individual execution control unit, managing the processing management table group, and generating and managing the memory management information A method is provided.

  Furthermore, according to the present invention, there is provided a program for causing a computer to function as a parallel processing system control device for controlling a parallel processing system including a plurality of different types of processors and a plurality of shared memories. When a program execution request is received, the execution request is a plurality of common commands each corresponding to each of a plurality of partial processes included in the application program, and each processor type included in the parallel processing system It is received as multiple common command execution requests that do not depend on which common memory included in the parallel processing system the input / output data buffer handled by each processor is analyzed, and each common command is analyzed Process to execute each partial process. Common command conversion for determining a shared memory in which a buffer for input / output data handled by each processor is arranged and converting each common command into a processor individual command corresponding to the determined processor. A memory management unit, a plurality of individual execution control units that respectively correspond to the plurality of processors, and perform control for causing the corresponding processor to execute the partial processing specified by the processor individual command; Memory management information including a function for controlling access to each of the plurality of shared memories, and an address conversion table for allowing each of the plurality of processors to access the plurality of shared memories on an address map unique to the processor The memory management information holding unit for holding the common command conversion and memory management unit. Information used for determining the processor to execute the partial processing to be performed, information used for conversion of the common command to the processor individual command performed by the common command conversion / memory management unit, the individual A process management table group in which information including commands, functions, and identifiers used in the control of the processor performed by the execution control unit is generated, and the process management table group is generated as the common command conversion / memory management unit and the individual There is provided a parallel processing system control program for registering with an execution control unit, managing the process management table group, and generating and managing the memory management information and functioning as an individual execution control registration unit.

  According to the present invention, in a parallel processing system including a plurality of different types of processors and a plurality of shared memories, a process management table group in which the individual execution control registration unit describes information including a command, a function, and an identifier (ID). And a function for controlling the access of a plurality of shared memories, and memory management information including address information on the address map of each processor of each shared memory, and based on this process management table group and memory management information, A command conversion / memory management unit converts a common command independent of a specific processor into a processor individual command that is an individual command to each processor, and an individual execution control unit performs processing specified by the processor individual command to the processor. By executing, it hides the difference between each processor and each processor's address map. The processor from the functions of the different processor abstraction higher level application program provides unified control.

It is an example of mapping to the parallel processing system of the application which embodiment of this invention makes object and the partial process contained in the application. It is an example of the processor specific space address map by embodiment of this invention. It is a block diagram which shows the structure of embodiment of this invention. It is an example of a structure of the common command of embodiment of this invention. It is an example of composition of common memory information of an embodiment of the invention. In the embodiment of the present invention, it is a management table group required for accessing each shared memory from each processor. In the embodiment of the present invention, it is a management table group required for actually controlling a processor from a common command. In the embodiment of the present invention, it is a flowchart showing a procedure from a common command to actually starting processing in a predetermined processor. 5 is a flowchart illustrating a procedure for an application program to secure or release a buffer area on a shared memory in the embodiment of the present invention. In embodiment of this invention, it is the first half of the flowchart which shows the process sequence in an individual execution control registration part. In embodiment of this invention, it is a latter half part of the flowchart which shows the process sequence in an individual execution control registration part.

  DESCRIPTION OF EMBODIMENTS Hereinafter, embodiments for carrying out the present invention will be described in detail with reference to the drawings.

  FIG. 1 shows an example of the configuration of application processing targeted by the embodiment of the present invention and mapping of partial processing to a parallel processing system 30 including a plurality of different processors and a plurality of shared memories. .

  In FIG. 1, an application 10 includes a plurality of partial processes 11 and a plurality of communication channels 12. Data transfer between these partial processes 11 is performed via the communication channel 12.

  In FIG. 1, the parallel processing system 30 includes a plurality of different processors 31, a plurality of shared memories 33, and a plurality of communication paths 32. The shared memory 33 is shared by a plurality of processors 31. Each communication path 32 is used for data transfer between each processor 31 and a plurality of shared memories 33 and notification of events such as interrupts.

  The application 10 in FIG. 1 includes, as an example, four partial processes 11 (P1, P2, P3, and P4) and seven communication channels 12 (CH1, CH2,..., CH7) between the partial processes. N processors 31 (Proc1, Proc2,..., Proc N), M shared memories 33 (Mem1, Mem 2,..., MemM), and L communication paths 32 (Com1, Com2,..., ComL) Shall exist.

  In the example of FIG. 1, the mapping unit 20 maps the partial processes P1 and P2 to the processor Proc1, maps the partial process P3 to the processor Proc2, and maps the partial process P4 to the processor ProcN. The mapping unit 20 maps the communication channels CH1, CH2, and CH3 to the shared memory Mem1, the communication channel CH4 to the shared memory Mem2, the communication channels CH5 and CH6 to the shared memory Mem3, and the communication channel CH7 to the shared memory MemL. To do.

  The mapping unit 20 causes each of the partial processes 11 to be executed by the processor 31 suitable for the process, so that the performance per power consumption can be optimized in the entire application 10. The shared memory 33 does not need to be shared by all the processors 31, but is shared between the processors 31 that require data transfer. A plurality of shared memories 33 are provided. The communication channel 12 is mapped to a shared memory 33 that can be accessed by the processor 31 to which the partial process 11 that performs data transfer via the communication channel 12 is mapped. By doing so, it is possible to improve the data transfer speed of the entire system with a small amount of hardware. In addition, by doing so, when the parallel processing system 30 is configured by one chip as SoC (System On Chip), the performance per chip area can be optimized.

  FIG. 2 is an example of a processor-specific space address map. This shows how each shared memory 32 is arranged in the private space of each processor 31. For example, the unique space address map 67-1 of the processor Proc1 indicates that the shared memories Mem1, Mem3, and Mem2 are mapped to the base addresses base1, 1, base3, 1, and base2,1. In general, the address map 67 is different for each processor 31, and one shared memory 33 is mapped to different base addresses 68 from different processors.

  FIG. 3 is a block diagram showing the relationship between the application program 40, the parallel processing system control device 50, and the parallel processing system 30.

  The application program 40 includes an application execution control code 41 and an execution control registration code 42.

  The application execution control code 41 defines in what manner each partial process 11 of the application 10 in FIG. On the other hand, the execution control registration code 42 is a program necessary for causing the plurality of processors 31 of the parallel processing system 30 to execute processing based on the application execution control code 41 or between programs executed by the plurality of processors 31. This is a code for registering the shared memory 33 corresponding to the communication path 32 in the parallel processing system control device 50. Therefore, the execution control registration code 42 is a code that is the basis of the individual execution control registration command 113.

  Each partial process 11 is described using a common command 110 having a unified structure that does not depend on each processor 31.

  The parallel processing system control device 50 includes a common command conversion / memory management unit 51, an individual execution control registration unit 52, memory management information 80, and a plurality of individual execution control units 53. The memory management information 80 is held by the memory management information holding unit 80A. The common command conversion / memory management unit 51 receives an execution instruction of the partial process 11 from the application execution control code 41 as a common command 110. In addition, the common command conversion / memory management unit 51 receives an instruction to secure and release a buffer area in the shared memory 33 from the application execution control code 41.

  The common command 110 includes a process ID 114 for identifying each partial process 11 of the application program, and a process parameter 115 for designating input / output data and the like of each partial process 11. The input / output data is stored in a buffer secured in the shared memory 33, but it is necessary to change the buffer address designation depending on which processor 31 the partial processing 11 is processed in. The processing parameter 115 of the common command 110 includes designation of an address of a buffer in which input / output data is stored. The address is specified in a common format independent of which processor processes input / output data. A common format for buffer addressing is called common memory information 60 (see FIG. 5).

  The common command conversion / memory management unit 51 specifies the processor 31 to execute the partial process 11 specified by the common command 110, and specifies the processor individual process ID 116 for identifying the partial process performed by the processor 31.

  The memory management information 80 includes management information for each shared memory 33. The common command conversion / memory management unit 51 refers to the memory management information 80 for the common memory information 60 included in the processing parameter 115 of the common command 110, and the eigenspace address map 67 of the processor 31 that should execute the partial processing 11. To the address. The converted address is included in the individual processing parameter 118.

  As described above, the common command conversion / memory management unit 51 converts the common command 110 into the processor individual command 111 including the processor individual process ID 116 and the individual process parameter 118. Based on the processor individual command 111, the individual execution control unit 53 for controlling the processor 31 causes the processor 31 to execute the partial process 11.

  In the individual execution control unit 53, functions necessary for execution control specific to the corresponding processor 31 are registered. In order for the processor 31 to execute the partial process 11 assigned to the processor 31 corresponding to the individual execution control unit 53, a program for executing the partial process 11 by the processor 31 and a processor for identifying the program It is necessary to register the individual process ID 116 in association with each other.

  The program registration method generally requires a procedure specific to each processor 31. For example, if the processor 31 is a CPU or DSP, the individual execution control registration unit 52 receives a pointer to a function for the partial process 11 as a parameter of the individual execution control command 113, and associates the pointer with the processor individual process ID 116. Can be managed. Further, for example, if the processor 31 is a reconfigurable processor that can repeatedly change the circuit, the individual execution control registration unit 52 receives the reconfiguration data for the partial process 11 as a parameter of the individual execution control command 113, and The association between the reconfiguration data and the processor individual process ID 116 is managed.

  Therefore, in the individual execution control unit 53, the processor individual process ID registration function 102 (see FIG. 7) is registered in advance according to the type of the processor 31, and the processor individual process ID 116 is registered as the processor individual process ID registration. Function 102 is used.

  The program for the processor 31 for executing the partial process 11 registered using the processor individual process ID registration function 102 can be designated by the processor individual process ID 116.

  As described above, the processor individual command 111 includes the processor individual process ID 116 and the individual process parameter 118. The processor individual processing ID 116 specifies, for example, a registered execution function if the processor is a CPU, and specifies reconfiguration data if the processor is a reconfigurable processor. The processor individual process ID 116 is given to the processor 31 together with the individual process parameter 118.

  In the individual execution control unit 53, a processor individual command execution function 103 (see FIG. 7) is registered in advance in accordance with the processor 31 corresponding thereto. The processor 31 corresponding to the individual execution control unit 53 is controlled by the processor individual execution control command 112 executed by calling the processor individual command execution function 103 with the processor individual processing ID 116 and the individual processing parameter 118 as arguments.

  Since the procedure for confirming the execution status of the processor 31 is also different for each processor 31, the confirmation is performed using the processor state check function 104 (see FIG. 7) registered in advance for each processor 31. .

  Based on the individual execution control registration command 113, the individual execution control registration unit 52 registers the individual execution control unit 53 for each processor 31, the processor individual process ID registration function 102, the processor individual command execution function 103, and the processor state check function 104. Registration of functions necessary for controlling the processor such as the individual execution control unit 53 and conversion of the processor individual processing ID 116 using the processor individual processing ID registration function 102 to the common command conversion / memory management unit 51 and the individual execution control unit 53 Register. In this case, specifically, the processor control method management table 72 is registered in the entry for the processor 31 in the processor management table 71. Various method groups registered here become the entity of the individual execution control unit.

  FIG. 4 shows a configuration example of the common command 110. The common command 110 includes a process ID 114 that designates the partial process 11 of the application program, and a process parameter 115 that designates input / output data to be processed in the partial process 11.

  FIG. 4 shows an example in which the partial processing 11 has two sets of input data and one set of output data.

  The processing parameter 115 is, for example, a pointer to the processing parameter body 16. By storing a pointer to the common memory information 60 necessary for accessing the input data buffer 13 and the output data buffer 14 in the processing parameter body 16, input data to be processed and output data as a result of the processing are stored. You can specify a place.

  By storing the number of input data sets and the number of output data sets in the processing parameter body 16, it is possible to cope with the case where the number of input data sets and the number of output data sets differ for each partial process 11. On the other hand, in general, if the processing contents of the partial process 11 are determined, the number of input / output sets is also determined. Therefore, the number of input / output sets unique to the program executing the partial process 11 may not be set in the processing parameter body 16. Is possible.

  FIG. 5 is a configuration example of the common memory information 60 necessary for accessing the input / output data buffer of the partial processing 11. The shared memory 33 in which the buffer 15 is placed is designated by the memory ID 61 (memID). Each shared memory 33 has an address map unique to the shared memory 33. This is called a memory private space address map 66. The buffer 15 can be accessed by designating an address on the memory private space address map 66 of the shared memory 33 designated by the memory ID 61 and the memory ID 61. An address on the memory private space address map 66 is called a memory private space address 62. The common memory information 60 includes a memory private space address 62 for designating the buffer 15. The buffer 15 can be uniquely specified by the memory ID 61 and the memory unique space address 62. The shared memory information 60 can also have a buffer size 63 (bufSize) that specifies the size of the buffer 15. With the buffer size 63, it is possible to restrict access outside the buffer 15 area.

  The processor 31 has a processor-specific space address map 67. In order to access the buffer 15 from the processor 31, the address of the buffer 15 on the processor private space address map 67 is required. An address for accessing the buffer 15 from the processor 31 is stored in the processor specific space address 64 (procAddr).

  The processor specific space address 64 includes information (base address 68) indicating which address on the processor specific space address map 67 of the processor 31 the shared memory 33 in which the buffer 15 is placed, and the shared memory 33 of the buffer 15. Can be obtained by adding the addresses on the memory private space address map 66 (memory private space address 62).

  The common memory information 60 can have memory unique management information 65 (memSpecInfo) unique to the shared memory 33 specified by the memory ID 61. This information can include unique management information necessary for securing and releasing the buffer area on the shared memory 33.

  FIG. 6 shows a management table and a conversion table constituting memory management information 80 necessary for uniformly accessing a plurality of shared memories 33 from the application execution control code 41. In the address conversion table 83, the shared memory 33 stores the base address 68 on the processor-specific space address map 67 of the processor 31. For example, the base address 68 for the processor 31 whose processor ID 117 is i to access the shared memory 33 whose memory ID is j is base j, i.

  In general, the processor 31 is not always accessible to all the shared memories 33. In order to reduce the cost of the system, it is desirable to configure so that only the minimum necessary shared memory 33 can be accessed. Therefore, it is necessary to identify the shared memory 33 that is difficult to access from the processor 31. For this identification, a special value (for example, 0) that can be distinguished from a normal base address is set as the value of the base address 68, or an identification flag is set in each base address 68 entry of the address conversion table 83. This is possible.

  In order to access the buffer 15 on the shared memory 33 from the application execution control code 41, it is necessary to secure a buffer area on the shared memory 33. In addition, an operation of releasing the buffer area after use is necessary for the reuse of the memory area later. Management operations such as area allocation and release for the shared memory 33 are performed by the processor 31 that can access the shared memory 33. In some cases, the shared memory 33 can be accessed from a plurality of processors 31. In this case, the processor 31 suitable for management operations such as area allocation and release among the plurality of processors 31 performs the management operation. Since the processor 31 that performs the management operation differs for each shared memory 33, it is necessary to provide a management operation program for each shared memory 31. This is realized by the memory management table 81 and the memory access method management table 82.

  The memory management table 81 is a table for managing a memory ID 61 for specifying the shared memory 33 and a memory access method necessary for the management operation of the shared memory 33.

  The memory access method management table 82 manages a method group necessary for the management operation of the shared memory 33 as a function. There are several methods required for the management operation of the shared memory 33. Here, an area securing function 87 for securing the area of the buffer 15 in the shared memory 33, and the area of the buffer 15 on the shared memory 33. An area release function 88 for releasing is shown. The memory access method function can be realized as a management operation command for the processor 31 that performs the management operation. The memory access method function includes the designation of the processor 31 and operates as a part of the processor individual execution control unit 53 of the designated processor 31.

  FIG. 7 is a management table in which information including commands, functions, and identifiers (IDs) necessary for actually controlling the processor 31 from the common command 110 is described. This management table includes a process ID management table 70, a processor management table 71, and a processor control method management table 72.

  The process ID management table 70 manages the process ID 114 corresponding to the partial process 11 included in the application. By searching the process ID management table 70 using the process ID 114 included in the common command 110, the processor ID 117 in charge of the partial process 11 corresponding to the process ID 114 and the processor 31 specified by the processor ID 117 are specific. The processor individual process ID 116 can be searched. When adding the partial process 11, an entry is added to the process ID management table 70.

  The processor management table 71 is a table for managing a processor control method necessary for execution control of each processor 31 of the parallel processing system.

  The processor control method management table 72 of the processor 31 associated with the processor ID 117 can be searched from the processor ID 117. When registering the processor 31, an entry is added to the processor management table 71.

  The processor control method management table 72 manages a method group necessary for execution control of the processor 31 as a function. Several operations necessary for execution control of the processor 31 can be considered. Here, a program corresponding to the partial process 11 is registered in the processor 31, and the processor individual process ID registration function 102 for associating with the processor individual process ID 116, the processor The processor individual command execution function 103 for performing the processing specified by the processor individual command 111 when the individual command 111 is given by the processor 31 and the processor state check function 104 for confirming the state of the processor 31 as necessary. It is shown. The operation to the processor 31 can obtain the pointer 101 to the required processor control method function by designating the processor control method ID 100 corresponding to the operation and searching the processor control method management table 72. it can.

  Next, the operation of the parallel processing system control apparatus 50 according to the present embodiment will be described with reference to the flowcharts of FIGS. 8, 9, 10 and 11. Here, FIG. 8 shows a procedure from when the application control code 41 issues the common command 110 to when the processing in the predetermined processor 31 is actually started. FIG. 9 shows a procedure for securing and releasing the area of the buffer 15 necessary for processing from the application execution control code 41 on the shared memory 33. 10 and 11 show the procedure from when the application execution control registration code 42 issues the individual execution control registration command 113 to when various registrations are performed.

  The process of FIG. 8 is executed by the common command conversion / memory management unit 51.

  First, in step S100, the common command conversion / memory management unit 51 extracts the process ID 114 from the received common command 110, and obtains the processor ID 117 and the processor individual process ID 116 from the process ID management table 70 using the process ID 114 as a key. .

  Subsequently, in step S110, the common command conversion / memory management unit 51 obtains a pointer 73 from the processor management table 71 to the processor control method management table using the processor ID 117 as a key.

  In step S120, the common command conversion / memory management unit 51 sets the processor control method management table 72 designated by the pointer 73 to the processor control method management table to the processor control method ID 100 indicating the execution of the processor individual command 111. By searching as a key, the processor individual command execution function 103 is obtained.

  In steps S130 to S170, the processing parameter 115 of the common command 110 is converted into the individual processing parameter 118. The processing parameter 115 includes one or more pieces of common memory information 60 designating an area of a processing data buffer (input data buffer or output data buffer). The conversion from the processing parameter 115 to the individual processing parameter 118 is performed by setting the processor specific space address 64 of all the common memory information 60 of the processing parameter 115 to the processor specific space address 64 of the processor 31 specified by the processor ID 117. Do. Steps S140 to S170 are repeated for each common memory information 60.

  In step S140, it is determined whether or not the conversion for all common memory information 60 constituting the processing parameter 115 is completed.

  In step S150, the memory ID 61 and the memory unique space address 62 of the buffer 15 are obtained from the common memory information 60.

  In step S160, the base address 68 is obtained from the address conversion table 83 using the memory ID 61 and the processor ID 117 as keys.

  In step S170, the processor private space address 64 is obtained by adding the memory private space address 62 and the base address 68. By setting the processor specific space address 64 in the common memory information 60, the conversion of the common memory information 60 is completed.

  The individual processing parameter 118 is obtained by converting all the common memory information 60 constituting the processing parameter 115.

  In step S180, the common command conversion / memory management unit 51 calls the processor individual command execution function 103 using the processor individual process ID 116 and the individual process parameter 118 as arguments.

  The called processor individual command execution function 103 operates as a part of the individual execution control unit 53.

  FIG. 9 shows a procedure for securing and releasing the area of the buffer 15 necessary for processing from the application execution control code 41 on the shared memory 33. This procedure is executed by the common command conversion / memory management unit 51. Steps S800 to S830 show a procedure for securing the area of the buffer 15, and S900 to S930 show a procedure for releasing the area of the buffer 15.

  The buffer area securing request is given to the common command conversion / memory management unit 51 using the memory ID 61 and the buffer size 63 as arguments (step S800). A pointer from the memory management table 81 to the memory access method management table 82 is obtained using the memory ID 61 as a key (step S810). An area allocation function 87 is obtained from the memory access method management table 82 pointed to by the pointer 84 to the memory access method management table 82 (step S820). Next, the area securing function 87 is called with the buffer size 63 as an argument. The area allocation function 87 operates as a part of the individual execution control unit 53 of the predetermined processor 31, allocates an area of the size specified by the buffer size 63 on the shared memory 33 specified by the memory ID 61, and uses it as a return value. The common memory information 60 for accessing the buffer 15 is returned (step S830).

  The area release request is given to the common command conversion / memory management unit 51 using the common memory information 60 as an argument (step S900). A pointer from the memory management table 81 to the memory access method management table 82 is obtained using the memory ID 61 of the common memory information 60 as a key (step S910). The area release function 88 is obtained from the memory access method management table 82 pointed to by the pointer 84 to the memory access method management table 82 (step S920). Next, the area release function 88 is called with the common memory information 60 as an argument. The area release function 88 operates as a part of the individual execution control unit 53 of the predetermined processor 31 and releases the buffer 15 on the shared memory 33 specified by the common memory information 60 (step S930).

  The processor individual command execution function 103 generally performs different processing for each processor 31. In general, a necessary program is searched using the processor individual process ID 116 given as an argument as a key, the processor 31 is started, and the program is executed.

  If the processor 31 is a CPU, the program is called by giving the individual processing parameter 118 as an argument.

  On the other hand, if it is necessary for the processor 31 to load a program prior to execution, the processor 31 loads the program and then passes the individual processing parameters 118 to the processor 31 by a method specific to the processor 31. Start program execution on.

  If the processor 31 takes a long time to load a program, it is possible to accumulate several processing requests that can be processed by the same program and to cause the processor 31 to execute processing corresponding to these processing requests collectively. . Control procedures unique to these processors 31 and management operations unique to the shared memory 33 can be registered in the individual execution control unit 53 and the memory management information 80 by the individual execution control registration unit 52 in advance.

  The processes of FIGS. 10 and 11 are executed by the individual execution control registration unit 52. 10 shows a procedure for registering a control procedure unique to the processor 31, and FIG. 11 shows a procedure for registering a management operation unique to the shared memory 33.

  First, in accordance with the contents of the individual execution control registration command 113, processor registration (steps S200, S210, S220), method registration (steps S300, S310, S320, S330), processor individual process registration (steps S400, S410, S420, S430, S440, S450), shared memory registration (steps S500, S510, S520), memory access method registration (steps S600, S610, S620, S630), base address registration (steps S700, S710, S720). ) Is performed.

  In step S200, if the individual execution control registration command 113 is processor registration related to the partial process 11 (True), the processor control method management table 72 is generated in step S210, and the processor ID 117 is generated and generated in step S220. The processor ID 117 and a pointer to the processor control method management table 72 are registered in the processor management table 71.

  In step S300, if the individual execution control registration command 113 is registration of a processor control method related to execution control of the processor 31 (True), the processor ID 117, the processor control method ID 100, and the processor control method function are used as arguments. The pointer 101 is given by the individual execution control registration command 113 (step S310).

  In subsequent step S320, the processor control method management table 72 is obtained from the processor management table 71 using the processor ID 117 given as an argument as a key.

  In step S330, a processor control method ID 100 and a pointer 101 to the processor control method function are registered in the processor control method management table 72.

  In step S400, if the individual execution control registration command 113 is a registration of processor individual processing (True), the processor definition 117 is used as an argument, and a program definition for performing a predetermined processing by the designated processor 31 is an individual execution control registration command. 113 (step S410).

  In the subsequent step S420, a pointer from the processor management table 71 to the processor control method management table 72 is obtained using the processor ID 117 as a key.

  In step S430, the processor individual process ID registration function 102 is obtained from the processor control method management table 72.

  In step S440, the processor individual process ID registration function 102 is called with the program definition given as an argument of the individual execution control registration command 113 as an argument. The processor individual process ID 116 is obtained as a return value of this call.

  In step S450, the process ID 114 is generated, and the process ID 114, the processor ID 117, and the processor individual process ID 116 are registered in the process ID management table 70.

  In step S500, if the individual execution control registration command 113 is shared memory registration (True), the memory access method management table 82 is generated in step S510, the memory ID 61 is generated in step S520, and the generated memory ID 61 and the memory A pointer to the access method management table 82 is registered in the memory management table 81.

  In step S600, if the individual execution control registration command 113 is a memory access method registration (True), the memory ID 61, the memory access method ID 85, and the pointer 86 to the memory access method function are individually set as arguments. It is given by the execution control registration command 113 (step S610).

  In the subsequent step S620, the memory access method management table 82 is obtained from the memory management table 81 using the memory ID 61 given as an argument as a key.

  In step S630, a memory access method ID 85 and a pointer to the memory access method function 86 are registered in the memory access method management table 82.

  In step S700, if the individual execution control registration command 113 is a registration of the base address 68 (True), the memory ID 61, the processor ID 117, and the base address 68 are given by the individual execution control registration command 113 as arguments. (Step S710).

  In the following step 720, the base address 68 is stored in the entry instructed by using the memory ID 61 and the processor ID 117 as keys in the address conversion table 83.

  As described above, according to the present embodiment, firstly, execution control independent of the hardware configuration becomes possible. The common command conversion / memory management unit 51 allows execution control of the partial processing 11 included in the application to be performed with a common command having a unified structure that does not depend on which processor is executed.

  For this reason, when an application is divided into partial processes 11 and processed in parallel by a plurality of processors, a plurality of execution control methods can be considered. For example, each partial process can be regarded as a pipeline stage, and can be processed while continuously transferring data to a path from input to output.

  In addition, a series of processing from input to output handling one unit of data is configured as one independent job, and partial processing included in the job is sequentially executed within one processing, but a plurality of jobs are parallelized. Another possible method is to perform processing. To control these parallel processes, different control structures are required. However, since execution control of each processor can be performed with a common command, different parallel processes can be performed simply by changing the control structure of essential parallel processes. It becomes possible to cope with.

  Secondly, according to the present embodiment, optimal control can be performed for each different processor. In the present embodiment, there is an individual execution control unit 53 for each different processor. The individual execution control unit 53 can be optimally configured according to the characteristics of each processor.

  For example, if the processor is a CPU or a DSP, the individual execution control unit may be a function call of a function that executes partial processing. Also, if the processor is a reconfigurable processor or DSP that executes a program after it has been pre-loaded into local memory, it first loads the program that executes partial processing into local memory, and then Control such as operating the processor with a program is required. According to this embodiment, it is possible to select and use the optimum execution control method for each processor regardless of the type of processor.

  Thirdly, according to the present embodiment, even when the platform is changed or when the mapping of each process of the application to the processor is changed, the application program is described for the reason described in the next paragraph. It is possible to respond flexibly without changing the control structure.

  By using the individual execution control registration unit 52, it is possible to register an individual execution control procedure for each different processor included in the parallel processing system. Therefore, when a partial process of an application executed on a certain processor is to be executed on another processor, a partial processing program for another processor is newly registered.

  Fourthly, according to the present embodiment, the communication channels 12 between the partial processes 11 can be distributed and placed on a plurality of shared memories. Also, in a parallel system where each processor has a unique address map and each shared memory is mapped to a different address on the processor's unique address map, one shared memory is shared by all processors As well as unified memory management.

  Fifth, according to the present embodiment, the number of processors that perform shared memory management operations is not one, and any processor that can access the shared memory may perform the shared memory management operation. This eliminates the need for a processor that can access all shared memories and a communication path therefor. A communication path that can access all the shared memories has a high hardware cost, and may cause a bottleneck in processing when executing an application program. A system configuration without a communication channel bottleneck is possible.

  Note that each unit (common command / memory management unit, individual execution control registration unit, individual execution control unit, etc. of the parallel processing system control apparatus) of the present embodiment can be realized by hardware, software, or a combination thereof. When software is included to configure the apparatus of the present embodiment, a computer CPU causes a program for causing the computer to function as each unit of the apparatus of the present embodiment from a computer-readable recording medium such as a hard disk drive. The apparatus of this embodiment is configured by reading and executing. The CPU may temporarily store the program in a main storage device or the like after the program is read from the computer-readable recording medium until it is executed.

  The memory management information, common command, and processor individual command are stored in a computer-readable recording medium such as a hard disk drive in the main storage device.

  The present invention can be used in a parallel processing system including a plurality of different types of processors and a plurality of shared memories.

10 Application 11 Partial processing 12 Communication channel 13 Input data buffer 14 Output data buffer 15 Buffer (input data buffer, output data buffer, etc.)
16 processing parameter body 20 mapping unit 30 parallel processing system 31 processor 32 communication path 33 shared memory 40 application program 41 application program execution control code 42 execution control registration code 50 parallel processing system controller 51 common command conversion / memory management unit 52 Individual execution control registration unit 53 Individual execution control unit 60 Common memory information 61 Memory ID
62 Memory space address 63 Buffer size 64 Processor space address 65 Memory space management information 66 Memory space space map 67 Processor space space map 67-1 Processor Proc1 address map 67-2 Processor Proc2 address map 67-N Processor ProcN address map 68 Base address 70 Process ID management table 71 Processor management table 72 Processor control method management table 73 Pointer to processor control method management table 80 Memory management information 81 Memory management table 82 Memory access method management table 83 Address Conversion table 84 Pointer to memory access method management table 85 Memory access method ID
86 Pointer to method function for memory access 87 Memory area securing function 88 Memory area release function 100 Processor control method ID
101 Pointer to Method Function for Processor Control 102 Processor Individual Process ID Registration Function 103 Processor Individual Command Execution Function 104 Processor Status Check Function 110 Common Command 111 Processor Individual Command 112 Processor Individual Execution Control Command 113 Individual Execution Control Registration Command 114 Process ID
115 Processing parameter 116 Processor individual processing ID
117 Processor ID
118 Individual processing parameters

Claims (33)

A parallel processing system controller for controlling a parallel processing system including a plurality of processors of different types and a plurality of shared memories,
When an application program execution request is received, the execution request is a plurality of common commands each corresponding to each of a plurality of partial processes included in the application program, and each of the processors included in the parallel processing system. Regardless of the type, the input / output data buffer handled by each processor is received as an execution request for a plurality of common commands independent of the common memory included in the parallel processing system, and each common command is received. By analyzing, a processor for executing each partial process is determined, a shared memory in which a buffer for input / output data handled by each processor is arranged is determined, and each common command is associated with the determined processor. Common command conversion to convert to individual processor commands And a memory management unit,
A plurality of individual execution control units each corresponding to each of the plurality of processors, and performing control for causing the corresponding processor to execute the partial processing specified by the processor individual command;
Memory management comprising a function for controlling access to each of the plurality of shared memories and an address translation table for each of the plurality of processors to access the plurality of shared memories on an address map specific to the processor A memory management information holding unit for holding information;
Information used for determining the processor that executes the partial processing performed by the common command conversion / memory management unit, conversion of the common command performed by the common command conversion / memory management unit into the processor individual command Generating a process management table group in which information including information used for processing, information used in the control of the processor performed by the individual execution control unit, information including a function, and an identifier is described, and the process management table group is used as the common Registering in the command conversion / memory management unit and the individual execution control unit, managing the processing management table group, generating and managing the memory management information, an individual execution control registration unit,
A parallel processing system control device comprising: The individual execution control registration unit
A process ID management table describing the correspondence between a process ID for identifying individual partial processes, a processor ID for identifying individual processors, and a processor individual process ID for identifying partial processes performed by the processor;
Each processor control method ID corresponding to an operation to the processor, and a pointer to a processor individual command execution function for performing processing specified by the processor individual command in the corresponding processor when the processor individual command is given A program corresponding to the partial process is registered in the processor, and a pointer to a processor individual process ID registration function for associating with the processor individual process ID and a processor state check function for checking the processor state as necessary Method control table for processor control that describes the correspondence with the pointer of
A processor management table describing the correspondence between the processor ID and a pointer to the processor control method management table is generated as the processing management table group, and
A memory access method management table describing correspondence between a memory access method ID and a pointer to a memory access method function for access control of the shared memory;
A memory management table that describes a correspondence between a memory ID for identifying the shared memory and a pointer to the memory access method management table;
A correspondence between a base address for the plurality of processors to access the plurality of shared memories on an address map unique to the processor and a combination of the memory ID of the shared memory and the processor ID of the processor is described. The parallel processing system control apparatus according to claim 1, wherein the address conversion table is generated as the memory management information. The common command conversion / memory management unit
Receiving the common command in a format including a process ID for identifying the partial process and a process parameter for designating data including input / output data related to the partial process;
The processing parameter includes a plurality of common memory information that is arranged in the shared memory and that specifies a plurality of the input / output data in a format independent of the processor and the shared memory,
The common memory information includes a memory private space address indicating the memory ID for identifying the shared memory, and an address on a unique address map of the shared memory of a buffer for storing the input / output data,
Using the process ID included in the common command as a key, search the process ID management table for a processor ID of the processor that executes the partial process and a processor individual process ID that specifies the partial process performed by the processor And
For each of the plurality of common memory information constituting the processing parameter, the base address is searched from the address conversion table using the memory ID and the processor ID of the common memory as keys, and the base address and the memory specific From the space address, the processor specified by the processor ID calculates an address for accessing the buffer on the processor-specific address map as a processor-specific space address, and sets it in the common memory information. Converting the processing parameters into individual processing parameters of the processor;
The parallel processing system control apparatus according to claim 2, wherein the processor individual command is obtained by combining the processor individual processing ID and the individual processing parameter. The individual execution control unit is executed by calling a processor individual command execution function whose pointer is registered in advance in the processor control method management table using the processor individual process ID and the process parameter as arguments. The processor executes the partial process by a processor individual execution control command,
4. The parallel processing system control apparatus according to claim 2, wherein the processor operating state is checked by a processor state checking function whose pointer is registered in advance in the processor control method management table.   5. The individual execution control registration unit generates the process management table group and the memory management information by an individual execution control registration command based on an execution control registration code included in the application program. The parallel processing system control device according to any one of the above.   The individual execution control registration unit generates the processor control method management table and the processor ID based on the individual execution control registration command when the individual execution control registration command is registration of a processor related to the partial process. 6. The parallel processing system control device according to claim 5, wherein the generated processor ID and the processor control method management table ID are registered in the processor management table.   The individual execution control registration unit is configured to register the processor ID and the processor control method included in the individual execution control registration command when the individual execution control registration command is registration of a processor control method related to execution control of the processor. ID and a pointer to the processor control method function are received as arguments, the processor control method management table is acquired from the processor management table using the processor ID as a key, and the processor control method management table is used for the processor control 7. The parallel processing system control apparatus according to claim 5, wherein a method ID and the processor control method function are registered.   The individual execution control registration unit, when the individual execution control registration command is registration of a processor individual process for designating the partial process performed by the processor, the processor ID, program definition body included in the individual execution control registration command And a pointer from the processor management table to the processor control method management table using the processor ID as a key, and the processor individual process ID registration function from the processor control method management table specified by the pointer , The processor individual process ID is acquired as a return value when the processor individual process ID registration function is called with the program definition as an argument, the process ID is generated, and the process ID, the processor ID and the processor individual processing ID Parallel processing system control apparatus according to any one of claims 5 to 7, characterized in that to register the serial processing ID management table.   The individual execution control registration unit generates the memory access method management table and the memory ID when the individual execution control registration command is registration of the shared memory, and generates the generated memory ID and the memory access method. The parallel processing system control apparatus according to any one of claims 5 to 8, wherein a pointer to a management table is registered in the memory management table.   The individual execution control registration unit, when the individual execution control registration command is a memory access method registration related to a management operation of the shared memory, the memory ID and the memory access method included in the individual execution control registration command ID and the memory access method function are received as arguments, a pointer from the memory management table to the memory access method management table is obtained using the memory ID as a key, and the memory access method management table stores the memory access method function 10. The parallel processing system control apparatus according to claim 5, wherein a method ID and a pointer to the memory access method function are registered.   The individual execution control registration unit receives the memory ID, the processor ID, and the base address included in the individual execution control registration command as arguments when the individual execution control registration command is registration of the base address, and 11. The parallel processing system control apparatus according to claim 5, wherein the base address is stored in an entry designated by using the memory ID and the processor ID as keys in an address conversion table. A parallel processing system control method performed by a parallel processing system control device for controlling a parallel processing system including a plurality of processors of different types and a plurality of shared memories,
When the common command conversion / memory management unit receives an execution request for an application program, the execution request is a plurality of common commands each corresponding to each of a plurality of partial processes included in the application program, Multiple common commands that do not depend on the type of each processor included in the parallel processing system and do not depend on which common memory included in the parallel processing system the input / output data buffer handled by each processor is located. By receiving each request as an execution request and analyzing each common command, a processor that executes each partial process is determined, a shared memory in which a buffer for input / output data handled by each processor is arranged, and each common command is Individual processor, which is an individual command corresponding to the determined processor And the step of converting the command,
Each of a plurality of individual execution control units respectively corresponding to each of the plurality of processors performs control for causing the corresponding processor to execute the partial processing specified by the processor individual command;
A memory management information holding unit controls a function for controlling access to each of the plurality of shared memories, and an address for each of the plurality of processors to access the plurality of shared memories on an address map unique to the processor Holding memory management information including a conversion table;
An individual execution control registration unit is used for determining the processor for executing the partial processing performed by the common command conversion / memory management unit, and for the common command performed by the common command conversion / memory management unit. Generating a processing management table group in which information used for conversion to the processor individual command, a command used in the control of the processor performed by the individual execution control unit, information including a function and an identifier is described, Registering a process management table group in the common command conversion / memory management unit and the individual execution control unit, managing the process management table group, generating and managing the memory management information;
A parallel processing system control method comprising: The individual execution control registration unit
A process ID management table describing the correspondence between a process ID for identifying individual partial processes, a processor ID for identifying individual processors, and a processor individual process ID for identifying partial processes performed by the processor;
Each processor control method ID corresponding to an operation to the processor, and a pointer to a processor individual command execution function for performing processing specified by the processor individual command in the corresponding processor when the processor individual command is given A program corresponding to the partial process is registered in the processor, and a pointer to a processor individual process ID registration function for associating with the processor individual process ID and a processor state check function for checking the processor state as necessary Method control table for processor control that describes the correspondence with the pointer of
Generating a processor management table describing a correspondence between the processor ID and a pointer to the processor control method management table as the process management table group;
The individual execution control registration unit
A memory access method management table describing correspondence between a memory access method ID and a pointer to a memory access method function for access control of the shared memory;
A memory management table that describes a correspondence between a memory ID for identifying the shared memory and a pointer to the memory access method management table;
A correspondence between a base address for the plurality of processors to access the plurality of shared memories on an address map unique to the processor and a combination of the memory ID of the shared memory and the processor ID of the processor is described. Generating the address conversion table as the memory management information;
The parallel processing system control method according to claim 12, comprising: The common command conversion / memory management unit receives the common command in a format including a process ID for identifying the partial process and a process parameter for designating data including input / output data related to the partial process. In addition,
The processing parameter includes a plurality of common memory information that is arranged in the shared memory and that specifies a plurality of the input / output data in a format independent of the processor and the shared memory,
The common memory information includes a memory private space address indicating the memory ID for identifying the shared memory, and an address on a unique address map of the shared memory of a buffer for storing the input / output data,
The common command conversion / memory management unit uses the process ID included in the common command as a key to determine from the process ID management table the processor ID of the processor that executes the partial process and the partial process performed by the processor. A step of searching for a processor individual process ID to be specified;
The common command conversion / memory management unit searches the base address from the address conversion table using the memory ID and the processor ID of the common memory as keys for each of the plurality of common memory information constituting the processing parameter. Then, from the base address and the memory specific space address, an address for the processor specified by the processor ID to access the buffer on the processor specific address map is calculated as a processor specific space address, Further comprising the step of converting the processing parameters into individual processing parameters of the processor by setting in the common memory information;
The parallel processing system according to claim 13, further comprising the step of the common command conversion / memory management unit obtaining the processor individual command by combining the processor individual processing ID and the individual processing parameter. Control method. The individual execution control unit is executed by calling a processor individual command execution function whose pointer is registered in advance in the processor control method management table using the processor individual process ID and the process parameter as arguments. Causing the processor to execute the partial processing by a processor individual execution control command;
The individual execution control unit checks the operation state of the processor by a processor state check function whose pointer is registered in advance in the processor control method management table;
The parallel processing system control method according to claim 13 or 14, further comprising:   The individual execution control registration unit further includes a step of generating the process management table group and the memory management information by an individual execution control registration command based on an execution control registration code included in the application program. Item 16. The parallel processing system control method according to any one of Items 12 to 15.   The individual execution control registration unit generates the processor control method management table and the processor ID based on the individual execution control registration command when the individual execution control registration command is registration of a processor related to the partial process. The parallel processing system control method according to claim 16, further comprising a step of registering the generated processor ID and the processor control method management table ID in the processor management table.   The individual execution control registration unit, when the individual execution control registration command is registration of a processor control method related to execution control of the processor, the processor ID and the processor control method included in the individual execution control registration command ID and a pointer to the processor control method function are received as arguments, the processor control method management table is acquired from the processor management table using the processor ID as a key, and the processor control method management table is used for the processor control 18. The parallel processing system control method according to claim 16, further comprising a step of registering a method ID and the processor control method function.   The individual execution control registration unit, when the individual execution control registration command is registration of a processor individual process designating the partial process performed by the processor, the processor ID, program definition body included in the individual execution control registration command And a pointer from the processor management table to the processor control method management table using the processor ID as a key, and the processor individual process ID registration function from the processor control method management table specified by the pointer , The processor individual process ID is acquired as a return value when the processor individual process ID registration function is called with the program definition as an argument, the process ID is generated, and the process ID, the processor ID and the processor individual processing ID Parallel processing system control method according to any one of claims 16 to 18, further comprising the step of registering the serial processing ID management table.   When the individual execution control registration command is registration of the shared memory, the individual execution control registration unit generates the memory access method management table and the memory ID, and generates the generated memory ID and the memory access method. The parallel processing system control method according to any one of claims 16 to 19, further comprising a step of registering a pointer to a management table in the memory management table.   When the individual execution control registration unit is a memory access method registration related to the management operation of the shared memory, the individual execution control registration unit includes the memory ID and the memory access method included in the individual execution control registration command. ID and the memory access method function are received as arguments, a pointer from the memory management table to the memory access method management table is obtained using the memory ID as a key, and the memory access method management table stores the memory access method function 21. The parallel processing system control method according to claim 16, further comprising a step of registering a method ID and a pointer to the memory access method function.   When the individual execution control registration command is the registration of the base address, the individual execution control registration unit receives the memory ID, the processor ID, and the base address included in the individual execution control registration command as arguments, The parallel processing system according to any one of claims 16 to 21, further comprising a step of storing the base address in an entry designated by using the memory ID and the processor ID as keys in an address conversion table. Control method. A program for causing a computer to function as a parallel processing system control device for controlling a parallel processing system including a plurality of processors of different types and a plurality of shared memories,
Computer
When an application program execution request is received, the execution request is a plurality of common commands each corresponding to each of a plurality of partial processes included in the application program, and each of the processors included in the parallel processing system. Regardless of the type, the input / output data buffer handled by each processor is received as an execution request for a plurality of common commands independent of the common memory included in the parallel processing system, and each common command is received. By analyzing, a processor for executing each partial process is determined, a shared memory in which a buffer for input / output data handled by each processor is arranged is determined, and each common command is associated with the determined processor. Common command conversion to convert to individual processor commands And a memory management unit,
A plurality of individual execution control units each corresponding to each of the plurality of processors, and performing control for causing the corresponding processor to execute the partial processing specified by the processor individual command;
Memory management comprising a function for controlling access to each of the plurality of shared memories and an address translation table for each of the plurality of processors to access the plurality of shared memories on an address map specific to the processor A memory management information holding unit for holding information;
Information used for determining the processor that executes the partial processing performed by the common command conversion / memory management unit, conversion of the common command performed by the common command conversion / memory management unit into the processor individual command Generating a process management table group in which information including information used for control, a command used in control of the processor performed by the individual execution control unit, information including a function and an identifier is described, and the process management table group is used as the common Registering in the command conversion / memory management unit and the individual execution control unit, managing the processing management table group, generating and managing the memory management information, an individual execution control registration unit,
Parallel processing system control program to function as The individual execution control registration unit
A process ID management table describing the correspondence between a process ID for identifying individual partial processes, a processor ID for identifying individual processors, and a processor individual process ID for identifying partial processes performed by the processor;
Each processor control method ID corresponding to an operation to the processor, and a pointer to a processor individual command execution function for performing processing specified by the processor individual command in the corresponding processor when the processor individual command is given A program corresponding to the partial process is registered in the processor, and a pointer to a processor individual process ID registration function for associating with the processor individual process ID and a processor state check function for checking the processor state as necessary Method control table for processor control that describes the correspondence with the pointer of
A processor management table describing the correspondence between the processor ID and a pointer to the processor control method management table is generated as the processing management table group, and
A memory access method management table describing correspondence between a memory access method ID and a pointer to a memory access method function for access control of the shared memory;
A memory management table that describes a correspondence between a memory ID for identifying the shared memory and a pointer to the memory access method management table;
A correspondence between a base address for the plurality of processors to access the plurality of shared memories on an address map unique to the processor and a combination of the memory ID of the shared memory and the processor ID of the processor is described. 24. The parallel processing system control program according to claim 23, wherein the address conversion table is generated as the memory management information. The common command conversion / memory management unit
Receiving the common command in a format including a process ID for identifying the partial process and a process parameter for designating data including input / output data related to the partial process;
The processing parameter includes a plurality of common memory information that is arranged in the shared memory and that specifies a plurality of the input / output data in a format independent of the processor and the shared memory,
The common memory information includes a memory private space address indicating the memory ID for identifying the shared memory, and an address on a unique address map of the shared memory of a buffer for storing the input / output data,
Using the process ID included in the common command as a key, search the process ID management table for a processor ID of the processor that executes the partial process and a processor individual process ID that specifies the partial process performed by the processor And
For each of the plurality of common memory information constituting the processing parameter, the base address is searched from the address conversion table using the memory ID and the processor ID of the common memory as keys, and the base address and the memory specific From the space address, the processor specified by the processor ID calculates an address for accessing the buffer on the processor-specific address map as a processor-specific space address, and sets it in the common memory information. Converting the processing parameters into individual processing parameters of the processor;
The parallel processing system control program according to claim 24, wherein the processor individual command is obtained by combining the processor individual processing ID and the individual processing parameter. The individual execution control unit is executed by calling a processor individual command execution function whose pointer is registered in advance in the processor control method management table using the processor individual process ID and the process parameter as arguments. The processor executes the partial process by a processor individual execution control command,
26. The parallel processing system control program according to claim 24 or 25, wherein an operation state of the processor is checked by a processor state check function whose pointer is registered in advance in the processor control method management table.   27. The individual execution control registration unit generates the process management table group and the memory management information by an individual execution control registration command based on an execution control registration code included in the application program. The parallel processing system control program according to any one of the above.   The individual execution control registration unit generates the processor control method management table and the processor ID based on the individual execution control registration command when the individual execution control registration command is registration of a processor related to the partial process. 28. The parallel processing system control program according to claim 27, wherein the generated processor ID and the processor control method management table ID are registered in the processor management table.   The individual execution control registration unit is configured to register the processor ID and the processor control method included in the individual execution control registration command when the individual execution control registration command is registration of a processor control method related to execution control of the processor. ID and a pointer to the processor control method function are received as arguments, the processor control method management table is acquired from the processor management table using the processor ID as a key, and the processor control method management table is used for the processor control 29. The parallel processing system control program according to claim 27 or 28, wherein a method ID and the processor control method function are registered.   The individual execution control registration unit, when the individual execution control registration command is registration of a processor individual process for designating the partial process performed by the processor, the processor ID, program definition body included in the individual execution control registration command And a pointer from the processor management table to the processor control method management table using the processor ID as a key, and the processor individual process ID registration function from the processor control method management table specified by the pointer , The processor individual process ID is acquired as a return value when the processor individual process ID registration function is called with the program definition as an argument, the process ID is generated, and the process ID, the processor ID and the processor individual processing ID Parallel processing system control program according to any one of claims 27 to 29 and registers the serial processing ID management table.   The individual execution control registration unit generates the memory access method management table and the memory ID when the individual execution control registration command is registration of the shared memory, and generates the generated memory ID and the memory access method. The parallel processing system control program according to any one of claims 27 to 30, wherein a pointer to a management table is registered in the memory management table.   The individual execution control registration unit, when the individual execution control registration command is a memory access method registration related to a management operation of the shared memory, the memory ID and the memory access method included in the individual execution control registration command ID and the memory access method function are received as arguments, a pointer from the memory management table to the memory access method management table is obtained using the memory ID as a key, and the memory access method management table stores the memory access method function 32. The parallel processing system control program according to claim 27, wherein a method ID and a pointer to the memory access method function are registered.   The individual execution control registration unit receives the memory ID, the processor ID, and the base address included in the individual execution control registration command as arguments when the individual execution control registration command is registration of the base address, and The parallel processing system control program according to any one of claims 27 to 32, wherein the base address is stored in an entry designated by using the memory ID and the processor ID as keys in an address conversion table.

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