JP2011065118A - Fpd array self-checking circuit and inspection method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an array substrate and an inspection method, efficiently finding a defect in a manufacturing stage by adding minimum inspection circuits, and preventing depression as a completed article after the end of inspection. <P>SOLUTION: In this inspection circuit and its method, an FPD array substrate contains a simple inspection circuit including a sense amplifier disposed in every data line, after writing data, data is read from a pixel, amplified by the sense amplifier, and retained. The data is compared with an expected value to detect pixel failure, and the defective part is determined at high speed. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to an active matrix type array substrate and an inspection method thereof.

  In recent years, the mainstream of display devices is becoming an active matrix type liquid crystal display device. As this active matrix type liquid crystal display device becomes widespread as a liquid crystal television in place of the conventional cathode ray tube television, the price competition is becoming more severe as the display screen becomes larger, and it is necessary to reduce the manufacturing cost.

  As the display screen increases in size, the number of pixels per display device increases, and the pixel electrode arrangement pitch is becoming finer year by year. As a result, defects tend to occur. Further, when the arrangement pitch becomes fine and the number of pixels increases, the inspection apparatus becomes large and expensive, and the probe for electrically contacting the substrate for inspection becomes fine, and the number of probe pins increases. Therefore, it becomes expensive. As a result, in order to reduce manufacturing costs, reducing inspection costs has become an important issue.

  Under these circumstances, in order to reduce the manufacturing cost, it is necessary to improve the product function and the manufacturing yield, design in consideration of the inspection method, and minimize the need for expensive inspection equipment. This is an important issue.

For this issue,
Data for transmitting a data line inspection signal by arranging a switching element for inspection (26a in FIG. 1 of Reference 1) on each data line (3 in FIG. 1 of Reference 1) of the active matrix type liquid crystal panel in Reference 1. By installing a display signal line for line inspection and a control signal line for data line inspection for conducting or blocking the switching element, and performing a lighting inspection while displaying red, green, and blue colors, between the defective bright spot and the data line An inspection method for inspecting leaks and the like is disclosed.

  However, this inspection method has a problem that a defect such as a short circuit between adjacent data lines cannot be easily digitally inspected and identified.

  Further, regarding the inspection of the active matrix liquid crystal panel in Reference 2, information for inspection is sequentially written in each pixel of the active matrix liquid crystal panel, and a scanning circuit is provided in the horizontal direction (see FIG. 1 of Reference 2, reference number 2). ) An inspection apparatus and an inspection method for detecting a defect of each pixel by reading each pixel information are disclosed.

  However, according to this inspection circuit / inspection method, there is a problem when the inspection time is long and the charge in the storage capacitor of the pixel is very small.

  Further, information for inspection is sequentially written in all pixels of the active matrix type liquid crystal panel in Reference 3, and each pixel data is read by a sense amplifier by sequentially reading the information after a predetermined time, and converted into analog-digital (analog-digital). And converting the digitally converted data to a shift register and sequentially shifting it out, thereby identifying a defective pixel.

  However, it is not realistic to perform AD conversion, and a specific inspection circuit is not disclosed.

  Further, similar to Reference 1, Reference 4 discloses a test method similar to Reference 1 in which a sense amplifier is disposed for a pair of signal lines of an active matrix liquid crystal panel.

  However, this inspection method has a problem in the gradation display of the pixels and cannot perform a sufficient inspection.

Japanese Patent No. 3879668 Japanese Patent No. 2728748 JP-A-2005-24558 JP2002-351430

  Therefore, when designing an active matrix TFT substrate, the inventor adds a circuit that facilitates inspection to the substrate, and applies an inspection signal to the substrate from a simple inspection device. The present inventors have made efforts to develop the substrate and the inspection method capable of grasping the presence / absence of a defect and the position of the defect.

  As a first idea, an inspection pixel is provided for each signal line of an active matrix TFT substrate, inspection data is written to all the pixels, and the data written to the inspection pixel and the pixels in the display area are gated. Compared to each pixel connected to the line, digitally pass / fail judgment, the result of inspection is temporarily stored in the shift register, and if a defective pixel is detected, the data in the shift register is shifted out By doing so, an active matrix TFT substrate and an inspection method for quickly inspecting the quality of all pixels were devised.

  However, in the first idea, it is necessary to form a shift register, and there is a drawback that an active element such as a transistor that is originally unnecessary must be installed other than inspection.

  As a second idea, there is an idea of using a CCD instead of the shift register. In this case, there is an advantage that an active element such as a transistor is not required. However, there is a drawback that all pixel data must be transmitted and inspected.

  Therefore, in principle, the inventor installs inspection pixels in each signal line, writes inspection data to the inspection pixels and all the pixels, as in the first and second ideas. This is the same in that the data written in the pixels for display and the pixels in the display area are compared for each pixel connected to the gate line, but there is no need to configure a shift register as in the first idea, and the second As in the idea, we devised an inspection device and inspection method that can minimize the circuit for inspection without sending out the data of the pixels connected to all gate lines and inspecting them . Hereinafter, the inspection apparatus and the inspection method are also referred to as a shift select type TFT substrate and an inspection method.

  In order to achieve the above object, an invention described in claim 1 is an array TFT substrate, comprising a pixel electrode on an insulating substrate, a pixel switching element individually connected to the electrode, and the pixel switching element. An active matrix substrate having a plurality of scanning lines and data lines arranged in a grid pattern for driving a pixel electrode, and having a test sense amplifier and a reference capacitor connected to each of the plurality of data lines It is characterized by that.

  The invention described in claim 2 relates to the active matrix substrate according to claim 1, and relates to a comparison signal line for sending an expected value as a reference for inspection, a signal from the comparison signal line, and the plurality of signals. An active matrix substrate comprising: an EOR circuit that performs an exclusive OR with an output of a test sense amplifier; and a scanning line scanning circuit that scans the plurality of scanning lines.

  A third aspect of the present invention relates to the active matrix substrate according to the second aspect, wherein the data line scanning circuit scans the plurality of data lines, the outputs of all the plurality of EOR circuits, and the data lines. An active matrix substrate having an output line portion for outputting a logical sum with a scanning circuit

  The invention described in claim 4 relates to the active matrix substrate according to claim 3, and has an output line portion that forms an OR circuit by connecting the outputs of all the plurality of EOR circuits. Characteristic active matrix substrate

  According to a fifth aspect of the present invention, there is provided the active matrix substrate according to the fourth aspect, further comprising a circuit for writing independent test data into the odd-numbered data lines and the even-numbered data lines. Matrix substrate

  A sixth aspect of the present invention relates to the active matrix substrate according to the fifth aspect, wherein inspection signals are applied to odd-numbered data lines and even-numbered data lines, and inspection data is applied to pixels by a scanning line scanning circuit. A step of writing, a step of applying a reference potential to the reference pixel for inspection, a step of sequentially reading data from the pixel by a scanning line scanning circuit, a step of amplifying and holding the read potential by a sense amplifier, a sense amplifier output and an expected value And a step of outputting a comparison result. An inspection method for an active matrix substrate, comprising:

  The invention described in claim 7 relates to the inspection method of the active matrix substrate according to claim 6, and when the output of the comparison EOR circuit according to claim 4 shows a mismatch with an expected value, By specifying the data line address by the input clock count of the data line scanning circuit that outputs a mismatch in the logical product of the above, and by specifying the scanning line address by the input clock count of the scanning line scanning circuit according to claim 2, An inspection method for uniquely determining the location of a defective pixel.

By simply adding a simple inspection circuit to the array substrate, it is possible to prevent the inspection apparatus from becoming large and expensive even if the number of pixels increases, and to make electrical contact with the substrate for inspection. The cost required for such a fine and expensive probe can be minimized, and the time required for inspection can be shortened. As a result, the manufacturing cost can be considerably reduced.

It is explanatory drawing which shows the outline | summary of the array substrate which concerns on Embodiment 1 of this invention, and this test | inspection method. FIG. 2 is a schematic view exemplarily showing a circuit diagram of the active matrix substrate according to the embodiment of the present invention shown in FIG. 1. It is a flowchart concerning the form for implementing this invention. FIG. 10 is an explanatory diagram showing an outline of the second embodiment in which a data line test circuit adjacent to the shift selector type test circuit according to the present invention is added;

(Embodiment 1)
Hereinafter, a first embodiment for carrying out the present invention will be described with reference to the drawings.
Embodiment 1 for carrying out the present invention relates to an array substrate to which a shift selector type inspection circuit according to the present invention is added and the inspection method.

FIG. 1 is an explanatory diagram showing an overview of an array substrate and an inspection method according to Embodiment 1 of the present invention.
In FIG. 1, reference numeral 100 denotes a pixel matrix on which a normal image is displayed.
For ease of understanding, it is illustrated as a 4 × 4 pixel matrix, but is not limited to this number in practice.
Reference numerals 131 to 134 are inspection reference pixels.
Reference numeral 190 denotes a signal line selector that selects a data line (generally referred to as a signal line) in the pixel matrix. Reference numeral 128 denotes a gate line selector for selecting a gate line (generally called a scanning line) in the pixel matrix.

101 is a data line, 102 is a data line, 103 is a data line, and 104 is a data line. 191 is a gate line, 192 is a gate line, 193 is a gate line, and 194 is also a gate line.
Reference numerals 151 to 154 denote sense amplifiers.

The sense amplifier 151 senses and amplifies data of pixels connected to the gate line selected from the gate lines 191 to 194 through the data line 101.
The same applies to the sense amplifiers 152 to 154.

Reference numerals 161 to 164 denote EOR (exclusive OR) comparison circuits.
Reference numeral 180 denotes a comparison signal line.

Reference numerals 171 to 174 denote OR (logical sum) output circuits.
An output line 181 is connected to the output of an OR (logical sum) output circuit to form a wired OR (logical sum).

  Next, an outline of the array substrate and the inspection method according to the first embodiment of the present invention will be described with reference to the drawings.

FIG. 2 is a schematic view exemplarily showing a circuit diagram of the active matrix substrate according to the embodiment of the present invention shown in FIG.
In FIG. 2, reference numeral 231 denotes an inspection reference pixel (inspection reference pixel corresponding to 131 in FIG. 1). Reference numeral 251 denotes a sense amplifier, and reference numeral 261 denotes an EOR (exclusive OR) comparison circuit. Reference numeral 299 denotes a pixel to be inspected. Reference numeral 291 denotes an output line, which forms a wired OR.

  However, the circuit shown in FIG. 2 is an exemplary circuit for realizing the present invention, and may be another circuit as long as the circuit performs a similar function.

  Note that in the inspection circuit shown in FIG. 2, the parasitic capacitance of the inspection signal line is taken into consideration when creating the inspection reference pixel. A method of adding approximately 50% of the reference pixel for inspection as the parasitic capacitance of the signal line is conceivable.

  In order to make the influence of gate coupling equivalent, the inspection reference pixel intersects with the inspection signal line at a place other than the display area. When the parasitic capacitance related to the inspection reference pixel is set to approximately 50% of the capacitance of the pixel to be inspected, adjustment is made by providing a difference between the writing voltage to the inspection reference pixel and the pixel to be inspected.

FIG. 3 is a flowchart according to an embodiment for carrying out the present invention.
First, data is written to all pixels in the display area of the array substrate (step 301). Next, test data is written to the test reference pixels installed for each data line (step 302). However, this step (step 302) may not be necessary depending on the substrate manufacturing method.

  Next, the scanning lines are sequentially selected, and the data of the pixels connected to the selected scanning lines and the data of the inspection reference pixels installed on the data lines are compared and amplified (step 303).

  Next, the exclusive OR (EOR) comparison circuit of the output of the sense amplifier and the signal from the comparison signal line is ORed (step 304).

Here, since the output of the logical sum of the exclusive OR (EOR) comparison circuit is connected to the output line to form a wired OR (wired logical sum), the output line is active (Yes in step 305). In this case, it is considered that a pixel connected to the scanning line is defective, and failure analysis is performed based on the state of the signal line selector and the gate line selector (step 306). If the output line is not active (No in Step 305), it is considered that there is no defect in the pixel connected to the scanning line. In this case, there is still a gate line that is not selected (Step 307). (Yes), the remaining gate lines are selected (step 308), and the pixels connected to the selected gate lines are inspected.
If there is no unselected gate line (No in step 307), the inspection is terminated.

As described above, in the TFT array built-in shift selector inspection method according to the present invention, it is necessary to use a shift register even when data is written into a pixel or a defective pixel is detected. Therefore, there is an advantage that it is possible to minimize a circuit which is active such as a transistor and is unnecessary after the inspection is completed, and further, it is possible to shorten a time required for the inspection and the failure analysis.
(Embodiment 2)
In the second embodiment, in addition to the array substrate according to the first embodiment to which the shift selector type inspection circuit according to the present invention is added and the inspection method, an inherent short ring is added to the outer periphery of the shift selector type inspection circuit. In particular, it is possible to more effectively inspect defects between adjacent data lines. This will be described with reference to the drawings.

FIG. 4 is an explanatory diagram showing an outline of the second embodiment in which a data line test circuit adjacent to the shift selector type test circuit according to the present invention is added.
In FIG. 4, reference numeral 100 denotes a pixel matrix on which a normal image is displayed.
Reference numerals 101 to 104 denote data lines of the pixel matrix 100, and reference numerals 191 to 194 denote gate lines.
461SW, 462SW, 63SW and 464SW are switching elements for data line inspection.

421 and 422 also serve as a so-called short ring, and 421 is connected to odd-numbered data lines 101 and 103 (hereinafter, 421 is also referred to as “data line-side odd short ring”). 422 is connected to the even-numbered data line 102 and the data line 104. (Hereinafter, 422 is also referred to as “data line side even-numbered short ring”).

In FIG. 4, the number of data lines is four, but the number is not limited to four, and depends on the number of data lines of the pixel matrix.
461SW is connected to an odd-numbered data line 101 counted from the left end of the pixel matrix 100 in FIG. 4 among the data lines of the pixel matrix 100, and 462SW is an even-numbered data counted from the left of the pixel matrix 100 data lines. 463 SW is connected to the odd-numbered data line 103 among the data lines of the pixel matrix 100, and 464 SW is connected to the even-numbered data 104 among the data lines of the pixel matrix 100.

  Hereinafter, the data lines connected to the odd-numbered data lines among the data lines of the pixel matrix 100 as 461SW are also referred to as “odd-number data inspection switching elements”, and the even-numbered data lines of the pixel matrix 100 as 462SW. Those connected to the data lines are also referred to as “even-numbered data line inspection switching elements”.

  Reference numeral 400 denotes a data line inspection switching element control line which is connected in common to the gates of the data inspection switching elements connected to the data lines of the pixel matrix 100 and simultaneously conducts or blocks all the data line inspection switching elements. It is.

(Embodiment 2)
In the inspection circuit inspection method according to the second embodiment, the inspection circuit inspection method according to the second embodiment is provided with a data line inspection switching element for each data line, so that two lines called so-called short rings are provided. In addition, a switching control line for data line inspection, which is connected to all the switching elements for data line inspection and simultaneously opens and closes the switching elements, is installed, and an odd-numbered data line is connected to one of the two short ring lines. The first data line is connected to the remaining one short ring line, and in particular, a function for efficiently inspecting a defect between adjacent data lines is added.

Hereinafter, of the inspection circuit inspection method according to the second embodiment, a part added to the invention according to the first embodiment will be described.
The short ring 421 is connected to an odd-numbered data line among the data lines of the pixel matrix 100 through an odd-numbered data line inspection switching element. Hereinafter, it is also referred to as “odd number data line inspection short ring”. Specifically, the data line 101 is connected to the source side of the data line inspection switching element 461SW, and if the data line inspection switching element 461SW is turned on by a signal from the data line inspection control line 400, the short ring 421 is connected.

  Similarly, the data line 103 is connected to the source side of the odd-numbered data line inspection switching element 463SW. If the data line inspection switching element 463SW is turned on by a signal from the data line inspection control line 400, the short ring 421 is connected. Connect to.

The short ring 422 is connected to the even-numbered data line among the data lines of the pixel matrix 100 through the even-numbered data line inspection switching element. Hereinafter, it is also referred to as “even number data line inspection short ring”. The data line 102 is connected to the source side of the data line inspection switching element 462SW. When the data line inspection switching element 462SW is turned on by a signal from the data line inspection control line 400, the data line 102 is connected to the short ring 422.
Similarly, the data line 104 is connected to the source side of the data line inspection switching element 464SW. When the data line inspection switching element 464SW is turned on by a signal from the data line inspection control 400, the data line 104 is connected to the short ring 422. .

In FIG. 4, the number of data lines is four, but the number is not limited to four, and depends on the number of data lines of the pixel matrix. The same applies to the number of switching elements for data line inspection.
In the array test, by using the odd short ring 421 and the even short ring 422, an independent inspection signal can be supplied to adjacent data lines that are likely to cause defects. The possibility of easy discovery and identification can be improved.
(Embodiment 3)
In the inspection circuit inspection method according to the third embodiment, a scanning line inspection switching element is provided for each scanning line in the inspection circuit inspection method according to the first or second embodiment. In addition, a switching control line for scanning line inspection, which is connected to all the switching elements for scanning line inspection and simultaneously opens and closes the switching elements, is installed, and one of the two short ring lines has an odd-numbered scan. Lines are connected, and the remaining one short ring line is connected with even-numbered scanning lines, and in particular, a function for efficiently inspecting defects between adjacent scanning lines is added. The short ring line to which the odd-numbered scanning lines are connected is called a scanning line-side odd short ring line, and the short ring line to which the even-numbered scanning lines are connected is also called the scanning line-side even short ring line.
As a result, in the case of an array test, an independent inspection signal can be supplied to adjacent scanning lines that are prone to defects by using odd short ring lines and even short ring lines. It is possible to easily find a defect between scanning lines to improve the specific efficiency of the defect location.

The array substrate used in the flat display display device can be effectively inspected, and the manufacturing cost can be reduced.

100 Pixel Matrix Displaying Normal Image 101 Data Line 102 Data Line 103 Data Line 104 Data Line 131 Test Reference Capacitor 132 Test Reference Capacitor 133 Test Reference Capacitor 134 Test Reference Capacitor 151 Sense Amplifier 152 Sense Amplifier 153 Sense Amplifier 154 Sense amplifier 161 EOR (exclusive OR) comparison circuit 162 EOR (exclusive OR) comparison circuit 163 EOR (exclusive OR) comparison circuit 164 EOR (exclusive OR) comparison circuit 171 OR (logical sum) Output circuit 172 OR (logical sum) output circuit 173 OR (logical sum) output circuit 174 OR (logical sum) output circuit 191 Gate line 192 Gate line 193 Gate line 194 Gate line 180 Comparison signal line 181 Output line 1 8 gate line scanning circuit 190 data line scanning circuit

Claims (7)

  An active matrix having a pixel electrode on an insulating substrate, a pixel switching element individually connected to the electrode, and a plurality of scanning lines and data lines arranged in a grid for driving the pixel electrode through the pixel switching element An active matrix substrate having a test sense amplifier and a reference capacitor connected to each of the plurality of data lines in the substrate   2. The active matrix substrate according to claim 1, wherein a comparison signal line for sending an expected value as a reference for inspection, an exclusive signal between the signal from the comparison signal line and the outputs of the plurality of inspection sense amplifiers An active matrix substrate comprising: an EOR circuit that takes a logical sum; and a scanning line scanning circuit that scans the plurality of scanning lines.   3. The active matrix substrate according to claim 2, wherein a data line scanning circuit that scans the plurality of data lines and an output line that outputs a logical product of outputs of all the plurality of EOR circuits and the data line scanning circuit. Active matrix substrate characterized in that it has a portion   4. The active matrix substrate according to claim 3, further comprising an output line portion that forms an OR circuit by connecting outputs of all of the plurality of EOR circuits.   5. The active matrix substrate according to claim 4, further comprising a circuit for writing independent inspection data to odd-numbered data lines and even-numbered data lines.   6. The active matrix substrate according to claim 5, wherein a test signal is applied to odd-numbered data lines and even-numbered data lines, and test data is written to the pixels by a scanning line scanning circuit, and a reference potential is applied to the test reference capacitor. A step of sequentially reading data from the pixel by the scanning line scanning circuit, a step of amplifying and holding the read potential by the sense amplifier, a step of comparing the sense amplifier output and the expected value by the EOR circuit, and outputting a comparison result And a step of inspecting the active matrix substrate.   7. The data line scanning circuit according to claim 6, wherein when the logical sum of the comparison EOR circuit output according to claim 4 shows a mismatch with an expected value, the logical product of claim 3 outputs a mismatch. A test method for determining a location of a defective pixel by specifying a data line address by the input clock count and specifying a scan line address by the input clock count of the scan line scanning circuit according to claim 2.

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