JP2011064479A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device having a test operation mode for determining a logic level of a plurality of internal signals by a current measurement result. <P>SOLUTION: A test circuit 100 includes current sources 11-14, a reference current source 21, an input initial stage circuit 31, an OR circuit 35, selector circuits 41-44 and a terminal capacity countermeasure transistor (N-channel type MOS transistor Mn31). The current sources 11-14 constitute a current control circuit, and sends to the ground, a current corresponding to the size of a constituted transistors connected in series from an external terminal INP through the terminal capacity countermeasure transistor (N-channel type MOS transistor Mn31) in a test operation mode. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a semiconductor device having a test function.

  In semiconductor devices typified by DRAM (Dynamic Random Access Memory) and the like, the degree of integration of elements such as transistors has been increasing, and along with this, the circuit itself mounted on the semiconductor device has become more complex. ing. As a result, for example, the time for evaluating the correctness (good / bad) of a circuit mounted in product development has increased.

  Therefore, in order to shorten the evaluation time, a circuit to be tested, a circuit to be subjected to a special operation (hereinafter referred to as a circuit under test) has a desired logic level (“0”, “1”) or a voltage level. A test function (signature) that makes it possible to test whether or not a signal (hereinafter referred to as a signal under measurement) is output (hereinafter, “0” is L level and “1” is H level in positive logic). ) Have been developed.

For example, in the semiconductor device disclosed in Patent Document 1, a transistor to which one signal to be measured is input is connected to one external terminal, and a current flowing through the transistor is measured, whereby an H level of the signal to be measured is obtained. / L level is detected (see FIG. 6 of Patent Document 1).
Also in the semiconductor device disclosed in Patent Document 2, when an inverter circuit to which one signal to be measured is input is connected to one external terminal through a transistor and a current flows through the transistor, the signal to be measured Is detected at the L level (see FIG. 66 of Patent Document 2).

  In the semiconductor device disclosed in Patent Document 3, one signal obtained by taking a wired OR logic of a plurality of signals under measurement is output to one external terminal, and the logic level of at least one signal under measurement is “ 1 ”(see FIG. 3 of Patent Document 3). In addition, it is also disclosed that a wired OR logic circuit is used as a selector circuit and control is performed so that signals under measurement are sequentially output to the outside (see page 15, line 21 to line 25 of Patent Document 3).

JP-A-8-262109 JP-A-9-107081 Republished patent WO00 / 11486

  However, the semiconductor devices disclosed in Patent Document 1 and Patent Document 2 detect the logic level of one signal under measurement with one external terminal, and cannot simultaneously detect the logic levels of a plurality of signals under measurement. Therefore, the logic level of the signal under measurement exceeding the number of external terminals cannot be detected, and it is necessary to increase the number of external terminals as the number of circuits under test to be evaluated increases, which increases the chip size. There was a problem. Alternatively, when the number of external terminals is limited, the number of signals to be measured that can be detected is limited, and there is a problem that the circuit under test cannot be sufficiently evaluated.

  The semiconductor device disclosed in Patent Document 3 detects the logic level of a plurality of signals under measurement with one external terminal, but cannot detect which signal under measurement is at an H level. Here, even if the selector circuit is used as described above, the logic levels of a plurality of signals under measurement cannot be detected simultaneously. This is because it is necessary to measure the logic level at the external terminal as many times as the number of signals under measurement. Therefore, since the logic levels of a plurality of signals under measurement cannot be detected at the same time, there is a problem that the evaluation time becomes long.

  The present invention provides a current comprising a plurality of current sources having a plurality of internal signals input and having different current driving capabilities, provided between a common output terminal and either the power supply voltage or the ground voltage. And a current control circuit including a plurality of internal signals between a power supply voltage or a ground voltage and an output terminal in a first test operation mode in which the logic levels of the plurality of internal signals are determined based on a current measurement result. The semiconductor device is characterized in that the addition currents of a plurality of current sources flow based on the combination of the logic levels of the internal signals.

  According to the present invention, the number of external terminals is increased with the increase in the number of circuits under test to be evaluated in order to monitor the addition current with a common output terminal and simultaneously detect the logic levels of a plurality of signals under measurement. There is no necessity, and an increase in chip size can be suppressed. In addition, since the logic levels of a plurality of signals under measurement can be detected simultaneously, the evaluation time can be shortened.

It is a block diagram of the test circuit with which the semiconductor device of this invention is provided. FIG. 2 is a supplementary explanatory diagram used for explaining the operation of the test circuit of FIG. 1. It is a block diagram of the test circuit with which the semiconductor device of this invention is provided.

A typical example of the technical idea for solving the problems of the present invention is shown below. However, it goes without saying that the claimed contents of the present invention are not limited to this technical idea, but are the contents described in the claims of the present invention.
In recent semiconductor devices, a signature circuit is built in to evaluate a circuit under test, and various information of the circuit under test is read to an external terminal via the signature circuit during the evaluation operation. As the amount of internal information to be evaluated increases as semiconductor devices become highly integrated and multifunctional, a signature circuit that can read a large amount of information is required. At that time, there is a demand to output a plurality of signals under measurement simultaneously to a small number of external terminals to reduce the measurement time, the number of external terminals, and the number of measurement channels of a measuring apparatus, for example, a tester.

  Here, as the circuit under test, each logic circuit block constituting an access path of a semiconductor device, for example, a DRAM can be considered. In the initial evaluation after development, it is necessary to evaluate whether or not the design is successfully performed by confirming that the circuit under test outputs a signal of a desired logic level in various operation modes. In recent years, while miniaturization of semiconductor processes has been promoted, ensuring reliability has become an increasingly important issue, and various reliability tests have been performed. When analyzing a defect generated in the reliability test, it is necessary to reproduce the defect. In this case, finally, it is necessary to open the package and expose the silicon chip to identify the defective portion. However, since the circuit scale is large, the identification is difficult. In such a case, the circuit environment formed on the silicon chip is changed by opening, and the possibility that the defect is not reproduced is output to a desired logic level up to the circuit under test. By confirming that there is a defect, it is possible to estimate the location of the defective portion.

  Further, in recent semiconductor devices, a fuse circuit or an antifuse circuit is mounted, and a control signal is output from a fuse signal circuit or the like according to information set corresponding to a conduction / non-conduction state of a fuse element, etc. For example, the delay characteristic of a circuit is varied. Since the setting information built in such a semiconductor device is known from outside the chip after the package is enclosed, it is necessary to output it to the outside of the chip.

  As the number of circuits under test increases as described above, a test circuit that outputs the logic level of the signal under test output from the circuit under test to the outside is required. There is a demand to output to few external terminals.

Therefore, in the semiconductor device according to the present invention, a signal under measurement is assigned to each of a plurality of current sources having different capacities, an added current flowing through one measurement terminal is measured, and a logic combination of the signals under measurement according to the added current Is determined. That is, the technical idea is to simultaneously measure the logic of a plurality of signals under measurement.
Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

(First embodiment)
FIG. 1 is a configuration diagram of a test circuit 100 provided in a semiconductor device according to an embodiment of the present invention. In FIG. 1, the test circuit 100 includes current sources 11 to 14, a reference current source 21, an OR circuit 35, selector circuits 41 to 44, and a terminal capacitance countermeasure transistor (N channel type MOS transistor Mn31). In addition, the test circuit 100 shares an external terminal INP used for exchanging signals between the semiconductor device and the outside with the input initial stage circuit 31.

  The input first stage circuit 31 is an address buffer circuit, for example, and is a circuit to which an external address signal is input via the external terminal INP. Note that the test circuit 100 is a circuit that operates in response to the test signals TEST1 and TEST2 that are input in the test operation mode. However, circuits other than the test circuit 100 including the circuit under test are read and write operations in the normal operation mode. Perform the operation. That is, the test circuit 100 operates in parallel with the circuit under test when the circuit under test outputs a signal under measurement.

  The current sources 11 to 14 constitute a current control circuit, and in the test operation mode, the size of the transistors connected in series is configured from the external terminal INP via the terminal capacitance countermeasure transistor (N-channel MOS transistor Mn31). Send the corresponding current to ground.

  The current source 11 is configured by connecting an N-channel MOS transistor Mn11a and an N-channel MOS transistor Mn11b in series. The drain terminal of the N-channel MOS transistor Mn11a is connected to the source terminal of the N-channel MOS transistor Mn31, the gate terminal is connected to the output of the selector circuit 41, and the source terminal is connected to the drain terminal of the N-channel MOS transistor Mn11b. The The drain terminal of the N-channel MOS transistor Mn11b is connected to the source terminal of the N-channel MOS transistor Mn11a, the gate terminal is connected to the wiring through which the test signal TEST1 is propagated, and the source terminal is grounded.

  The current source 12 is configured by connecting an N-channel MOS transistor Mn12a and an N-channel MOS transistor Mn12b in series. The drain terminal of the N-channel MOS transistor Mn12a is connected to the source terminal of the N-channel MOS transistor Mn31, the gate terminal is connected to the output of the selector circuit 42, and the source terminal is connected to the drain terminal of the N-channel MOS transistor Mn12b. The The drain terminal of the N-channel MOS transistor Mn12b is connected to the source terminal of the N-channel MOS transistor Mn12a, the gate terminal is connected to the wiring through which the test signal TEST1 is propagated, and the source terminal is grounded.

  The current source 13 is configured by connecting an N-channel MOS transistor Mn13a and an N-channel MOS transistor Mn13b in series. The drain terminal of the N-channel MOS transistor Mn13a is connected to the source terminal of the N-channel MOS transistor Mn31, the gate terminal is connected to the output of the selector circuit 43, and the source terminal is connected to the drain terminal of the N-channel MOS transistor Mn13b. The The drain terminal of the N-channel MOS transistor Mn13b is connected to the source terminal of the N-channel MOS transistor Mn13a, the gate terminal is connected to the wiring through which the test signal TEST1 is propagated, and the source terminal is grounded.

  The current source 14 is configured by connecting an N-channel MOS transistor Mn14a and an N-channel MOS transistor Mn14b in series. The drain terminal of the N-channel MOS transistor Mn14a is connected to the source terminal of the N-channel MOS transistor Mn31, the gate terminal is connected to the output of the selector circuit 44, and the source terminal is connected to the drain terminal of the N-channel MOS transistor Mn14b. The The drain terminal of the N-channel MOS transistor Mn14b is connected to the source terminal of the N-channel MOS transistor Mn14a, the gate terminal is connected to the wiring through which the test signal TEST1 is propagated, and the source terminal is grounded. In each of the current sources 11 to 14, the order of the N-channel MOS transistors connected in series may be such that the source terminal of any transistor is connected to the ground.

  Here, the on-resistances of the N-channel MOS transistors Mn11a to 14a, that is, the on-resistance when an H level signal is input from the corresponding selector, are N-channel MOS transistor Mn11a, N-channel MOS transistor Mn12a, The transistor size is determined so that the on-resistance ratio is, for example, 8: 4: 2: 1 so that the N-channel MOS transistor Mn13a and the N-channel MOS transistor Mn14a become smaller in this order. This can be realized by making the channel length L constant and the channel width W 1: 2: 4: 8 in this order in the N-channel MOS transistors Mn11a to 14a.

  The on-resistances of the N-channel MOS transistors Mn11b to 14b, that is, the on-resistance when the H level test signal TEST1 is input are all the same, and are sufficiently smaller than the on-resistance of the N-channel MOS transistor Mn14a. The transistor size is set so that This can be realized by setting the channel length L to be the same as that of the N-channel MOS transistor Mn14a and setting the channel width W to 5 to 10 times, for example.

  The N-channel MOS transistor Mn31 is a terminal capacity countermeasure transistor that is turned off in the normal operation mode and disconnects the external terminal INP from the current sources 11 to 14 or the reference current source 21. That is, it has a function of not increasing the input capacitance of the external terminal INP by turning off in the normal operation mode. For example, in the case where the external terminal INP is an address terminal to which an address signal requiring high-speed operation is input, if the N-channel MOS transistor Mn31 is not turned off in the normal operation mode, only this address terminal is parasitic among the plurality of address terminals. Capacity will increase. As a result, the signal characteristics of the external terminal INP are different from those of other address terminals, and the operation speed of the input first stage circuit 31 is delayed. The N-channel MOS transistor Mn31 is a compensation element (capacitance countermeasure transistor) for preventing such delay.

  The transistor size is set so that the on-resistance of the N-channel MOS transistor Mn31, that is, the on-resistance in the test operation mode is sufficiently smaller than the on-resistance of the N-channel MOS transistor Mn14a. This can be realized by setting the channel length L to be the same as that of the N-channel MOS transistor Mn14a and the channel width W being 5 to 10 times, for example, like the N-channel MOS transistors Mn11b to 14b.

  With this configuration, the current source 11, the current source 12, the current source 13, and the current source 14 are driven in this order in which the current value ratio is 1: 2: 4: 8 (the ability to draw current from the external terminal INP). ) And the impedance between the external terminal INP and the ground, that is, the on-resistance is 8: 4: 2: 1.

  The reference current source 21 is configured by connecting an N-channel MOS transistor Mn21a and an N-channel MOS transistor Mn21b in series. The drain terminal of the N-channel MOS transistor Mn21a is connected to the source terminal of the N-channel MOS transistor Mn31, the gate terminal is connected to the wiring through which the test signal TEST2 is propagated, and the source terminal is the drain terminal of the N-channel MOS transistor Mn21b. Connected. The drain terminal of the N-channel MOS transistor Mn21b is connected to the source terminal of the N-channel MOS transistor Mn21a, the gate terminal is connected to the wiring through which the test signal TEST2 is propagated, and the source terminal is grounded.

  Here, the on-resistance of the N-channel MOS transistor Mn21a, that is, the on-resistance when the H-level test signal TEST2 is input is the same as the on-resistance of the N-channel MOS transistor Mn11a. Has been determined. This can be realized by making the channel length L and the channel width W of the N-channel MOS transistor Mn21a and the N-channel MOS transistor Mn11a the same.

  The transistor size is set so that the on-resistance of the N-channel MOS transistor Mn21b, that is, the on-resistance when the H-level test signal TEST2 is input is the same as the on-resistance of the N-channel MOS transistor Mn11b. It is determined. This can be realized by making the channel length L and the channel width W of the N-channel MOS transistor Mn21b and the N-channel MOS transistor Mn11b the same.

  With such a configuration, the driving capabilities of the current source 11 and the reference current source 21 are the same, and the impedance between the external terminal INP and the ground, that is, the on-resistance is also the same.

  The selector circuits 41 to 44 are controlled by a control signal (not shown), for example, a test code inputted from the outside, selects a combination of signals to be measured, and outputs the selected signals to be measured to the current sources 11 to 14, respectively. . In FIG. 1, the signals under measurement input to the selector circuits 41 to 44 are indicated by Ai, Bi, Ci, Di (i = 1 to 4), respectively. Any one selected signal is output to each of the current sources 11 to 14. Hereinafter, it is assumed that the selector circuits 41 to 44 simultaneously select signals to be measured having the same symbol i and output them to the current sources 11 to 14.

  Further, the combination of the logic levels of the signals under test Ai, Bi, Ci, Di is represented by (Ai, Bi, Ci, Di) = (H / L, H / L, H / L, H / L) To do. For example, in the test operation mode, the selector circuits 41 to 44, when (A1, B1, C1, D1) = (H, L, H, L), output the signal under test A1 at the H level to the N-channel MOS transistor Mn11a. An L level measured signal A2 is applied to the gate terminal of the N channel type MOS transistor Mn12a, an H level measured signal A3 is applied to the gate terminal of the N channel type MOS transistor Mn13a, and an L level measured signal A4 is applied to the gate terminal. Each is output to the gate terminal of the N-channel MOS transistor Mn14a.

  The OR circuit 35 turns on the N-channel MOS transistor Mn31 when one of the test signal TEST1 and the test signal TEST2 becomes H level, and connects the external terminal INP and the current sources 11 to 14 or the reference current source 21.

  Next, the operation of the test circuit 100 configured as described above in the test operation mode will be described. In the test operation mode, the test signal TEST1 is at the H level in the first test operation mode, and the test signal TEST2 is at the H level in the second test operation mode. In the following description, it is assumed that the selector circuits 41 to 44 select the signals under test A1, B1, C1, and D1 in the first test operation mode. Further, the driving capability of the current source 11, the current source 12, the current source 13, and the current source 14 is assumed to have a current driving capability of a ratio of 1: 2: 4: 8 in this order as in the above-described example. . That is, the current source 11, the current source 12, the current source 13, and the current source 14 have an impedance between the external terminal INP and the ground, that is, an on-resistance ratio of 8: 4: 2: 1.

In the first test operation mode, the test signal TEST1 becomes H level, the OR circuit 35 outputs H level, and the N-channel MOS transistor Mn31 is turned on.
Further, the N-channel MOS transistors Mn11b, Mn12b, Mn13b, and Mn14b are turned on because the voltage levels of their gate terminals are H level.
At this time, the impedance between the external terminal INP and the ground depends on whether the logic levels of the signals under test A1, B1, C1, and D1 are at the H level or the L level, respectively. Changes. That is, the combined impedance of the current sources 11 to 14 takes a total of 16 (= 2 ⁴ ) values from when all the signals under measurement are at the L level to when they are all at the H level.

FIG. 2 shows the combinations of the measured signals A1, B1, C1, and D1 at the H level / L level, and the resultant impedance of the current control circuit, the current value I1, and the ratio of the current value I1 to the reference current value I0. It is a figure.
For example, if the combined impedance in the case of (A1, B1, C1, D1) = (H, H, H, H) is R0, the combination of (A1, B1, C1, D1) as shown in FIG. The combined impedance by R0, R0 × (15/14), R0 × (15/13), R0 × (15/12), R0 × (15/11), R0 × (15/10) in ascending order. ), R0 × (15/9), R0 × (15/8), R0 × (15/7), R0 × (15/6), R0 × 3, R0 × (15/4), R0 × 5, There are 16 values of R0 × (15/2), R0 × 15, and HiZ (high impedance).

  As described above, since the impedance between the external terminal INP and the ground changes depending on the combination of the logic levels of the signals under test A1, B1, C1, and D1, a current source, for example, is connected to the external terminal INP in the first test operation mode. By connecting to a tester current source and applying a constant voltage and measuring the current, 16 types of measured current values can be obtained. For example, assuming that the current value flowing when (A1, B1, C1, D1) = (H, L, L, L) is the reference current value I0, as shown in FIG. 2, (A1, B1, C1, D1) ), The 16 types of measured current values are, in order from the lowest impedance, I0 × 15, I0 × 14, I0 × 13, I0 × 12, I0 × 11, I0 × 10, I0 × 9, I0x8, I0x7, I0x6, I0x5, I0x4, I0x3, I0x2, I0, 0.

On the other hand, in the second test mode, when the transistor constant constituting the reference current source 21 is set to the same constant as the transistor constant constituting the current source 11 as in the above example, the reference current source 21 is connected to the tester. When a current source is connected and the same voltage as in the first operation mode is applied, the measured current value is I0.
The reason for providing the second operation mode in this way is as follows. That is, in the first test operation mode, as described above, one measurement value out of 16 types of measurement values can be acquired by combining the logic levels of the signals under measurement. However, the current value that can be acquired can vary depending on the manufacturing variation of the semiconductor chip on which the test circuit is mounted, for example, the performance of the threshold voltage (Vt) of the N-channel MOS transistor.

  For example, when (A1, B1, C1, D1) = (L, H, L, H), the measured current is I0 × 10, but the threshold voltage of the N-channel MOS transistor is greatly increased. When the drain current (Ion) decreases by, for example, 5%, the measured current shifts to a low value of I0 × 9.5. This makes it difficult to distinguish from the measured current value of I0 × 9 flowing in the case of (H, L, L, H). Therefore, the current value I0 is measured when the reference current source 21 is connected to the external terminal INP in the second test operation mode. In this way, the combination of the H level / L level of the signal under measurement can be obtained without error in the first and second test modes.

  Specifically, the current measurement value (I1) in the first operation mode is divided by the current measurement value (I0) in the second operation mode, that is, (I1 / I0) is obtained. As shown in FIG. 2, (I1 / I0) can take a value substantially close to an integer value of 0 to 15. In the above example, since (I1 / I0) = 10, the combination of the logic levels of the signals under measurement is (A1, B1, C1, D1) = (L, H, L, H). Can be known more easily.

  That is, by performing current measurement twice in the first and second test modes and obtaining (I1 / I0), an error in the measured current value caused by manufacturing variation is reduced, and as shown in FIG. The combination of the logic levels of the signals under measurement can be known.

  As described above, the semiconductor device according to the present embodiment is provided between one common output terminal (external terminal INP) and either the power supply voltage or the ground voltage, and a plurality of internal signals (signals to be measured). A1, B1, C1, D1) are input, and a current control circuit including a plurality of current sources (current sources 11 to 14) having different current drive capabilities from each other is provided. The current control circuit has a logic level of a plurality of internal signals. In the first test operation mode determined by the current measurement result, addition of a plurality of current sources is performed between one of the power supply voltage or the ground voltage and the output terminal based on a combination of logic levels of a plurality of internal signals. A semiconductor device is characterized by passing a current (0 to I0 × 15).

  According to the present invention, the addition current is monitored by one common output terminal (external terminal INP), and the logic levels of a plurality of signals under measurement are detected at the same time. There is no need to increase the number of terminals, and an increase in chip size can be suppressed. In addition, since the logic levels of a plurality of signals under measurement can be detected simultaneously, the evaluation time can be shortened.

  In addition, according to the present invention, the current value flowing from the external terminal to the power source or ground of the semiconductor chip (ground in the description of the above embodiment) is measured, and based on the combination of the logic levels of the signal under measurement, It is not the structure which outputs an output voltage from a semiconductor chip to an external terminal. If the latter configuration is adopted, as explained in the above example, 16 output voltages are output to the external terminal according to the combination of the H level / L level of the signal under measurement. Determination is required, and the measurement time required to know the combination of signals under measurement increases.

  Further, as the operating voltage of the semiconductor chip is lowered, the output voltage level is also lowered, so that the setting interval of the threshold voltage by the comparator is narrowed, and the number of signals to be measured held by one terminal cannot be increased. On the other hand, in the present invention, since the monitoring result (combination of the logic levels of the signal under measurement) can be obtained with the current value flowing through the external terminal INP, the determination of the number of times according to the signal under measurement by the tester is unnecessary Measurement time can be shortened. Further, even when the voltage is lowered, it is not necessary to reduce the signal to be measured that one external terminal has, and it is possible to cope with the increase in the signal to be measured without increasing the number of external terminals.

(Second Embodiment)
Next, another embodiment of the present invention will be described.
FIG. 3 is a configuration diagram of a test circuit 200 in a semiconductor device according to another embodiment of the present invention. In FIG. 3, the same components as those in FIG.
The test circuit in FIG. 3 is different from the test circuit in FIG. 1 in the following points.

That is, a test signal generation circuit 51 for generating the test signal TEST1 and the test signal TEST2 is provided. The test signal generation circuit 51 includes a reset terminal R.
The reset terminal R is connected to the input first stage circuit 31a and is configured to receive a reset signal. Here, the input first stage circuit 31a is a circuit having a function of resetting the operation of the semiconductor chip when an L level signal is input via the external terminal INP, for example.
When an operation failure occurs during the transition to the above-described first and second test operation modes, the test circuit 200 receives the reset signal to input the test signal TEST1 or the test signal TEST2 to the L level. To change. As a result, the semiconductor device ends the test operation mode and shifts to the normal operation mode. As the above operation failure, for example, when a current flows from the external terminal INP, the ground wiring rises, a failure occurs in one of the circuit blocks in the semiconductor chip, the signal transmission is interrupted, and the subsequent signals May not be transmitted, and the test operation mode cannot be reset, making it impossible to shift to the normal operation mode.

  In the embodiment described above, the reference current source 21 is provided. However, the reference current source 21 can be replaced by the current source 11 to which TEST1 is input. For example, the output from the selector circuit 41 input to the N-channel MOS transistor Mn11a may be controlled to be the test signal TEST2, and the outputs from the other selector circuits 42 to 44 may be controlled to L level. That is, in the description of the above embodiment, the signals under measurement input to the selector circuits 41 to 44 are Ai, Bi, Ci, Di (i = 1 to 4). The selector circuits 41 to 44 are further configured to receive test signals TEST2, GND, GND, and GND (GND is a ground voltage). In the second test operation mode, the test signal TEST1 is also set to the H level. Thus, the current value of the current source 11 may be measured and used as the reference current I0. That is, the current source 11 can be substituted without providing the reference current source 21.

  In the embodiment, each of the selector circuits 41 to 44 is configured to receive four signals. However, the number is not limited to this number, and any number is possible. In the embodiment, the number of current sources is four. However, the number of current sources is not limited to this number, and may be any number. For example, a current source having a driving capability 16 times that of the current source 11 (impedance is 1/16 times) may be added to form a total of five units. In this case, there are 32 combinations of H level / L level of the signal under measurement. Further, since there are 32 types of combined impedance between the external terminal of the current control circuit and the ground or the power supply in accordance with the combination of the logic levels of the signals under measurement, any one of the 32 current values in the current measurement. Can be obtained.

  In the embodiment, the current sources 11 to 14 and the reference current source 21 are configured by N-channel MOS transistors, but may be configured by P-channel MOS transistors. At that time, the selector circuits 41 to 44 may be configured to logically invert the signal under measurement and output it. In this case, a current flows from the power supply voltage of the test circuits 100 and 200 to the external terminal INP by the same combination of the logic levels of the signal under measurement as described in the above embodiment. Then, the combination of the logic levels of the signal under measurement can be determined by monitoring the addition current with the external terminal INP.

In the embodiment, the memory device is disclosed. However, the basic technical idea of the present application is not limited thereto, and may be a logic, a CPU, an MCU, a DSP device, or the like. Furthermore, it can be applied to semiconductor devices such as SIP and POP (package on package). The transistor may be a field effect transistor (FET), and may be applied to various FETs such as MIS (Metal-Insulator Semiconductor) and TFT (Thin Film Transistor) in addition to MOS (Metal Oxide Semiconductor). it can. In addition, a transistor other than an FET (for example, a bipolar transistor) can be used as a part of the constituent elements of the present invention. Further, the NMOS transistor (N-type channel MOS transistor) is a representative example of the first conductivity type transistor, and the PMOS transistor (P-type channel MOS transistor) is a representative example of the second conductivity type transistor.
Various combinations and selections of various disclosed elements are possible within the scope of the claims of the present invention. That is, the present invention of course includes various modifications and corrections that could be made by those skilled in the art according to the entire disclosure including the claims and the technical idea.

  DESCRIPTION OF SYMBOLS 100,200 ... Test circuit, 11, 12, 13, 14 ... Current source, 21 ... Reference current source, 31, 31a ... Input first stage circuit, 35 ... OR circuit, 41, 42, 43, 44 ... Selector circuit, INP ... External terminals, TEST1, TEST2 ... test signals, Mn11a, Mn11b, Mn12a, Mn12b, Mn13a, Mn13b, Mn14a, Mn14b, Mn21a, Mn21b, Mn31 ... N-channel MOS transistors, 51 ... test signal generating circuits, A1, Ai, A2 , A3, A4, B1, C1, D1... Signal under measurement,

Claims (7)

Provided between one common output terminal and either the power supply voltage or the ground voltage, and provided with a current control circuit composed of a plurality of current sources to which a plurality of internal signals are input and have different current drive capabilities ,
In the first test operation mode in which the current control circuit determines the logic levels of the plurality of internal signals based on the current measurement result, the plurality of internal signals are provided between one of a power supply voltage or a ground voltage and the output terminal. A semiconductor device, wherein an addition current of the plurality of current sources is supplied based on a combination of signal logic levels. A current control circuit including a plurality of current sources connected to a common output terminal, to which a plurality of internal signals are input, and having different current drive capabilities;
In the first test operation mode in which the logic level of the plurality of internal signals is determined based on the current measurement result, the current control circuit maintains a high impedance between either the power supply voltage or the ground voltage and the output terminal. A semiconductor device characterized in that a gap between the other of the power supply voltage or the ground voltage and the output terminal is changed from a high impedance to a low impedance based on a combination of logic levels of the plurality of internal signals. The current control circuit is
A first transistor to which the internal signal is input to the gate and a second transistor to which the first test signal indicating the transition to the first test operation mode is input to the gate are connected in series. A series circuit is configured by connecting in parallel between one of a power supply voltage or a ground voltage and the output terminal,
3. The semiconductor device according to claim 1, wherein the semiconductor device is activated based on the first test signal in the first test operation mode. 4. A reference current source connected in parallel to the current control circuit;
The reference current source causes a reference current to flow between one of a power supply voltage or a ground voltage and the output terminal in a second test operation mode in which a reference current is measured. The semiconductor device according to claim 3. The reference current source is
A third transistor in which a second test signal indicating transition to the second test operation mode is input to the gate and a fourth transistor in which the second test signal is input to the gate are connected in series. The connected series circuit is configured by connecting either the power supply voltage or the ground voltage between the output terminal,
5. The semiconductor device according to claim 4, wherein the semiconductor device is activated based on the second test signal in the second test operation mode. An input circuit connected to the output terminal;
A fifth transistor connected between the output terminal and the current control circuit;
The semiconductor device according to claim 1, wherein the fifth transistor is turned on in the first test mode or the second test mode.   7. The semiconductor device according to claim 6, wherein when the input circuit is selected in the first test mode or the second test mode, the test mode is reset and the mode is changed to a normal mode.

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