JP2011060226A - Parity check circuit and computer system - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a parity check circuit that forcibly generates a parity error signal. <P>SOLUTION: The parity check circuit 132a includes: a first parity calculation circuit 133a for calculating a parity bit of data input to a register 131a; a second parity calculation circuit 136a for calculating a parity bit of data output from the register 131a; and an EXOR circuit 137a for comparing the parity bit calculated by the first parity calculation circuit 133a with the parity bit calculated by the second parity calculation circuit 136a, and outputting a parity error signal when the both parity bits are different from each other. The parity check circuit 132a is further provided with an EXOR circuit 134a for inverting the parity bit calculated by the first parity calculation circuit 133a on the basis of a parity error signal generation command input from the outside of the parity check circuit. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a parity check circuit and a computer system.

  In recent years, as represented by the functional safety standard IEC61508, electronic devices that control systems that may cause human lives or injuries, such as machinery for manufacturing industries, transportation and transportation facilities, chemical plants, and medical equipment. Therefore, it is becoming necessary to implement a mechanism for ensuring the safety of the system as a “function”.

  For example, automobiles are equipped with a large number of computers as electronic devices that control automobiles called electronic control units (ECUs). The ECU is an indispensable component for realizing basic performance, environmental performance, comfort performance, safety performance, and the like. The ECU includes a microprocessor, peripheral devices (input / output devices, etc.), and a communication module. The ECU executes judgments (calculations) necessary for operation based on input values from various sensors, and controls the operation of each part of the automobile by giving instructions to various actuators. For example, a brake ECU for controlling the posture and braking of a vehicle calculates an output value to be transmitted to an actuator for operating a brake based on an input value from a sensor installed on a brake pedal from a driver. .

  As one of the mechanisms for functional safety related to such an ECU group, when the ECU has a failure diagnosis function for detecting a failure of the EUC itself and the occurrence of the failure is recognized by the failure diagnosis function, A function of shifting to a control (safety control) that prevents a running vehicle from shifting to a dangerous state due to a failure is mentioned. Hereinafter, this function is referred to as a risk avoidance function, and a circuit that bears the risk avoidance function is referred to as a risk avoidance function circuit. The operation of this danger avoidance function can be confirmed only when there is a failure in the ECU having the failure diagnosis function. Therefore, it is necessary to test whether or not the danger avoidance function operates normally separately from the product shipment test for testing the danger avoidance function circuit using the SCAN test or the like. come. Hereinafter, this test is referred to as an operation test of the danger avoidance function circuit. The operation test of the danger avoidance function circuit is desirably performed every time as a self-diagnosis, for example, when the ignition is turned on, in order to improve reliability.

  By the way, registers are used in various places in the ECU group. One of the failure modes of the register is a permanent failure of the constituent hardware. This failure causes a failure such that data cannot be written to the register. The other is a failure called a soft error, which includes a temporary failure before reaching a permanent failure, or a temporary change in register contents due to radiation or power supply noise. As one of failure diagnosis functions for finding these failures, there is a parity check that calculates the parity of data before and after data input / output to / from a register and compares both parities (see, for example, Patent Document 1).

  A circuit for performing a parity check (parity check circuit) generates a parity error signal when a parity error having different parity before and after data input / output is detected. The danger avoidance function circuit uses the parity error signal from the parity check circuit as one of the inputs for recognizing the failure. It is desirable that the operation test of the danger avoidance function circuit includes a test of the soundness of the transfer path of the parity error signal. For this purpose, a mechanism for forcibly generating a parity error signal in the parity check circuit is required.

Japanese Patent Application Laid-Open No. 08-314812

  It is an object of the present invention to provide a parity check circuit and a computer system that can forcibly generate a parity error signal.

  According to an aspect of the present invention, a first parity calculation circuit that calculates a parity bit of data input to a register, a second parity calculation circuit that calculates a parity bit of data output from the register, and the first A parity check circuit comprising: a comparison circuit that compares a parity bit calculated by one parity calculation circuit and a parity bit calculated by the second parity calculation circuit and outputs a parity error signal when both parity bits are different from each other The parity check circuit further comprises an inverting circuit for inverting the parity bit calculated by the first parity calculation circuit based on a command input from the outside of the parity check circuit.

  According to another aspect of the present invention, a CPU, a register, a first parity calculation circuit that calculates a parity bit of data input to the register, and a parity bit of data output from the register are calculated. The second parity calculation circuit compares the parity bit calculated by the first parity calculation circuit with the parity bit calculated by the second parity calculation circuit, and outputs a parity error signal when both parity bits are different from each other. A parity check circuit comprising: a comparison circuit; wherein the parity check circuit includes an inverting circuit that inverts the parity bit calculated by the first parity calculation circuit based on a command input from the CPU. Provided by a computer system characterized by further comprising It is.

  According to the present invention, it is possible to provide a parity check circuit capable of forcibly generating a parity error signal.

  In addition, according to the present invention, it is possible to provide a computer system capable of forcibly generating a parity error signal.

FIG. 1 is a diagram showing an ECU group. FIG. 2 is a diagram showing a configuration of the ECU according to the embodiment of the present invention. FIG. 3 is a diagram for explaining the configuration of the parity check circuit according to the embodiment of the present invention. FIG. 4 is a diagram illustrating a configuration of a parity check circuit according to a comparative example.

  Hereinafter, a parity check circuit according to an embodiment of the present invention will be described in detail with reference to the accompanying drawings. In addition, this invention is not limited by this embodiment.

(Embodiment)
Hereinafter, a case where the computer system according to the embodiment of the present invention is applied to an electronic control unit (ECU) for an automobile will be described.

  FIG. 1 is a diagram illustrating a connection relationship between ECUs. As illustrated, a plurality (six in this case) of ECUs 1 to 6 are connected to each other via a communication network. The ECUs 1 to 5 are, for example, an engine ECU that controls the engine, a brake ECU that controls the attitude and braking of the vehicle, a steering ECU that controls the assist force during steering operation, and the speed ratio according to the speed and the engine speed. A transmission ECU for switching, a suspension ECU for controlling a damping force of a shock absorber or a bush, a spring constant of a spring, and the like, an airbag ECU for instructing an airbag module to deploy an airbag. The ECU 6 corresponds to the danger avoidance function circuit described above. That is, when the ECU 6 recognizes a failure of a register included in the ECUs 1 to 5, the ECU 6 controls the ECU 1 to 5 or some of the ECUs 1 to 5 to prevent the running vehicle from shifting to a dangerous state due to the failure. An instruction to shift to (safety control) is transmitted. The safety control includes, for example, control in which the brake ECU operates the brake to stop the vehicle.

  FIG. 2 is a diagram illustrating the configuration of the ECUs 1 to 5. Here, ECU1 will be described as a representative of ECU1 to ECU5. As illustrated, the ECU 1 includes a CPU (Central Processing Unit) 11, a ROM (Read Only Memory) 12, a plurality (three in this case) of IP (Intellectual Property Core) cores 13 a to 13 c, and an OR circuit 14. It has. The CPU 11, the ROM (control program storage unit) 12, and the IP cores 13a to 13c are connected to each other via a bus. Note that the bus width of this bus is, for example, 32 bits.

  The IP cores 13a to 13c are circuits grouped in functional units, such as a timer and a PWM circuit. Each of the IP cores 13a to 13c includes one or more registers, and further includes a parity check circuit that performs a parity check of each of the registers. Here, the IP core 13a includes a parity check circuit 132a that performs a parity check of the register 131a and the register 131a, the IP core 13b includes a parity check circuit 132b that performs a parity check of the register 131b and the register 131b, and the IP core 13c It is assumed that a parity check circuit 132c for checking the parity of 131c and the register 131c is provided. The registers 131a to 131c can store data having a bit width smaller than the bus width. Here, as an example, it is assumed that the registers 131a to 131c are 24-bit registers.

  The output terminals for outputting the parity check results of the parity check circuits 132a to 132c are connected to the input terminal of the OR circuit 14, respectively. The output terminal of the OR circuit 14 is connected to the ECU 6. When the parity check circuits 132a to 132c detect a parity error, the parity check circuits 132a to 132c shift the output terminal to the OR circuit 14 to High (“1”) (that is, generate a parity error signal). The generated parity error signal is transmitted to the ECU 6 via the OR circuit 14. The parity error signal from the OR circuit 14 to the ECU 6 may be transmitted using a dedicated signal line, or may be transmitted via a communication network connecting the ECUs 1 to 6 respectively. Good.

  The ROM 12 stores a control program 121. The CPU 11 executes control of the entire ECU 1 by executing the control program 121.

  Here, the ECU 6 normally shifts to safety control based on whether or not the parity error signal is normally transmitted to the ECU 6 immediately after starting, that is, when the ignition is on, and based on the transmitted parity error signal. Self-diagnosis is performed for items such as whether or not a command for issuing a command can be issued. The ECU 1 includes a mechanism for forcibly generating a parity error signal used for the self-diagnosis of the ECU 6 in the IP cores 13a to 13c. As a part of this mechanism, the CPU 1 forcibly causes the parity data to be generated in the test data stored in the registers 131a to 131c and the parity check circuits 132a to 132c based on the control by the control program 121 immediately after startup. A parity error signal generation command is transmitted.

  Next, a detailed configuration of the parity check circuit 132a for forcibly generating a parity error signal will be described. FIG. 3 is a diagram illustrating the configuration of the parity check circuit 132a.

  In the present embodiment, 24 bits of the 32-bit bus width are used for transferring data input to the register 131a. The parity error signal generation command is transmitted using a portion of the 32-bit bus width that is not included in the 24-bit data. Here, the CPU 11 generates data of 25-bit width under the control of the control program 121, and uses 1 bit thereof as a parity error signal generation command. More specifically, the CPU 11 generates 24-bit test data (DATA [23: 0]) and a 1-bit parity error signal generation command (DATA [24]), and the total 25-bit data is 32 bits. To a bus with a width of. When DATA [24] is “1”, DATA [24] functions as a parity error signal generation command. That is, when the parity error signal is not forcibly generated, such as when the register 131a is normally used, the CPU 11 sets DATA [24] to “0” when writing to the register 131a.

  The parity check circuit 132a includes a first parity calculation circuit 133a, an EXOR circuit (inversion circuit) 134a, a 1-bit register 135a, a second parity calculation circuit 136a, and an EXOR circuit 137a.

  The first parity calculation circuit 133a calculates a parity bit from the test data DATA [23: 0] before being stored in the register 131a. The first parity calculation circuit 133a is configured by cascading a plurality of EXOR circuits, for example, as illustrated. The output terminal of the first parity calculation circuit 133a is connected to the input terminal of the EXOR circuit 134a.

  DATA [24] is input to the other input terminal of the EXOR circuit 134a. The output terminal of the EXOR circuit 134a is connected to the input terminal of the register 135a. The EXOR circuit 134a outputs a value obtained by inverting the parity bit calculated by the first parity calculation circuit 133a when DATA [24] is “1”, and the parity bit when the DATA [24] is “0”. Is output without inversion.

  The second parity calculation circuit 136a has the same circuit configuration as the first parity calculation circuit 133a, and calculates a parity bit from the test data (REGDATA [23: 0]) read from the register 131a.

  The output terminal of the register 135a and the output terminal of the second parity calculation circuit 136a are connected to the input terminal of the EXOR circuit 137a, respectively. That is, the EXOR circuit 137a outputs “0” when the input from the second parity calculation circuit 136a is equal to the input from the register 135a, and “1” as a parity error signal when both inputs are different from each other. Is output.

  In the above configuration, when there is no failure in the register 131a and the parity check circuit 132a and DATA [24] is “1”, that is, a parity error signal generation command, the two inputs to the EXOR circuit 137a are different from each other. The parity check circuit 132a outputs “1”. Further, when the register 131a is normally used, DATA [24] is “0”, so that the EXOR circuit 134a stores the parity bit calculated by the first parity calculation circuit 133a in the register 135a without inverting it. To do. Accordingly, when there is no failure in the register 131a and the parity check circuit 132a, the parity check circuit 132a outputs “0”.

  Note that the configurations of the parity check circuit 132b and the parity check circuit 132c have the same configuration as the parity check circuit 132a, and thus the description of the configurations of the parity check circuit 132b and the parity check circuit 132c is omitted.

  In the above description, the parity error signal generation command is stored in the DATA [24] value. However, the parity error signal generation command is stored anywhere except for DATA [23: 0]. Good. For example, DATA [25] or DATA [26] may be used. The number of bits of the parity error signal generation command may be a value of 2 bits or more.

  In addition, it has been described that the CPU 11 generates a parity error signal generation command and the parity error signal generation command is transmitted to the parity check circuit 132a via the bus. However, the generation source of the parity error signal generation command is limited to the CPU 11 only. Not. Any element outside the parity check circuit 132a may be used. For example, the generation of the parity error signal generation command may be configured to be generated by another hardware circuit different from the CPU 11. The generation source of the parity error signal generation command may be provided outside the ECU 1. Further, the transmission of the generated parity error signal generation command may be configured not to pass through the bus. For example, the generated parity error signal generation command may be transmitted to the parity check circuit 132a via a dedicated signal line.

  FIG. 4 is a diagram illustrating the configuration of a parity check circuit that does not have a mechanism for forcibly generating a parity error signal. This parity check circuit is referred to as a parity check circuit according to a comparative example. As illustrated, in the parity check circuit 138a according to the comparative example, the EXOR circuit 134a is omitted from the parity check circuit 132a of the present embodiment, and the output terminal of the first parity calculation circuit 133a is directly connected to the input terminal of the register 135a. Has a structured. In other words, the generation of the parity error signal generation command is generated by another hardware circuit different from the CPU 11, and the generated parity error signal generation command is transmitted to the parity check circuit 132a via a dedicated signal line. If the CPU 11 generates a parity error signal generation command and can transmit the generated parity error signal generation command via the bus, the parity check according to the comparative example is applied when the embodiment of the present invention is applied. There is an effect that the amount of hardware to be newly added to the configuration of the circuit 138a can be further reduced.

  FIG. 3 of Patent Document 1 discloses a circuit similar to the combination of the first parity calculation circuit 133a and the EXOR circuit 134a described above. However, the input parity bit PI input to the circuit corresponding to the EXOR circuit 134a in FIG. 3 of Patent Document 1 indicates the parity of 8-bit input data (DI7 to DI0). Therefore, it is not a signal that inverts the parity of the 8-bit input data, that is, a signal that compulsorily generates a parity error signal, but an operation test of the danger avoidance function circuit that is a problem in the embodiment of the present invention. The health of the error signal transfer path cannot be tested.

  As described above, according to the embodiment of the present invention, the first parity calculation circuit 133a that calculates the parity bit of the data input to the register 131a and the parity bit of the data output from the register 131a are calculated. The second parity calculation circuit 136a compares the parity bit calculated by the first parity calculation circuit 133a with the parity bit calculated by the second parity calculation circuit 136a, and outputs a parity error signal if both parity bits are different from each other. And an EXOR circuit 137a that further inverts the parity bit calculated by the first parity calculation circuit 133a based on the parity error signal generation command. It can be issued.

  In the above description, the case where the present invention is applied to an ECU for an automobile has been described as an example. However, the embodiment of the present invention is not limited to an ECU for an automobile, and a parity for performing a parity check of the register and the register. The present invention can be applied to any electronic device provided with a check circuit.

1-6 ECU, 11 CPU, 12 ROM, 13a-13c IP core, 14 OR circuit, 121 control program, 131a-131c register, 132a-132c parity check circuit, 133a first parity calculation circuit, 134a EXOR circuit, 135a register 136a Second parity calculation circuit, 137a EXOR circuit, 138a Parity check circuit.

Claims (5)

A first parity calculation circuit for calculating a parity bit of data input to the register;
A second parity calculation circuit for calculating a parity bit of data output from the register;
A comparison circuit that compares the parity bit calculated by the first parity calculation circuit and the parity bit calculated by the second parity calculation circuit, and outputs a parity error signal when both parity bits are different from each other;
A parity check circuit comprising:
An inversion circuit that inverts the parity bit calculated by the first parity calculation circuit based on a command input from outside the own parity check circuit;
A parity check circuit characterized by the above.   The parity check circuit according to claim 1, wherein the inverting circuit is an EXOR circuit that receives the command and the parity bit calculated by the first parity calculation circuit. CPU,
Registers,
A first parity calculation circuit for calculating a parity bit of data input to the register; a second parity calculation circuit for calculating a parity bit of data output from the register; and a parity calculated by the first parity calculation circuit. A parity check circuit comprising: a comparison circuit that compares a bit with a parity bit calculated by the second parity calculation circuit and outputs a parity error signal when both parity bits are different from each other;
In a computer system comprising:
The parity check circuit includes:
An inversion circuit that inverts the parity bit calculated by the first parity calculation circuit based on a command input from the CPU;
A computer system characterized by that.   4. The CPU according to claim 3, wherein the CPU and the parity check circuit are connected via a bus, and the CPU inputs the generated command to the parity check circuit via the bus. Computer system.   The computer system according to claim 3, wherein the inverting circuit is an EXOR circuit that receives the command and the parity bit calculated by the first parity calculation circuit.

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