JP2011055098A - Amplifier circuit and receiving device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an amplifier circuit and a receiving device which are capable of obtaining high reception sensitivity against the change of a reception radio wave environment. <P>SOLUTION: The amplifier circuit includes: an input circuit which performs output to a first output end in the case of the intensity of an input signal being in a first state and performs output to a second output end in the case of the intensity of the input signal being in a second state higher than the first state; an inverting amplifier circuit which amplifies a signal output from the first output end and inverts its phase and then outputs the signal; a bypass circuit which attenuates and outputs a signal output from the second output end as it is; and an output circuit which outputs the output of the inverting amplifier circuit after phase inversion or in the same phase in the case of the first state and outputs the output of the bypass circuit in the same phase or after phase inversion in the case of the second state. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to an amplifier circuit and a receiving device.

In a radio receiver, a weak radio wave input from an antenna is amplified to increase reception sensitivity. However, if the input signal is too large, distortion components such as intermodulation generated in the amplifier circuit may increase, and the reception sensitivity may decrease.
Therefore, an amplifier circuit provided with a bypass circuit in parallel is used, and when the input signal strength is excessive, the bypass circuit is passed to avoid an increase in distortion components due to amplification. When the input signal strength is weak, the signal is passed through an amplifier circuit, and the reception sensitivity is increased by amplification with a low noise figure.

On the other hand, when the output signal amplified by the amplifier circuit and an output signal that has passed through the bypass circuit is a phase difference, if the output signal is switched by the change of the input signal strength, the discontinuous signal phases are output become. For example, when the amplifier circuit is an inverting amplifier circuit, the output signal has a phase difference of 180 degrees.
Therefore, when there is information in the phase of the signal, for example, when the phase modulation is performed, if this phase difference is large, a malfunction or a demodulation error may occur in the subsequent processing for receiving the output signal. For example, in the case of demodulating digital data such as digital broadcasting, there is a possibility that if the phase of the signal is inverted 180 degrees in the middle, the data may be demodulated into erroneous data.

  Therefore, there is also a proposal of an antenna amplifier that includes a phase adjustment circuit that matches the phases of the output signal of the amplifier circuit and the output signal of the bypass circuit, and suppresses signal level fluctuations that occur during switching differential (see, for example, Patent Document 1). .

JP 2007-281912 A

However, when the phase is detected by the output signal and the phase of the bypass circuit is matched by feedback control, the phase cannot be aligned accurately unless the feedback time is taken into consideration. In addition, the processing takes time and the circuit configuration becomes complicated.
The present invention provides an amplifier circuit and a receiving apparatus that can obtain good reception sensitivity with respect to changes in the reception radio wave environment.

  According to one aspect of the present invention, when the intensity of the input signal is in the first state, the signal is output to the first output terminal, and when the intensity of the input signal is in the second state that is larger than the first state. Is an input circuit that outputs to the second output terminal, an inverting amplifier circuit that amplifies the signal output from the first output terminal and inverts and outputs the signal, and a signal output from the second output terminal A bypass circuit that outputs the signal as it is or after being attenuated, and in the first state, the phase of the output of the inverting amplifier circuit is inverted or outputted in the same phase, and in the second state, the bypass circuit And an output circuit that outputs the output of the output with the same phase or the inverted phase.

  According to another aspect of the present invention, an amplification circuit, a frequency conversion circuit that frequency-converts an output signal of the amplification circuit and outputs an intermediate frequency signal, and an intermediate frequency amplification circuit that amplifies the intermediate frequency signal. And a demodulation circuit for demodulating the intermediate frequency signal.

  ADVANTAGE OF THE INVENTION According to this invention, the amplifier circuit and receiver which can obtain favorable receiving sensitivity with respect to the change of a received radio wave environment are provided.

It is a block diagram which illustrates the composition of the amplifier circuit concerning the embodiment of the present invention. FIG. 6 is a block diagram illustrating another configuration of the amplifier circuit according to the embodiment of the invention. FIG. 6 is a block diagram illustrating another configuration of the amplifier circuit according to the embodiment of the invention. FIG. 6 is a block diagram illustrating another configuration of the amplifier circuit according to the embodiment of the invention. FIG. 6 is a block diagram illustrating another configuration of the amplifier circuit according to the embodiment of the invention. FIG. 6 is a block diagram illustrating another configuration of the amplifier circuit according to the embodiment of the invention. FIG. 6 is a block diagram illustrating another configuration of the amplifier circuit according to the embodiment of the invention. FIG. 6 is a block diagram illustrating another configuration of the amplifier circuit according to the embodiment of the invention. FIG. 6 is a block diagram illustrating another configuration of the amplifier circuit according to the embodiment of the invention. FIG. 6 is a block diagram illustrating another configuration of the amplifier circuit according to the embodiment of the invention. FIG. 6 is a block diagram illustrating another configuration of the amplifier circuit according to the embodiment of the invention. It is a block diagram which illustrates the composition of the receiving device concerning the embodiment of the present invention.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
Note that, in the present specification and each drawing, the same elements as those described above with reference to the previous drawings are denoted by the same reference numerals, and detailed description thereof is omitted as appropriate.

FIG. 1 is a block diagram illustrating the configuration of an amplifier circuit according to an embodiment of the invention.
As shown in FIG. 1, the amplifier circuit 100 of this embodiment includes a bypass circuit 20, an inverting amplifier circuit 40, an output circuit 60, and an input circuit 90.

  The amplifier circuit 100 can be used when the received radio wave environment changes and the input signal strength from the receiving antenna changes. For example, it can be used when the reception point moves and the distance from the transmission antenna is different, or when the reception point is fixed and the radio wave environment changes.

  The input 51 of the amplifier circuit 100 is connected to the first input terminal 91 of the input circuit 90, and the first output terminal 93 and the second output terminal 92 of the input circuit 90 are respectively connected to the input terminal 41 of the inverting amplifier circuit 40. The input terminal 21 of the bypass circuit is connected.

  When the intensity of the input signal input from the outside to the first input terminal 91 is in the first state, the input circuit 90 outputs the input signal to the first output terminal 93, and the input signal intensity is When the second state is larger than the first state, the input signal is output to the second output terminal 92.

That is, in the first state, the input signal input to the first input end 91 is output to the first output end 93 as it is. At this time, an input signal may or may not be output to the second output end 92. As will be described later, since the signal of the second output end 92 is not transmitted to the subsequent stage in the first state, there is no problem with the state of the second output end 92.
In the second state, the input signal input to the first input terminal 91 is output to the second output terminal 92 as it is. At this time, an input signal may be output to the first output end 93 or may not be output. In the second state, the signal of the first output end 93 is not transmitted to the subsequent stage, so that the state of the first output end 93 is not a problem.

  Here, the first state is a case where the input signal is weak as will be described later, and a case where the reception sensitivity is enhanced by amplifying the input signal by the inverting amplifier circuit 40 having a low noise figure. The second state is a case where the input signal strength is larger than that in the first state, and the reception sensitivity is lowered when the inverting amplifier circuit 40 is passed through. The first state and the second state are switched by the output circuit 60 as will be described later.

  The output terminal 42 of the inverting amplifier circuit 40, the power supply input terminal 43, and the output terminal 22 of the bypass circuit 20 are each connected to the output circuit 60, and the output of the output circuit 60 becomes the output 52 of the amplifier circuit 100.

  The inverting amplifier circuit 40 inverts and amplifies the input signal input to the input terminal 41 with a gain of G times, and outputs the amplified signal to the output terminal. The inverting amplifier circuit 40 is constituted by, for example, a one-stage low noise amplifier circuit. Further, by supplying power to the power input terminal 43 or stopping the power supply, the output to the output terminal 42 can be turned on or off. The supply and stop of the power are switched by the output circuit 60.

  In the present embodiment, the inverting amplifier circuit 40 has a configuration having a power input terminal 43 that is switched to energization or stop by the output circuit 60. However, depending on the configuration of the output circuit 60, the power input terminal 43 may not be provided, and the inverting amplifier circuit 40 may be configured to always supply power.

  As described above, the input signal of the inverting amplifier circuit 40 is input from the external antenna via the input circuit 90 as described above. The input signal strength varies depending on the distance between the antenna and the transmitting antenna and the radio wave environment at the receiving point such as an obstacle. For this reason, the input signal changes depending on whether it is weak where amplification is necessary, amplification is unnecessary, or attenuation is necessary. Further, when the reception point moves, for example, while walking or by a vehicle such as an automobile or a railroad, the input signal strength changes with time.

  The bypass circuit 20 outputs the input signal input to the input terminal 21 via the input circuit 90 to the output terminal 22 as it is or after being attenuated. Then, it is output to the output circuit 60. Note that when the bypass circuit 20 is configured to attenuate the input signal, the gain of the bypass circuit 20 can be adjusted by the attenuation amount to optimize the radio wave environment at the reception point.

As described above, the output circuit 60 switches the output terminal 42 of the inverting amplifier circuit 40, the power supply input terminal 43, the output terminal 22 of the bypass circuit 20, and the input circuit 90.
The output circuit 60 has a case where the input signal strength is in the first state and a state where the input signal strength is greater than the first state.

  As described above, the first state is a case where the input signal is weak, and the reception sensitivity is increased by amplifying the input signal by the inverting amplifier circuit 40 having a low noise figure. The second state is a case where the input signal strength is larger than that in the first state, and the reception sensitivity is lowered when the inverting amplifier circuit 40 is passed through.

  That is, in the wireless receiver, in the first state where the input signal is weak, the reception sensitivity can be increased by amplifying the input signal by the low noise figure amplification circuit and then performing frequency conversion. For this reason, it is important to maintain the reception sensitivity to suppress distortion components such as intermodulation distortion generated in the amplifier circuit sufficiently low with respect to the desired signal.

  Incidentally, there are cases where a plurality of input signals are arranged close to each other on the frequency axis. For example, when a multi-channel signal such as a TV broadcast is received, another channel signal exists as an interference signal near the reception channel frequency of the desired signal. In such a case, a distortion component such as intermodulation distortion caused by a desired signal and an interference signal, or a plurality of interference signals may occur in the reception band of the desired signal, and is difficult to remove using a filter or the like. .

  Further, this distortion component is caused by the nonlinearity of the amplifier circuit, and is proportional to the product of the magnitudes of the respective input signals that cause it. For example, in the case of third-order distortion, it is proportional to the magnitude of the three signals that cause it, or the product of the square of one adjacent signal and the other signal, and proportional to the cube of the input signal strength. For this reason, when such an input signal is amplified, the distortion component increases more than the desired signal increment.

  For example, when the input signal is amplified twice, the desired signal strength is doubled, but the distortion component as an interference signal is eight times. Accordingly, when an excessive input signal is input to the amplifier circuit, the influence of distortion on the intensity of the desired signal becomes strong, and as a result, the reception sensitivity is lowered. That is, it is a 2nd state.

When the input signal strength is in the first state, the output circuit 60 outputs the output of the inverting amplifier circuit 40 with the phase inverted or in phase, and when in the second state, the output of the bypass circuit 20 is in phase. Alternatively, the phase is inverted and output.
Therefore, in the first state, the output of the bypass circuit 20 is not transmitted. In the second state, the output of the inverting amplifier circuit 40 is not transmitted.

The first state and the second state are output in the same phase.
Thus, in the amplifier circuit 100 of the present embodiment, the output signals in the first state and the second state are output so as to have the same phase. This is because if the phase of the output changes by 180 degrees due to the input signal strength, the following circuit that inputs and processes the output signal may be affected as follows.

  For example, when information is included in the phase of the input signal, a demodulation error may occur when demodulating in the subsequent stage. That is, a demodulation error occurs when the phase of the output signal of the amplifier circuit 100 changes by 180 degrees during the demodulation and changes between the first state and the second state. Further, when error correction is performed on erroneous demodulated data, it is discarded as error data, or an error propagates, leading to a decrease in reception sensitivity.

Further, in the amplifier circuit 100 illustrated in FIG. 1, the output circuit 60 illustrates a configuration including the first switch circuit S <b> 1 and the differential amplifier circuit 30.
The first switch circuit S1 outputs the output of the inverting amplifier circuit 40 or the output of the bypass circuit 20 to the third output terminal 11 or the fourth output terminal 12 without phase change. When the input signal strength is in the first state, the output of the inverting amplifier circuit 40 is output to the third output terminal 11, and when in the second state, the output of the bypass circuit 20 is output to the fourth output terminal 12. .

  That is, in the first state, a signal obtained by amplifying the input signal by the inverting amplifier circuit 40 is output to the third output terminal 11. At this time, the output of the bypass circuit 20 is not transmitted to the fourth output terminal 12. In the second state, the bypass circuit 20 outputs the input signal as it is or attenuated to the fourth output terminal 12. At this time, the output of the inverting amplifier circuit 40 is not transmitted to the third output terminal 11.

The output signal output to the third output terminal 11 in the first state and the output signal output to the fourth output terminal 12 in the second state have a phase difference of 180 degrees.
Therefore, the differential amplifier circuit 30 differentially amplifies the signals input to the inverting input terminal 31 and the non-inverting input terminal 32 and outputs the amplified signal to the output terminal 33. The output terminal 33 of the differential amplifier circuit 30 is connected to the output 52 of the amplifier circuit 100.
In the present embodiment, the third output terminal 11 and the fourth output terminal 12 are connected to the inverting input terminal 31 and the non-inverting input terminal 32 of the differential amplifier circuit 30, respectively. Accordingly, the differential amplifier circuit 30 differentially amplifies signals input from the fourth output terminal 12 and the third output terminal 11 respectively.

As described above, in the first state, the third output terminal 11 outputs an output signal that is 180 degrees out of phase with the input signal. At this time the fourth output terminal 12 has a direct current potential by the bias of the differential amplifier circuit 30. Therefore, the signal input to the inverting input terminal 31 is inverted and amplified and output to the output terminal 33 of the differential amplifier circuit 30.
In the second state, the fourth output terminal 12 outputs an output signal in phase with the input signal. In this case a third output terminal 11 has a direct current potential by the bias of the differential amplifier circuit 30. Therefore, the signal input to the non-inverting input terminal 32 is non-inverting amplified and output to the output terminal 33 of the differential amplifier circuit 30.
Therefore, the gain of the differential amplifier circuit 30 is inverted between the first state and the second state, and the phase of the output signal of the differential amplifier circuit 30 is the first state and the second state. And will not change.

  In the present embodiment, the third output terminal 11 and the fourth output terminal 12 are connected to the inverting input terminal 31 and the non-inverting input terminal 32 of the differential amplifier circuit 30, respectively. Therefore, the output signal of the differential amplifier circuit 30 is in phase with the input signal. However, the signals output to the third output terminal 11 and the fourth output terminal 12 only need to be differentially amplified, and the third output terminal 11 and the fourth output terminal 12 are respectively differentially amplified. The circuit 30 may be connected to the non-inverting input terminal 32 and the inverting input terminal 31. In this case, the output signal of the differential amplifier circuit 30 is 180 degrees out of phase with the input signal.

  As described above, the amplifier circuit 100 according to the present embodiment is an amplifier circuit including the bypass circuit 20 in parallel. That is, in the first state where the input signal strength is weak, the signal is passed through the inverting amplifier circuit 40, and the reception sensitivity is increased by amplification with a low noise figure. Further, in the second state where the input signal intensity is excessive, the bypass circuit 20 is allowed to pass, and an increase in distortion components due to amplification in the inverting amplifier circuit 40 is avoided. Therefore, it is possible to suppress a decrease in reception sensitivity due to a change in input signal strength.

  Furthermore, since the phase of the output signal of the amplifier circuit 100 does not change between the first state and the second state, the subsequent circuit that processes the output signal is not affected. The reception sensitivity can be maintained without the possibility of malfunction of the subsequent circuit, for example, demodulation error.

Further, in the amplifier circuit 100 of this embodiment, the first state and the second state are switched by feedforward depending on the input signal strength, so that the circuit configuration is simple and the switching time is fast.
According to the amplifier circuit 100 of this embodiment, it is possible to obtain good receiving sensitivity to changes in the received radio wave environment.

  In the present embodiment, the first state and the second state are switched by the first switch circuit S1 and the input circuit 90 according to the input signal strength. At the time of switching, the output signal may be interrupted, but it is considered that the influence on the subsequent processing is small.

  That is, when switching between the first state and the second state by the first switch circuit S1 and the input circuit 90, the output signal is interrupted, or the output of the inverting amplifier circuit 40 and the output of the bypass circuit 20 overlap. To do. However, a normal output signal is output in a short time and is output in phase with the original output signal. Therefore, for example, it is considered that the subsequent processing returns from the error state at the time of switching between the first state and the second state to the normal state in a short time.

  In the present embodiment, the bypass circuit 20 exemplifies a configuration in which the input signal is output as it is or after being attenuated in the second state. However, this second state may have a plurality of states further subdivided according to the input signal strength, for example, a 21st state, a 22nd state, and a 23rd state. For example, the bypass circuit 20 outputs the input signal as it is in the 21st state, and attenuates the input signal with attenuation amounts A and B (A <B) in the 22nd state and the 23rd state, respectively. It can also be set as the structure to make.

FIG. 2 is a block diagram illustrating another configuration of the amplifier circuit according to the embodiment of the invention.
As illustrated in FIG. 2, in the amplifier circuit 100a of the present embodiment, the configuration in which the first switch circuit S1a includes the first switching circuit S2 and the second switching circuit S3 is illustrated.
Except for the first switch circuit S1a, the amplifier circuit 100 is the same as that shown in FIG.

The first switching circuit S2 outputs the output of the inverting amplifier circuit 40 to the fifth output terminal 13 in the first state, and outputs the output of the bypass circuit 20 to the fifth output terminal in the second state. 13 is output.
The second switching circuit S3 connects the fifth output terminal 13 to the third output terminal 11 when in the first state, and connects the fifth output terminal 13 to the fourth output when in the second state. Is connected to the output terminal 12.

Therefore, in the amplifier circuit 100a, when the input signal is in the weak first state, the input signal is amplified by the inverting amplifier circuit 40 and output to the fifth output terminal 13 and the third output terminal 11. Then, it is differentially amplified by the differential amplifier circuit 30 and output.
In the second state, the input signal is output as it is or attenuated by the bypass circuit 20 to the fifth output terminal 13 and the fourth output terminal 12. Then, it is differentially amplified and output by the differential amplifier circuit 30.

Furthermore, since the phase of the output signal of the differential amplifier circuit 30 does not change between the first state and the second state, it does not affect the subsequent circuit that processes the output signal.
According to the amplifier circuit 100a of the present embodiment, good reception sensitivity can be obtained with respect to changes in the reception radio wave environment.
Further, by providing the fifth output terminal 13 as an intermediate point and using the second switching circuit S3, the configuration of the first switch circuit S1 is simplified.

  Note that the second switching circuit S3 can be configured by a switch using an NMOS transistor, a PMOS transistor, a diode, or the like. That is, the NMOS transistor and the PMOS transistor can be configured as a switch that can be turned on / off by applying a switching signal to the gate. Further, the diode can be configured as a switch that can be turned on / off by applying a switching signal to the anode. Further, the first switch circuit S1a switches the first switching circuit S2 and the second switching circuit S3 to the first state or the second state by this switching signal.

Figure 3 is a block diagram illustrating another configuration of the amplifier circuit according to the embodiment of the present invention.
As shown in FIG. 3, the amplifier circuit 100b of this embodiment, the output circuit 60a of the amplification circuit 100a represented in FIG. 2, an input circuit 90, respectively output circuit 60b, and is configured by replacing the input circuit 90a Yes. Further, the output circuit 60b has a configuration in which the first switching circuit S2 of the output circuit 60 is replaced with the first switching circuit S2a.

  The input circuit 90 a has a configuration in which a first input terminal 91 is connected to first and second output terminals 93 and 92, and the first and second output terminals 93 and 92 have a first The input signal input to the input terminal 91 is always output in the first and second states. In the present embodiment, the case where the input circuit 90a is used is illustrated, but the input circuit 90 can also be used.

  The first switching circuit S2a includes a switch element S4 and a second switch element S5. Further, in the first switching circuit S <b> 2 a, the fifth output terminal 13 is connected to the output terminal 42 of the inverting amplifier circuit 40.

The switch element S4 is connected to the output terminal 22 and the fifth output terminal 13 of the bypass circuit 20, and is turned off in the first state and turned on in the second state.
The second switch element S5 is connected to the power supply input terminal 43 of the inverting amplifier circuit 40 and the power supply VDD. Then, it is turned on in the first state to supply power to the inverting amplifier circuit 40, and is turned off in the second state to stop supplying power to the inverting amplifier circuit 40.

In the amplifier circuit 100b, as in the amplifier circuit 100a, in the first state, the input signal is amplified by the inverting amplifier circuit 40 and output to the fifth output terminal 13 and the third output terminal 11. Then, the signal is differentially amplified by the differential amplifier circuit 30 and output.
In the second state, the input signal is output to the fifth output terminal 13 and the fourth output terminal 12 as it is or after being attenuated by the bypass circuit 20. Then, it is differentially amplified and output by the differential amplifier circuit 30.

Furthermore, since the phase of the output signal of the differential amplifier circuit 30 does not change between the first state and the second state, it does not affect the subsequent circuit that processes the output signal.
According to the amplifier circuit 100b of the present embodiment, good reception sensitivity can be obtained with respect to changes in the reception radio wave environment.

In the amplifier circuit 100b, when the input signal is in the second state passing through the bypass circuit 20, switching is performed so that the power supply to the inverting amplifier circuit 40 is stopped, so that power saving can be achieved.
Further, the switch element S4 and the second switch element S5 can be configured by switches using NMOS transistors, PMOS transistors, diodes, or the like.

Figure 4 is a block diagram illustrating another configuration of the amplifier circuit according to the embodiment of the present invention.
As shown in FIG. 4, the amplifier circuit 100c of the present embodiment has a configuration in which the output circuit 60b of the amplifier circuit 100b shown in FIG. 3 is replaced with an output circuit 60c. The output circuit 60c has a configuration in which the first switching circuit S2a of the output circuit 60b is replaced with the first switching circuit S2b.
The first switching circuit S2b includes a second switch element S5 and a switch element S6.

The second switch element S5 is the same as the second switch element S5 shown in FIG. 3, and supplies power to the inverting amplifier circuit 40 in the first state, and supplies power in the second state. Stop.
The switch element S6 connects the fifth output terminal 13 to the output terminal 42 of the inverting amplifier circuit 40 in the first state, and connects the fifth output terminal 13 to the bypass circuit 20 in the second state. Is connected to the output terminal 22.

In the amplifier circuit 100c, as in the amplifier circuit 100b, in the first state, the input signal is amplified by the inverting amplifier circuit 40 and output to the fifth output terminal 13 and the third output terminal 11. Then, the signal is differentially amplified by the differential amplifier circuit 30 and output.
In the second state, the input signal is output to the fifth output terminal 13 and the fourth output terminal 12 as it is or after being attenuated by the bypass circuit 20. Then, it is differentially amplified and output by the differential amplifier circuit 30.

Furthermore, since the phase of the output signal of the differential amplifier circuit 30 does not change between the first state and the second state, it does not affect the subsequent circuit that processes the output signal.
According to the amplifier circuit 100c of the present embodiment, it is possible to obtain good reception sensitivity against changes in the reception radio wave environment.

In the amplifier circuit 100c of the present embodiment, the first switching circuit S2b is illustrated as having a second switch element S5. Therefore, when the input signal is in the second state passing through the bypass circuit 20, switching is performed so as to stop the power supply of the inverting amplifier circuit 40, so that power saving can be achieved. However, the second switch element S5 may not be provided. Further, the inverting amplifier circuit 40 does not have the power input terminal 43 that is switched to energization or stop by the first switch circuit S1c, and may be configured to always supply power.
As described above, the amplifier circuit 100c can be configured not to switch the power supply of the inverting amplifier circuit 40 by using the switch element S6.
The switch element S6 can be configured by a switch using an NMOS transistor, a PMOS transistor, a diode, or the like.

Figure 5 is a block diagram illustrating another configuration of the amplifier circuit according to the embodiment of the present invention.
As shown in FIG. 5, the amplifier circuit 100 d of this embodiment is different from the amplifier circuit 100 shown in FIG. 1 in that the second switch circuit S <b> 7 is further provided. That is, the output circuit 60d has a configuration in which the second switch circuit S7 is added to the output circuit 60.

  The second switch circuit S7 fixes the fourth output terminal 12 to the reference potential in the first state, and fixes the third output terminal 11 to the reference potential in the second state. In this embodiment, a configuration in which the reference potential is fixed to the ground potential is illustrated.

As described with reference to FIG. 1, in the first state, an output signal that is 180 degrees out of phase with the input signal is output to the third output terminal 11. At this time the fourth output terminal 12 has a direct current potential by the bias of the differential amplifier circuit 30.
In the second state, the fourth output terminal 12 outputs an output signal in phase with the input signal. In this case a third output terminal 11 has a direct current potential by the bias of the differential amplifier circuit 30.

Therefore, in this embodiment, the second switch circuit S7, the fourth output terminal 12 which signal when the first state is not output, the third output signal when the second state is not output 11 Are fixed to the ground potential as a reference potential.
According to the amplifier circuit 100d of the present embodiment, good reception sensitivity can be obtained with respect to changes in the reception radio wave environment.
Further, according to the amplifier circuit 100d, it is possible to reduce fluctuations in the DC potential between the first state and the second state. That is, by fixing the third or fourth output terminals 11 and 12 to which no signal is output to the reference potential, fluctuations in the DC potential at the input and output of the differential amplifier circuit 30 are reduced.

  In addition, the configuration of the first switch circuit S1 can be simplified, and the number of switch elements required for the configuration can be reduced to reduce the loss of the input signal. Further, by setting the third output terminal 11 or the fourth output terminal 12 as the reference potential by the second switch circuit S7, one of the inverting input terminal 31 and the non-inverting input terminal 32 of the differential amplifier circuit 30 is floated. The output phase can be stabilized by fixing the potential so as not to be in a state.

Figure 6 is a block diagram illustrating another configuration of the amplifier circuit according to the embodiment of the present invention.
As shown in FIG. 6, in the amplifier circuit 100e of the present embodiment, the first switch circuit S1e of the output circuit 60e includes the first switch element S8 and the second switch element S5, and the input circuit 90a The structure using is illustrated.

The input circuit 90a is the same as the amplifier circuit 100b shown in FIG. In other words, the first input end 91 is connected to the first and second output ends 93 and 92. The first and second output terminals 93 and 92 always output the input signal input to the first input terminal 91 in the first and second states. In the present embodiment, the case where the input circuit 90a is used is illustrated, but the input circuit 90 can also be used.
Further, the components other than the input circuit 90a and the first switch circuit S1e are the same as those of the amplifier circuit 100d shown in FIG.

  The second switch element S5 is the same as the second switch element S5 in the amplifier circuit 100b shown in FIG. 3, and is connected to the power supply input terminal 43 of the inverting amplifier circuit 40 and the power supply VDD. Then, it is turned on in the first state to supply power to the inverting amplifier circuit 40, and is turned off in the second state to stop supplying power to the inverting amplifier circuit 40.

The first switch element S8 is connected to the output terminal 22 and the fourth output terminal 12 of the bypass circuit 20, and is turned off in the first state and turned on in the second state.
Further, in the first switch circuit S1e, the output terminal 42 of the inverting amplifier circuit 40 is connected to the third output terminal 11.

  In the amplifier circuit 100e, when the second switch element S5 is turned on in the first state, the input signal is amplified by the inverting amplifier circuit 40 and output to the third output terminal 11. Further, the first switch element S8 is turned off, and the fourth output terminal 12 becomes the ground potential by the second switch circuit S7. Therefore, the output of the third output terminal 11 is differentially amplified by the differential amplifier circuit 30 and output.

  In the second state, when the first switch element S8 is turned on, the input signal is output as it is or attenuated by the bypass circuit 20 to the fourth output terminal 12. Further, the second switch element S5 is turned off, and the third output terminal 11 becomes the ground potential by the second switch circuit S7. Therefore, the output of the fourth output terminal 12 is differentially amplified by the differential amplifier circuit 30 and output.

Furthermore, since the phase of the output signal of the differential amplifier circuit 30 does not change between the first state and the second state, it does not affect the subsequent circuit that processes the output signal.
According to the amplifier circuit 100e of the present embodiment, good reception sensitivity can be obtained with respect to changes in the reception radio wave environment.

  Further, according to the amplifier circuit 100e of the present embodiment, the number of switch elements through which the output of the inverting amplifier circuit 40 and the output of the bypass circuit 20 pass can be reduced in the first switch circuit S1e. Therefore, signal loss between the inverting amplifier circuit 40 and the third output terminal 11 and between the bypass circuit 20 and the fourth output terminal 12 can be reduced.

Further, the output level of the bypass circuit 20 is increased by reducing the loss between the bypass circuit 20 and the fourth output terminal 12. Therefore, the level range of the input signal that does not need to be amplified by the inverting amplifier circuit 40 is increased, and the range of the input signal intensity that passes through the bypass circuit 20, that is, the second state is expanded. Further power saving can be achieved by stopping the power supply of the inverting amplifier circuit 40.
The first switch element S8 can be configured by a switch using an NMOS transistor, a PMOS transistor, a diode, or the like.

Figure 7 is a block diagram illustrating another configuration of the amplifier circuit according to the embodiment of the present invention.
As shown in FIG. 7, in the amplifier circuit 100f of the present embodiment, the first switch circuit S1f of the output circuit 60f includes the second switch element S5, the first switch element S8, and the third switch element S9. The structure which has is illustrated.
The points other than the first switch circuit S1f are the same as those of the amplifier circuit 100e shown in FIG.

Further, the first switch element S8 and the second switch element S5 are the same as the first switch circuit S1e in the amplifier circuit 100e shown in FIG.
The third switch element S9 is connected to the output terminal 42 and the third output terminal 11 of the inverting amplifier circuit 40, and is turned on in the first state and turned off in the second state.

  In the amplifier circuit 100f, when the second switch element S5 and the third switch element S9 are turned on in the first state, the input signal is amplified by the inverting amplifier circuit 40 and is supplied to the third output terminal 11. Is output. Further, the first switch element S8 is turned off, and the fourth output terminal 12 becomes the ground potential by the second switch circuit S7. Therefore, the output of the third output terminal 11 is differentially amplified by the differential amplifier circuit 30 and output.

  In the second state, when the first switch element S8 is turned on, the input signal is output as it is or attenuated by the bypass circuit 20 to the fourth output terminal 12. Further, the third switch element S9 is turned off, and the third output terminal 11 becomes the ground potential by the second switch circuit S7. Therefore, the output of the fourth output terminal 12 is differentially amplified by the differential amplifier circuit 30 and output. In the second state, the second switch element S5 may be either on or off.

Furthermore, since the phase of the output signal of the differential amplifier circuit 30 does not change between the first state and the second state, it does not affect the subsequent circuit that processes the output signal.
According to the amplifier circuit 100f of the present embodiment, it is possible to obtain good reception sensitivity against changes in the reception radio wave environment.

  Further, according to the amplifier circuit 100f of the present embodiment, the number of switch elements through which the output of the inverting amplifier circuit 40 and the output of the bypass circuit 20 pass can be reduced in the first switch circuit S1f. Therefore, signal loss between the inverting amplifier circuit 40 and the third output terminal 11 and between the bypass circuit 20 and the fourth output terminal 12 can be reduced.

Further, the output level of the bypass circuit 20 is increased by reducing the loss between the bypass circuit 20 and the fourth output terminal 12. Therefore, the level range of the input signal that does not need to be amplified by the inverting amplifier circuit 40 is increased, and the range of the input signal intensity that passes through the bypass circuit 20, that is, the second state is expanded.
Note that further power saving can be achieved by stopping the power supply to the inverting amplifier circuit 40.
The third switch element S9 can be configured by a switch using an NMOS transistor, a PMOS transistor, a diode, or the like.

In the present embodiment, the case where the first switch circuit S1f includes the second switch element S5 is illustrated. However, the second switch element S5 may not be provided, and the power input terminal 43 of the inverting amplifier circuit 40 may be connected to the power supply VDD so as to always supply power.
Thus, according to the amplifier circuit 100f, the power supply of the inverting amplifier circuit 40 can be configured not to be switched.

Figure 8 is a block diagram illustrating another configuration of the amplifier circuit according to the embodiment of the present invention.
As shown in FIG. 8, the amplifier circuit 100g of the present embodiment has a configuration in which the output circuit 60d shown in FIG. 5 is replaced with an output circuit 60g. The output circuit 60g has a configuration in which the second switch circuit S7 of the output circuit 60d is replaced with a second switch circuit S7a.
The second switch circuit S7a includes switch elements S10 and S11.

The switch element S10 is connected to the third output terminal 11 and the ground, and is turned off in the first state and turned on in the second state.
The switch element S11 is connected to the fourth output terminal 12 and the ground, and is turned on in the first state and turned off in the second state.

  In the amplifier circuit 100g, in the first state, the input signal is amplified by the inverting amplifier circuit 40 via the input circuit 90 and output to the third output terminal 11. Further, when the switch element S10 is turned off and the switch element S11 is turned on, the fourth output terminal 12 becomes the ground potential. Therefore, the output of the third output terminal 11 is differentially amplified by the differential amplifier circuit 30 and output.

  In the second state, the input signal is output from the first switch circuit S 1 to the fourth output terminal 12 as it is or attenuated by the bypass circuit 20 via the input circuit 90. Further, when the switch element S11 is turned off and the switch element S10 is turned on, the third output terminal 11 becomes the ground potential. Therefore, the output of the fourth output terminal 12 is differentially amplified by the differential amplifier circuit 30 and output.

Furthermore, since the phase of the output signal of the differential amplifier circuit 30 does not change between the first state and the second state, it does not affect the subsequent circuit that processes the output signal.
According to the amplifier circuit 100g of the present embodiment, it is possible to obtain good reception sensitivity with respect to changes in the reception radio wave environment.

  Further, according to the amplifier circuit 100g of this embodiment, in the first switch circuit S1, it is possible to reduce the number of switch elements through which the output of the inverting amplifier circuit 40 and the output of the bypass circuit 20 respectively pass, and the signal loss. Can be reduced.

Further, the output level of the bypass circuit 20 is increased by reducing the number of switch elements through which the output of the bypass circuit 20 passes. Therefore, the level range of the input signal that does not need to be amplified by the inverting amplifier circuit 40 is increased, and the range of the input signal intensity that passes through the bypass circuit 20, that is, the second state is expanded. Further power saving can be achieved by stopping the power supply of the inverting amplifier circuit 40.
In the amplifier circuit 100g, the switch elements S10 and S11 can be configured by switches using NMOS transistors, PMOS transistors, diodes, or the like.

Figure 9 is a block diagram illustrating another configuration of the amplifier circuit according to the embodiment of the present invention.
As shown in FIG. 9, the amplifier circuit 100h of the present embodiment has a configuration in which the output circuit 60d shown in FIG. 5 is replaced with an output circuit 60h. The output circuit 60h has a configuration in which the second switch circuit S7 of the output circuit 60d is replaced with a second switch circuit S7b.
The second switch circuit S7b connects the ground to the fourth output terminal 12 when in the first state, and connects the ground to the third output terminal 11 when in the second state.

  When the amplifier circuit 100 h is in the first state, the input signal is amplified by the inverting amplifier circuit 40 via the input circuit 90 and output to the third output terminal 11. Further, the fourth output terminal 12 becomes the ground potential by the second switch circuit S7b. Therefore, the output of the third output terminal 11 is differentially amplified by the differential amplifier circuit 30 and output.

  In the second state, the input signal is output from the first switch circuit S 1 to the fourth output terminal 12 as it is or attenuated by the bypass circuit 20 via the input circuit 90. Further, the third output terminal 11 becomes the ground potential by the second switch circuit S7b. Therefore, the output of the fourth output terminal 12 is differentially amplified by the differential amplifier circuit 30 and output.

Furthermore, since the phase of the output signal of the differential amplifier circuit 30 does not change between the first state and the second state, it does not affect the subsequent circuit that processes the output signal.
According to the amplifier circuit 100h of the present embodiment, it is possible to obtain good reception sensitivity with respect to changes in the reception radio wave environment.

  Further, according to the amplifier circuit 100h of the present embodiment, in the first switch circuit S1, the number of switches through which the output of the inverting amplifier circuit 40 and the output of the bypass circuit 20 pass can be reduced, thereby reducing the signal loss. Similar to the amplifier circuit 100g, it can be reduced.

Further, the output level of the bypass circuit 20 is increased by reducing the number of switch elements through which the output of the bypass circuit 20 passes. Therefore, the level range of the input signal that does not need to be amplified by the inverting amplifier circuit 40 is increased, and the range of the input signal intensity that passes through the bypass circuit 20, that is, the second state is expanded. Further, power saving can be further achieved by stopping the power supply of the inverting amplifier circuit 40.
In the amplifier circuit 100h, the second switch circuit S7b can be configured by a switch using an NMOS transistor, a PMOS transistor, a diode, or the like.

Figure 10 is a block diagram illustrating another configuration of the amplifier circuit according to the embodiment of the present invention.
As illustrated in FIG. 10, the amplifier circuit 100 i of this embodiment includes the output circuit 60 a, the input circuit 90, and the bypass circuit 20 of the amplifier circuit 100 a illustrated in FIG. 2, and the output circuit 60 i, input circuit 90 b, and bypass circuit, respectively. The configuration is replaced with 20a. The output circuit 60i has a configuration in which the first switch circuit S1a of the output circuit 60a is replaced with the first switch circuit S1i.

The bypass circuit 20 a is a wiring circuit that connects the input terminal 21 and the output terminal 22 thereof. The input signal input to the input terminal 21 is output to the output terminal 22 as it is.
In the first state, the input circuit 90b connects the first input end 91 to the first output end 93 and opens the second output end 92. In the second state, the first input terminal 91 is connected to the second output terminal 92, and the first output terminal 93 is opened.

The first switch circuit S1i has a configuration in which the first switch circuit S2 in the first switch circuit S1a illustrated in FIG. 2 is replaced with a first switch circuit S2c.
The first switching circuit S2c has a second switch element S5. In the first switching circuit S2c, the fifth output terminal 13 is connected to the output terminal 21 of the bypass circuit 20a and the output terminal 42 of the inverting amplifier circuit 40, respectively.

  The second switch element S5 is the same as the second switch element S5 shown in FIG. That is, the second switch element S5 is connected to the power supply input terminal 43 of the inverting amplifier circuit 40 and the power supply VDD. Then, it is turned on in the first state to supply power to the inverting amplifier circuit 40, and is turned off in the second state to stop supplying power to the inverting amplifier circuit 40.

In the amplifier circuit 100i, as in the amplifier circuit 100a, in the first state, the input signal is amplified by the inverting amplifier circuit 40 via the input circuit 90b, and the fifth output terminal 13 and the third output terminal 11 are amplified. Is output. Then, the signal is differentially amplified by the differential amplifier circuit 30 and output.
In the second state, the input signal is directly output from the bypass circuit 20a via the input circuit 90b and output to the fifth output terminal 13 and the fourth output terminal 12. Then, it is differentially amplified and output by the differential amplifier circuit 30.

Furthermore, since the phase of the output signal of the differential amplifier circuit 30 does not change between the first state and the second state, it does not affect the subsequent circuit that processes the output signal.
According to the amplifier circuit 100i of the present embodiment, good reception sensitivity can be obtained with respect to changes in the reception radio wave environment.
Furthermore, the load connected to the input 51 of the amplifier circuit 100i can be reduced by using the input circuit 90b.

  In the amplifier circuit 100b, when the input signal is in the second state passing through the bypass circuit 20, switching is performed to stop the power supply of the inverting amplifier circuit 40, so that power saving can be achieved.

FIG. 11 is a block diagram illustrating another configuration of the amplifier circuit according to the embodiment of the invention.
As shown in FIG. 11, in the amplifier circuit 100j of the present embodiment, the output circuit 60d of the amplifier circuit 100d represented in FIG. 5, an input circuit 90, the bypass circuit 20, respectively output circuit 60j, an input circuit 90b, a bypass The configuration is replaced with the circuit 20a. The output circuit 60j has a configuration in which the first switch circuit S1 of the output circuit 60d is replaced with the first switch circuit S1j.

  The input circuit 90b and the bypass circuit 20a are the same as the amplifier circuit 100i shown in FIG. The first switch circuit S1j has a second switch element S5, the third output terminal 11 is the output terminal 42 of the inverting amplifier circuit 40, and the fourth output terminal 12 is the output terminal of the bypass circuit 20a. 22 are connected to each other.

  The second switch element S5 is the same as the second switch element S5 in the amplifier circuit 100b shown in FIG. 3, and is connected to the power supply input terminal 43 of the inverting amplifier circuit 40 and the power supply VDD. Then, it is turned on in the first state to supply power to the inverting amplifier circuit 40, and is turned off in the second state to stop supplying power to the inverting amplifier circuit 40.

  In the amplifier circuit 100j, when the second switch element S5 is turned on in the first state, the input signal is amplified by the inverting amplifier circuit 40 via the input circuit 90b and output to the third output terminal 11. The Further, the fourth output terminal 12 becomes the ground potential by the input circuit 90b and the second switch circuit S7. Therefore, the output of the third output terminal 11 is differentially amplified by the differential amplifier circuit 30 and output.

  In the second state, the input signal is output as it is to the fourth output terminal 12 by the input circuit 90 b and the bypass circuit 20. Further, the second switch element S5 is turned off, and the third output terminal 11 becomes the ground potential by the second switch circuit S7. Therefore, the output of the fourth output terminal 12 is differentially amplified by the differential amplifier circuit 30 and output.

Furthermore, since the phase of the output signal of the differential amplifier circuit 30 does not change between the first state and the second state, it does not affect the subsequent circuit that processes the output signal.
According to the amplifier circuit 100j of the present embodiment, good reception sensitivity can be obtained with respect to changes in the reception radio wave environment.

  Further, according to the amplifier circuit 100j of the present embodiment, in the first switch circuit S1j, it is possible to reduce the number of switch elements through which the signals passing through the inverting amplifier circuit 40 and the bypass circuit 20a pass, respectively. Can be reduced.

  Further, the output level of the bypass circuit 20 is increased by reducing the number of switch elements through which the signal passing through the bypass circuit 20 passes. Therefore, the level range of the input signal that does not need to be amplified by the inverting amplifier circuit 40 is increased, and the range of the input signal intensity that passes through the bypass circuit 20, that is, the second state is expanded. Further power saving can be achieved by stopping the power supply of the inverting amplifier circuit 40.

FIG. 12 is a block diagram illustrating the configuration of the receiving apparatus according to the embodiment of the invention.
As illustrated in FIG. 12, the receiving device 110 according to the present exemplary embodiment includes a bandpass filter 71, an amplifier circuit 100, a high frequency amplifier circuit 72, a frequency conversion circuit 73, an intermediate frequency amplifier circuit 74, and a demodulation circuit 75.

The input terminal 58 of the receiving apparatus 110 is connected to, for example, a receiving antenna, and a high frequency signal is input to the input terminal 58 from the outside.
The high-frequency signal is input to the bandpass filter 71, and unnecessary noise and interference signals are reduced by the bandpass filter 71 and input to the amplifier circuit 100. The output of the amplifier circuit 100 is input to the high frequency amplifier circuit 72.

  As described above, the amplifier circuit 100 amplifies the input signal according to the input signal strength, or outputs the input signal to the output 52 of the amplifier circuit 100 as it is or after attenuation. For this reason, the signal intensity of the high-frequency amplifier circuit 72 in the subsequent stage can be within an appropriate range, and good reception sensitivity can be obtained with respect to changes in the reception radio wave environment.

  In this embodiment, the configuration including the band-pass filter 71 is illustrated, but a filter having other characteristics can be used according to the frequency of the desired signal and the frequency of the interference signal or noise. For example, a trap for removing an interference signal or a high-pass filter may be used. Further, the high frequency signal input to the input terminal 58 of the receiving apparatus 110 may be input to the amplifier circuit 100 as it is without using the band pass filter 71.

The high frequency amplifier circuit 72 selectively amplifies the desired signal and outputs it to the frequency conversion circuit 73.
The frequency conversion circuit 73 includes a frequency mixing circuit 76, a local oscillation circuit 77, and a phase synchronization circuit 78. The frequency conversion circuit 73 converts the input high frequency signal into an intermediate frequency signal and outputs the intermediate frequency signal to the intermediate frequency amplification circuit 74.

  The frequency mixing circuit 76 inputs the high frequency signal and the output of the local oscillation circuit 77 and outputs an intermediate frequency signal. The phase synchronization circuit 78 sets the oscillation frequency of the local oscillation circuit 77 and selects a desired signal to be received.

Intermediate frequency signal is selected by the intermediate frequency amplifying circuit 74, is amplified and output to the demodulation circuit 75.
The demodulation circuit 75 demodulates the intermediate frequency signal. For example, when the high-frequency signal input from the outside is a television broadcast signal, the demodulation circuit 75 outputs a video signal and an audio signal.

  In the present embodiment, the configuration including the high frequency amplifier circuit 72 is illustrated, but the configuration may be omitted, and the frequency conversion circuit 73 may selectively amplify the desired signal and perform frequency conversion.

  The high frequency signal input to the receiving device 110 is input from an external antenna, for example. The input signal strength varies depending on the distance between the antenna and the transmitting antenna and the radio wave environment at the receiving point such as an obstacle. For this reason, the input high-frequency signal changes depending on whether it is weak where amplification is necessary, amplification is unnecessary, or attenuation is necessary. Further, when the reception point moves, for example, while walking or by a vehicle such as an automobile or a railroad, the input signal strength changes with time.

  In response to such a change in the received radio wave environment, the amplifier circuit 100 passes the bypass circuit 20 in the second state where the input signal strength is excessive, and the distortion component due to amplification by the inverting amplifier circuit 40 is reduced. Avoid the increase. In the first state where the input signal strength is weak, the signal is passed through the amplifier circuit, and the reception sensitivity is increased by amplification with a low noise figure. Therefore, even if the input signal strength changes, there is no possibility that the reception sensitivity will decrease.

  Furthermore, since the phase of the output signal of the differential amplifier circuit 30 does not change between the first state and the second state, the subsequent circuit that processes the output signal is not affected. The reception sensitivity can be maintained without fear of malfunction of a circuit at the subsequent stage, for example, the demodulation circuit 75, for example, demodulation error.

Thus, according to the receiving apparatus 110 of the present embodiment, it is possible to obtain good reception sensitivity with respect to changes in the reception radio wave environment.
In the present embodiment, a configuration using the amplifier circuit 100 is illustrated, but amplifier circuits 100a to 100j can also be used.

The embodiments of the present invention have been described above with reference to specific examples. However, the present invention is not limited to these specific examples. For example, regarding the specific configuration of each element constituting the amplifier circuit and the receiving device, those skilled in the art can implement the present invention in a similar manner by appropriately selecting from a known range, and the same effect can be obtained. It is included in the scope of the present invention.
Moreover, what combined any two or more elements of each specific example in the technically possible range is also included in the scope of the present invention as long as the gist of the present invention is included.

In addition, all amplifier circuits and receivers that can be implemented by those skilled in the art based on the amplifier circuits and receivers described above as embodiments of the present invention are included in the present invention as long as they include the gist of the present invention. It belongs to the scope of the invention.
Other, within the spirit of the invention, those skilled in the art, which can conceive various modifications and should therefore be seen as within the scope of the present invention also such modifications and alterations .

DESCRIPTION OF SYMBOLS 11 3rd output terminal 12 4th output terminal 13 5th output terminal 20, 20a Bypass circuit 21, 41, 58, 91 Input terminal 22, 33, 42, 92, 93 Output terminal 30 Differential amplifier circuit 31 Inversion Input terminal 32 Non-inverting input terminal 40 Inverting amplifier circuit 43 Power supply input terminal 51 Input of amplifier circuit 52 Output of amplifier circuit 60, 60a to 60j Output circuit 71 Band pass filter 72 High frequency amplifier circuit 73 Frequency converter circuit 74 Intermediate frequency amplifier circuit 75 demodulation circuit 76 frequency mixing circuit 77 local oscillator 78 phase locked loop 90, 90a, 90b input circuit 91 first input 92 second output terminal 93 first output 100,100a~100j amplifier circuit 110 receiving apparatus S1 , S1a to S1j first switch circuit S2, S2a, S2b, S2c first switching circuit S3 first 2 switching circuit S4, S6, S10, S11 switch element S5 second switch element S7, S7a, S7b second switch circuit S8 first switch element S9 third switch element VDD power supply

Claims (7)

When the intensity of the input signal is in the first state, the signal is output to the first output terminal. When the intensity of the input signal is in the second state, which is greater than the first state, the signal is output to the second output terminal. An input circuit;
An inverting amplifier circuit that amplifies the signal output from the first output terminal and inverts and outputs the phase;
A bypass circuit that outputs the signal output from the second output terminal as it is or after being attenuated;
In the first state, the phase of the output of the inverting amplifier circuit is inverted or outputted in the same phase, and in the second state, the output of the bypass circuit is outputted with the phase or phase inverted. Circuit,
An amplifier circuit comprising: The output circuit is
In the first state, the output of the inverting amplifier circuit is output to the third output terminal in the same phase, and in the second state, the output of the bypass circuit is output to the fourth output terminal in the same phase. A first switch circuit;
A differential amplifier circuit that differentially amplifies and outputs signals respectively output from the third output terminal and the fourth output terminal;
The amplifier circuit according to claim 1, further comprising: The first switch circuit includes:
The output of the inverting amplifier circuit is output to the fifth output terminal in the first state, and the output of the bypass circuit is output to the fifth output terminal in the second state. A switching circuit;
In the first state, the fifth output terminal is connected to the third output terminal, and in the second state, the fifth output terminal is connected to the fourth output terminal. Two switching circuits;
The amplifier circuit according to claim 2, further comprising: A second switch circuit for fixing the fourth output terminal to a reference potential in the first state, and fixing the third output terminal to the reference potential in the second state; ,
3. The amplifier circuit according to claim 2, wherein fluctuations in direct current potential are reduced. The inverting amplifier circuit further includes a power input terminal to which power supply is energized or stopped by the first switch circuit,
The first switch circuit includes:
A first switch element connected to the output terminal and the fourth output terminal of the bypass circuit, which is turned off in the first state and turned on in the second state;
Connected to the power supply input terminal and a power supply, turned on in the first state to supply power to the inverting amplifier circuit, and turned off in the second state to supply power to the inverting amplifier circuit. A second switch element to stop;
Have
The third output terminal is connected to the output terminal of the inverting amplifier circuit;
The amplifier circuit according to claim 4, wherein a loss between the bypass circuit and the fourth output terminal is reduced. The first switch circuit includes:
A first switch element connected to the output terminal and the fourth output terminal of the bypass circuit, which is turned off in the first state and turned on in the second state;
A third switch element connected to the output terminal and the third output terminal of the inverting amplifier circuit, which is turned on in the first state and turned off in the second state;
Have
The amplifier circuit according to claim 4, wherein a loss between the bypass circuit and the fourth output terminal is reduced. An amplifier circuit according to any one of claims 1 to 6,
A frequency conversion circuit for converting an output signal of the amplification circuit to output an intermediate frequency signal;
An intermediate frequency amplification circuit for amplifying the intermediate frequency signal;
A demodulation circuit for demodulating the intermediate frequency signal;
A receiving apparatus comprising:

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