JP2011049880A - Delay circuit and semiconductor storage device with delay circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To set delay characteristics of a delay circuit according to variation of transistor characteristics. <P>SOLUTION: The delay circuit is equipped with: a bias circuit part 10 which includes a constant current source 12 and a MOS transistor 14 to which a gate and a drain are coupled and through which current of a constant current source flows, and outputs bias voltage from a node of a gate of the MOS transistor 14; and a delay part 20 which includes an inverter 26, a MOS transistor 21 into which a current path is serially inserted between an input node of the inverter and a reference potential node and to the gate of which the bias voltage is supplied, a MOS transistor 22 to the gate of which an input signal IN is supplied, capacity 25 which is inserted between the input node of the inverter and the reference potential node, and a MOS transistor 23 into which the current path is inserted between the power potential node and the input node of the inverter and to the gate of which an input signal is supplied, and outputs a signal from an output node of the inverter. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a delay circuit and a semiconductor memory device including the delay circuit, and more particularly, to a delay circuit used for timing adjustment by delaying a clock signal generated internally based on an external signal.

  The demand for NAND flash memory, which is one of semiconductor storage devices, has been increasing rapidly with an increase in applications for handling large volumes of data such as images and moving pictures in mobile devices. A flash memory can store more data with a small chip area by adopting a multi-value technology capable of storing data of 2 bits or more in one memory cell.

  When manufacturing NAND flash memory, it becomes very difficult to optimize the improvement of memory cell characteristics due to deterioration of memory cell characteristics accompanying miniaturization, and it becomes necessary to change the manufacturing process after design, or design There may be variations in later manufacturing processes. Transistor characteristics and resistance values are modeled from device simulation and prototype measurement results, but are affected by changes in manufacturing processes and variations. In particular, in order to achieve high throughput in data input / output with the outside, detailed timing adjustment is performed inside the chip at the time of design.

  Conventionally, in order to perform such timing adjustment, an inverter chain and a delay circuit configured using resistors and capacitors are provided inside the chip. However, as transistor characteristics and resistance values in memory cells change as miniaturization progresses, an error occurs between the design value of the delay time of the delay circuit and the delay timing in the actual chip, and the desired throughput is reduced. It can no longer be obtained.

  According to Patent Document 1, a ramp voltage is generated by charging a capacitor with a MOS field effect transistor current source or discharging an accumulated charge according to the state of a digital signal, and until the ramp voltage reaches a threshold value. A delay circuit for setting a delay time using time is disclosed.

JP-A-3-109812

  The present invention has been made in consideration of the above-described circumstances, and an object of the present invention is to provide a delay characteristic capable of setting a delay characteristic in accordance with variations in transistor characteristics, thereby realizing data input / output in a semiconductor memory device at a high throughput. A semiconductor memory device including a circuit and a delay circuit is provided.

  A delay circuit according to an embodiment of the present invention includes a constant current source, a first MOS transistor in which a gate and a drain are coupled, and a current of the constant current source flows in a current path between the source and the drain. A bias circuit unit for outputting a bias voltage from the node of the gate of the first MOS transistor, a current path between the gate circuit and the source and drain are inserted in series between the input node of the gate circuit and the reference potential node. A capacitor inserted between the second MOS transistor to which the bias voltage is supplied to the gate and the third MOS transistor to which the input signal is supplied to the gate, and the input node of the gate circuit and the node of the reference potential And a current path between the source and drain is inserted between the power supply potential node and the input node of the gate circuit, and the input signal is applied to the gate. And a sheet is the fourth MOS transistor is, and a delay unit for outputting a signal from the output node of the gate circuit.

  A semiconductor memory device according to an embodiment of the present invention is generated by a memory circuit, a clock signal generation circuit that generates an internal clock signal based on an enable control signal input from the outside, and the clock signal generation circuit. A delay circuit that delays the clock signal, and a control circuit that operates in synchronization with the clock signal delayed by the delay circuit and controls a data read operation from the memory circuit and a data write operation to the memory circuit. The delay circuit includes a constant current source, a first MOS transistor in which a gate and a drain are coupled, and a current of the constant current source flows in a current path between the source and the drain. The bias circuit that outputs the bias voltage from the gate node, the gate circuit, and the current path between the source and drain A second MOS transistor which is inserted in series between an input node of the gate circuit and a reference potential node, the bias voltage is supplied to the gate, a third MOS transistor where the input signal is supplied to the gate, and the gate A capacitor inserted between the input node of the circuit and the node of the reference potential, and a current path between the source and drain are inserted between the power supply potential node and the input node of the gate circuit, and the input signal is applied to the gate. And a fourth MOS transistor to be supplied, and a delay unit that outputs a signal from the output node of the gate circuit.

  According to the present invention, it is possible to provide a delay circuit that can set delay characteristics according to variations in transistor characteristics, and thus can realize data input / output in the semiconductor memory device with high throughput, and a semiconductor memory device including the delay circuit. it can.

FIG. 2 is a circuit diagram showing a configuration of a delay circuit according to the first embodiment. FIG. 2 is a timing waveform diagram illustrating an example of the operation of the delay circuit in FIG. 1. The block diagram which shows the structure of the delay circuit which concerns on the modification of 1st Embodiment. A circuit diagram showing composition of a delay circuit concerning a 2nd embodiment. A circuit diagram showing composition of a delay circuit concerning a 3rd embodiment. A circuit diagram showing composition of a delay circuit concerning a 4th embodiment. 1 is a plan view of a semiconductor memory device according to a first embodiment. FIG. 8 is a block diagram showing a part of a circuit extracted from the semiconductor memory device of FIG. 7.

  The present invention will be described below with reference to the drawings. Note that in various embodiments, corresponding portions in the drawings are denoted by the same reference numerals, and redundant description is omitted.

(Delay Circuit of First Embodiment)
FIG. 1 is a circuit diagram showing a configuration of a delay circuit according to the first embodiment. The delay circuit according to this embodiment includes a bias circuit unit 10 and a delay unit 20.

  The bias circuit section 10 includes a switching P-channel MOS transistor 11, a constant current source 12, a resistor 13, and an N-channel MOS transistor 14. The source of the MOS transistor 11 is connected to the node of the power supply potential VDD. A switch control signal / SW is supplied to the gate of the MOS transistor 11. The constant current source 12 is connected between the drain of the MOS transistor 11 and one end of the resistor 13. The other end of the resistor 13 is connected to the drain of the MOS transistor 14. The gate of the MOS transistor 14 is connected to a common connection node of the constant current source 12 and the resistor 13. The source of the MOS transistor 14 is connected to the reference potential node. That is, the bias circuit unit 10 includes a constant current source 12, a MOS transistor 14 whose gate and drain are coupled via a resistor 13, and the current of the constant current source 12 flows in a current path between the source and drain. The bias voltage Vbias is output from the node of the 14 gates.

  The delay unit 20 includes N-channel MOS transistors 21 and 22, a P-channel MOS transistor 23, a resistor 24, a capacitor 25, and an inverter 26. A resistor 24, a current path between the source and drain of the MOS transistor 21, and a current path between the source and drain of the MOS transistor 22 are inserted in series between the input node of the inverter 26 and the reference potential node. A bias voltage Vbias is supplied to the gate of the MOS transistor 21. An input signal IN is supplied to the gate of the MOS transistor 22. A capacitor 25 is inserted between the input node of the inverter 26 and the reference potential node. Further, a current path between the source and drain of the MOS transistor 23 is inserted between the input node of the inverter 26 and the node of the power supply potential VDD. The input signal IN is also supplied to the gate of the MOS transistor 23. Then, the signal OUT is output from the output node of the inverter 26. That is, the delay unit 20 includes an inverter 26, a MOS transistor 21 in which a current path between a source and a drain is inserted in series between an input node of the inverter 26 and a reference potential node, and a bias voltage Vbias is supplied to the gate. The MOS transistor 22 to which the input signal IN is supplied to the gate, the capacitor 25 inserted between the input node of the inverter 26 and the reference potential node, and the current path between the source and drain are input to the power supply potential node and the inverter 26. And a MOS transistor 23 inserted between the nodes and supplied with the input signal IN to the gate, and outputs a signal OUT from the output node of the inverter 26.

  Such a delay circuit is built in a semiconductor memory device, for example, a NAND flash memory provided with a memory cell transistor having a floating gate and a control gate. Therefore, when variations in transistor characteristics and resistance values occur in the chip after the NAND flash memory chip is manufactured, variations in transistor characteristics and resistance values also occur in the delay circuit of FIG. 1 accordingly. .

FIG. 2 is a timing waveform diagram showing an example of the operation of the delay circuit of FIG.
When the switch control signal / SW is at the low (“0”) level, the MOS transistor 11 is turned on, and the bias circuit unit 10 is controlled to be in the operating state. At this time, the bias voltage Vbias having a value corresponding to the current value of the constant current source 12, the value of the resistor 13, and the characteristics of the MOS transistor 14, for example, the driving capability of the transistor, such as a threshold value, is applied to the node of the gate of the MOS transistor 14. appear. When the switch control signal / SW is at a high (“1”) level, the MOS transistor 11 is turned off, the bias circuit unit 10 is controlled to the non-operating state, and the bias voltage Vbias is not generated.

  When the bias circuit section 10 is in an operating state and the input signal IN input to the delay section 20 is at a low level, the MOS transistor 23 is turned on and the input node of the inverter 26 is connected to the node A in FIG. Is charged to the high (“1”) level of the power supply potential VDD. At this time, the signal OUT output from the output node of the inverter 26 is at a low level.

  When the input signal IN changes to a high level, the MOS transistor 23 is turned off and the MOS transistor 22 is turned on. Since the bias voltage Vbias is supplied to the gate of the MOS transistor 21, the current path between the source and drain of the MOS transistor 21 has a value equal to the current flowing through the current path between the source and drain of the MOS transistor 14. Current flows. That is, since the charge previously charged in the capacitor 25 is started to be discharged by a constant current, the voltage at the node A decreases with a constant gradient as shown in the figure. When the voltage at the node A reaches the circuit threshold value (Vth) of the inverter 26, the signal OUT is inverted from the low level to the high level. Next, when the input signal IN changes to the low level again, the MOS transistor 23 is turned on, and the signal OUT is immediately inverted to the high level. That is, in the delay circuit of FIG. 1, the rising edge of the input signal IN is delayed by the time tdr and output as the signal OUT.

  Consider a case where both the resistors 13 and 24 are manufactured higher than the designed value. When the value of the resistor 13 increases, the voltage drop across the both ends increases, so that the value of the bias voltage Vbias becomes larger than the design value. Accordingly, the current flowing through the MOS transistor 21 in the delay unit 20 to which the bias voltage Vbias is supplied to the gate also increases. That is, in the delay unit 20, the current flowing through the MOS transistor 21 increases as the value of the resistor 24 increases. Therefore, when discharging from the capacitor 25, the voltage at the node A decreases with the same gradient as when the resistors 13 and 24 are manufactured so as to have the design values. As a result, fluctuations in the delay time tdr are suppressed.

  Contrary to the above, when both the resistors 13 and 24 are manufactured lower than the designed value, the value of the bias voltage Vbias becomes smaller as the value of the resistor 13 decreases, and thereby the current flowing through the MOS transistor 21 decreases. , Fluctuations associated with a decrease in the value of the resistor 24 are offset. As a result, fluctuations in the delay time tdr are suppressed.

  Next, consider the case where the characteristics of the MOS transistor, for example, the driving capability is manufactured lower than the design value. When the driving capability of the MOS transistor 14 becomes low, the constant current source 12 tries to flow the same current to the MOS transistor 14 as before, so that the value of the bias voltage Vbias becomes larger than the design value. That is, in the delay unit 20, the gate voltage is increased by the amount that the driving capability of the MOS transistor 21 is lowered. Therefore, the driving capability of the MOS transistors 14 and 21 becomes the design value of the current flowing through the MOS transistor 21. It is not different from the case where it is manufactured. As a result, fluctuations in the delay time tdr are suppressed.

  In contrast to the above, when the MOS transistor drive capability is manufactured higher than the design value, the bias voltage Vbias decreases as the drive capability of the MOS transistor 14 increases, and the drive capability of the MOS transistor 21 increases. Since the gate voltage is lowered by an amount corresponding thereto, fluctuations associated with an increase in the driving capability of the MOS transistor 21 are offset. As a result, fluctuations in the delay time tdr are suppressed.

  As described above, in the delay circuit of FIG. 1, even when there are variations in transistor characteristics and resistance values, fluctuations in the delay time tdr are suppressed.

(Delay circuit of a modification of the first embodiment)
FIG. 3 is a block diagram showing a configuration of a delay circuit according to a modification of the first embodiment. A number of delay circuits are arranged and formed on the chip in which the delay circuit is built. In such a case, if the bias circuit section 10 and the delay section 20 are arranged in a one-to-one correspondence, the number of elements increases and the chip area increases. Therefore, in this modification, one bias circuit unit 10 is arranged for the plurality of delay units 20 and the bias voltage Vbias output from the bias circuit unit 10 is supplied to the plurality of delay units 20 in parallel. Yes.

  With such a configuration, an increase in the number of elements can be prevented, an increase in chip area can be prevented, and current consumption can be reduced.

(Delay Circuit of Second Embodiment)
FIG. 4 is a circuit diagram showing a configuration of a delay circuit according to the second embodiment. The delay circuit according to this embodiment includes a bias circuit unit 10 and a delay unit 20a. The delay circuit according to this embodiment is different from that of the first embodiment shown in FIG. 1 in that a two-input NOR gate circuit 27 is provided instead of the inverter 26 in the delay unit 20a. Are connected to one input node of the NOR gate circuit 27, and an inverter 28 is added to invert the input signal IN and supply it to the other input node of the NOR gate circuit 27.

  In the delay circuit of FIG. 1, when the input signal IN changes from the high level to the low level, the P-channel MOS transistor 23 is turned on, and the node A is charged via the MOS transistor 23, whereby the output signal OUT is changed. Set to low level. In this case, since the capacitor 25 is connected to the node A, the rise of the voltage at the node A is delayed during charging, and the timing at which the output signal OUT is inverted to a low level may be delayed.

  In the delay circuit of FIG. 4, when the input signal IN changes from the high level to the low level, the signal of one input node of the NOR gate circuit 27 can be immediately set to the high level by the output signal of the inverter 28.

  That is, in the delay circuit of the present embodiment, in the same way as the delay circuit of FIG. 1, even when the transistor characteristics and the resistance value vary, the delay time tdr can be suppressed, and the output can be further reduced. It is also possible to improve the delay in timing at which the signal OUT is inverted to the low level.

  Also in this embodiment, as in the modification of FIG. 3, one bias circuit unit 10 is arranged for a plurality of delay units 20a, and the bias voltage Vbias output from the bias circuit unit 10 is set to a plurality of delays. You may deform | transform so that it may supply in parallel to the part 20a.

(Delay Circuit of Third Embodiment)
By the way, in the first and second embodiments and modifications, the delay circuit in which only the rising edge of the input signal IN is delayed and the falling edge is not delayed has been described. However, the present invention can also be implemented in a delay circuit that delays both the rising edge and falling edge of the input signal IN.

  FIG. 5 is a circuit diagram showing a configuration of a delay circuit according to the third embodiment that delays both the rising edge and the falling edge. The delay circuit according to this embodiment includes a bias circuit unit 30 and a delay unit 40.

  The bias circuit unit 30 includes a first bias output circuit 30a and a second bias output circuit 30b. The first bias output circuit 30a includes a switching P-channel MOS transistor 11, a constant current source 12, a resistor 13, and an N-channel MOS transistor 14, similar to that shown in FIG. The first bias voltage Vbias1 is output from the node of the gate.

  The second bias output circuit 30b has a configuration complementary to the first bias output circuit 30a, and has a configuration in which the connection of the power supply potential VDD and the reference potential is reversed from that of the first bias output circuit 30a. . That is, the second bias output circuit 30b includes an N-channel MOS transistor 11b for switching, a constant current source 12b, a resistor 13b, and a P-channel MOS transistor 14b. The second bias output circuit 30b is connected to the second node from the gate node of the MOS transistor 14b. The bias voltage Vbias2 is output. Accordingly, a switch control signal SW having a level complementary to the switch control signal / SW is input to the gate of the N-channel MOS transistor 11b for switching.

  The delay unit 40 includes N-channel MOS transistors 41 and 42, P-channel MOS transistors 43 and 44, a resistor 45, a capacitor 46, and an inverter 47. One end of a resistor 45 is connected to the input node of the inverter 47. Between the other end of the resistor 45 and the reference potential node, a current path between the source and drain of the MOS transistor 41 and a current path between the source and drain of the MOS transistor 42 are inserted in series. The gate of the MOS transistor 41 is supplied with the first bias voltage Vbias1. An input signal IN is supplied to the gate of the MOS transistor 42. Between the other end of the resistor 45 and the node of the power supply potential VDD, a current path between the source and drain of the MOS transistor 43 and a current path between the source and drain of the MOS transistor 44 are inserted in series. The gate of the MOS transistor 43 is supplied with the second bias voltage Vbias2. An input signal IN is supplied to the gate of the MOS transistor 44. A capacitor 46 is inserted between the input node of the inverter 47 and the reference potential node. Then, the signal OUT is output from the output node of the inverter 47.

  That is, the delay unit 40 includes an inverter 47, a resistor 45 having one end connected to the input node of the inverter 47, and a current path between the source and the drain in series between the other end of the resistor 45 and the reference potential node. The MOS transistor 41 inserted and supplied with the first bias voltage Vbias1 to the gate and the MOS transistor 42 supplied with the input signal IN to the gate, and the current path between the source and drain is connected to the other end of the resistor 45 and the power supply potential. A MOS transistor 43 inserted in series between the node and the second bias voltage Vbias2 to be supplied to the gate, a MOS transistor 44 to which the input signal IN is supplied to the gate, an input node of the inverter 47, a reference potential node, A signal OUT is output from the output node of the inverter 47.

The operation of the delay circuit of FIG. 5 is as follows.
When the switch control signal / SW is at a low level and SW is at a high level, both the MOS transistors 11 and 11b are turned on, and both the first and second bias output circuits 30 and 30b are controlled to operate. At this time, in the first bias output circuit 30a, the current value of the constant current source 12, the value of the resistor 13, and the characteristics of the MOS transistor 14, for example, the driving capability of the transistor such as a threshold value, are present at the gate node of the MOS transistor 14. A first bias voltage Vbias1 having a value corresponding to the above is generated. Similarly, in the second bias output circuit 30b, at the gate node of the MOS transistor 14b, the current value of the constant current source 12b, the value of the resistor 13b, and the characteristics of the MOS transistor 14b, for example, the driving capability of the transistor such as a threshold value, etc. A second bias voltage Vbias2 having a value corresponding to the above is generated. When the switch control signal / SW is at the high level and the SW is at the low level, both the MOS transistors 11 and 11b are turned off, and both the bias circuit units 30 and 30b are controlled to the non-operating state. Bias voltages Vbias1 and Vbias2 are not generated.

  When both the first and second bias output circuits 30 and 30b are in operation and the input signal IN input to the delay unit 40 is at low level, the MOS transistor 44 is turned on and the input node of the inverter 47 is connected. The node A in FIG. 5 is charged to the high level of the power supply potential VDD. At this time, the signal OUT output from the output node of the inverter 47 is at a low level.

  Next, when the input signal IN changes to a high level, the MOS transistor 44 is turned off and the MOS transistor 42 is turned on. Since the first bias voltage Vbias1 is supplied to the gate of the MOS transistor 41, the current flowing between the source and the drain of the MOS transistor 41 includes the current flowing through the current path between the source and the drain of the MOS transistor 14. An equal current flows. That is, since the charge previously charged in the capacitor 46 is started to be discharged by a constant current, the voltage at the node A decreases with a constant gradient. When the voltage at the node A reaches the circuit threshold value (Vth) of the inverter 47, the signal OUT is inverted from the low level to the high level. That is, as in the case described in the first embodiment, the rising edge of the input signal IN is from when the signal IN changes to the high level until the voltage at the node A reaches the circuit threshold (Vth) of the inverter 47. Delayed by time (corresponding to tdr in FIG. 2).

Next, when the input signal IN changes to the low level again, the MOS transistor 44 is turned on and the MOS transistor 42 is turned off. Since the second bias voltage Vbias2 is supplied to the gate of the MOS transistor 43, the current flowing between the source and drain of the MOS transistor 43 has a current flowing through the current path between the source and drain of the MOS transistor 14b. An equal current flows. This current is a constant current flowing through the constant current source 12b. That is, since the capacitor 46 that has been previously discharged is started to be charged by a constant current flowing through the MOS transistor 43, the voltage at the node A rises with a constant gradient. When the voltage at the node A reaches the circuit threshold value (Vth) of the inverter 47, the signal OUT is inverted from the high level to the low level. That is, the falling edge of the input signal IN is delayed by the time from when the signal IN changes to the low level until the voltage at the node A reaches the circuit threshold value (Vth) of the inverter 47.
Thus, in the delay circuit of FIG. 5, both the rising edge and the falling edge of the input signal IN are delayed.

  Here, consider the case where the resistors 13, 13b, 24 are manufactured to be higher than the design value. When the value of the resistor 13 increases, the voltage drop across the both ends increases, so the value of the first bias voltage Vbias1 becomes larger than the design value. Accordingly, the current flowing through the MOS transistor 41 in the delay unit 40 to which the first bias voltage Vbias1 is supplied to the gate also increases. That is, in the delay unit 40, the current flowing through the MOS transistor 41 increases by the amount of increase in the value of the resistor 45. Therefore, when discharging from the capacitor 46, the voltage at the node A decreases with the same gradient as when the resistors 13 and 45 are manufactured to have the design values. As a result, fluctuations in the delay time at the rising edge of the input signal IN are suppressed. Further, when the value of the resistor 13b increases, the voltage drop across the both ends increases, so the value of the second bias voltage Vbias2 becomes smaller than the design value. Accordingly, the current flowing through the MOS transistor 43 in the delay unit 40 to which the second bias voltage Vbias2 is supplied to the gate also increases. That is, in the delay unit 40, the current flowing through the MOS transistor 41 increases by the amount of increase in the value of the resistor 45. Therefore, when charging the capacitor 46, the voltage at the node A increases with the same gradient as when the resistors 13b and 45 are manufactured so as to have the design values. As a result, variation in the delay time at the falling edge of the input signal IN is suppressed.

  Contrary to the above, when the resistors 13, 13b, 24 are manufactured lower than the designed value, the value of the first bias voltage Vbias1 decreases as the value of the resistor 13 decreases, and thereby flows into the MOS transistor 41. The current decreases, and the fluctuation accompanying the decrease in the value of the resistor 45 is offset. Further, the value of the second bias voltage Vbias2 increases with a decrease in the value of the resistor 13b, whereby the current flowing through the MOS transistor 43 decreases, and the fluctuation accompanying the decrease in the value of the resistor 45 is offset.

  Next, consider the case where the characteristics of the MOS transistor, for example, the driving capability is manufactured lower than the design value. When the driving capability of the MOS transistor 14 is lowered, the constant current source 12 tries to pass the same current to the MOS transistor 14 as before, so that the value of the first bias voltage Vbias1 becomes larger than the design value. That is, in the delay unit 40, the gate voltage is increased by the amount that the driving capability of the MOS transistor 41 is lowered. It is not different from the case where it is manufactured. As a result, fluctuations in the delay time at the rising edge of the input signal IN are suppressed. Further, when the driving capability of the MOS transistor 14b is lowered, the constant current source 12b tries to flow the same value of current to the MOS transistor 14b, so that the value of the second bias voltage Vbias2 becomes smaller than the design value. . That is, in the delay unit 40, the gate voltage drops by the amount that the driving capability of the MOS transistor 43 is lowered. Therefore, the value of the current flowing through the MOS transistor 43 becomes the design value of the driving capability of the MOS transistors 14b and 43. It is not different from the case where it is manufactured. As a result, variation in the delay time at the falling edge of the input signal IN is suppressed.

  In contrast to the above, when the driving capability of the MOS transistor is manufactured higher than the design value, the value of the first bias voltage Vbias1 decreases as the driving capability of the MOS transistor 14 increases and the second bias voltage Vbias2 is increased. Increases as the driving capability of the MOS transistor 14b increases, the gate voltage decreases as the driving capability of the MOS transistor 41 increases, and the gate increases as the driving capability of the MOS transistor 43 increases. The voltage increases, and the fluctuation accompanying the increase in the driving capability of the MOS transistors 41 and 43 is offset. As a result, fluctuations in the delay time at the rising edge and falling edge of the input signal IN are suppressed.

  As described above, in the delay circuit of FIG. 5, even when transistor characteristics and resistance values vary, fluctuations in delay time at the rising edge and falling edge of the input signal IN are suppressed.

  Also in the present embodiment, as in the modification of FIG. 3, one bias circuit unit 30 is arranged for the plurality of delay units 40, and the first and second biases output from the bias circuit unit 30. The voltages Vbias1 and Vbias2 may be modified to be supplied to the plurality of delay units 40 in parallel.

(Delay Circuit of Fourth Embodiment)
In the delay circuit of the third embodiment shown in FIG. 5, fluctuations in delay time when variations in transistor characteristics and resistance values occur are suppressed. However, it may be configured to suppress fluctuations in delay time when the transistor characteristics vary.

  FIG. 6 is a circuit diagram showing a configuration of a delay circuit according to the fourth embodiment. The delay circuit in FIG. 6 differs from that in FIG. 5 in that the resistors 13 and 13b in the bias circuit unit 30 are omitted and the resistor 45 in the delay unit 40 is omitted.

  In the delay circuit having such a configuration, even when transistor characteristics vary, fluctuations in delay time at the rising edge and falling edge of the input signal IN are suppressed.

  Also in the present embodiment, as in the modification of FIG. 3, one bias circuit unit 30 is arranged for the plurality of delay units 40, and the first and second biases output from the bias circuit unit 30. The voltages Vbias1 and Vbias2 may be modified to be supplied to the plurality of delay units 40 in parallel.

(Semiconductor Memory Device of First Embodiment)
FIG. 7 is a plan view of the semiconductor memory device according to the first embodiment. This semiconductor memory device is, for example, a NAND flash memory, and includes a plurality of cell arrays 50 in which a plurality of memory cell transistors having floating gates and control gates are arranged, and a plurality of row decoders 51 for selecting word lines in the cell array 50. , A plurality of column decoders 52 for selecting bit lines in the cell array 50, and a peripheral circuit 53. In the peripheral circuit 53, there are formed a clock signal generation circuit, an input / output circuit for inputting / outputting data and a control signal, a pipeline processing circuit for transferring a plurality of data in time series, and the like.

  In the NAND flash memory, an internal clock signal is generated from a clock signal generation circuit based on a chip enable signal CE or a read enable signal RE supplied from the outside, and the operation of each circuit in the memory is synchronized with this clock signal. Timing is controlled. The characteristics and resistance values of the memory cell transistors in the cell array 50 vary with changes in manufacturing processes and variations. Therefore, it is necessary to adjust the operation timing of a control circuit that controls the data read operation from the cell array 50 and the data write operation to the cell array 50, such as the column decoder 52, for example. Since the operation of the control circuit that controls the data read operation from the cell array 50 and the data write operation to the cell array 50 is controlled based on the internal clock signal, it is necessary to adjust the timing of the internal clock signal. Therefore, in the NAND flash memory, a delay circuit is arranged in the middle of the internal clock signal transfer path indicated by an arrow in FIG. 7 to adjust the timing of the internal clock signal.

  FIG. 8 is a block diagram showing a part of circuits extracted from the semiconductor memory device of FIG. The column decoder 52, the pipeline processing circuit 54, and the input / output circuit 55 control a data read operation from the cell array 50 and a data write operation to the cell array 50. The clock signal generation circuit 56 generates an internal clock signal CK based on a chip enable signal CE or a read enable signal RE supplied from the outside. Delay circuits 57, 58, and 59 are inserted between the clock signal generation circuit 56, the column decoder 52, the pipeline processing circuit 54, and the input / output circuit 55.

  When a chip enable signal CE or a read enable signal RE is input from the outside, the clock signal generation circuit 56 generates an internal clock signal CK for data input / output. The delay circuits 57, 58, 59 guarantee data setup time and hold time when data is input / output by the column decoder 52, the pipeline processing circuit 54, and the input / output circuit 55. Therefore, the timing is adjusted by delaying the internal clock signal CK generated by the clock signal generation circuit 56. As these delay circuits 57, 58 and 59, the delay circuits of the first, second, third and fourth embodiments and modifications as described above are used. In these delay circuits, delay characteristics can be set according to variations in transistor characteristics of memory cell transistors, so that data input / output can be realized with high throughput. In particular, in the control circuit that controls the data read operation from the cell array 50 and the data write operation to the cell array 50 as the memory becomes faster and the cycle time of the chip enable signal CE or the read enable signal RE becomes shorter, more accurately. It is necessary to secure data setup time and hold time. That is, a highly accurate delay circuit is required. When the delay circuits of the first and second embodiments and the modification are used, the data output operation is a so-called SDR method synchronized only with the rising edge of the internal clock signal, and the third and fourth embodiments and When the modified delay circuit is used, the data output operation is a so-called DDR method synchronized with both the rising edge and the falling edge of the internal clock signal.

  For example, the delay time of the delay circuit is designed to be 5 ns, the temperature variation is −40 ° C. to + 100 ° C., the operation voltage variation is 1.8 V to 2.4 V, the transistor threshold variation is ± 100 mV, and the resistance variation is ± Under various conditions of 15%, a conventional delay circuit configured using an inverter chain, a conventional delay circuit configured using a resistor and a capacitor, and a variation in delay time generated in the delay circuit of each embodiment As a result of simulation, the following results were obtained. That is, the delay time variation generated in the conventional delay circuit configured using the inverter chain is ± 50%, and the delay time variation generated in the conventional delay circuit configured using the resistor and the capacitor is ± 40%. On the other hand, the variation in delay time generated in the delay circuit of each embodiment was ± 15%.

  In addition, this invention is not limited to said each embodiment and modification, It cannot be overemphasized that a various deformation | transformation is possible further. For example, in the embodiment of FIG. 1, the two MOS transistors 21 and 22 in which the current path between the source and drain is inserted in series between the node A and the reference potential node are arranged on the side closer to the node A. May be.

  DESCRIPTION OF SYMBOLS 10, 30 ... Bias circuit part, 20, 20a, 40 ... Delay part, 57, 58, 59 ... Delay circuit.

Claims (5)

A bias current applied from a node of the gate of the first MOS transistor to a constant current source; and a first MOS transistor in which a gate and a drain are coupled and a current of the constant current source flows in a current path between the source and the drain. A bias circuit section for outputting
A gate circuit and a current path between the source and drain are inserted in series between the input node and the reference potential node of the gate circuit, and the second MOS transistor to which the bias voltage is supplied to the gate and the input signal are gated. A third MOS transistor supplied to the capacitor, a capacitor inserted between the input node of the gate circuit and the node of the reference potential, and a current path between the source and the drain are a power supply potential node and an input node of the gate circuit. And a fourth MOS transistor to which the input signal is supplied to the gate, and a delay unit that outputs a signal from the output node of the gate circuit. A first constant current source; and a first polarity first MOS transistor in which a gate and a drain are coupled, and a current of the first constant current source flows in a current path between the source and the drain. The first bias output circuit for outputting the first bias voltage from the node of the gate of the MOS transistor, the second constant current source, the gate and the drain are coupled, and the second current path is connected to the current path between the source and the drain. And a second bias output circuit for outputting a second bias voltage from a node of the gate of the second MOS transistor. A circuit section;
A gate circuit and a current path between the source and drain are inserted in series between the input node of the gate circuit and a reference potential node, and a third polarity of the first polarity is supplied to the gate. A MOS transistor and a fourth MOS transistor having a first polarity to which the input signal is supplied to the gate, and an input node of the gate circuit and a node of the power supply potential are inserted in series, and the second bias voltage is applied to the gate. The second polarity fifth MOS transistor to be supplied to the gate and the sixth polarity MOS transistor to which the input signal is supplied to the gate, and the gate circuit are inserted between the input node and the reference potential node. And a delay unit that outputs a signal from an output node of the gate circuit.   3. The bias circuit unit includes a plurality of the delay units, and a bias voltage output from the bias circuit unit is supplied to the plurality of delay units in parallel. The delay circuit described. A memory circuit;
A clock signal generation circuit for generating an internal clock signal based on an enable control signal input from the outside;
A delay circuit for delaying the clock signal generated by the clock signal generation circuit;
A control circuit that operates in synchronization with the clock signal delayed by the delay circuit and controls a data read operation from the memory circuit and a data write operation to the memory circuit;
The delay circuit is
A bias current applied from a node of the gate of the first MOS transistor to a constant current source; and a first MOS transistor in which a gate and a drain are coupled and a current of the constant current source flows in a current path between the source and the drain. A bias circuit section for outputting
A gate circuit and a current path between the source and drain are inserted in series between the input node and the reference potential node of the gate circuit, and the second MOS transistor to which the bias voltage is supplied to the gate and the input signal are gated. A third MOS transistor supplied to the capacitor, a capacitor inserted between the input node of the gate circuit and the node of the reference potential, and a current path between the source and the drain are a power supply potential node and an input node of the gate circuit. And a delay section for outputting a signal from an output node of the gate circuit, and a fourth MOS transistor to which the input signal is supplied to the gate. A memory circuit;
A clock signal generation circuit for generating an internal clock signal based on an enable control signal input from the outside;
A delay circuit for delaying the clock signal generated by the clock signal generation circuit;
A control circuit that operates in synchronization with the clock signal delayed by the delay circuit and controls a data read operation from the memory circuit and a data write operation to the memory circuit;
The delay circuit is
A first constant current source; and a first polarity first MOS transistor in which a gate and a drain are coupled, and a current of the first constant current source flows in a current path between the source and the drain. The first bias output circuit for outputting the first bias voltage from the node of the gate of the MOS transistor, the second constant current source, the gate and the drain are coupled, and the second current path is connected to the current path between the source and the drain. And a second bias output circuit for outputting a second bias voltage from a node of the gate of the second MOS transistor. A circuit section;
A gate circuit and a current path between the source and drain are inserted in series between the input node of the gate circuit and a reference potential node, and a third polarity of the first polarity is supplied to the gate. A MOS transistor and a fourth MOS transistor having a first polarity to which the input signal is supplied to the gate, and an input node of the gate circuit and a node of the power supply potential are inserted in series, and the second bias voltage is applied to the gate. The second polarity fifth MOS transistor to be supplied to the gate and the sixth polarity MOS transistor to which the input signal is supplied to the gate, and the gate circuit are inserted between the input node and the reference potential node. A semiconductor memory device comprising: a delay unit that outputs a signal from an output node of the gate circuit.

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