JP2011049877A - Clock signal control circuit and clock signal control method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To make frequency control of a clock signal more properly. <P>SOLUTION: A table value TVAL is outputted from a set point storing circuit 13 according to the frequency of a monitor signal MS as a monitor result by a ring oscillator 16 of a monitor circuit 12. A clock signal CLK of a frequency equal to that of an oscillation signal generated by PLL circuits 15a and 15b of a clock signal generating circuit 14 according to the table value TVAL is supplied to a target circuit 11. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a clock signal control circuit and a clock signal control method.

  Conventionally, a circuit (for example, CPU) of a semiconductor device operates based on a clock signal supplied from, for example, a clock signal generation circuit 40 shown in FIG. The clock signal generation circuit 40 supplies a reference signal SCLK supplied from the outside to the CPU 42 via a frequency divider 41, for example.

  A circuit of a semiconductor device may cause a so-called thermal runaway in which operation cannot be controlled when the temperature exceeds an allowable range due to factors such as an operating environment. For this reason, it is conceivable to detect the temperature of the semiconductor device and change the frequency of the clock signal supplied to the circuit. For example, in the circuit shown in FIG. 4, the clock signal So obtained by dividing the reference signal SCLK by the frequency divider 41 is supplied to the CPU 42. By reducing the frequency of the clock signal, heat generation of the CPU 42 can be suppressed and thermal runaway can be prevented.

  However, in the clock signal generation circuit 40 shown in FIG. 4, since the frequency of the signal So is extremely lower than the frequency of the reference signal SCLK, the operation speed of the CPU 42 is extremely decreased. Therefore, the operation of the semiconductor device becomes extremely slow.

  The purpose of this clock signal control circuit is to suitably control the frequency of the clock signal.

  According to one aspect of the present invention, a set value storage circuit that outputs a set value according to a monitoring result of a monitor circuit that monitors a state of a target circuit, and a clock signal that is supplied to the target circuit according to the set value The clock signal generation circuit includes a plurality of PLL circuits, and sets a first set value in one of the plurality of PLL circuits, and When the second set value output from the set value storage circuit is different from the first set value, the clock signal generated by the first PLL circuit in which the set value is set is output. The set value of 2 is set in a second PLL circuit different from the first PLL circuit, and a clock signal generated by the second PLL circuit is output.

  According to one aspect of the present invention, clock signal frequency control can be more suitably performed.

It is a schematic block diagram of a clock signal control circuit. It is a block circuit diagram of a clock signal generation circuit. It is an operation | movement waveform diagram of a clock signal control circuit. It is a block diagram which shows a prior art example.

Hereinafter, an embodiment will be described with reference to FIGS.
As shown in FIG. 1, the clock signal control circuit 10 supplies a clock signal CLK to the target circuit 11. The target circuit 11 is, for example, a central processing unit (CPU).

  The clock signal control circuit 10 includes a monitor circuit 12, a set value storage circuit 13, and a clock signal generation circuit 14. The monitor circuit 12 monitors the operating state of the target circuit 11 and outputs a monitor signal MS corresponding to the monitoring result. The set value storage circuit 13 stores a plurality of set values and outputs a set value corresponding to the monitor signal MS. The set value is, for example, the frequency value of the clock signal CLK supplied to the target circuit 11.

  The clock signal generation circuit 14 includes a plurality (two in this embodiment) of phase-locked loop circuits (hereinafter referred to as PLL circuits) 15a and 15b in order to generate a clock signal CLK to be supplied to the target circuit 11. The clock signal generation circuit 14 alternately selects the PLL circuits 15a and 15b and sets a set value for the selected PLL circuit. The selected PLL circuit generates a clock signal having a frequency corresponding to the set value. The clock signal generation circuit 14 outputs the clock signal generated by the selected PLL circuit as the clock signal CLK.

  The target circuit 11 operates based on the clock signal CLK output from the clock signal generation circuit. That is, the operating frequency of the target circuit 11 corresponds to the clock signal CLK, and the frequency of the clock signal CLK corresponds to the set value, that is, the monitor signal MS output from the monitor circuit 12.

  Therefore, the monitor circuit 12 is arranged so that the heat generated by the operation of the target circuit 11 propagates to the monitor circuit 12. Then, the frequency of the clock signal CLK supplied to the target circuit 11 is controlled according to the temperature of the target circuit 11. For example, by lowering the frequency of the clock signal CLK when the target circuit 11 rises, it becomes possible to prevent the operation of the target circuit 11 from becoming unstable due to heat.

  The monitor circuit 12 includes a ring oscillator 16, a frequency counter 17, a frequency storage device 18, and a trigger counter 19. The ring oscillator 16 includes an odd number (three in this embodiment) of inverter circuits 16 a connected in a ring shape, and outputs a monitor clock signal MCK having a frequency corresponding to the operating speed of the inverter circuit 16 a to the frequency counter 17. The inverter circuit 16a operates at a speed corresponding to the process (P), the operating power supply voltage (V), and the temperature (T). Therefore, the frequency of the monitor clock signal MCK output from the ring oscillator 16 varies depending on temperature, environmental temperature, manufacturing process variation, and power supply voltage fluctuation.

  The frequency counter 17 counts up the count value in response to the monitor clock signal MCK output from the ring oscillator 16 and outputs the count value CT. That is, the frequency counter 17 counts the number of pulses of the monitor clock signal MCK.

  The frequency storage device 18 receives the count value CT output from the frequency counter 17. In addition, the trigger signal TS output from the trigger counter 19 is input to the frequency counter 17 and the frequency storage device 18.

  The trigger counter 19 receives the reference signal SCLK. The reference signal SCLK is a pulse signal having a predetermined frequency. The trigger counter 19 counts up the count value in response to the reference signal SCLK. The trigger counter 19 compares the count value with the set value, and when the count value becomes equal to the set value, outputs one pulse-like trigger signal TS, and clears the count value. Therefore, the trigger counter 19 outputs the trigger signal TS at every cycle according to the set value.

  The set value is set according to the sampling cycle of the monitor circuit 12. The set value is set according to the operation of the PLL circuits 15a and 15b. The PLL circuits 15a and 15b require time from the setting change until the frequency of the oscillation signal is stabilized. This time is called lock-up time. The set value is set so that the cycle of the trigger signal TS is longer than the lockup time.

  The frequency counter 17 resets the count value in response to the trigger signal TS. For example, the frequency counter 17 resets the count value in response to the H level trigger signal TS (= 0), and counts up in response to the L level trigger signal TS.

  The frequency storage device 18 stores the count value CT in response to the trigger signal TS. That is, the frequency storage device 18 updates the stored value every time the trigger signal TS is input. Then, the frequency storage device 18 outputs a monitor signal MS having the stored value.

  The frequency counter 17 outputs a count value CT obtained by counting the monitor clock signal MCK. The trigger counter 19 outputs one pulse of the trigger signal TS for each cycle according to the set value. The value stored in the frequency storage device 18, that is, the value of the monitor signal MS is the number of pulses of the monitor clock signal MCK in the period corresponding to the set value of the trigger counter 19, and corresponds to the frequency of the monitor clock signal MCK. That is, the frequency storage device 18 outputs the monitor signal MS having a value corresponding to the frequency of the monitor clock signal MCK.

  The set value storage circuit 13 has a frequency table, and a plurality of set values are stored in the frequency table. The set value is a set value to be set in the PLL circuits 15a and 15b of the clock signal generation circuit 14. For example, a set value corresponding to 10 MHz to 100 MHz is stored in a step corresponding to 10 MHz. The set value storage circuit 13 reads a set value corresponding to the input monitor signal MS from the frequency table and outputs the read value as a table value TVAL.

  The clock signal generation circuit 14 alternately selects the PLL circuits 15a and 15b, and sets the table value TVAL for the selected PLL circuit. The selected PLL circuit generates a clock signal having a frequency corresponding to the table value TVAL. The clock signal generation circuit 14 outputs the clock signal generated by the selected PLL circuit as the clock signal CLK.

Next, the configuration of the clock signal generation circuit 14 will be described.
As shown in FIG. 2, the table value TVAL is input to the comparator 21. Further, the PLL set value PCST is input to the comparator 21. The PLL set value PCST is a table value TVAL previously output from the set value storage circuit 13, and is set value information of the operating frequency of the target circuit 11 (CPU) at the present time. The comparator 21 compares the PLL set value PCST and the table value TVAL. If the PLL set value PCST and the table value TVAL are equal, the comparator 21 outputs a set signal CST having a predetermined value (for example, 0), and at the L level. A trigger signal CTRG is output. On the other hand, when the PLL set value PCST and the table value TVAL are different, the comparator 21 outputs a setting signal CST having a value equal to the table value TVAL and also outputs an H level trigger signal CTRG.

  The selector 22 receives the setting signal CST and the selection signal PSEL. The selector 22 has a first output terminal to which the setting register 23a is connected and a second output terminal to which the setting register 23b is connected. The selector 22 connects the input terminal to the first output terminal or the second output terminal according to the selection signal PSEL. For example, the selector 22 connects the input terminal to the first output terminal in response to the selection signal PSEL at the H level (shown by a solid line in FIG. 2), and connects the input terminal to the first output terminal in response to the selection signal PSEL at the L level. 2 is connected to the output terminal 2 (illustrated by a broken line in FIG. 2). Therefore, the setting signal CST is output to the first setting register 23a or the second setting register 23b according to the selection signal PSEL.

  The first setting register 23a stores the value of the setting signal CST and outputs the setting signal PCSa having the stored value to the PLL circuit 15a. The reference signal SCLK is input to the PLL circuit 15a. The PLL circuit 15a includes a voltage controlled oscillator (VCO), a phase comparator, and a variable frequency divider, and generates an oscillation signal POa having a frequency that is an integral multiple of the frequency of the reference signal SCLK according to the set value PCSa.

  Similarly, the second setting register 23b stores the value of the setting signal CST and outputs the setting signal PCSb having the stored value to the PLL circuit 15b. The reference signal SCLK is input to the PLL circuit 15b. The PLL circuit 15b includes a voltage controlled oscillator (VCO), a phase comparator, and a variable frequency divider, and generates an oscillation signal POb having a frequency that is an integral multiple of the frequency of the reference signal SCLK according to the set value PCSb.

  The comparator 21 outputs a setting signal CST having a table value TVAL or a predetermined value (= 0) according to the comparison result. Accordingly, the table value TVAL or the predetermined value (= 0) is set in both the PLL circuits 15a and 15b. When the table value TVAL is set, the PLL circuits 15a and 15b generate oscillation signals POa and POb having frequencies corresponding to the table value TVAL. On the other hand, when a predetermined value (= 0) is set, each of the PLL circuits 15a and 15b stops the oscillation operation.

  The output selection circuit 24 receives the oscillation signals POa and POb generated by the PLL circuits 15a and 15b and the selection signal PSEL. The output selection circuit 24 selects one of the oscillation signals POa and POb according to the selection signal PSEL, and outputs a clock signal CLK that is substantially equal to the selected oscillation signal. For example, the output selection circuit 24 selects the oscillation signal POa according to the L-level selection signal PSEL, and selects the oscillation signal POb according to the H-bell selection signal PSEL.

  The setting signals PCSa and PCSb output from the setting registers 23a and 23b are input to the setting value selection circuit 25. Further, a selection signal PSEL is input to the set value selection circuit 25. The setting value selection circuit 25 selects one of the setting signals PCSa and PCSb based on the selection signal PSEL. For example, the setting value selection circuit 25 selects the first setting signal PCSa in response to the L level selection signal PSEL, and selects the second setting signal PCSb in response to the H level selection signal PSEL. Then, the set value selection circuit 25 outputs the PLL set value PCST having a value equal to the value of the selected set signal to the comparator 21.

  The trigger signal CTRG output from the comparator 21 is input to the counter 27. Further, the reference signal SCLK is input to the counter 27. The counter 27 starts or stops the counting operation based on the trigger signal CTRG. For example, the counter 27 starts a count operation in response to an H level trigger signal CTRG.

  In the count operation, the counter 27 counts up the count value in response to the pulse of the reference signal SCLK. When the count value becomes equal to the set value, the counter 27 inverts the level of the control signal CNT to be output. On the other hand, the counter 27 stops the count operation in response to the L level trigger signal CTRG.

  The set value of the counter 27 is set according to the maximum value of the lock-up time of the PLL circuits 15a and 15b. Specifically, the set value is set to a sufficient time required for the PLL circuits 15a and 15b to be locked up after the H level trigger signal CTRG is output.

  The control signal CNT output from the counter 27 is input to an exclusive OR circuit (EOR circuit) 28. A selection signal PSEL is input to the EOR circuit 28. The EOR circuit 28 outputs a signal corresponding to the result of the exclusive OR operation of the control signal CNT and the selection signal PSEL to the selector 29.

  The selector 29 receives the selection signal PSEL and the trigger signal CTRG. The selector 29 selects one of the selection signal PSEL and the output signal of the EOR circuit 28 according to the signal level of the trigger signal CTRG, and outputs a signal PSEL_N having a level equal to the level of the selected signal.

  The output signal PSEL_N of the selector 29 is input to the selection signal register 26. The selection signal register 26 stores the signal PSEL_N and outputs a selection signal PSEL having a level equal to the stored level.

  A selection signal PSEL is input to the EOR circuit 28. The output selection circuit 24 selects the first PLL circuit 15a or the second PLL circuit 15b according to the selection signal PSEL. Then, the clock signal CLK is generated by the oscillation signal of the selected PLL circuit. Therefore, the selection signal PSEL corresponds to a PLL circuit that generates the clock signal CLK being output.

  Further, the control signal CNT is input to the EOR circuit 28. The counter 27 inverts the level of the control signal CNT when the count value matches the set value. The EOR circuit 28 outputs an L level signal when the levels of the two input signals match, and outputs an H level signal when the levels of the two input signals do not match.

  The counter 27 inverts the level of the control signal CNT according to the trigger signal CTRG output from the comparator 21, that is, the comparison result of the comparator 21. Therefore, the EOR circuit 28 outputs a signal obtained by inverting the logic level of the selection signal PSEL every time the level of the control signal CNT is inverted. The selection signal PSEL indicates a PLL circuit that generates a clock signal CLK being output, and the value is stored in the selection signal register 26. Therefore, the output signal of the EOR circuit 28 changes the value of the selection signal register 26 in order to switch the PLL circuit to be selected. Thus, the counter 27, the EOR circuit 28, and the selector 29 are included in a selection change circuit that changes the value stored in the selection signal register 26 to a value indicating the PLL circuit to be selected next.

The operation of the clock signal control circuit 10 configured as described above will be described.
For easy understanding, the value of the monitor signal MS output from the frequency storage device 18 is the frequency of the monitor clock signal MCK output from the ring oscillator 16. The table value TVAL output from the set value storage circuit 13 is set as the frequency of the oscillation signals POa and POb of the PLL circuits 15a and 15b.

  Now, the setting value (80 MHz) is stored in the first setting register 23a, and the first PLL circuit 15a outputs the oscillation signal POa having a frequency (80 MHz) corresponding to the setting signal PCSa output from the setting register 23a. To do. An L level selection signal PSEL is output from the selection signal register 26.

In response to the L level selection signal PSEL, the selector 22 connects the input terminal to the second output terminal as indicated by a broken line in FIG.
The output selection circuit 24 selects the oscillation signal POa of the first PLL circuit 15a in response to the L level selection signal PSEL, and outputs a clock signal CLK having a frequency equal to the frequency of the oscillation signal POa.

  The setting value selection circuit 25 selects the setting signal PCSa output from the first setting register 23a in response to the L level selection signal PSEL, and compares the PLL setting value PCST having a value equal to the value of the setting signal PCSa. To the device 21. Accordingly, the comparator 21 receives the 80 MHz PLL set value PCST.

  Next, the frequency storage device 18 outputs a monitor signal MS having a frequency (for example, 8 MHz) of the monitor clock signal MCK output from the ring oscillator 16. The set value storage circuit 13 outputs a table value TVAL (for example, 80 MHz) of a frequency corresponding to the frequency (8 MHz) of the signal MS. The comparator 21 compares the table value TVAL with the PLL set value PCST. In this case, since the table value TVAL and the PLL set value PCST are equal, the comparator 21 outputs a set value CST of a predetermined value (= 0). This setting value CST is supplied to the second setting register 23b via the selector 22, and the second setting register 23b stores the setting value CST (= 0) and outputs a setting value PCSb equal to the value. . The second PLL circuit 15b stops the oscillation operation because the set value PCSb is a predetermined value (= 0). At this time, since the current path in the second PLL circuit 15b is smaller than that in the oscillation operation, the current consumption is reduced accordingly.

  Next, when the environmental temperature or the temperature of the ring oscillator 16 increases, the frequency of the monitor clock signal MCK output from the ring oscillator 16 decreases, and the value of the monitor signal MS output from the frequency storage device 18 decreases. For example, the value of the monitor signal MS is 7 MHz. Then, the set value storage circuit 13 outputs a table value TVAL of 70 MHz based on the monitor signal MS (time T1 in FIG. 3).

  Comparator 21 compares table value TVAL and PLL set value PCST. Since the table value TVAL is different from the PLL set value PCST, the comparator 21 outputs a set value CST having a value equal to the table value TVAL and also outputs an H level trigger signal CTRG (time T2 in FIG. 3).

  The setting value CST output from the comparator 21 is supplied to the second setting register 23b via the selector 22, and the second setting register 23b stores the setting value CST (= 70 MHz) and is set equal to the value. The value PCSb is output (time T3 in FIG. 3).

The second PLL circuit 15b starts an oscillation operation based on the set value PCSb, and brings the frequency of the oscillation signal POb close to the set value PCSb (70 MHz).
When the H level trigger signal CTRG is output at time T2 in FIG. 3, the counter 27 in FIG. 2 starts counting. Then, when the count value becomes equal to the set value, the counter 27 outputs an H level control signal CNT (time T4 in FIG. 3). Since the set value is set to be larger than the value corresponding to the lock-up time of the PLL circuit 15b, the PLL circuit 15b is in a locked state at time T4 when the H-level control signal CNT is output.

  2 outputs an H level signal based on the H level control signal CNT and the L level selection signal PSEL, and the selector 29 selects the output signal of the EOR circuit 28 and selects the H level signal. Signal PSEL_N is output.

  The selection signal register 26 outputs an H level selection signal PSEL based on the H level signal PSEL_N (time T5 in FIG. 3). Then, the output selection circuit 24 selects the oscillation signal POb of the second PLL circuit 15b in response to the H level selection signal PSEL, and outputs a clock signal CLK having a frequency equal to the frequency of the oscillation signal POb.

  Thus, the frequency of the clock signal CLK is switched from 80 MHz to 70 MHz. Then, since the operation speed of the target circuit 11 (CPU) is lowered, heat generation is suppressed accordingly. Further, the operating frequency of the target circuit 11 is switched from 80 MHz to 70 MHz. Thus, since the difference in operating frequency is small, it is possible to suppress the operation of the target circuit 11 from being extremely lowered.

  At the time of switching the frequency, since the second PLL circuit 15b is in a locked state, the frequency fluctuation of the clock signal CLK is suppressed. For this reason, fluctuations in the operation of the target circuit 11 (CPU) that operates based on the clock signal CLK are suppressed.

  The setting value selection circuit 25 selects the setting signal PCSb output from the second setting register 23b in response to the H level selection signal PSEL, and compares the PLL setting value PCST having a value equal to the value of the setting signal PCSb. To the device 21. Accordingly, the comparator 21 receives the 70 MHz PLL set value PCST.

  The comparator 21 compares the table value TVAL with the PLL set value PCST. At this time, since the table value TVAL is 70 MHz, the table value TVAL and the PLL set value PCST are equal. Accordingly, the comparator 21 outputs a set value CST having a predetermined value (= 0).

  In response to the H level selection signal PSEL, the selector 22 connects the input terminal to the first output terminal as shown by the solid line in FIG. Accordingly, the setting value CST is supplied to the first setting register 23a via the selector 22, and the first setting register 23a stores the setting value CST (= 0) and outputs the setting value PCSa equal to the value. (Time T6 in FIG. 3).

  The first PLL circuit 15a stops the oscillation operation because the set value PCSa is a predetermined value (= 0). At this time, since the current path in the first PLL circuit 15a is smaller than that in the oscillation operation, the current consumption is reduced accordingly.

  When the environmental temperature or the temperature of the ring oscillator 16 decreases, the frequency of the monitor clock signal MCK output from the ring oscillator 16 increases, and the value of the monitor signal MS output from the frequency storage device 18 increases. Then, similarly to the case where the temperature rises, an oscillation signal having a frequency higher than the frequency of the clock signal CLK is generated by the PLL circuit, and the oscillation signal is selected and output as the clock signal CLK.

  In the above description, the frequency is changed according to the temperature change. However, when the power supply voltage fluctuates, the frequency of the monitor clock signal MCK output from the ring oscillator 16 included in the monitor circuit 12 changes. Similarly, the frequency of the clock signal CLK can be changed. Further, when the power supply voltage is individually supplied to the monitor circuit 12 and the target circuit 11 and the power supply voltage supplied to the target circuit 11 fluctuates, the monitor output from the ring oscillator 16 according to the temperature change of the target circuit 11 Since the frequency of the clock signal MCK changes, the frequency of the clock signal CLK can be similarly changed.

  In addition, it is possible to cope with variations in processes for forming a semiconductor device. The process variation affects the operation speed of the ring oscillator 16 in the target circuit 11. Therefore, similarly to the above, the frequency of the clock signal CLK can be changed.

As described above, according to the present embodiment, the following effects can be obtained.
(1) The table value TVAL is output from the set value storage circuit 13 in accordance with the frequency of the monitor signal MS which is the monitoring result by the ring oscillator 16 of the monitor circuit 12. Then, the clock signal CLK having the same frequency as the oscillation signals POa and POb generated by the PLL circuits 15 a and 15 b of the clock signal generation circuit 14 according to the table value TVAL is supplied to the target circuit 11. By adopting such a configuration, the frequency can be adjusted by each of the PLL circuits 15a and 15b. Therefore, it is possible to change the frequency step by step when switching the frequency. As a result, the target circuit 11 (CPU) is not operated at a frequency divided by 1 / n as in the prior art, and the frequency of the clock signal can be suitably controlled.

  (2) Using two PLL circuits 15a and 15b, for example, after locking up the PLL circuit 15b, the output selection circuit 24 outputs a clock signal CLK having a frequency equal to the oscillation signal POb. For this reason, for example, since the clock signal CLK is not changed during the lock-up of the PLL circuit, it is prevented that the frequency of the signals of the PLL circuits 15a and 15b accompanying the lock-up is shifted from a desired frequency. That is, the target circuit 11 can be more reliably operated at a desired frequency.

  (3) A monitor circuit 12 having a ring oscillator 16 using an odd number (for example, three) of inverter circuits 16a is used. That is, since the ring oscillator 16 having a simple configuration is used, the monitor circuit can be configured easily and inexpensively.

  (4) Since the monitor circuit 12 includes the ring oscillator 16 having an odd number (for example, three) of inverter circuits 16a, the target circuit 11 (CPU) is indirectly configured with a simple circuit. Can be monitored.

  (5) In the frequency table of the set value storage circuit 13, the frequency of the clock signal CLK corresponding to S3, which is a signal equivalent to the value of the monitor signal MS equal to the count value of the monitor clock signal MCK, is set in the PLL circuit. The set value to be stored is stored. Thereby, the frequency of the clock signal CLK can be determined by using the set value stored in the frequency table.

In addition, you may implement each said embodiment in the following aspects.
In the above embodiment, the frequency of the clock signal CLK supplied to the target circuit 11 is changed by alternately using the two PLL circuits 15a and 15b, but a configuration using three or more PLL circuits is adopted. Also good. By adopting such a configuration, it is possible to set the frequency according to the temperature of the ring oscillator 16 at that time, the environmental temperature, and process variations during the lock-up time in the PLL circuit. The frequency control of the clock signal CLK supplied to 11 can be performed.

In the above embodiment, the number of setting values stored in the frequency table of the setting value storage circuit 13 may be changed as appropriate. Further, the set value step may be changed as appropriate.
In the above embodiment, the ring oscillator 16 is configured by the three inverter circuits 16a. However, the ring oscillator may be configured by five or more odd number of inverter circuits.

In the above embodiment, the ring oscillator 16 is used for the monitor circuit 12. However, the present invention is not limited to this.
In the above embodiment, the frequency of the clock signal CLK supplied to the CPU as the target circuit 11 is changed according to the monitoring result, but the target circuit may be other than the CPU, for example, a clock supplied to a DSP, MPU, etc. The frequency of the signal may be changed.

The following notes are disclosed regarding the above embodiments.
(Appendix 1)
A set value storage circuit that outputs a set value according to the monitor result of the monitor circuit that monitors the state of the target circuit;
A clock signal generation circuit for generating a clock signal to be supplied to the target circuit according to the set value;
Have
The clock signal generation circuit includes a plurality of PLL circuits, a first setting value is set in one of the plurality of PLL circuits, and the first PLL circuit sets the first setting value. When the generated clock signal is output and the second set value output from the set value storage circuit is different from the first set value, the second set value is set to the first PLL circuit. Set to a different second PLL circuit, and output the clock signal generated by the second PLL circuit,
A clock signal control circuit.
(Appendix 2)
The clock signal generation circuit operates a counter based on the setting of the second set value, and based on the count up of the counter, an output signal is generated from the clock signal generated by the first PLL circuit. Switch to the clock signal generated by the PLL circuit of 2.
The clock signal control circuit according to claim 1.
(Appendix 3)
The clock signal generation circuit includes a plurality of setting registers that store setting values to be set in each of the plurality of PLL circuits;
A setting value selection circuit that selects a setting value set in the PLL circuit from a setting register corresponding to the PLL circuit that generates the clock signal being output, and outputs the PLL setting value according to the selected setting value;
A comparator that compares the PLL set value with the set value output from the set value storage circuit and outputs a value according to the comparison result;
A switching circuit that outputs a value output from the comparator to a setting register different from a setting register corresponding to a PLL circuit that generates a clock signal being output;
The clock signal control circuit according to claim 1, wherein:
(Appendix 4)
The comparator outputs a predetermined value when the PLL set value is equal to the set value;
4. The clock signal control circuit according to claim 3, wherein the PLL circuit stops operation when a predetermined value is set in a corresponding setting register.
(Appendix 5)
5. The clock signal control circuit according to claim 1, further comprising: a selection signal register that stores a selection signal corresponding to a PLL circuit selected from among the plurality of PLL circuits. 6.
(Appendix 6)
6. The clock signal control circuit according to claim 5, further comprising a selection change circuit that changes a setting signal stored in the selection signal register in accordance with a comparison result of the comparator.
(Appendix 7)
The setting value storage circuit includes a frequency table in which a setting frequency for setting the frequency of the clock signal corresponding to the monitoring result in the PLL circuit is stored. The clock signal control circuit according to the item.
(Appendix 8)
The monitor circuit includes a ring oscillator including an odd number of inverter circuits connected in a ring shape;
A counter that counts the output signal of the ring oscillator;
A trigger circuit that outputs a trigger signal at a predetermined period;
A register that holds the output of the counter in response to the trigger signal and outputs the held value;
The clock signal control circuit according to any one of appendices 1 to 7, wherein the clock signal control circuit includes:
(Appendix 9)
A first setting value corresponding to a monitoring result of a monitor circuit that monitors a state of a target circuit is set in one of the plurality of PLL circuits, and the first setting value is Output the clock signal generated by the set first PLL circuit,
Next, when the second set value corresponding to the monitor result of the monitor circuit that monitors the state of the target circuit is different from the first set value, the second set value is set to the first PLL circuit. Set to a different second PLL circuit, and output the clock signal generated by the second PLL circuit,
A clock signal control method.

10: Clock signal control circuit 11 Target circuit (CPU)
12 monitor circuit 13 set value storage circuit 14 clock signal generation circuit 15a, 15b PLL circuit 16 ring oscillator 17 frequency counter 18 frequency storage circuit 19 trigger counter (trigger circuit)
22 Selector (switching circuit)
CLK: Clock signal

Claims (5)

A set value storage circuit that outputs a set value according to the monitor result of the monitor circuit that monitors the state of the target circuit;
A clock signal generation circuit for generating a clock signal to be supplied to the target circuit according to the set value;
Have
The clock signal generation circuit includes a plurality of PLL circuits, a first setting value is set in one of the plurality of PLL circuits, and the first PLL circuit sets the first setting value. When the generated clock signal is output and the second set value output from the set value storage circuit is different from the first set value, the second set value is set to the first PLL circuit. Set to a different second PLL circuit, and output the clock signal generated by the second PLL circuit,
A clock signal control circuit. The clock signal generation circuit operates a counter based on the setting of the second set value, and based on the count up of the counter, an output signal is generated from the clock signal generated by the first PLL circuit. Switch to the clock signal generated by the PLL circuit of 2.
The clock signal control circuit according to claim 1. The clock signal generation circuit includes a plurality of setting registers that store setting values to be set in each of the plurality of PLL circuits;
A setting value selection circuit that selects a setting value set in the PLL circuit from a setting register corresponding to the PLL circuit that generates the clock signal being output, and outputs the PLL setting value according to the selected setting value;
A comparator that compares the PLL set value with the set value output from the set value storage circuit and outputs a value according to the comparison result;
A switching circuit that outputs a value output from the comparator to a setting register different from a setting register corresponding to a PLL circuit that generates a clock signal being output;
The clock signal control circuit according to claim 1, wherein: The comparator outputs a predetermined value when the PLL set value is equal to the set value;
4. The clock signal control circuit according to claim 3, wherein the PLL circuit stops operation when a predetermined value is set in a corresponding setting register. A first setting value corresponding to a monitoring result of a monitor circuit that monitors a state of a target circuit is set in one of the plurality of PLL circuits, and the first setting value is Output the clock signal generated by the set first PLL circuit,
Next, when the second set value corresponding to the monitor result of the monitor circuit that monitors the state of the target circuit is different from the first set value, the second set value is set to the first PLL circuit. Set to a different second PLL circuit, and output the clock signal generated by the second PLL circuit,
A clock signal control method.

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