JP2011047826A - Semiconductor device and test method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device capable of shortening a time necessary for competition evaluation, and achieving timing competition evaluation. <P>SOLUTION: This device includes a test master (110) wherein, when receiving access to an evaluation object macro (120) from a CPU (200) which is a host device, and detecting that the access is a competition evaluation start access determined beforehand, a command for competition evaluation is inputted into the evaluation object macro at a prescribed timing with respect to the access. The test master can vary an input timing of the command for competition evaluation into the evaluation object macro over a part or the whole of a time range from a starting point of time of operation of the evaluation object macro up to just before finish time with respect to the access. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a test technique for a semiconductor device, and more particularly to a semiconductor device and a test method suitable for a timing competition test.

  In the case of evaluating an access timing conflict condition for a macro or the like realized by an FPGA (Field Programmable Gate Array), a simulation or the like is generally used. In the evaluation of timing conflict, typically, for an access request (instruction, command) issued from a higher-level device such as a CPU to an evaluation target macro, contention of a common resource or the like occurs in the evaluation target macro. This is performed by giving another access request (command, command) to the macro to be evaluated and evaluating the execution status of the access request in the macro to be evaluated.

  Regarding FPGA testing, for example, Patent Document 1 uses a plurality of variable logic circuits (FPGAs) capable of rewriting arbitrary logic as test circuits for the purpose of shortening test time. In FIG. 6, the test circuit FPGAa / b / c (11-13) capable of executing the test contents is mounted, and the MUX (10) connects one of these and the semiconductor integrated circuit (17) to be tested to perform the test. I do. During the test execution, it is possible to ignore the program rewrite time by writing the test contents to the FPGA that is not executing the test via 14 or 15, and consequently the test time can be shortened. However, although the test time is shortened by rewriting the test program in parallel, the test program can be finely adjusted. However, timing competition evaluation is not described at all.

JP 2005-3630 A

  The analysis of related technology is given below.

  When timing competition evaluation is performed using simulation, it takes time. For this reason, realization of timing competition evaluation in a test apparatus using FPGA is desired.

  Therefore, an object of the present invention is to provide an apparatus and a test method that can reduce the time required for evaluation and realize timing competition evaluation as compared with the case where simulation or the like is used.

  In order to solve the above-mentioned problems, the present invention is generally configured as follows.

  According to the present invention, when the access from the host device to the evaluation target circuit is monitored and the arrival of a predetermined competition evaluation start access is detected, a predetermined instruction stored and held in advance for a conflict test is transmitted to the host device. There is provided a semiconductor device including a test circuit that is input to the circuit to be evaluated at a predetermined timing with respect to the access from.

  According to the present invention, the test circuit inputs the instruction for the contention test to the evaluation target circuit over a part or all of the timing interval from the start to the end of the operation of the evaluation target circuit for the access. A circuit for varying the timing is provided.

  According to the present invention, it is possible to reduce the time required for the evaluation and to evaluate the timing competition of the semiconductor device as compared with the case of using a simulation or the like.

It is a figure which shows the structure of one Embodiment of this invention. It is a figure which shows the structure of the test master of one Embodiment of this invention. It is a figure which shows the timing operation | movement of one Embodiment of this invention. It is a flowchart which shows the operation | movement procedure of one Embodiment of this invention. It is a figure explaining one Example of this invention. It is a figure which shows the structure of patent document 1. FIG.

  An embodiment of the present invention will be described. In the present invention, the semiconductor device monitors the access to the evaluation target circuit (evaluation target) from a higher-level device such as a CPU, and stores and holds it in advance for a competition test when detecting the arrival of a predetermined competition evaluation start access. A test circuit (test master) that inputs a predetermined instruction to the evaluation target circuit in a predetermined timing relationship with respect to the access from the host device, and realizes timing competition evaluation that has not been realized so far .

  FIG. 1 is a diagram showing a configuration of a semiconductor device according to an embodiment of the present invention. The test apparatus 100 is configured with an FPGA and is connected to the CPU 200 via a bus 210. The test apparatus 100 includes a test master 110 that executes a test (referred to as “competition evaluation test”) for evaluating an access timing conflict condition, and an evaluation target macro 120 connected to the test master 110. The evaluation target macro 120 is a macro that realizes an original function of the FPGA product, such as a communication macro or a signal processing macro. In the embodiment shown in FIG. 1, the test master 110 is incorporated in the same FPGA as the evaluation target macro 120, but the present invention is not limited to such a configuration. For example, the test master 110 may be mounted on an FPGA different from the evaluation target macro 120 (preferably driven by a common clock).

  When executing the competition evaluation test, the test master 110 generates an access (command) that causes the CPU 200 to compete with the access to the evaluation target macro 120 and gives it to the evaluation target macro 120. In addition, the test master 110 issues a competition evaluation completion interrupt to the CPU 200.

  The test master 110 generates an access for evaluation to be hit against an access (command) to the evaluation target macro 120 from the CPU 200 at different timings.

  The CPU 200 analyzes each operation result when the competition timing is changed with respect to the evaluation target macro 120, thereby enabling the evaluation evaluation of the evaluation target macro 120. When the evaluation target macro 120 has access performance deteriorated depending on the timing of access contention and does not satisfy a predetermined standard, the present invention can detect the timing condition of contention.

  FIG. 2 is a diagram illustrating an example of the configuration of the test master 110. Referring to FIG. 2, the test master 110 includes a decoder 111, a selector 112, an operation B instruction storage unit 113, wait plus 1 (wait + 1) means 114, and an interrupt generation circuit 115.

  The decoder 111 receives the bus access 130 from the CPU 200. An access (command or instruction) input from the CPU 200 to the evaluation target macro 120 is transferred from the CPU 200 as the bus access 130 and is output to the evaluation target macro 120 via the selector 112. The decoder 111 inputs and decodes (monitors) the access from the CPU 200 transferred as the bus access 130. When the decoder 111 recognizes the competition evaluation start access as a result of the decoding, the decoder 111 outputs the competition evaluation start access 116 to the weight plus 1 (wait + 1) means 114 and the selector 112.

  The selector 112 inputs the result of decoding by the decoder 111 (contention evaluation start access 116) as a selection control signal, selects the bus access 130 from the CPU 200, and evaluates it as it is, except when the arrival of the contention evaluation start access is detected. As an access 140 to the target macro, it is output to the evaluation target macro 120.

  When a competition evaluation start access arrives from the CPU 200, the selector 112 receives the activation of the competition evaluation start access 116, selects an operation B instruction used for the competition evaluation of the evaluation target macro 120, and accesses the evaluation target macro. 140 is output to the evaluation target macro 120. For convenience, access to the evaluation target macro 120 from the CPU 200 is referred to as “operation A”, and access inserted for the timing conflict test by the test master 110 with respect to the operation A is referred to as “operation B”. An instruction that causes the evaluation target macro 120 to execute the operation B is referred to as an “operation B instruction”.

  When a competition evaluation start access arrives from the CPU 200 to the test master 110, the selector 112 selects the competition evaluation start access and supplies it directly to the evaluation target macro 120. Subsequently, the decoder 111 decodes the competition evaluation start access. Based on the result, the operation B instruction is supplied to the macro 120 to be evaluated at a predetermined timing defined by the wait plus 1 means 114.

  The operation B command storage unit 113 stores the operation B command in advance. The operation B instruction stored in the operation B instruction storage unit 113 is the timing set by the weight plus 1 (wait + 1) means 114 when the competition evaluation start access from the CPU 200 arrives (when the competition evaluation start access 116 is activated). And is selected by the selector 112.

  When a contention evaluation start access arrives from the CPU 200 (when the contention evaluation start access 116 is activated), the wait plus 1 (wait + 1) means 114 (timer counter) sets the clock of the evaluation target macro 120 to the current wait (wait). Add a delay corresponding to the clock cycle (wait + 1). Then, after the elapse of the delay time of the (wait + 1) cycle from the arrival of the competition evaluation start access, the operation B instruction is evaluated by the evaluation target macro 120 via the selector 112 (at this time, the selector 112 selects the operation B instruction). To give. Note that the test master 110 may input the clock of the evaluation target macro 120, or the clock of the evaluation target macro 120 and the clock of the test master 110 may be a common internal clock in the FPGA.

  When the competition test start period n (the time until the execution of the operation A and the operation B in the evaluation target macro 120) ends after the arrival of the competition evaluation start access, the interrupt generation circuit 115 (counter) Output a competition evaluation completion interrupt. That is, the interrupt generation circuit 115 completes the contention evaluation after the number of clock cycles corresponding to the sum of the wait time and the execution time of the operations A and B (the contention test period) has elapsed from the arrival of the contention evaluation start access. Output an interrupt. The interrupt generation circuit 115 (counter) includes, for example, a counter that counts the number of clock cycles for the contention test period from the arrival of the contention evaluation start access. , Interrupt the competition evaluation completion.

  When the CPU 200 receives the i-th competition evaluation completion interrupt from the test master 110, the CPU 200 performs (i + 1) -th (where i + 1 ≦ n) competition evaluation start access (operation A) for the evaluation target macro 120. However, the competition test ends when (i + 1)> n.

  FIG. 3 is a diagram schematically showing timing competition evaluation in the present embodiment. 3 shows the clock of the evaluation target macro 120, the timing of access from the CPU 200 (operation A), the timing of contention access from the test master 110 (operation B), and the contention evaluation completion interrupt generated by the test master 110. Are shown for each of the first, second,... N times.

  In FIG. 3, one end (left end) of the operation A corresponds to the timing of the operation A that is an access input from the CPU 200 to the evaluation target macro 120 via the test master 110. On the other hand, one end (left end) of the operation B in FIG. 3 corresponds to the input timing of the operation B instruction from the test master 110 to the evaluation target macro 120. The initial wait value (initial weight value) is obtained until the operation 200 corresponding to the access is started in the evaluation target macro 120 after the contention evaluation start access of the CPU 200 arrives at the test master 110 and is supplied to the evaluation target macro 120. Is the time.

  In FIG. 3, for the sake of simplicity, the operation A and the operation B are represented in parallel, but the operation A and the operation B do not necessarily have to be performed in parallel. When operation A and operation B compete for one common resource in the evaluation target macro 120, standby or time division is appropriately performed under the control of an arbiter circuit (not shown) in the evaluation target macro 120, a scheduler, and the like. Of course, scheduling such as processing may be executed. Further, in the macro 120 to be evaluated, when the access requests (commands) for the operations A and B are input, the operations A and B may be executed immediately or may not be executed. (For example, if the operation A is being executed when the operation B instruction is input, the execution of the operation B may be waited or suspended). Alternatively, the operation A corresponding to the access request from the CPU 200 may be prioritized over the operation B corresponding to the operation B command from the test master 110, or the operation B may be reversed to the operation A depending on the test specification. May be prioritized.

  After the first competition evaluation start access from the CPU 200 has arrived, the operation B instruction is input to the evaluation target macro 120 via the selector 112 after the initial wait value set on the test master 110 has elapsed. In the evaluation target macro 120, the operation A is executed after the initial wait value after the competition evaluation start access has arrived at the test master 110. Therefore, in the first test, the operation A is simultaneously executed in the evaluation target macro 120. , The operation B command is input. In the first test, the wait time in the wait plus 1 (wait + 1) means 114 after the arrival of the competition evaluation start access becomes the initial wait value.

  When the contention test period set in the test master 110 elapses after the arrival of the contention evaluation start access or when the bus access indicating the end of the operation A is input from the evaluation target macro 120 to the test master 110 The master 110 outputs a competition evaluation completion interrupt to the CPU 200.

  When the contention test period elapses, the interrupt generation circuit 115 of the test master 110 counts the number of clock cycles of the macro to be evaluated. When the count value reaches a predetermined value, the interrupt generation circuit 115 sends a contention evaluation completion interrupt to the CPU 200. Output. Alternatively, if the bus generation indicating the end of the operation A is input from the evaluation target macro 120 to the test master 110 while the interrupt generation circuit 115 is counting the number of clock cycles of the evaluation target macro, the interrupt generation circuit 115 sets the clock cycle. And the competition evaluation completion interrupt is output to the CPU 200. Alternatively, it is assumed that the operation A requires a longer number of clock cycles than the operation B. Alternatively, when a bus access indicating the end of both operation A and operation B is input from the evaluation target macro 120 to the test master 110, the interrupt generation circuit 115 stops the clock cycle counting operation and the CPU 200 completes the competition evaluation. An interrupt may be output.

  When the CPU 200 receives a competition evaluation completion interrupt from the test master 110, the CPU 200 reads the results of the operation A and the operation B of the evaluation target macro 120 and checks whether the operation A and the operation B are correctly performed in the evaluation target macro 120. . Assume that the evaluation target macro 120 holds the results of the operations A and B in a storage unit (not shown).

  The operations A and B are operations that have been arbitrated (access contention has been arbitrated) for accessing a common resource such as a RAM (Random Access Memory). Although not particularly limited, the operation A is a bus access that takes a relatively long time, and the operation B is, for example, a single access.

  In the second test, when the competition evaluation start access arrives from the CPU 200, the test master 110 detects the arrival of the competition evaluation start access by the decoder 111, and the wait plus 1 (wait + 1) means 114 uses the initial wait as the wait time. The time corresponding to one clock cycle of the clock of the evaluation target macro 120 is added to the value. Then, the operation B instruction is input to the evaluation target macro 120 via the selector 112 of the test master 110 when the evaluation target macro 120 starts the operation A and is delayed by one clock cycle. Is done. The test master 110 outputs a competition evaluation completion interrupt to the CPU 200 when the competition test period ends or when a bus access indicating the end of the operation A arrives. After receiving the competition evaluation completion interrupt from the test master 110, the CPU 200 reads the results of the operation A and the operation B of the evaluation target macro 120 and checks whether the operation A and the operation B are correctly performed in the evaluation target macro 120. To do.

  When the third competition evaluation start access arrives from the CPU 200, the test master 110 detects the arrival of the decoder 111 competition evaluation start access, and the weight plus 1 (wait + 1) means 114 evaluates the initial wait value as the wait time. The time corresponding to two clock cycles of the clock of the target macro 120 is added. Then, the operation B instruction is input to the evaluation target macro 120 via the selector 112 of the test master 110 when the evaluation target macro 120 starts the operation A and is delayed by two clock cycles. Is done. The test master 110 outputs a competition evaluation completion interrupt to the CPU 200 when the competition test period ends or when a bus access indicating the end of the operation A arrives. When the CPU 200 receives a competition evaluation completion interrupt from the test master 110, the CPU 200 reads out the execution result bits of the operation A and the operation B in the evaluation target macro 120, and determines whether the operation A and the operation B are correctly performed in the evaluation target macro 120. To check.

  After the nth competition evaluation start access arrives from the CPU, after the initial wait value + (n−1) clock cycles set in the test master 110, the operation B instruction is sent to the evaluation target macro 120 via the selector 112. Supplied. The test master 110 outputs a competition evaluation completion interrupt to the CPU 200 when the competition test period ends or when a bus access indicating the end of the operation A arrives. When receiving the competition evaluation completion interrupt from the test master 110, the CPU 200 reads the execution result bits of the operation A and the operation B in the evaluation target macro 120, and whether or not the operation A and the operation B are correctly performed in the evaluation target macro 120. To check.

  The wait plus 1 (wait + 1) means 114 of the test master 110 delays the input timing of the operation B instruction to the evaluation target macro 120 by one clock cycle. In the nth test, the start time of the operation A (initial wait value) ) To (n−1) clock cycles later than the evaluation target macro 120 of the operation B instruction.

  As shown in FIG. 3, the operation A ends in n clock cycles from the start point of the operation A (the time when the initial wait value has elapsed since the arrival of the competition evaluation start access). That is, in the above-described embodiment, the competition evaluation is sequentially performed by delaying the input time of the operation B instruction in units of one clock cycle in the entire time range from the start time of the operation A to each clock cycle immediately before the end. In this way, the competitive evaluation is performed with high accuracy, and the time required for the competitive evaluation is particularly shortened compared to the case of simulation. In this embodiment, it is needless to say that the operation B instruction input time may be delayed not in one clock cycle with the minimum resolution but in units of two clock cycles or more. Alternatively, in the time range from the start point of the operation A to each clock cycle immediately before the end, the input of the operation B instruction may be changed from the back to the front instead of the front to the back on the time axis.

  FIG. 4 is a flowchart showing the processing procedure of the timing competition evaluation of the evaluation target macro in this embodiment. FIG. 4 shows a processing procedure for one competition evaluation start access test. When n tests are executed as shown in FIG. 3, the process of FIG. 4 is repeated n times.

  Referring to FIG. 4, the test master 110 receives a competition evaluation start access from the CPU (step S1). If the test is the first time (YES in step S2), the test master 110 inputs an operation B command after the initial wait value (step S3). After a certain time (competition test period), the test master 110 issues a competition evaluation completion interrupt (step S4). After the competition evaluation completion interrupt output from the test master 110, the CPU 200 reads out the execution result bits of the operation A and the operation B (step S5). The test master 110 adds a delay for one clock cycle to the wait value (step S6). Subsequently, the process from step S1 is executed for the second and subsequent times. The test master 110 outputs the data of the CPU 200 as it is to the evaluation target macro except for the arrival of the competition evaluation start access. When the competition evaluation start access arrives, the test master 110 executes the competition evaluation of the operation A and the operation B with the evaluation target macro after the initial wait value set in accordance with the time from the arrival until the operation A starts. After the contention evaluation start access arrives, the contention test period set in the test master 110 elapses, or when the bus access indicating the end of the operation A arrives, the test master 110 sends a contention evaluation completion interrupt to the CPU. Output. After receiving this interrupt, the CPU 200 reads out the results of the operations A and B and determines the results. Each time a competition evaluation start access arrives, execution of operation B is delayed by one clock cycle of the macro to be evaluated, and competition evaluation is performed.

  According to the present invention, it is possible to perform timing competition evaluation that cannot be realized by related technologies and the like, and it is possible to deal with random competition evaluation start by controlling the input timing of the operation B instruction.

  Next, as an embodiment of the present invention, a case where the evaluation target macro 120 of FIG. 1 is a communication macro will be described with reference to FIG. In this embodiment, the operation A is a communication macro transmission operation. When a transmission command is received from the CPU 200 to the communication macro 121, the communication macro 121 searches a message buffer register in the RAM 122 for a message as a transmission candidate, and determines a transmission message from the retrieved transmission candidate messages. And send the determined message. During most of the operation A, the communication macro 121 accesses the RAM 122 and searches for transmission candidates. The result of the operation A transmission operation is determined by whether or not an ACK (acknowledgment) from the communication macro 121 is transmitted.

  The operation B is an operation for rewriting a predetermined bit in the RAM 122. The access to the RAM 122 in the operation B conflicts with the search operation A in the RAM 122 by the operation A. When the test master 110 receives a rewrite command to the communication macro 121, the communication macro 121 accesses the RAM 122. The success or failure of the rewrite result by the operation B can be determined by whether or not the target bit is correctly rewritten.

  In the present embodiment, it is possible to evaluate whether the operation A and the operation B both end normally even if the operation B interrupts at any point in time of the operation A (clock unit of the macro to be evaluated). Also, it can be evaluated whether the operation B interrupts when the operation B interrupts at any point in time of the operation A (clock unit of the macro to be evaluated).

  It should be noted that the disclosures of the above patent documents are incorporated herein by reference. Within the scope of the entire disclosure (including claims) of the present invention, the embodiments and the embodiments can be changed and adjusted based on the basic technical concept. Various combinations and selections of various disclosed elements are possible within the scope of the claims of the present invention. That is, the present invention of course includes various variations and modifications that could be made by those skilled in the art according to the entire disclosure including the claims and the technical idea.

2 Test equipment 10 Multiplexer (MUX)
11-13 FPGA-ac
17 Semiconductor integrated circuit
100 test equipment (FPGA)
110 Test Master 111 Decoder 112 Selector 113 Operation B Instruction Storage Unit 114 Wait Plus 1 (Wait + 1) Means 115 Interrupt Generation Circuit (Counter)
116 Competition evaluation start access
120 Macro to be evaluated 121 Communication macro 122 RAM
130 Bus access 140 Access between test master and evaluation target macro
150 Competitive evaluation completion interrupt 200 CPU
210 bus

Claims (15)

  When access to the evaluation target circuit from the host device is monitored and the arrival of a predetermined contention evaluation start access is detected, a predetermined instruction stored and held in advance for a conflict test is applied to the access from the host device. And a test circuit that is inserted into the circuit to be evaluated at a predetermined timing.   A circuit in which the test circuit varies the timing of input of the instruction for the contention test to the evaluation target circuit over a part or all of the timing interval from the start to the end of the operation of the evaluation target circuit for the access; The semiconductor device according to claim 1, further comprising:   The test circuit starts counting a predetermined number of clock cycles corresponding to the contention test period after the arrival of the contention evaluation start access, and counts the number of clock cycles for the contention test period after the arrival of the contention evaluation start access. 3. The semiconductor device according to claim 2, further comprising an interrupt circuit for notifying the higher-level device of a competition evaluation completion interrupt at the time.   The test circuit starts counting a predetermined number of clock cycles corresponding to the contention test period after the arrival of the contention evaluation start access, and counts the number of clock cycles for the contention test period after the arrival of the contention evaluation start access. 3. The competitive evaluation completion interrupt is notified to the higher-level device at the time when the notification is received or when the operation completion corresponding to the access is received from the evaluation target circuit. Semiconductor device.   The host device that has received the competition evaluation completion interrupt from the test circuit reads out the operation result corresponding to the access from the host device and the operation result of the predetermined instruction for the competition test from the evaluation target circuit. 5. The semiconductor device according to claim 3, wherein competition evaluation is performed. In the first test, after an initial wait time that is a predetermined time from the arrival of the contention evaluation start access to the test circuit, the operation for the access is executed in the evaluation target circuit.
In the test circuit, when the wait initial value has elapsed since the arrival of the competition evaluation start access, the predetermined instruction for the competition test is input to the evaluation target circuit,
In the second and subsequent tests, in the test circuit, the predetermined instruction for the contention test is input to the circuit to be evaluated at a timing delayed by unit time from the initial value of wait after the arrival of the contention evaluation start access. The semiconductor device according to claim 1, wherein the semiconductor device is a semiconductor device. A decoder that receives and decodes a bus access to the evaluation target circuit from the host device;
A storage unit for storing and holding the predetermined instruction for the competition test;
A selector that receives, as a first input, a bus access from the host device to the evaluation target circuit;
A timer counter that outputs a predetermined instruction for the contention test stored in the storage unit to a second input of the selector at a predetermined timing;
With
The selector inputs the arrival detection result of the contention evaluation start access by the decoder as a selection control signal, and when the arrival of the contention evaluation start access is detected by the decoder, at the predetermined timing, 7. The semiconductor device according to claim 1, wherein the predetermined instruction for the contention test supplied to the input is supplied to the circuit to be evaluated.   2. The test circuit that performs competition evaluation between the evaluation target circuit and the evaluation target circuit is mounted on the same or different FPGA (Field Programmable Gate Array) chip and operates on the same clock. 8. The semiconductor device according to any one of 7 above. The test circuit monitors access to the evaluation target circuit from the host device,
When the test circuit detects the arrival of a predetermined contention evaluation start access, a predetermined instruction stored and held in advance for a contention test is transmitted in a predetermined timing relationship with respect to the access from the host device. A test method characterized in that the test method is put into the circuit to be evaluated.   The test circuit varies the timing of input of the instruction for the contention test to the evaluation target circuit over a part or all of the timing interval from the start to the end of the operation of the evaluation target circuit for the access. The test method according to claim 9.   The test circuit starts counting a predetermined number of clock cycles corresponding to the contention test period after the arrival of the contention evaluation start access, and counts the number of clock cycles for the contention test period after the arrival of the contention evaluation start access. 11. The test method according to claim 10, wherein a competition evaluation completion interrupt is notified to the higher-level device at the point of time.   The test circuit starts counting a predetermined number of clock cycles corresponding to the contention test period after the arrival of the contention evaluation start access, and counts the number of clock cycles for the contention test period after the arrival of the contention evaluation start access. 11. The test method according to claim 10, wherein a competition evaluation completion interrupt is notified to the higher-level device at the time of being received, or when an operation end notification corresponding to the access is received from the evaluation target circuit. .   The host device that has received the contention evaluation completion interrupt from the test circuit receives an operation result corresponding to the access from the host device and an operation result of the predetermined instruction for the contention test from the evaluation target circuit. The test method according to claim 11, wherein reading and competition evaluation are performed. In the first test, after an initial wait time that is a predetermined time from the arrival of the contention evaluation start access to the test circuit, the operation for the access is executed in the evaluation target circuit.
In the test circuit, when the wait initial value has elapsed since the arrival of the competition evaluation start access, the predetermined instruction for the competition test is input to the evaluation target circuit,
In the second and subsequent tests, in the test circuit, the predetermined instruction for the contention test is input to the circuit to be evaluated at a timing delayed by unit time from the initial value of wait after the arrival of the contention evaluation start access. The test method according to any one of claims 9 to 13, wherein:   15. The test circuit that performs competitive evaluation between the evaluation target circuit and the evaluation target circuit is mounted on the same or different FPGA (Field Programmable Gate Array) chip and operates with the same clock. The test method according to any one of the above.

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