JP2011040977A - Device for importing and holding data - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a device for importing and holding data capable of importing input data without an error. <P>SOLUTION: The device for importing and holding data includes a holding means having a first data importing/storing part for importing and holding input data in a pulse width zone of a latching pulse PLS from a pulse generation means 20. The pulse generation means 20 includes a second data importing/storing part 231 of a structure identical or equivalent to that of the first data importing/storing part, generates pulse signals PLS in a pulse width zone for an importing time of input data in the second data importing/storing part 231 from clock signals CLK, and supplies the generated pulse signals to the first data importing/storing part as latching pulses. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a data capturing / holding device that latches and captures input data consisting of, for example, one bit or a plurality of bits.

  As a data capturing / holding device that captures and stores input digital data in synchronization with a clock signal, a device that uses a so-called D latch (through latch) as shown in FIG. (For example, see Patent Document 1 (Japanese Patent Laid-Open No. 11-259274)).

  FIG. 17 shows a data capturing / holding device per bit. The input data Din (see FIG. 18A) is supplied to the D input terminal of the D latch circuit 1 serving as a data take-in storage unit.

  Then, the clock signal CLK (see FIG. 18B) is supplied to the pulse generator 2. In this example, the pulse generator 2 generates a pulse signal Ps (see FIG. 18C) having a predetermined pulse width from the rising point of the clock signal CLK.

  The pulse signal Ps from the pulse generator 2 is a signal having two phases, a phase inverted by the inverter 3 and a phase inverted by the inverter 4, and is supplied to the D latch circuit 1 as a latching pulse. Is done.

  As a result, in the D latch circuit 1, the input data Din is captured during the pulse width period of the pulse signal Ps, and the output in which the input data Din captured during the pulse width period is held after the pulse width period of the pulse signal Ps. A signal Dout (see FIG. 18D) is obtained.

  That is, the D latch circuit 1 takes in the input data Din in the pulse width period of the pulse signal Ps, generates the output signal Dout that holds it, and outputs it.

  By the way, the pulse width of the pulse signal Ps from the pulse generator 2 needs to have a time width equal to or greater than the input data capture (write) time required by the data capture storage unit (D latch circuit 1). There is. This is because if the pulse width of the pulse signal Ps is shorter than the input data capture (write) time required by the D latch circuit 1, the input data capture (write) will fail, resulting in malfunction.

  FIG. 19 shows a configuration diagram of an example of a conventional pulse generator 2. The pulse generator 2 in this example is called a delay difference type, and includes a NAND gate 3, an inverter 4, and an inverter chain 5 in which a plurality of inverters are connected in series.

  Then, the clock signal CLK (see FIG. 20A) is supplied as it is to one input terminal of the NAND gate 3 and is also supplied to the inverter chain 5, delayed by the number of inverters, and the delayed clock signal DCLK (FIG. 20). (See (B)). The delayed clock signal DCLK is supplied to the other input terminal of the NAND gate 3.

  Accordingly, in the example of FIG. 19, a pulse signal Ps having a pulse width period corresponding to the number of inverters in the inverter chain 5 is generated. That is, in the case of the configuration of the example of FIG. 19, the number of inverters in the inverter chain 5 is adjusted so as to guarantee the input data capture (write) time required by the D latch circuit 1.

  FIG. 21 shows a pulse generator called a skewed inverter type, which generates a pulse signal by duty ratio modulation.

  In this example, the clock signal CLK (see FIG. 22A) is supplied to the inverter chain 6 of a plurality of inverters 6a, 6b, 6c, 6d connected in series. The modulation ratio of the duty ratio modulation is determined by the degree of deviation of the pn ratio of each inverter in the inverter chain 6. Here, the pn ratio is the size ratio of the p-type MOSFET and the n-type MOSFET in each inverter.

  In this example, the size ratio of the p-type MOSFET and the n-type MOSFET in the inverters 6a and 6c in the inverter chain 6 is 3: 1, and the ratio of the p-type MOSFET and the n-type MOSFET in the inverters 6b and 6d is 1: It is set to 1.

  In the case of the example of FIG. 21, the pulse generator 2 generates a pulse signal Ps having a duty ratio of 20:80 from a clock signal CLK having a duty ratio of 50:50, as shown in FIG. Generated.

  In the case of the example of FIG. 21, if the cycle of the clock signal CLK is fixed, the pulse width of the pulse signal Ps is determined by the inverter chain 6 built in advance.

JP 11-259274 A

  As described above, the conventional pulse generator is determined by the delay time by the inverter chain built in advance.

  By the way, it is generally well known that the operation speed of a circuit varies depending on the process variation of how to combine a low-speed element, a high-speed element, etc. as elements constituting the circuit, the operating temperature of the circuit, the operating voltage, etc. ing. When such a variation factor occurs, the data write time (capture time) required by the data capture / holding device (D latch circuit 1) and the pulse width of the pulse signal Ps from the pulse generator 2 vary. To do.

  Since the data acquisition and holding device and the pulse generator are different in circuit, there is no guarantee that the method of fluctuation and the rate of fluctuation will be the same.

  For this reason, when the above fluctuation factors occur, the pulse width of the pulse signal Ps is equal to or longer than the input data capture (write) time required by the data capture and holding device (D latch circuit 1). In some cases, the relationship having the time width cannot be maintained. That is, the pulse width of the pulse signal Ps becomes shorter than the input data capture (write) time required by the D latch circuit 1, and the input data capture (write) may fail, leading to a malfunction.

  An object of the present invention is to provide a data capturing / holding device that can avoid the above-described problems even when the above-described fluctuation factors occur.

In order to solve the above problems, a data capturing / holding device according to the present invention provides:
Holding means comprising a first data acquisition storage unit for acquiring and holding input data in a pulse width section of a latching pulse;
A second data capture storage unit having the same or equivalent configuration as the first data capture storage unit, and a pulse corresponding to a capture time of input data in the second data capture storage unit from a clock signal Pulse generating means for generating a pulse signal of a width section and supplying the pulse signal as the latch pulse to the first data capture storage unit;
It is characterized by providing.

  In the data capturing / holding device configured as described above, the pulse generating means includes a first data capturing / storage unit having the same or equivalent configuration as the first data capturing / storing unit, and the second data capturing / storing unit. A pulse signal of a pulse width interval corresponding to the input data capture time in the unit is generated. Then, the generated pulse signal is supplied to the first data capture storage unit as a latch pulse for input data.

  If the operation speed of the circuit fluctuates due to the fluctuation factors as described above, the first data acquisition storage unit and the pulse generation unit have the same or equivalent data acquisition storage unit. Therefore, the operating speed fluctuations in them are almost the same.

  For this reason, even if the data acquisition time in the first data acquisition storage unit fluctuates, the pulse width of the pulse signal from the pulse generator also varies in the same manner, and the pulse width of the pulse signal is the same as the first data acquisition unit. It is possible to prevent the input data required by the storage unit from being shorter than the input data capture time. As a result, it is possible to prevent a malfunction due to a failure in fetching input data into the first data fetch storage unit.

  According to the present invention, even if the data acquisition time in the first data acquisition storage unit varies, the pulse width of the pulse signal from the pulse generator also varies in the same manner, so the first data acquisition storage unit It is possible to prevent malfunction due to failure in fetching input data into the.

It is a block diagram which shows the whole structure of embodiment of the data taking-in holding | maintenance apparatus by this invention. It is a figure which shows the structural example of the bit latch part as a data acquisition memory | storage part which comprises a part of embodiment of the data acquisition holding | maintenance apparatus by this invention. It is a figure which shows the structural example of the pulse generation part which comprises a part of embodiment of the data acquisition holding | maintenance apparatus by this invention. It is a figure which shows the timing chart used in order to demonstrate operation | movement of the pulse generation part of the example of FIG. It is a figure used in order to demonstrate the effect of the embodiment of the data acquisition holding device by this invention. It is a figure which shows the other structural example of the pulse generation part which comprises a part of embodiment of the data acquisition holding | maintenance apparatus by this invention. It is a figure which shows the timing chart used in order to demonstrate operation | movement of the pulse generation part of the example of FIG. It is a figure used in order to demonstrate the effect of the embodiment of the data acquisition holding device by this invention. It is a block diagram which shows the prior art example of a data acquisition holding device of a double edge trigger type. It is a figure which shows the structural example of the pulse generation part which comprises a part of embodiment in the case of the double edge trigger type of the data acquisition holding | maintenance apparatus by this invention. It is a figure which shows the timing chart used in order to demonstrate operation | movement of the pulse generation part of the example of FIG. FIG. 11 is a block diagram of a configuration example of a partial circuit of the pulse generation unit in the example of FIG. 10. FIG. 11 is a block diagram of a configuration example of a partial circuit of the pulse generation unit in the example of FIG. 10. FIG. 11 is a block diagram of a configuration example of a partial circuit of the pulse generation unit in the example of FIG. 10. It is a figure used in order to demonstrate the effect of the embodiment in the case of the double edge trigger type of the data acquisition holding device by this invention. It is a figure used in order to demonstrate the effect of the embodiment in the case of the double edge trigger type of the data acquisition holding device by this invention. It is a block diagram for demonstrating an example of the conventional data taking-in holding | maintenance apparatus. It is a figure which shows the timing chart used in order to demonstrate the prior art example of FIG. It is a block diagram which shows the structural example of the pulse generation part in the conventional data acquisition holding | maintenance apparatus. It is a figure which shows the timing chart used in order to demonstrate the pulse generation part of the prior art example of FIG. It is a block diagram which shows the other structural example of the pulse generation part in the conventional data acquisition holding | maintenance apparatus. FIG. 21 is a diagram used for explaining the conventional pulse generator of FIG. 20.

  DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of a data capture / holding device according to the present invention will be described below with reference to the drawings.

[First Embodiment]
FIG. 1 is a block diagram showing an example of the overall configuration of an embodiment of a data capturing / holding device according to the present invention. The example of FIG. 1 is a case where 8-bit input data Din0 to Din7 are captured and held by the pulse signal PLS.

  As shown in FIG. 1, in this embodiment, the data fetching and holding device fetches and holds each bit data Din0, Din1, Din2,..., Din7 of the input data. , 17 and a pulse generator 20.

  Each of the bit latch units 10, 11, 12,..., 17 corresponds to a holding means for each bit data and has the same configuration. Each of the bit latch units 10, 11, 12,..., 17 includes a data input terminal, a latch pulse input terminal, and a data output terminal. An internal configuration example of these bit latch units 10, 11, 12,..., 17 will be described later.

  Each of the bit data Din0, Din1, Din2,..., Din7 of the input data is input to the data input terminals of these bit latch units 10, 11, 12,.

  The pulse generator 20 generates a pulse signal PLS having a predetermined pulse width from the rising point in this example while rising or falling of the clock signal CLK input thereto. A configuration example of the pulse generator 20 will be described later.

  The pulse signal PLS generated by the pulse generator 20 is commonly supplied to the latch pulse input terminals of the bit latch units 10, 11, 12,.

  Each of the bit latch units 10 to 17 latches each input bit data Din0 to Din7 during the pulse width period of the pulse signal PLS. Each of the bit latch units 10 to 17 outputs the output data Dout0 to Dout7 from the data output terminal by holding the latched value after the pulse width period.

<Example of Bit Latches 10-17>
As described above, since the bit latch units 10 to 17 have exactly the same configuration, in the following description, the configuration example will be described using the bit latch unit 10 as an example.

  FIG. 2 is a diagram illustrating an internal configuration example of the bit latch unit 10. The bit latch unit 10 includes a 1-bit storage unit 101 and inverters 102, 103, and 104. The 1-bit storage unit 101 corresponds to the first data capture storage unit.

  In this example, the 1-bit storage unit 101 is a three-state buffer type 1-bit storage cell. That is, as shown in FIG. 2, the 1-bit storage unit 101 of this example includes a three-state buffer 110 that receives input bit data Din0, and a keeper (holding unit) 111 provided on the output side of the three-state buffer 110. It consists of.

  The keeper 111 includes a three-state buffer 112 and an inverter 113. The output signal of the three-state buffer 110 is inverted in polarity by the inverter 113 and supplied to the three-state buffer 112. The output of the three-state buffer 112 is supplied to the output side of the three-state buffer 110, that is, the output terminal of the 1-bit storage unit 101.

  In the example of FIG. 2, since the output of the 1-bit storage unit 101 is obtained by inverting the polarity of the input bit data Din0, the polarity is inverted by the inverter 102 to obtain the output Dout0 of the bit latch unit 10.

  The pulse signal PLS from the pulse generator 20 is inverted in polarity by the inverter 103 and supplied to the 1-bit storage unit 101, and further returned to the original polarity by the inverter 104 and supplied to the 1-bit storage unit 101. . In the 1-bit storage unit 101, the two phase signals φ, φ! (In this specification, φ! Has the same meaning as an overbar of φ, and! Means an inverted phase) is a gate control signal for the three-state buffers 110 and 112.

  In this example, two phase signals φ, φ! However, [φ, φ! ] = [1, 0], the three-state buffer 110 is controlled to be opened and the three-state buffer 112 is controlled to be closed (high impedance state). Also, the two phase signals φ, φ! However, [φ, φ! ] = [0, 1], the three-state buffer 112 is controlled to be opened, and the three-state buffer 110 is controlled to be closed (high impedance state).

  In this specification, the signal state “1” means a high level state, and the signal state “0” means a low level state.

  That is, in the pulse width section of the pulse signal PLS, the three-state buffer 110 is in the gate open state and the three-state buffer 112 is in the gate closed state, and in the section after the pulse width section, the reverse state is performed.

  Therefore, the bit latch unit 10 operates as follows.

  When the pulse width section in which the pulse signal PLS supplied to the bit storage unit 10 is “1” is reached, the three-state buffer 110 of the 1-bit storage unit 101 is in a gate open state. Therefore, the input bit data Din0 is passed through in the pulse width section of the pulse signal PLS and is directly used as output data Dout0.

  Then, in the period after the pulse width period of the pulse signal PLS (the pulse signal PLS is in the “0” state), the three-state buffer 110 is in the gate closed state, but the three-state buffer 112 is in the gate open state. Therefore, the output of the three-state buffer 110 is held in the keeper 111.

  Thus, the data captured and held in the 1-bit storage unit 101 in the pulse width section of the pulse signal PLS is inverted in polarity by the inverter 102 and then becomes output data Dout0.

<Example of pulse generator 20>
FIG. 3 shows a block diagram of a configuration example of the pulse generator 20 in this embodiment. The pulse generator 20 of this embodiment includes a NAND gate 21 and an inverter 22 that constitute a pulse generator that generates a pulse signal PLS, and a chopper circuit 23. The chopper circuit 23 constitutes trailing edge timing generation means for generating the trailing edge timing of the pulse width section of the pulse signal PLS.

  The clock signal CLK is supplied to one input terminal of the NAND gate 21, and the output signal CHP from the chopper circuit 23 is supplied to the other input terminal. When the output signal CHP from the chopper circuit 33 is “1” and the rising edge of the clock signal CLK arrives, the polarity of the output of the NAND gate 21 is inverted by the inverter 22 so that the pulse signal rises to “1”. A PLS is generated.

  The chopper circuit 23 has a function of generating a pulse width period of the pulse signal PLS. In this example, the chopper circuit 23 includes a 1-bit storage unit 231 having the same configuration as each 1-bit storage unit 101 of the bit latch units 10 to 17. To do. However, in the case of the 1-bit storage unit 231, in this example, a low level (ground level) is input instead of input bit data.

  Further, the chopper circuit 23 includes not only the 1-bit storage unit 231 but also an inverter 232 and inverters 233 and 234 as in the bit latch unit 10 described above. That is, the output of the chopper circuit 23 is inverted in polarity by the inverter 232 to become the output signal CHP.

  The inverter 233 is supplied with the pulse signal PLS which is the output of the inverter 22, and the two phase signals φ! Of the pulse signal PLS from the inverters 233 and 234 are supplied. , Φ are supplied to the 1-bit storage unit 231.

  That is, in the pulse generation unit 20 of this example, the circuit portion including the 1-bit storage unit 231 and the inverters 232, 233, and 234 in the chopper circuit 23 is exactly the same as the bit latch unit 10.

  However, the chopper circuit 23 of the pulse generator 20 is not exactly the same as the bit latch unit 10. That is, as shown in FIG. 3, the connection point between the output terminal of the 1-bit storage unit 231 and the inverter 232 is grounded via a switch 235 made of an n-type MOSFET in this example.

  The clock signal CLK is supplied to the gate of the n-type MOSFET constituting the switch 235 with the polarity inverted by the inverter 236. Therefore, in a section where the clock signal CLK is “0” (low level), the input side of the inverter 232 is always at the ground potential because the switch 235 is turned on, and the output signal CHP is in the “1” state.

  Further, in a section where the clock signal CLK is “1” (high level), the switch 235 is turned off, so that the output of the 1-bit storage unit 231 is supplied to the input side of the inverter 232, and the output signal CHP corresponds to the output of the 1-bit storage unit 231.

  In other words, in the example of FIG. 3, by enabling the output of the 1-bit storage unit 231 in the “1” section of the clock signal CLK, the pulse signal having the rising edge of the clock signal CLK as the leading edge of the pulse width section. A PLS is generated.

  Next, the pulse generation operation of the pulse generator 20 of this example will be described with reference to the timing chart of FIG.

  When the clock signal CLK is “0” before the rising of the clock signal CLK (see FIG. 4A), the switch 235 is supplied with a polarity inversion signal (see FIG. 4B) of the clock signal CLK. Therefore, this switch 235 is on. Therefore, the input side of the inverter 232 is at the ground potential, and the output signal CHP (see FIG. 4C) is in the “1” state.

  When the clock signal CLK is “0”, since one input of the NAND gate 21 is “0”, the pulse signal PLS (see FIG. 4D) is in the “0” state. .

  When the clock signal CLK rises and becomes “1”, the pulse signal PLS becomes “1” through the pulse generation unit including the NAND gate 21 and the inverter 22, and the leading edge of the pulse width (rising of the pulse) is formed. The

  In response to the pulse signal PLS becoming “1”, the bit latch units 10 to 17 start taking (writing) the input data Din0 to Din17. At the same time, the chopper circuit 23 starts taking in (writing) input data (ground potential = “0”) in the 1-bit storage unit 231 to which the pulse signal PLS is supplied through the inverters 233 and 234.

  At this time, when the pulse signal PLS is “1”, the clock CLK is [1] and the switch 235 is OFF. Therefore, the output of the 1-bit storage unit 231 is inverted through the inverter 232 and is output as the output signal CHP. It is in an output state.

  When the pulse signal PLS is “1” and the potential of the input data (ground potential) captured by the 1-bit storage unit 231 of the chopper circuit 23 reaches a sufficient level as the logical potential, the 1-bit storage unit 231 The output is “1”.

  Then, the output signal CHP of the chopper circuit 23 becomes “0”, and the pulse signal PLS also becomes “0”. That is, it is the trailing edge (falling edge of the pulse) of the pulse width period of the pulse signal PLS. In this case, a write time margin in the 1-bit storage unit 231 is added to the pulse width of the pulse signal PLS.

  As described above, a pulse equal to the input data capture time in the 1-bit storage unit 101 included in each of the bit latch units 10 to 17 is output from the pulse generation unit 20 by the 1-bit storage unit 231 of the chopper circuit 23. A pulse signal PLS having a width is obtained.

  In this embodiment, the 1-bit storage unit 231 of the chopper circuit 23 has the same configuration as the 1-bit storage unit 101 included in each of the bit latch units 10 to 17. Therefore, even if the operation speed of the 1-bit storage unit 101 fluctuates due to process variations, circuit operating temperature, operating voltage, etc., the pulse width of the pulse signal PLS fluctuates so as to follow it. Data import (write) failures can be avoided.

  FIG. 5 shows an operation waveform in the pulse generator 20 of the embodiment described above and a comparison with respect to process variations.

  FIGS. 5A to 5D show operation waveforms in the pulse generation unit 20 in the combination of the n-type MOSFET and the p-type MOSFET constituting the entire circuit of the 1-bit storage unit. For example, “SlowSlow” means a case where the n-type MOSFET and the p-type MOSFET are both low-speed type elements and the entire circuit of the 1-bit storage unit is configured. Further, for example, “SlowFast” means a case where an n-type MOSFET is a low-speed type element and a p-type MOSFET is a high-speed type element and the entire circuit of the 1-bit storage unit is configured.

  5A to 5D, the solid line indicates the clock signal CLK. A fine broken line shows an operation waveform of the pulse signal PLS. A rough broken line indicates an operation waveform of a signal obtained at the output terminal of the 1-bit storage unit 231 of the chopper circuit 23. A one-dot chain line indicates an operation waveform of a signal obtained at the output terminal of the 1-bit storage unit 101 of the bit latch unit.

  As can be seen from FIG. 5, the pulse signal PLS is generated in synchronization with the rising edge of the clock signal CLK.

  The holding node potential waveform (coarse broken line) in the 1-bit storage unit 231 of the chopper circuit 23 and the holding node potential waveform (one-dot chain line) in the 1-bit storage unit 101 for data latching are extremely different during the data write operation. You can see that they are very similar. Moreover, even if the process variation conditions are variously changed as shown in FIGS.

  In the pulse width period of the pulse signal PLS (fine broken line), the held node potential waveform (one-dot chain line) of the 1-bit storage unit 101 for data latch reaches the sufficiently stable potential of the captured data. You can see that

  In the above-described embodiment, the 1-bit storage unit 231 of the chopper circuit 23 captures only one of the two data input values, that is, the low level in this example. Therefore, when the input captured by the 1-bit storage unit 101 of the bit latch unit is different from the input data level captured by the 1-bit storage unit 231, the pulse width period of the pulse signal PLS is captured by the 1-bit storage unit 101. It does not exactly match the time.

  Therefore, in practice, tuning is also required in the pulse generator 23. However, in the case of the conventional case, verification work under various conditions is required. In this embodiment, it is necessary to verify the predetermined preset to be captured by the 1-bit storage unit 231. Only when the value is different from the input data level. For this reason, the verification work becomes very easy as compared with the prior art.

  It is obtained by providing two chopper circuits each having a 1-bit storage unit that uses each of the two values fetched by the 1-bit storage unit 101 of the bit latch unit as a preset value and combining the outputs of the two chopper circuits. You may comprise so that a chop signal may be used.

  In addition, according to the data fetching and holding device of this embodiment, there is also an effect that high speed operation is achieved. That is, the conventional general data fetching and holding device of this type uses a master-slave type flip-flop as a latch circuit.

  For high-speed operation of the data fetching and holding device, it is important that the operation speed of the latch circuit (flip-flop circuit), in particular, the insertion delay is small. Here, the insertion delay is the time consumed by the latch circuit (flip-flop circuit) in one cycle of the clock signal CLK, and the shorter this is, the faster the operation is.

  Generally, the insertion delay is defined as the sum of a setup time and a valid delay. In the conventional master-slave flip-flop, a write time to the master side latch is required immediately before the rise of the clock signal CLK, and this is the setup time.

  On the other hand, each of the bit latch units 10 to 17 in the data fetching and holding device of the above-described embodiment does not have a write operation immediately before the rising of the clock signal CLK. For this reason, the setup time is zero.

  In the case of the conventional master-slave type flip-flop, the valid delay is substantially equal to the data writing time from the master side latch to the slave side latch. On the other hand, in this embodiment, the valid delay is substantially equal to the writing time to the 1-bit storage unit 101. Therefore, the valid delay is considered to be substantially the same between the conventional case and the case of this embodiment.

  From the above, the data acquisition and holding device of the above-described embodiment has a smaller insertion delay because there is no setup time compared to the data acquisition and holding device using the conventional master-slave flip-flop, High speed operation is possible.

  In the embodiment of FIG. 1, since the input data Din is 8 bits, eight bit latch circuits 10 to 17 are provided. However, the number of bit latch circuits is equal to the number of bits of the input data Din. Needless to say, a number corresponding to the number is provided.

[Second Embodiment (Another Example of Pulse Generator)]
In the actual use in the data fetching and holding apparatus shown in FIG. 1, it is essential to control the execution / stop of the operation of the data latch function by the enable signal. The second embodiment is a data capturing / holding device having this enable function.

  The basic overall configuration of the data fetching and holding apparatus of the second embodiment is the same as that of the first embodiment shown in FIG. Each of the configurations of the bit latch units 10 to 17 has the configuration shown in FIG. 2 just as in the first embodiment.

  In the second embodiment, the configuration of the pulse generator 20 is partially different from that of the first embodiment. FIG. 6 is a diagram showing a configuration example of the pulse generation unit 20 in the second embodiment, and the same reference numerals are given to the same parts as those in the example of FIG.

  The pulse generator 20 of the second embodiment is different in that a chopper circuit 24 is provided instead of the chopper circuit 23 of the pulse generator 20 of the first embodiment. That is, as shown in FIG. 6, the configuration of the part that generates the pulse signal PLS in the chopper circuit 24 of the pulse generator 20 of the second embodiment is the same as that of the pulse generator 20 of the first embodiment. .

  That is, the chopper circuit 24 includes a 1-bit storage unit 231, inverters 233 and 234, a switch 235, and an inverter 236, and generates a pulse signal PLS as in the first embodiment.

  The chopper circuit 24 of the pulse generator 20 of the second embodiment is further different from the first embodiment in that a so-called clock enabler 241 is additionally provided.

  The clock enabler 241 includes a 1-bit storage unit 242 having the same configuration as the 1-bit storage unit 101 and the 1-bit storage unit 231, and an inverter 243.

  An enable signal EN is supplied as input data to the 1-bit storage unit 242. The clock signal CLK is supplied to the 1-bit storage unit 242 through the inverter 236, and the polarity inversion signal of the clock signal CLK from the inverter 236 is further supplied to the 1-bit storage unit 242 through the inverter 243.

  That is, in the 1-bit storage unit 242, the two phase signals φ and φ! Is supplied as a gate control signal for a three-state buffer built in the 1-bit storage unit 242.

  Thus, the enable signal EN is latched and held by the clock signal CLK. In this example, the pulse signal PLS is a pulse whose leading edge is the rising edge of the clock signal CLK. However, in the 1-bit storage unit 242, the enable signal is generated by the falling edge of the clock signal CLK before the generation of the pulse signal PLS. EN is latched and held.

  In the chopper circuit 24 of the pulse generator 20 of the second embodiment, a NOR gate 244 is provided instead of the inverter 232. One input terminal of the NOR gate 244 is connected to a connection point between the output terminal of the 1-bit storage unit 231 and the switch 235. As the other input of the NOR gate 244, the latch output CEN of the enable signal EN by the clock signal CLK from the 1-bit storage unit 242 of the clock enabler 241 is supplied.

  The output signal of the NOR gate 244 is used as the output signal CHP of the chopper circuit 24.

  The operation of the pulse generator 20 in the second embodiment having the above configuration will be described with reference to the timing chart of FIG.

  As shown in FIG. 7A, in this example, the enable signal EN that controls execution / stop of the operation of the data latch function is set to “1” when it should be in an enable state for executing the operation of the data latch function. . The enable signal EN is set to “0” when it should be in a disabled state that stops the operation of the data latch function.

  Since the enable signal EN is latched and held at the falling edge of the clock signal CLK (see FIG. 7B) in the 1-bit storage unit 242 of the clock enabler 241, the output signal CEN of the 1-bit storage unit 242 is As shown in FIG. 7C. That is, the output signal CEN of the 1-bit storage unit 242 is set to “1” only in one or a plurality of period sections (one period section in FIG. 7) of the clock signal CLK designated as being disabled by the enable signal EN. The

  On the other hand, as described in the first embodiment, the signal DS obtained at one input side of the NOR gate 244, that is, at the connection point between the output terminal of the 1-bit storage unit 231 and the switch 235 is shown in FIG. ). That is, the signal DS is “0” in the low level section of the clock signal CLK, and the time from the rising edge to the completion of writing of the input data in the 1-bit storage unit 231 is high in the high level section of the clock signal CLK. , “0”, and thereafter “1”.

  Therefore, the signal CHP which is a NOR gate output of the signal DS and the output signal CEN of the clock enabler 241 is, as shown in FIG. 7E, one or a plurality of period sections (see FIG. 7) of the clock signal CLK designated as the disabled state. 7 is “0” in one period section).

  Therefore, in the NAND gate 21 constituting the pulse generation unit, the generation of the pulse signal PLS is stopped in one or a plurality of period sections (one period section in FIG. 6) of the clock signal CLK designated as the disabled state (FIG. 6). 7 (F)).

  As described above, the pulse generator 20 of the second embodiment has the same effect as that of the first embodiment described above, and generates and executes the pulse signal PLS for each cycle of the clock signal CLK. There is an effect that the generation stop can be controlled. According to the second embodiment, the execution / stop of the data latch function can be controlled in units of one cycle of the clock signal CLK by controlling the generation of the pulse signal PLS by the enable signal EN.

  In the second embodiment, since the clock signal CLK is not gate-controlled by the enable signal EN, the clock signal CLK is always supplied to the pulse generator. For this reason, the pulse signal PLS can be promptly generated when the enable state is entered.

  In the second embodiment, the output signal CEN of the clock enabler 241 is fixed to “0” while the pulse signal PLS is being generated (in the enabled state), so that there is a glitch in the pulse output. There is also an effect that it does not occur.

  Further, the data fetching and holding device including the pulse generator 20 with the clock enabler according to the second embodiment uses a conventional master-slave flip-flop as a data latch circuit and has a conventional data fetch with a clock enabler. There is also an effect that the circuit scale can be made smaller than that of the holding device.

  FIG. 8 shows a table comparing the number of devices used (approximate number of transistors) in the case of the conventional data acquisition and holding device and the case of the data acquisition and holding device of the second embodiment. .

  That is, in the case of the master-slave type flip-flop corresponding to the bit storage unit in the conventional device, the number of devices per bit is 26, whereas the bit storage unit in the case of the device of the second embodiment Is 18 devices per bit.

  On the other hand, the pulse generation unit with a clock enabler has 24 devices in the case of the conventional apparatus, but 55 devices in the apparatus of the second embodiment.

  Therefore, in the case of the apparatus of the second embodiment, the number of devices of the pulse generation unit with the clock enabler is larger than the conventional case, but the number of devices used for the bit storage unit per bit is small. When capturing input data of a plurality of bits, the circuit scale is reduced.

  Then, as shown in FIG. 8, when the input data to be captured is 4 bits or more, it can be understood that the device according to the second embodiment reduces the number of devices used and the circuit scale.

[Third Embodiment (Double Edge Trigger Type Data Acquisition and Holding Device)]
The first and second embodiments described above are single edge trigger type data capture and holding devices that capture input data only at the rising edge of the clock signal CLK. On the other hand, the third embodiment is a double edge trigger type (hereinafter referred to as DET type) data capturing / holding device that captures and retains input data at both rising and falling edges of the clock signal CLK. Is the case.

<Conventional DET type data capture / holding device>
FIG. 9 shows a general configuration example of a conventional DET type data capturing / holding device. FIG. 9 shows a configuration of a data fetching and holding device for 1-bit input data. When the input data is a plurality of bits, the circuit of FIG. 9 is provided in parallel for the plurality of bits.

  That is, the data capturing / holding device 30 in the example of FIG. 9 includes a rising edge latch unit 31, a falling edge latch unit 32, an inverter 33, and a selector 34.

  The input data Din is supplied to the data input terminals of the rising edge latch circuit 31 and the falling edge latch circuit 32. The clock signal CLK is supplied to the clock input terminal of the rising edge latch circuit 31 with the same polarity, and is inverted in polarity by the inverter 33 and supplied to the clock input terminal of the falling edge latch circuit 32.

  The rising edge latch circuit 31 takes in the input data Din during the rising period of the clock signal CLK (through state), and switches from the falling edge of the clock signal CLK to the holding state (hold state). Then, the rising edge latch circuit 31 supplies the captured signal D_POS to one input terminal A of the selector 34.

  Further, in the falling edge latch circuit 32, the input data Din is captured (through state) in the falling section of the clock signal CLK, and the rising edge of the clock signal CLK is switched to the holding state (hold state). Then, the falling edge latch circuit 32 supplies the signal D_NEG fetched and held to the other input terminal B of the selector 34.

  The selector 34 is supplied with the clock signal CLK as a select signal. The selector 34 selects the output D_POS of the rising edge latch circuit 31 when the clock signal CLK is “0”, and selects the output D_NEG of the falling edge latch circuit 31 when the clock signal CLK is “1”. The output signal Dout.

  That is, input data is taken in by the latch unit not selected as an output by the selector 34, and is switched to the holding state (hold state) at the change point of the clock signal CLK, and the latch circuit is in the holding state. Is derived as an output Dout.

  Thus, the selector 34 outputs the output signal Dout in which the input data Din is latched at both the rising and falling edges of the clock signal CLK.

<DET Type Data Capture / Holding Device of Third Embodiment>
The DET type data capturing / holding device of the third embodiment is the same as that of the first embodiment as shown in FIG. Each of the bit latch units 10 to 17 has the configuration shown in FIG. 2 in the same manner as in the first embodiment.

  That is, the DET type data capturing / holding device of the third embodiment is similar to the conventional DET type data capturing / holding device described above, and includes a rising edge latch circuit 31 and a falling edge latch circuit 32 for the clock signal CLK. The two latch circuits are not provided. In the DET type data capture / holding device of the third embodiment, one bit storage unit 101 shown in FIG. 2 is used to latch one bit data at the rising and falling edges of the clock signal CLK. It is something to be done only.

  Therefore, in the case of the third embodiment, the hardware scale is halved compared to the bit latch unit in the conventional DET type data capture and holding device.

  The pulse generator of the DET type data capture / holding device of the third embodiment generates a pulse signal PLSud having a predetermined pulse width from both rising and falling edge points of the clock signal CLK.

  In the DET type data capturing / holding device of the third embodiment, the pulse signal PLSud is supplied to the latch pulse input terminals of the bit latch units 10 to 17 in FIG. Therefore, from each of the bit latch units 10 to 17, the bit data DIN0, D1, D2,..., D7 of the input data Din are not only received at the rising point of the clock signal CLK but also at the falling point. The latched output signal is output.

<Pulse Generation Unit of Third Embodiment>
FIG. 10 shows a configuration example of the DET type pulse generator 20ud of the third embodiment. FIG. 11 shows a timing chart including signal waveforms of respective parts of the pulse generator 20ud for DET type according to the third embodiment.

  As shown in FIG. 10, the pulse generator 20ud of the third embodiment includes a rising edge chopper circuit 40, a falling edge chopper circuit 50, and a DET clock enabler 60.

  A p-type MOSFET 71p and an n-type MOSFET 71n constituting the switching gate 71 are provided on the output side of the rising edge chopper circuit 40. A p-type MOSFET 72p and an n-type MOSFET 72n constituting the switching gate 72 are provided on the output side of the falling edge chopper circuit 50.

  Further, the DET type pulse generator 20ud of the third embodiment includes inverters 73, 74, and 75.

  The clock signal CLK is supplied to each of the rising edge chopper circuit 40, the falling edge chopper circuit 50, and the DET clock enabler 60.

  Further, the rising edge chopper circuit 40 and the falling edge chopper circuit 50 are supplied with the pulse signal PLSud, which is the output of the pulse generator 20ud, as in the above example.

  The rising edge chopper circuit 40 performs an operation similar to the operation of the chopper circuit of the above-described embodiment, and in this example, a predetermined period from the rising edge of the clock signal CLK (see FIG. 11A) is obtained. , A signal CHPu (see FIG. 11B) that is in a state of “1” is generated. The configuration and operation of the rising edge chopper circuit 40 will be described in detail later.

  Similarly, the rising edge chopper circuit 50 performs the same operation as the operation of the chopper circuit of the above-described embodiment, so that in this example, the rising edge of the clock signal CLK (see FIG. 11A) is started. During the predetermined period, a signal CHPd (see FIG. 11D) that is in a state of “1” is generated. The configuration and operation of the falling edge chopper circuit 50 will also be described in detail later.

  The output signal CHPu of the rising edge chopper circuit 40 is supplied to the switching gate 71, and the output signal CHPd of the falling edge chopper circuit 50 is supplied to the switching gate 72.

  Then, the clock signal CLK is supplied to the gate of the n-type MOSFET 71n of the switching gate 71 with the same polarity and to the gate of the p-type MOSFET 72p of the switching gate 72. Further, the polarity of the clock signal CLK is inverted by the inverter 73 and supplied to the gate of the p-type MOSFET 71 p of the switching gate 71 and also supplied to the gate of the n-type MOSFET 72 n of the switching gate 72.

  Therefore, in the switching gate 71, during the period “1” of the clock signal CLK, the p-type MOSFET 71p and the n-type MOSFET 71n are turned on to be in a conductive state, and pass the output signal CHPu of the rising edge chopper circuit 40. As a result, the switching gate 71 obtains a pulse signal Gu (see FIG. 11C) having a pulse width corresponding to the write time in the 1-bit storage unit of the chopper circuit 40 from the rising edge of the clock signal CLK.

  In the switching gate 72, the p-type MOSFET 72p and the n-type MOSFET 72n are turned on during the period of “0” of the clock signal CLK to be in a conductive state, and pass the output signal CHPd of the falling edge chopper circuit 50. . As a result, the switching gate 72 obtains a pulse signal Gd (see FIG. 11E) having a pulse width corresponding to the writing time in the 1-bit storage unit of the chopper circuit 50 from the falling edge of the clock signal CLK.

  In the pulse generator 20ud, the output sides of the switching gates 71 and 72 are connected to each other, and wired or connected. Then, the output of the wired OR is output as the output PLSud (see FIG. 11F) of the pulse generation unit 20ud through the inverters 74 and 75.

  The above is a description when the clock enabler 60 is not present or when the clock enabler 60 enables the rising and falling edge pulses of the clock signal CLK (enabled state).

  In the pulse generator 20ud of the third embodiment, the clock enabler 60 generates the rising pulse signal Gu and / or the falling pulse signal Gd in the same manner as in the second embodiment. It is controlled in synchronization with CLK.

  Thereby, in each of the bit latch units 10 to 17, the operation of taking in and holding the input data Din is controlled to be in an execution state or a stop state with respect to one or both of the rising edge and the falling edge of the clock signal CLK.

  That is, in the third embodiment, the rising edge clock enable signal EN_P and the falling edge clock enable signal EN_N are supplied to the DET clock enabler 60.

  In the clock enabler 60, the clock enable signal EN_P for the rising edge is latched by the falling of the clock signal CLK, and the rising latch enable signal EN_LAT_P is generated and output in the same manner as in the second embodiment. Then, the generated rising latch enable signal EN_LAT_P is supplied to the rising edge chopper circuit 40.

  The rising edge chopper circuit 40 is controlled to generate the output signal CHPu that generates the pulse Gu only during the clock cycle period enabled by the rising latch enable signal EN_LAT_P.

  Similarly, the clock enabler 60 latches the clock enable signal EN_N for the falling edge at the rising edge of the clock signal CLK, and generates and outputs the falling latch enable signal EN_LAT_N. The generated rising latch enable signal EN_LAT_N is supplied to the falling edge chopper circuit 50.

  The falling edge chopper circuit 50 is controlled so as to generate the output signal CHPd that generates the pulse Gd only during the clock cycle period enabled by the falling latch enable signal EN_LAT_N.

  A configuration example of the DET clock enabler 60 will also be described in detail later.

<Configuration Example of Rising Edge Chopper Circuit 40>
FIG. 12 is a block diagram illustrating a configuration example of the rising edge chopper circuit 40.

  The rising edge chopper circuit 40 has a function of generating a pulse width period of the pulse Gu of the pulse signal PLSud. In this example, the chopper circuit 40 has the same configuration as each 1-bit storage unit 101 of the bit latch units 10 to 17. 1-bit storage unit 401 is provided. A low level (ground level) is input to the data input terminal of the 1-bit storage unit 401.

  Further, the rising edge chopper circuit 40 includes a NOR gate 402, inverters 403, 404, and 406 corresponding to the NOR gate 244, the inverters 233, 234, and 236, and the switch 235 of the chopper circuit 24 of the pulse generator 20 of the second embodiment. , A switch 405 is provided.

  In the third embodiment, the clock enabler 241 in the chopper circuit 24 of the pulse generator 20 of the second embodiment is provided separately from the pulse generator 20. Therefore, here, the rising input latch enable signal EN_LAT_P from the external DET clock enabler 60 is supplied to the other input terminal of the NOR gate 402, and the enable control is performed in units of the period of the clock signal CLK. The NOR gate 402 outputs the output signal CHPu of the rising edge chopper circuit 40.

  The pulse signal PLSud is supplied to the inverter 403. In the third embodiment, a switching gate 407 is provided on the output side of the inverter 403.

  The output obtained at the output terminal of the switching gate 407 is supplied to the 1-bit storage unit 401 as it is, and the polarity is inverted by the inverter 404 and supplied to the 1-bit storage unit 401.

  In the third embodiment, a switching gate 408 to which a high level (“1”) potential is supplied as an input signal is provided on the input side of the inverter 404. When the switching gate 408 is in a conductive state, the high-level potential signal is supplied to the 1-bit storage unit 401 as it is, and the polarity is inverted by the inverter 404 and supplied to the 1-bit storage unit 401.

  The switching gate 407 includes a p-type MOSFET 407p and an n-type MOSFET 407n. The switching gate 408 includes a p-type MOSFET 408p and an n-type MOSFET 408n.

  The clock signal CLK is supplied to the gate of the n-type MOSFET 407n of the switching gate 407 and the gate of the p-type MOSFET 408p of the switching gate 408 with the same polarity. Further, the polarity of the clock signal CLK is inverted by the inverter 406 and supplied to the gate of the p-type MOSFET 407 p of the switching gate 407 and to the gate of the n-type MOSFET 408 n of the switching gate 408.

  Therefore, the switching gate 407 is conductive only during the “1” interval of the clock signal CLK, and the switching gate 408 is conductive only during the “0” interval of the clock signal CLK.

  For this reason, in the section “1” of the clock signal, the switching gate 407 is in a conducting state and the switching gate 408 is in a non-conducting state, so that the pulse signal PLSud whose polarity is inverted by the inverter 403 is obtained through the switching gate 407. The polarity-inverted pulse signal PLSud is supplied to the 1-bit storage unit 401 as a gate control signal with the same polarity, and further inverted in polarity by the inverter 404 and supplied to the 1-bit storage unit 401 as a gate control signal. . That is, two phase signals φ! , Φ are supplied to the 1-bit storage unit 401 as gate control signals.

  On the other hand, in the period of “0” of the clock signal, the switching gate 407 is non-conductive and the switching gate 408 is conductive, so that a high level signal is obtained through the switching gate 408. This high level signal is supplied as a gate control signal to the 1-bit storage unit 401 with the same polarity, and further inverted in polarity by the inverter 404 and supplied to the 1-bit storage unit 401 as a gate control signal. That is, in this case, the two phase signals φ! , Φ has a polarity opposite to that of the clock signal “1” and is supplied to the 1-bit storage unit 401 as a gate control signal.

  As described above, the two phase signals φ and φ! However, [φ, φ! ] = [1, 0], the 1-bit storage unit 401 operates to capture and hold the input data. Therefore, the 1-bit storage unit 401 of the rising edge chopper circuit 40 captures the ground potential as input data in the pulse period (“1”) of the pulse signal PLSud only when the clock signal CLK is “1”. To.

  Therefore, the rising edge chopper circuit 40 outputs an output signal CHPu as shown in FIG. As described above, the output signal CHPu is used to generate a pulse Gu having a leading edge of the rising edge of the clock signal CLK and a pulse width corresponding to the input data fetch time of the 1-bit storage unit 401. .

<Configuration Example of Chopper Circuit 50 for Falling Edge>
FIG. 13 is a block diagram showing a configuration example of the falling edge chopper circuit 50.

  The falling edge chopper circuit 50 has a function of generating a pulse width period of the pulse Gd in the pulse signal PLSud, and has substantially the same configuration as the rising edge chopper circuit 40.

  That is, in this example, a 1-bit storage unit 501 having the same configuration as each 1-bit storage unit 101 of the bit latch units 10 to 17 is provided.

  The falling edge chopper circuit 50 includes a NOR gate 502, inverters 503, 504, 506, and a switch 505 in the same manner as the NOR gate 402, inverters 403, 404, and 406 and the switch 405 of the rising edge chopper circuit 40.

  A falling latch enable signal EN_LAT_N from an external DET clock enabler 60 is supplied to the other input terminal of the NOR gate 502, and enable control is performed for each cycle of the clock signal CLK. The NOR gate 502 outputs the output signal CHPd of the falling edge chopper circuit 50.

  Further, the falling edge chopper circuit 50 is provided with switching gates 507 and 508 corresponding to the switching gates 407 and 408 of the rising edge chopper circuit 40. The switching gate 507 includes a p-type MOSFET 507p and an n-type MOSFET 507n. The switching gate 508 includes a p-type MOSFET 508p and an n-type MOSFET 508n.

  In the falling edge chopper circuit 50, the conduction / non-conduction state of the switching gates 507 and 508 with respect to “1” and “0” of the clock signal CLK is the conduction / non-conduction state of the switching gates 407 and 408 of the rising edge chopper circuit 40. This is the opposite of the situation. This is the only difference in configuration between the falling edge chopper circuit 50 and the rising edge chopper circuit 40.

  That is, the clock signal CLK is supplied to the gate of the p-type MOSFET 507p of the switching gate 507 and the gate of the n-type MOSFET 508n of the switching gate 508 with the same polarity. The clock signal CLK is inverted in polarity by the inverter 506 and supplied to the gate of the n-type MOSFET 507 n of the switching gate 507 and also supplied to the gate of the p-type MOSFET 508 p of the switching gate 508.

  Therefore, the switching gate 507 is conductive only during the “0” period of the clock signal CLK, and the switching gate 508 is conductive only during the “1” period of the clock signal CLK.

  For this reason, in the period of “0” of the clock signal, the switching gate 507 is in the conductive state and the switching gate 508 is in the non-conductive state, so that the pulse signal PLSud whose polarity is inverted by the inverter 503 is obtained through the switching gate 507. The polarity-inverted pulse signal PLSud is supplied to the 1-bit storage unit 501 as a gate control signal with the same polarity, and further inverted in polarity by the inverter 504 and supplied to the 1-bit storage unit 501 as a gate control signal. . That is, two phase signals φ! , Φ are supplied to the 1-bit storage unit 501 as gate control signals.

  On the other hand, in the section “1” of the clock signal, since the switching gate 507 is non-conductive and the switching gate 508 is conductive, a high-level signal is obtained through the switching gate 508. This high level signal is supplied as a gate control signal to the 1-bit storage unit 501 with the same polarity, and further inverted in polarity by the inverter 504 and supplied to the 1-bit storage unit 501 as a gate control signal. That is, in this case, the two phase signals φ! , Φ has a polarity opposite to that of the clock signal “0” and is supplied to the 1-bit storage unit 501 as a gate control signal.

  As described above, the two phase signals φ and φ! However, [φ, φ! ] = [1, 0], the 1-bit storage unit 501 operates to capture and hold the input data. Therefore, the 1-bit storage unit 501 of the falling edge chopper circuit 50 takes in the ground potential as the input data in the pulse period (“1”) of the pulse signal PLSud only when the clock signal CLK is “0”. Like that.

  Therefore, the falling edge chopper circuit 50 outputs an output signal CHPd as shown in FIG. As described above, this output signal CHPd is used to generate a pulse Gd having a falling edge of the clock signal CLK as a leading edge and a pulse width corresponding to the input data capture time of the 1-bit storage unit 501. The

<Example of Configuration of DET Clock Enabler 60>
FIG. 14 is a block diagram showing a configuration example of the DET clock enabler 60 of the third embodiment.

  The DET clock enabler 60 of the third embodiment includes a rising edge 1-bit storage unit 601, a falling edge 1-bit storage unit 602, and inverters 603 and 604. In this example, the 1-bit storage unit for rising edge 601 and the 1-bit storage unit for falling edge 602 have the same configuration as the 1-bit storage units 101 of the bit latch units 10 to 17.

  The rising edge enable signal EN_P is supplied as input data to the rising edge 1-bit storage unit 602. The falling edge enable signal EN_N is supplied as input data to the falling edge 1-bit storage unit 602.

  Further, the clock signal CLK is supplied as a positive-phase gate control signal φ to the rising-edge 1-bit storage unit 601 through the inverter 603, and the anti-phase gate control is supplied to the falling-edge 1-bit storage unit 602. Signal φ! Supplied as

  Further, the polarity inversion signal of the clock signal CLK from the inverter 603 is further inverted by the inverter 604 to be the original polarity of the clock signal CLK. The clock signal CLK having the original polarity from the inverter 604 is supplied to the 1-bit storage unit 601 for rising edge, and the gate control signal φ! And a positive-phase gate control signal φ to the 1-bit storage unit 602 for the falling edge.

  That is, in the 1-bit storage unit 601 for the rising edge and the 1-bit storage unit 602 for the falling edge, the clock signal CLK has two phase signals φ and φ! Supplied as

  Accordingly, the rising edge enable signal EN_P is latched and held by the falling edge of the clock signal CLK in the rising edge 1-bit storage unit 601 and is output as the rising latch enable signal EN_LAT_P.

  Further, in the falling edge 1-bit storage unit 602, the falling edge enable signal EN_N is latched and held by the rising edge of the clock signal CLK, and is output as the falling latch enable signal EN_LAT_N.

  As described above, the rising latch enable signal EN_LAT_P is supplied to the NOR gate 402 of the rising edge chopper circuit 40, and the falling latch enable signal EN_LAT_N is supplied to the NOR gate 502 of the falling edge chopper circuit 50, respectively. Latch enable control is performed.

  FIG. 15 shows an operation waveform in the DET pulse generator 20ud of the third embodiment described above and a comparison with respect to process variations.

  FIGS. 15A to 15D show operation waveforms in the pulse generation unit 20ud in the combination of the n-type MOSFET and the p-type MOSFET constituting the entire circuit of the 1-bit storage unit. For example, “SlowSlow” means a case where the n-type MOSFET and the p-type MOSFET are both low-speed type elements and the entire circuit of the 1-bit storage unit is configured. Further, for example, “SlowFast” means a case where an n-type MOSFET is a low-speed type element and a p-type MOSFET is a high-speed type element and the entire circuit of the 1-bit storage unit is configured.

  15A to 15D, the solid line indicates the clock signal CLK. A fine broken line shows an operation waveform of the pulse signal PLS. A rough broken line indicates an operation waveform of a signal obtained at the output terminal of the 1-bit storage unit of the chopper circuits 40 and 50. A one-dot chain line indicates an operation waveform of a signal obtained at the output terminal of the 1-bit storage unit 101 of the bit latch unit.

  As can be seen from FIG. 15, the pulse signal PLS is generated in synchronization with the rising and falling edges of the clock signal CLK.

  As shown in FIGS. 15A to 15D, during the pulse width period of the pulse signal PLS (fine broken line), the holding node potential waveform (one-dot chain line) of the 1-bit storage unit 101 for data latch is the captured data. It can be seen that the potential reaches a sufficiently stable potential. In addition, even when the process variation conditions are variously changed as shown in FIGS. 15A to 15D, it is understood that the relationship is maintained.

  In the case of the third embodiment, it is needless to say that the same effects as those of the first embodiment and the second embodiment described above are provided. Furthermore, in the case of the DET type data capture / holding device of the third embodiment, the configuration of the bit latch unit is simpler than that of the conventional DET type device, so that the circuit scale can be reduced. There is an effect.

  FIG. 16 shows a table comparing the number of devices used (approximate number of transistors) in the case of the conventional DET type data acquisition and holding device and the case of the data acquisition and holding device of the third embodiment. Is.

  That is, in the case of the master-slave type flip-flop corresponding to the bit storage unit in the conventional DET type device, the number of devices per bit is 40, whereas in the case of the device of the third embodiment, The bit storage unit has 18 devices per bit.

  On the other hand, the number of devices in the pulse generator with the clock enabler is 24 in the case of the conventional apparatus, whereas the number of devices is 84 in the apparatus of the third embodiment.

  Therefore, in the case of the apparatus of the third embodiment, the number of devices of the pulse generation unit with the clock enabler is larger than in the conventional case, but the number of devices used for the bit storage unit per bit is small. When capturing input data of a plurality of bits, the circuit scale is reduced.

  Then, as shown in FIG. 16, when the input data to be captured is 4 bits or more, it can be understood that the number of devices used is reduced and the circuit scale is reduced in the case of the apparatus of the third embodiment.

[Other Embodiments and Other Modifications]
In the first and second embodiments described above, the rising edge of the clock signal is the leading edge of the pulse width interval of the pulse signal PLS, but the falling edge of the clock signal is the leading edge of the pulse width interval of the pulse signal PLS. Needless to say, the configuration may be an edge.

  That is, the pulse generation unit 20 in that case may use the circuit portion for the falling edge of the clock signal CLK in the double edge trigger type data acquisition and holding device of the third embodiment described above.

  The 1-bit storage unit 231 of the chopper circuit 23 has the same configuration as that of the 1-bit storage unit 101. However, the 1-bit storage unit 231 does not have to have the same configuration but may have an equivalent configuration. That is, the point is that the time required for the input data to be captured and held by the input pulse signal is the same as that of the 1-bit storage unit 101 as long as the time is the same as that of the 1-bit storage unit 101. Also good.

  Needless to say, the configuration of the bit latch units 10 to 17 is not limited to the one using the three-state buffer as in the above-described embodiment.

  10 to 17: bit latch unit, 20, 20ud: pulse generation unit, 101, 231, 40, 501, 1 bit storage unit, 23, 24, 40, 50: chopper circuit, 241, 60: clock enabler

Claims (10)

Holding means comprising a first data acquisition storage unit for acquiring and holding input data in a pulse width section of a latching pulse;
A second data capture storage unit having the same or equivalent configuration as the first data capture storage unit, and a pulse corresponding to a capture time of input data in the second data capture storage unit from a clock signal Pulse generating means for generating a pulse signal of a width section and supplying the pulse signal as the latch pulse to the first data capture storage unit;
A data capture and holding device. In the data acquisition holding device according to claim 1,
The pulse generating means includes
The rising or falling edge of the clock signal is used as a leading edge of a pulse width interval, and the trailing edge of the pulse width interval is determined based on the output captured and held in the second data capture storage unit. A pulse generator for generating a pulse signal;
The second data acquisition storage unit includes the predetermined data stored in the second data acquisition storage unit according to the pulse signal generated by the pulse generation unit, and the output acquired Trailing edge timing generation means for supplying the pulse generation unit to
A data capture and holding device. In the data acquisition holding device according to claim 1,
Latch means for latching the enable signal with the clock signal;
A data fetching and holding device for controlling generation of the pulse signal from the pulse generation means by the enable signal latched by the latch means. In the data acquisition holding device according to claim 2,
Latch means for latching the enable signal with the clock signal;
The supply of the fetched and held output from the trailing edge timing generation unit to the pulse generation unit is controlled by the enable signal latched by the latch unit, and the generation of the pulse signal by the pulse generation unit is controlled. Means for controlling;
A data capture and holding device. In the data acquisition holding device according to any one of claims 1 to 4,
The holding means includes a plurality of the first data capture storage units corresponding to the number of bits of the input data,
A data capturing / holding device, wherein a pulse signal from the pulse generating means is supplied to the plurality of first data capturing / storing units synchronously as the latching pulse. Holding means comprising a first data acquisition storage unit for acquiring and holding input data in a pulse width section of a latching pulse;
A second data capturing / storage unit having the same or equivalent configuration as the first data capturing / storing unit, and the time taken for the input data in the second data capturing / storing unit from the rising edge of the clock signal Generating a first pulse signal of the pulse width interval of the first pulse signal and supplying the first pulse signal as the latching pulse to the first data capture storage unit,
A third data capture storage unit having the same or equivalent configuration as the first data capture storage unit, and capture of input data in the third data capture storage unit from the fall of the clock signal Pulse generating means for generating a second pulse signal of a pulse width section for a time period and supplying the second pulse signal as the latch pulse to the first data capture storage unit;
A data capture and holding device. In the data acquisition holding device according to claim 6,
The pulse generating means includes
The rising edge of the clock signal is used as the leading edge of the pulse width interval, and the trailing edge of the pulse width interval is determined based on the output captured and held in the second data capture storage unit. A first pulse generator for generating a pulse signal;
The second data acquisition storage unit includes the second data acquisition storage unit, and the first pulse signal generated by the first pulse generation unit acquires and holds a predetermined preset value in the second data acquisition storage unit, First trailing edge timing generation means for supplying the captured and held output to the first pulse generation unit;
The falling edge of the clock signal is used as the leading edge of the pulse width interval, and the trailing edge of the pulse width interval is determined based on the output captured and held in the third data capture storage unit. A second pulse generator for generating a pulse signal of
The third data acquisition storage unit, the second pulse signal generated by the second pulse generation unit, the predetermined preset value is acquired and held in the third data acquisition storage unit, Second trailing edge timing generation means for supplying the captured and held output to the second pulse generation unit;
A data capture and holding device. In the data acquisition holding device according to claim 6,
First latch means for latching a first enable signal with the clock signal;
Second latch means for latching a second enable signal with the clock signal;
Means for controlling the generation of the first pulse signal of the pulse generation means by the first enable signal latched by the first latch means;
Means for controlling the generation of the second pulse signal of the pulse generation means by the second enable signal latched by the second latch means;
A data capture and holding device. In the data acquisition holding device according to claim 7,
First latch means for latching a first enable signal with the clock signal;
Second latch means for latching a second enable signal with the clock signal;
The supply of the captured and held output from the first trailing edge timing generation unit to the first pulse generation unit is controlled by the first enable signal latched by the first latch unit. Means for controlling the generation of the first pulse signal of the pulse generating means;
The second enable signal latched by the second latch means controls the supply of the captured and held output from the second trailing edge timing generating means to the second pulse generating unit. Means for controlling the generation of the second pulse signal of the pulse generating means;
A data capture and holding device. In the data acquisition holding device in any one of Claims 6-9,
The holding means includes a plurality of the first data capture storage units corresponding to the number of bits of the input data,
A data capturing / holding device, wherein a pulse signal from the pulse generating means is supplied to the plurality of first data capturing / storing units in synchronization with the latch pulses.

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