JP2011040524A - Method of manufacturing semiconductor device, and semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce formation area of an nMOS transistor and a pMOS transistor that a semiconductor device includes. <P>SOLUTION: The method of manufacturing the semiconductor device includes the processes of: forming an annular projection portion on a substrate; forming a first n-type channel region at the annular projection portion; forming a first p-type channel region at the annular projection portion; and forming a first nMOS transistor and a first pMOS transistor by forming a first gate electrode straddling the first n-type channel region and first p-type channel region formed at the annular projection portion. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a semiconductor device manufacturing method and a semiconductor device.

  Advances in exposure technology make it possible to manufacture miniaturized semiconductor devices having a pattern with a width of several tens of nanometers or less. If the trend of miniaturization is further advanced and mass production of a miniaturized semiconductor device is attempted, a large investment is required for a stepper, a reticle, etc., and the manufacturing cost of the semiconductor device increases.

JP 2007-235037 A JP 2008-205168 A

  An object of the present invention is to provide a technique for reducing the formation area of an nMOS transistor and a pMOS transistor included in a semiconductor device.

  According to one aspect of the present invention, a method for manufacturing a semiconductor device includes a step of forming an annular protrusion on a substrate, a step of forming a first n-type channel region on the annular protrusion, and an annular protrusion. Forming a first p-type channel region, and forming a first n-type channel region formed in the annular protrusion and a first gate electrode straddling the first p-type channel region, Forming a first nMOS transistor and a first pMOS transistor.

  According to this case, the formation area of the nMOS transistor and the pMOS transistor included in the semiconductor device can be reduced.

FIG. 6 is a partial top view and a partial cross-sectional view of a semiconductor device when an annular protrusion 2 is formed on a semiconductor substrate 1. FIG. 4 is a partial top view and a partial cross-sectional view of a semiconductor device in a first example of a step of forming an annular protrusion 2 on a semiconductor substrate 1. 2 is a partial cross-sectional view of a semiconductor device in a first example of a step of forming an annular protrusion 2 on a semiconductor substrate 1; FIG. FIG. 5 is a partial cross-sectional view of a semiconductor device in a second example of a step of forming an annular protrusion 2 on a semiconductor substrate 1. FIG. 6 is a partial cross-sectional view of a semiconductor device in a third example of a step of forming an annular protrusion 2 on a semiconductor substrate 1. FIG. 4 is a partial top view and a partial cross-sectional view of a semiconductor device when different types of impurities are added to the annular protrusions 2 formed on the semiconductor substrate 1 from different directions. 2 is a partial cross-sectional view of a semiconductor device when p-type impurity ion implantation is performed from the upper left direction and when n type impurity ion implantation is performed from the upper right direction. FIG. 7 is a partial cross-sectional view of a semiconductor device when different types of impurities are added to annular projections 2 from different directions by ion implantation. FIG. FIG. 6 is a partial top view of a semiconductor device when a resist pattern 30 is formed on a specific portion of an annular protrusion 2. It is a partial top view of a semiconductor device when a part of the annular protrusion 2 is removed. 2 is a partial top view of a semiconductor device when a gate electrode 50 is formed on a semiconductor substrate 1; FIG. 2 is a partial top view of a semiconductor device when connection wiring 40 is formed on a semiconductor substrate 1; FIG. 2 is a partial top view of a semiconductor device when an interlayer insulating film is formed on a semiconductor substrate 1 and a contact is formed on the interlayer insulating film. FIG.

Hereinafter, a semiconductor device manufacturing method and a semiconductor device according to a mode for carrying out the invention (hereinafter referred to as an embodiment) and the semiconductor device will be described with reference to the drawings. Hereinafter, a method of manufacturing a semiconductor device having an SRAM (Static Random Access Memory) element by applying the method of manufacturing a semiconductor device according to the present embodiment will be described.

  In the method for manufacturing a semiconductor device according to the present embodiment, as shown in FIGS. 1A and 1B, an annular protrusion 2 is formed on a semiconductor substrate 1. The semiconductor substrate 1 is, for example, a silicon (Si) substrate. The ring in the present embodiment may be an ellipse or a polygon such as a quadrangle. FIG. 1A is a partial top view of a semiconductor device when an annular protrusion 2 is formed on a semiconductor substrate 1. FIG. 1B is a partial cross-sectional view of the semiconductor device when the position indicated by the dotted line A1 in FIG.

  A specific example of the process of forming the annular protrusion 2 on the semiconductor substrate 1 will be described with reference to FIGS. A first example of the step of forming the annular protrusion 2 on the semiconductor substrate 1 will be described with reference to FIGS.

  In the first example of the step of forming the annular protrusion 2 on the semiconductor substrate 1, first, the thin film 3 made of a material different from that of the semiconductor substrate 1 is formed on the semiconductor substrate 1. The thin film 3 may be any material that can be selectively removed with respect to the semiconductor substrate 1 and the annular protrusion 2, unlike the material constituting the semiconductor substrate 1 and the annular protrusion 2. The metal nitride contained is silicon nitride (SiN) or titanium nitride (TiN). The thin film 3 is formed by, for example, a chemical vapor deposition (CVD) method or a physical vapor deposition (PVD, sputter deposition) method. The film thickness of the thin film 3 is, for example, 60 nm.

  Next, a resist pattern is formed on the thin film 3. The resist pattern is formed, for example, by forming a photoresist film on the thin film 3 by a spin coating method and patterning the photoresist film using a photolithography technique.

  Then, anisotropic etching is performed on the thin film 3 using the resist pattern as a mask, and the pattern transfer is performed by partially removing the thin film 3. By partially removing the thin film 3, the thin film 3 functioning as a dummy pattern is formed on the semiconductor substrate 1. The pattern shape of the thin film 3 functioning as a dummy pattern may be an ellipse or a polygon such as a quadrangle. Next, the resist remaining on the thin film 3 is removed. FIG. 2A is a partial top view of the semiconductor device when the thin film 3 is partially removed. FIG. 2B is a partial cross-sectional view of the semiconductor device when the position indicated by the dotted line B1 in FIG.

The minimum width of the thin film 3 functioning as a dummy pattern is 30 nm, which is the resolution limit of photolithography used in this embodiment. That is, the minimum width 30 nm of the thin film 3 functioning as a dummy pattern is the minimum processing dimension that can be formed by the photolithography technique used in this embodiment. However, the minimum width 30 nm of the thin film 3 functioning as a dummy pattern is an example, and the minimum width of the thin film 3 functioning as a dummy pattern varies according to the length of the exposure wavelength in the photolithography technique used in the present embodiment. In FIG. 2A, the minimum width of the thin film 3 is indicated by the symbol X.

  Then, a semiconductor film 4 is formed so as to cover the semiconductor substrate 1 and the thin film 3. The semiconductor film 4 is, for example, silicon (Si), germanium (Ge), silicon germanium (SiGe), or amorphous silicon (a-Si). The formation of the semiconductor film 4 is performed by, for example, a CVD method. FIG. 3A is a partial cross-sectional view of the semiconductor device when the semiconductor film 4 is formed so as to cover the semiconductor substrate 1 and the thin film 3. The position of the cross section of the semiconductor device illustrated in FIG. 3A is the same as the position of the cross section of the semiconductor device illustrated in FIG.

  Next, anisotropic etching is performed on the semiconductor film 4 to partially remove the semiconductor film 4, thereby forming the annular protrusion 2 made of the semiconductor film 4 deposited on the side surface of the thin film 3. That is, the semiconductor film 4 formed on the upper surfaces of the semiconductor substrate 1 and the thin film 3 is removed, and the semiconductor film 4 is left on the side surfaces of the thin film 3 to form the annular protrusions 2 on the side surfaces of the thin film 3. For example, the anisotropic etching is a plasma etching method using plasma generated by applying a high frequency to a gas containing at least one of a chlorine gas (Cl), a fluorine gas (F), and a bromine gas (Br). Is done. FIG. 3B is a partial cross-sectional view of the semiconductor device when the annular protrusion 2 is formed on the side surface of the thin film 3.

  The width of the annular protrusion 2 is 10 nm, which is narrower than the resolution of photolithography used in this embodiment. That is, the width 10 nm of the annular protrusion 2 is narrower than the minimum processing dimension that can be formed by the photolithography technique used in this embodiment.

Then, the thin film 3 existing inside the annular protrusion 2 is selectively removed. Removal of the thin film 3 present inside the annular protrusion 2 is performed by etching the thin film 3 using, for example, a high-temperature phosphoric acid (H ₃ PO ₄ ) solution or a hydrofluoric acid (HF) solution. FIG. 3C is a partial cross-sectional view of the semiconductor device when the thin film 3 existing inside the annular protrusion 2 is removed.

  Here, an example in which the thin film 3 existing inside the annular projection 2 is removed is shown. However, in the first example of the step of forming the annular protrusion 2 on the semiconductor substrate 1, the thin film 3 existing inside the annular protrusion 2 is not removed, and the annular shape is formed after the ion implantation step described later. The thin film 3 present inside the protrusion 2 may be removed.

In the first example of the step of forming the annular protrusion 2 on the semiconductor substrate 1, a silicon oxide film (SiO ₂ film) 5 is formed on the semiconductor substrate 1, and a thin film 3 is formed on the silicon oxide film 5. May be. That is, the annular protrusion 2 may be formed on the silicon oxide film 5 formed on the silicon on insulator (SOI) substrate. The silicon oxide film 5 is formed by, for example, a CVD method using silane gas (SiH ₄ ) and nitrous oxide (N ₂ O) gas. FIG. 3D is a partial cross-sectional view of the semiconductor device when the annular protrusion 2 is formed on the silicon oxide film 5. The difference between the semiconductor device shown in FIG. 3C and the semiconductor device shown in FIG. 3D is that the semiconductor device shown in FIG. 3C has an annular protrusion 2 on the semiconductor substrate 1. In contrast, in the semiconductor device shown in FIG. 3D, the annular protrusion 2 is formed on the silicon oxide film 5.

A second example of the step of forming the annular protrusion 2 on the semiconductor substrate 1 will be described with reference to FIG. In the second example of the step of forming the annular protrusion 2 on the semiconductor substrate 1, first, the semiconductor film 10 is formed on the semiconductor substrate 1. The semiconductor film 10 is, for example, silicon (Si), polycrystalline silicon (poly-Si), germanium (Ge), silicon germanium (SiGe), or amorphous silicon (a-Si).

Then, a thin film 11 made of a material different from that of the semiconductor film 10 is formed on the semiconductor film 10. The thin film 11 is, for example, silicon dioxide (SiO ₂ ), silicon nitride (SiN), or titanium nitride (TiN). The thin film 11 is formed by, for example, a CVD method or a PVD method. More specifically, when the thin film 11 is silicon dioxide (SiO ₂ ) or silicon nitride (SiN), the thin film 11 is formed using a CVD method. When the thin film 11 is titanium nitride (TiN), the thin film 11 is formed using a CVD method or a PVD method.

  Next, a resist pattern is formed on the thin film 11. The resist pattern is formed by, for example, forming a photoresist film on the thin film 11 by a spin coating method and patterning the photoresist film using a photolithography technique.

Then, anisotropic etching is performed on the thin film 11 using the resist pattern as a mask, and pattern transfer is performed by partially removing the thin film 11. The thin film 11 that functions as a dummy pattern is formed on the semiconductor film 10 by partially removing the thin film 11. The pattern shape of the thin film 11 functioning as a dummy pattern may be an ellipse or a polygon such as a quadrangle. For example, anisotropic etching is performed by a plasma etching method using plasma generated by applying a high frequency to a gas of fluorocarbon gas (CxFy). Next, the resist remaining on the thin film 11 is removed. For example, the resist removal may be performed by an ashing (ashing) method in which plasma generated by applying a high frequency to a gas containing oxygen gas (O ₂ ) or hydrogen gas (H ₂ ) is generated and activated species are applied, This is performed by either or both of wet etching methods using an organic solvent having a peeling action. FIG. 4A is a partial cross-sectional view of the semiconductor device when the thin film 11 is partially removed. The position of the cross section of the semiconductor device illustrated in FIG. 4A is the same as the position of the cross section of the semiconductor device illustrated in FIG.

  The minimum width of the thin film 11 functioning as a dummy pattern is 30 nm, which is the resolution limit of photolithography used in this embodiment. That is, the minimum width 30 nm of the thin film 11 functioning as a dummy pattern is the minimum processing dimension that can be formed by the photolithography technique used in this embodiment. However, the minimum width 30 nm of the thin film 11 functioning as a dummy pattern is an example, and the minimum width of the thin film 11 functioning as a dummy pattern varies depending on the length of the exposure wavelength in the photolithography technique used in this embodiment. In FIG. 4A, the minimum width of the thin film 11 is indicated by the symbol X.

Next, a thin film 12 made of a material different from that of the semiconductor film 10 and the thin film 11 is formed so as to cover the semiconductor film 10 and the thin film 11. The thin film 12 is, for example, silicon dioxide (SiO ₂ ), silicon nitride (SiN), or titanium nitride (TiN). In this case, the material used for the thin film 11 and the material used for the thin film 12 are different materials. That is, when the thin film 11 is silicon dioxide (SiO ₂ ), the thin film 12 is silicon nitride (SiN) or titanium nitride (TiN). When the thin film 11 is silicon nitride (SiN), the thin film 12 is silicon dioxide (SiO ₂ ) or titanium nitride (TiN). When the thin film 11 is titanium nitride (TiN), the thin film 12 is silicon dioxide (SiO ₂ ) or silicon nitride (SiN).

The thin film 12 is formed by, for example, a CVD method or a PVD method. More specifically, when the thin film 12 is silicon dioxide (SiO ₂ ) or silicon nitride (SiN), the thin film 12 is formed using a CVD method. When the thin film 12 is titanium nitride (TiN), the thin film 12 is formed using a CVD method or a PVD method. FIG. 4B shows a semiconductor film 10 and a thin film 11.
It is a fragmentary sectional view of the semiconductor device at the time of forming the thin film 12 so that it may cover.

  Next, anisotropic etching is performed on the thin film 12, and the thin film 12 is partially removed to form the annular thin film 12 on the side surface of the thin film 11. That is, the thin film 12 formed on the upper surfaces of the semiconductor film 10 and the thin film 11 is removed, and the thin film 12 deposited on the side surfaces of the thin film 11 is left to form the annular thin film 12 on the side surfaces of the thin film 11. For example, anisotropic etching is performed by a plasma etching method using plasma generated by applying a high frequency to a gas of fluorocarbon gas (CxFy). The anisotropic etching when titanium nitride (TiN) is used for the thin film 12 is a plasma generated by applying a high frequency to a gas containing at least one of a fluorine gas (F) and a chlorine gas (Cl). This is performed by a plasma etching method using FIG. 4C is a partial cross-sectional view of the semiconductor device when the annular thin film 12 is formed on the side surface of the thin film 11.

Next, the thin film 11 existing inside the annular thin film 12 is selectively removed. The selective removal of the thin film 11 existing inside the annular thin film 12 can use a high temperature phosphoric acid (H ₃ PO ₄ ) solution when silicon nitride (SiN) is used for the thin film 11. Alternatively, when titanium nitride (TiN) is used for the thin film 11, a mixed solution of an alkaline chemical solution and hydrogen peroxide solution (H ₂ O ₂ ) can be used. Alternatively, when silicon dioxide (SiO ₂ ) is used for the thin film 11, a hydrofluoric acid (HF) solution, hydrogen fluoride (
HF) gas is used for dry etching. That is, when the thin film 11 is silicon dioxide (SiO ₂ ), a hydrofluoric acid (HF) solution or hydrogen fluoride (HF) gas is used. When the thin film 11 is silicon nitride (SiN), a high temperature phosphoric acid (H ₃ PO ₄ ) solution is used. When the thin film 11 is titanium nitride (TiN), for example, a mixed solution of an alkaline chemical solution such as ammonia (NH ₃ ) and hydrogen peroxide solution (H ₂ O ₂ ) is used. As described above, since the material used for the thin film 11 and the material used for the thin film 12 are different materials, only the thin film 11 existing inside the annular thin film 12 can be removed.

  Next, anisotropic etching is performed on the semiconductor film 10 using the annular thin film 12 as a mask to partially remove the semiconductor film 10, thereby forming the annular protrusion 2 on the semiconductor substrate 1. For example, the anisotropic etching is a plasma etching method using plasma generated by applying a high frequency to a gas containing at least one of a chlorine gas (Cl), a fluorine gas (F), and a bromine gas (Br). Is done. FIG. 4D is a partial cross-sectional view of the semiconductor device when the annular protrusion 2 is formed on the semiconductor substrate 1 by partially removing the semiconductor film 10.

  The width of the annular protrusion 2 is 10 nm, which is narrower than the resolution of photolithography used in this embodiment. That is, the width 10 nm of the annular protrusion 2 is narrower than the minimum processing dimension that can be formed by the photolithography technique used in this embodiment.

In the second example of the step of forming the annular protrusion 2 on the semiconductor substrate 1, a silicon oxide film (SiO ₂ film) 13 is formed on the semiconductor substrate 1 and the semiconductor film 10 is formed on the silicon oxide film 13. May be. That is, the annular protrusion 2 may be formed on the silicon oxide film 13 formed on the SOI substrate. FIG. 4E is a partial cross-sectional view of the semiconductor device when the annular protrusion 2 is formed on the silicon oxide film 13. A difference between the semiconductor device shown in FIG. 4D and the semiconductor device shown in FIG. 4E is that the semiconductor device shown in FIG. 4D has an annular protrusion 2 on the semiconductor substrate 1. In contrast, in the semiconductor device shown in FIG. 4E, the annular protrusion 2 is formed on the silicon oxide film 13.

  In the second example of the step of forming the annular protrusion 2 on the semiconductor substrate 1, the annular thin film 12 formed on the annular protrusion 2 may be removed after the ion implantation step described later. .

  A third example of the step of forming the annular protrusion 2 on the semiconductor substrate 1 will be described with reference to FIG. In the third example of the step of forming the annular protrusion 2 on the semiconductor substrate 1, first, the semiconductor film 20 is formed on the semiconductor substrate 1. The semiconductor film 20 is, for example, silicon (Si), polycrystalline silicon (poly-Si), germanium (Ge), silicon germanium (SiGe), or amorphous silicon (a-Si). The formation of the semiconductor film 20 is performed by, for example, a CVD method.

  Next, a resist pattern is formed on the semiconductor film 20. The resist pattern is formed by, for example, forming a photoresist film on the semiconductor film 20 by spin coating and patterning the photoresist film using a photolithography technique.

  Then, anisotropic etching is performed on the semiconductor film 20 using the resist pattern as a mask, and pattern transfer is performed by partially removing the semiconductor film 20. By partially removing the semiconductor film 20, the semiconductor film 20 that functions as a dummy pattern is formed on the semiconductor substrate 1. The pattern shape of the semiconductor film 20 functioning as a dummy pattern may be an ellipse or a polygon such as a quadrangle. Next, the resist pattern on the semiconductor film 20 is removed. For example, the anisotropic etching is a plasma etching method using plasma generated by applying a high frequency to a gas containing at least one of a chlorine gas (Cl), a fluorine gas (F), and a bromine gas (Br). Is done. FIG. 5A is a partial cross-sectional view of the semiconductor device when the semiconductor film 20 is partially removed. The position of the cross section of the semiconductor device illustrated in FIG. 5A is the same as the position of the cross section of the semiconductor device illustrated in FIG.

  The minimum width of the semiconductor film 20 functioning as a dummy pattern is 30 nm, which is the resolution limit of photolithography used in this embodiment. That is, the minimum width 30 nm of the semiconductor film 20 functioning as a dummy pattern is the minimum processing dimension that can be formed by the photolithography technique used in this embodiment. However, the minimum width 30 nm of the semiconductor film 20 functioning as a dummy pattern is an example, and the minimum width of the semiconductor film 20 functioning as a dummy pattern varies according to the length of the exposure wavelength in the photolithography technique used in this embodiment. To do. In FIG. 5A, the minimum width of the semiconductor film 20 is indicated by a symbol X.

Then, a thin film 21 made of a material different from that of the semiconductor substrate 1 and the semiconductor film 20 is formed so as to cover the semiconductor substrate 1 and the semiconductor film 20. The thin film 21 is, for example, a silicon oxide film (SiO ₂ film). The thin film 21 is formed by, for example, a CVD method. (B) of FIG.
FIG. 3 is a partial cross-sectional view of a semiconductor device when a thin film 21 is formed so as to cover the semiconductor substrate 1 and the semiconductor film 20.

  Next, anisotropic etching is performed on the thin film 21, and the thin film 21 is partially removed to form the annular thin film 21 on the side surface of the semiconductor film 20. That is, the thin film 21 formed on the upper surface of the semiconductor film 20 is removed, and the thin film 21 is left on the side surface of the semiconductor film 20, thereby forming the annular thin film 21 on the side surface of the semiconductor film 20. For example, anisotropic etching is performed by a plasma etching method using plasma generated by applying a high frequency to a gas of fluorocarbon gas (CxFy). FIG. 5C is a partial cross-sectional view of the semiconductor device when the annular thin film 21 is formed on the side surface of the semiconductor film 20.

Then, the semiconductor film 20 existing inside the annular thin film 21 is removed. The removal of the semiconductor film 20 existing inside the annular thin film 21 is performed, for example, by wet treatment with an alkaline chemical such as ammonia (NH ₃ ) or trimethylammonium (TMA). At this time, in the case where the semiconductor substrate 1 is a crystal and the semiconductor film 20 is polycrystalline or amorphous, the semiconductor film 20 is selectively removed by performing etching under conditions where the etching rate for the polycrystalline or amorphous is high. Is called. FIG. 5D is a partial cross-sectional view of the semiconductor device when the semiconductor film 20 existing inside the annular thin film 21 is removed.

  In addition, if an oxide film (not shown) such as a natural oxide film is formed on the underlying semiconductor substrate 1 before the semiconductor film 20 is formed, the oxide film formed on the semiconductor substrate 1 However, by functioning as a protective film in the etching process of the semiconductor film 20, only the semiconductor film 20 on the semiconductor substrate 1 can be selectively removed. In this case, the semiconductor film 20 is selectively removed by etching using a gas containing at least chlorine gas (Cl) or fluorine gas (F). This is because when the semiconductor film 20 is polycrystalline silicon (poly-Si) or amorphous silicon (a-Si), the semiconductor substrate 1 and the semiconductor film 20 are made of chlorine gas (Cl) or fluorine gas (F). Since the etching rates are different, only the semiconductor film 20 on the semiconductor substrate 1 can be selectively removed.

  Next, anisotropic etching is performed on the semiconductor substrate 1 using the annular thin film 21 as a mask, and the semiconductor substrate 1 is partially removed to form the annular protrusions 2 on the semiconductor substrate 1. For example, the anisotropic etching is a plasma etching method using plasma generated by applying a high frequency to a gas containing at least one of a chlorine gas (Cl), a fluorine gas (F), and a bromine gas (Br). Is done. FIG. 5E is a partial cross-sectional view of the semiconductor device when the annular protrusion 2 is formed on the semiconductor substrate 1 by partially removing the semiconductor substrate 1.

  The width of the annular protrusion 2 is 10 nm, which is narrower than the resolution of photolithography used in this embodiment. That is, the width 10 nm of the annular protrusion 2 is narrower than the minimum processing dimension that can be formed by the photolithography technique used in this embodiment.

  In the third example of the step of forming the annular protrusion 2 on the semiconductor substrate 1, the annular thin film 21 formed on the annular protrusion 2 may be removed after the ion implantation step described later. Good.

  After the step of forming the annular protrusion 2 on the semiconductor substrate 1, different types of impurities are added (doping) to the annular protrusion 2 from different directions by ion implantation. FIG. 6 shows an example in which different types of impurities are added to the annular protrusion 2 from different directions by ion implantation.

  FIG. 6A is a partial top view of the semiconductor device when different types of impurities are added to the annular protrusions 2 formed on the semiconductor substrate 1 from different directions. 6B is a partial cross-sectional view of the semiconductor device when the position indicated by the dotted line C1 in FIG. 6A is viewed from the arrow direction C2. In FIGS. 6A and 6B, the direction of ion implantation is indicated by arrows. 6A is a partial top view of the semiconductor device, the direction of ion implantation is indicated by a vertical arrow. However, in practice, the ion implantation is performed obliquely to the left of the semiconductor substrate 1. FIG. It is performed from above or diagonally upward from the right.

As shown in FIG. 6B, a p-type impurity is added to the annular protrusion 2 from the upper left direction by ion implantation, and an n-type impurity is added to the annular protrusion from the upper right direction by ion implantation. Add to 2. Examples of p-type impurities include boron (B) and boron compounds (BF ₂ , BxHy).
). The n-type impurity is, for example, phosphorus (P) or arsenic (As), or a compound of phosphorus or arsenic. The tilt angle of ion implantation is determined by the shape of the annular protrusion 2 and the dose of impurities. However, the direction of ion implantation shown in FIG. 6 is merely an example, and the present embodiment is not limited to this. For example, a p-type impurity may be added to the annular protrusion 2 from the upper right direction by ion implantation, or an n-type impurity may be added to the annular protrusion 2 from the upper left direction by ion implantation. Also good.

  Different types of channel regions are formed in the annular projection 2 by adding different types of impurities to the annular projection 2 from different directions by ion implantation. For example, as shown in FIG. 6B, a p-type impurity is added to the annular protrusion 2 from the upper left direction by ion implantation, whereby an n-type channel is formed in a part of the annular protrusion 2. A region is formed. Here, a voltage is applied to a gate electrode to be described later, and the surface of the p-type semiconductor portion of the protrusion 2 is inverted by a gate electric field to form an n-type channel. Further, as shown in FIG. 6B, an n-type impurity is added to the annular protrusion 2 from the upper right direction by ion implantation, whereby a p-type channel is formed in a part of the annular protrusion 2. A region is formed. Here, a voltage is applied to a gate electrode described later, and the surface of the n-type semiconductor portion of the protrusion 2 is inverted by a gate electric field to form a p-type channel.

  FIG. 7A is a partial cross-sectional view of the semiconductor device in the case where ion implantation of p-type impurities is performed from the upper left oblique direction. The position of the cross section of the semiconductor device illustrated in FIG. 7A is the same as the position of the cross section of the semiconductor device illustrated in FIG. As shown in FIG. 7A, when ion implantation of p-type impurities is performed from the upper left oblique direction, the left portion of the annular protrusion 2 is p-type on the entire left side and the entire upper surface. Impurities are added. On the other hand, the right portion of the annular protrusion 2 is shielded by the left portion of the annular protrusion 2, so that p-type impurities are added to a part of the left side and the entire upper surface.

  FIG. 7B is a partial cross-sectional view of the semiconductor device in the case where ion implantation of n-type impurities is performed from the upper right direction. The position of the cross section of the semiconductor device illustrated in FIG. 7B is the same as the position of the cross section of the semiconductor device illustrated in FIG. As shown in FIG. 7B, in the case where ion implantation of n-type impurities is performed from the upper right direction, the right portion of the annular protrusion 2 is n-type on the entire right side and the entire upper surface. Impurities are added. On the other hand, the left portion of the annular protrusion 2 is shielded by the right portion of the annular protrusion 2 so that an n-type impurity is added to a part of the right side and the entire upper surface.

  As shown in FIGS. 7A and 7B, the left portion and the right portion of the annular protrusion 2 have different dose amounts to which p-type impurities are added, and n-type impurities are added. Different dose amount. Since the dose of p-type impurities is larger than the dose of n-type impurities in the left portion of the annular protrusion 2, an n-type channel region is formed in the left portion of the annular protrusion 2. On the other hand, since the dose amount of the n-type impurity is larger than the dose amount of the p-type impurity in the right portion of the annular protrusion 2, a p-type channel region is formed in the right portion of the annular protrusion 2.

  As described above, in the first example of the step of forming the annular protrusion 2 on the semiconductor substrate 1, the thin film 3 present inside the annular protrusion 2 may not be removed. FIG. 8A shows an example in which different types of impurities are added to the annular projection 2 from different directions by ion implantation without removing the thin film 3 existing inside the annular projection 2. . FIG. 8A shows a state in which different types of impurities are added to the annular protrusions 2 from different directions without removing the thin film 3 existing inside the annular protrusions 2 formed on the semiconductor substrate 1. It is a fragmentary sectional view of the semiconductor device in the case of doing. The position of the cross section of the semiconductor device illustrated in FIG. 8A is the same as the position of the cross section of the semiconductor device illustrated in FIG.

As shown in FIG. 8A, p-type impurities are added to the annular protrusion 2 from the upper left direction by ion implantation, and n-type impurities are added to the annular protrusion from the upper right direction by ion implantation. Add to 2. Examples of p-type impurities include boron (B) and boron compounds (BF ₂ , BxHy).
). The n-type impurity is, for example, phosphorus (P) or arsenic (As), or a compound of phosphorus or arsenic. The tilt angle of ion implantation is determined by the shape of the annular protrusion 2 and the dose of impurities.

  As shown in FIG. 8A, when ion implantation of a p-type impurity is performed from the diagonally upper left direction, the left portion of the annular protrusion 2 is p-type on the entire left side and the entire top surface. Impurities are added. On the other hand, the right portion of the annular protrusion 2 is shielded by the thin film 3 existing inside the annular protrusion 2, so that p-type impurities are added to the entire upper surface.

  As shown in FIG. 8A, when ion implantation of n-type impurities is performed from the upper right direction, the right portion of the annular protrusion 2 is n-type on the entire right side and the entire upper surface. Impurities are added. On the other hand, the left portion of the annular protrusion 2 is shielded by the thin film 3 existing inside the annular protrusion 2, so that an n-type impurity is added to the entire upper surface.

  As shown in FIG. 8A, the left portion and the right portion of the annular protrusion 2 differ in the dose amount to which the p-type impurity is added and the dose amount to which the n-type impurity is added. Different. Since the dose of p-type impurities is larger than the dose of n-type impurities in the left portion of the annular protrusion 2, an n-type channel region is formed in the left portion of the annular protrusion 2. On the other hand, since the dose amount of the n-type impurity is larger than the dose amount of the p-type impurity in the right portion of the annular protrusion 2, a p-type channel region is formed in the right portion of the annular protrusion 2.

  As shown in FIG. 8A, when ion implantation of p-type impurities is performed from the diagonally upper left direction, the p-type impurities are added only to the upper surface of the right portion of the annular protrusion 2. Therefore, the amount of p-type impurities added to the right portion of the annular protrusion 2 is smaller than when the thin film 3 is not present inside the annular protrusion 2. In addition, as shown in FIG. 8A, when ion implantation of n-type impurities is performed from the upper right direction, n-type impurities are added only to the upper surface of the left portion of the annular protrusion 2. The Therefore, compared with the case where the thin film 3 does not exist inside the annular protrusion 2, the dose amount of the n-type impurity added to the left portion of the annular protrusion 2 is small.

  In addition, as described above, in the second example of the step of forming the annular protrusion 2 on the semiconductor substrate 1, the annular thin film 12 formed on the annular protrusion 2 may not be removed. Furthermore, as described above, in the third example of the step of forming the annular protrusion 2 on the semiconductor substrate 1, the annular thin film 21 formed on the annular protrusion 2 may not be removed. An example of adding different types of impurities to the annular projection 2 from different directions by ion implantation without removing the annular thin film 12 formed on the annular projection 2 is shown in FIG. ). FIG. 8B shows an annular protrusion from different directions in different types of impurities without removing the annular thin film 12 formed on the annular protrusion 2 formed on the semiconductor substrate 1. 2 is a partial cross-sectional view of a semiconductor device when added to 2. FIG. The position of the cross section of the semiconductor device illustrated in FIG. 8B is the same as the position of the cross section of the semiconductor device illustrated in FIG.

  Hereinafter, an example in which ion implantation is performed without removing the annular thin film 12 formed on the annular protrusion 2 will be described. However, the annular thin film 21 formed on the annular protrusion 2 is removed. The case where ion implantation is performed in a state where no ion is applied is similar to the example shown in FIG. That is, in the state where the annular thin film 21 formed on the annular projection 2 is not removed, different types of impurities are added to the annular projection 2 from different directions by ion implantation. The thin film 12 in (B) may be changed to the thin film 21.

As shown in FIG. 8B, a p-type impurity is added to the annular protrusion 2 from the upper left direction by ion implantation, and an n-type impurity is added to the annular protrusion from the upper right direction by ion implantation. Add to 2. Examples of p-type impurities include boron (B) and boron compounds (BF ₂ , BxHy).
). The n-type impurity is, for example, phosphorus (P) or arsenic (As), or a compound of phosphorus or arsenic. The tilt angle of ion implantation is determined by the shape of the annular protrusion 2 and the dose of impurities.

  As shown in FIG. 8B, when ion implantation of p-type impurities is performed from the upper left direction, the left portion of the annular protrusion 2 is formed on the annular protrusion 2. By being shielded by the annular thin film 12, a p-type impurity is added only to the left side surface. On the other hand, the right portion of the annular protrusion 2 is shielded by the left portion of the annular protrusion and the annular thin film 12, so that no p-type impurity is added.

  As shown in FIG. 8B, when ion implantation of n-type impurities is performed from the upper right direction, the right portion of the annular protrusion 2 is formed on the annular protrusion 2. By being shielded by the annular thin film 12, an n-type impurity is added only to the right side surface. On the other hand, the left portion of the annular protrusion 2 is shielded by the right portion of the annular protrusion 2 and the annular thin film 12, so that no n-type impurity is added.

  As shown in FIG. 8B, when ion implantation of p-type impurities is performed from the diagonally upper left direction, only the p-type impurities are added to the left portion of the annular protrusion 2, so that An n-type channel region is formed on the left portion of the protrusion 2 of the first electrode. On the other hand, as shown in FIG. 8B, when n-type impurity ions are implanted from the upper right direction, only the n-type impurity is added to the right portion of the annular protrusion 2. A p-type channel region is formed in the right part of the annular protrusion 2.

  When ion implantation of n-type impurities is performed, a resist pattern 30 is formed on a specific portion of the annular protrusion 2 so that the n-type impurity is not added to the annular protrusion 2. May be. FIG. 9 is a partial top view of the semiconductor device when the resist pattern 30 is formed on a specific portion of the annular protrusion 2. As shown in FIG. 9, when a resist pattern 30 is formed on a specific portion of the annular protrusion 2 and ion implantation of n-type impurities is performed, the portion below the portion where the resist pattern 30 is formed. The ring-shaped protrusion 2 existing in is added with only p-type impurities. Therefore, an n-type channel region is formed in the annular protrusion 2 existing under the portion where the resist pattern 30 is formed. Further, when ion implantation of p-type impurities is performed, a p-type impurity is not added to the annular protrusion 2 by forming a resist pattern 30 on a specific portion of the annular protrusion 2. It may be. When ion implantation of n-type impurities is performed, the resist pattern 30 is not formed on the annular protrusion. In this case, a p-type channel region is formed in the annular protrusion 2 existing under the portion where the resist pattern 30 is formed.

  After the ion implantation step for the annular protrusion 2 formed on the semiconductor substrate 1, the annular protrusion 2 is thermally oxidized to form a gate oxide film on the surface of the annular protrusion 2. For example, the semiconductor substrate 1 on which the annular protrusion 2 is formed is placed in a heat treatment furnace set at 900 ° C., and thermal oxidation is performed on the annular protrusion 2 in an oxidizing atmosphere. A gate oxide film is formed on the surface of the annular protrusion 2 by thermal oxidation.

The oxidizing atmosphere may be an atmosphere containing dry oxygen, water vapor by hydrogen / oxygen combustion flame (pyrogenic), and oxygen atoms dissociated and generated by plasma from an oxygen-containing gas. The oxidizing atmosphere may be an atmosphere containing a nitrogen-containing compound. Furthermore, the oxidizing atmosphere may be an atmosphere containing a gas or plasma containing nitrogen monoxide (NO), nitrous oxide (N ₂ O), nitrogen (N ₂ ), ammonia (NH ₃ ), or the like.

When the annular protrusion 2 is amorphous silicon (a-Si), a silicon oxide film (SiO ₂ film) is formed on the surface of the annular protrusion 2 by thermally oxidizing the annular protrusion 2. Thus, stress is applied to the annular protrusion 2. Therefore, a crystallized nanowire-like silicon channel is formed in the silicon at the center of the annular protrusion 2. For example, the semiconductor substrate 1 on which the annular protrusion 2 is formed is placed in a heat treatment furnace set at 900 ° C., and the annular protrusion 2 is thermally oxidized. Due to thermal oxidation, a silicon oxide film (SiO ₂ film) grows on the surface of the annular protrusion 2, and silicon concentrates on the central portion of the annular protrusion 2, resulting in a diameter cross section of 10 n.
m silicon channels are formed. Alternatively, thermal oxidation may be performed again on the annular protrusion 2 having a silicon oxide film (SiO ₂ film) on the surface and a silicon channel in the center.

  Alternatively, in addition to silicon oxidation, a high dielectric constant gate insulating film (High-k) may be deposited by CVD to form, for example, hafnium oxynitride (HfSiON) on the surface of the annular protrusion 2.

  After the step of forming a gate oxide film on the surface of the annular protrusion 2, a resist pattern for removing a part of the annular protrusion 2 is formed on the semiconductor substrate 1. Then, a part of the annular protrusion 2 is removed by etching. The resist pattern is formed by, for example, forming a photoresist film on the semiconductor substrate 1 by spin coating and patterning the photoresist film using a photolithography technique.

An example in which a part of the annular protrusion 2 having a silicon oxide film (SiO ₂ film) on the surface and a silicon channel in the center is removed will be described below. For example, a gate is obtained by etching a silicon oxide film (SiO ₂ film) formed on the surface of the annular protrusion 2 by a plasma etching method using plasma generated by applying a high frequency to a fluorocarbon gas (CxFy) gas. The oxide film is removed. Then, silicon is removed by a plasma etching method using plasma generated by applying a high frequency to a gas containing at least one of chlorine gas (Cl), fluorine gas (F) and bromine gas (Br). Remove the silicon channel. When the gate insulating film is a high-k film, boron trichloride (BCl ₃ ) or chlorine (
This is performed using a plasma etching method using plasma generated by applying a high frequency to a gas containing at least Cl). FIG. 10 is a partial top view of the semiconductor device when a part of the annular protrusion 2 is removed. As shown in FIG. 10, a part of the annular protrusion 2 formed in a wide pattern is removed, and a part of the protrusion 2 is divided into two thin lines.

  Then, the gate electrode 50 is formed on the semiconductor substrate 1. In this case, two types of gate electrodes 50 are formed on the semiconductor substrate 1. FIG. 11 is a partial top view of the semiconductor device when the gate electrode 50 is formed on the semiconductor substrate 1. In FIG. 11, one of the two types of gate electrodes 50 is represented as a gate electrode 50A. As shown in FIG. 11, the gate electrode 50 </ b> A is formed on the semiconductor substrate 1 so as to straddle the annular protrusion 2. In FIG. 11, the other of the two types of gate electrodes 50 is referred to as a gate electrode 50B. The gate electrode 50B is formed on the semiconductor substrate 1 so as to straddle one of the protrusions 2 divided into two thin lines.

  For example, silicon to which impurities are added is deposited by CVD to a thickness of 50 nm on the semiconductor substrate 1, then a resist pattern is formed on the silicon, and anisotropic etching is performed using the resist pattern as a mask. A gate electrode 50 may be formed on the semiconductor substrate 1. Note that impurities may be added to silicon after silicon is formed on the semiconductor substrate 1.

As the material of the gate electrode 50, titanium (Ti), tantalum (Ta), tungsten (W), hafnium (Hf), molybdenum (Mo), aluminum (Al), gold (Au), platinum (Pt), cobalt (Co ), Nickel (Ni), or silicon (Si) may be employed.

  As a material for the gate electrode 50, any one of nitrides of titanium (Ti), tantalum (Ta), tungsten (W), hafnium (Hf), and molybdenum (Mo) may be employed.

  As a material of the gate electrode 50, silicide of titanium (Ti), cobalt (Co), nickel (Ni), platinum (Pt), tungsten (W), molybdenum (Mo), or tantalum (Ta) may be employed.

  As a material of the gate electrode 50, a material containing nitrogen in a silicide of titanium (Ti), cobalt (Co), nickel (Ni), platinum (Pt), tungsten (W), molybdenum (Mo) or tantalum (Ta). It may be adopted. Furthermore, the gate electrode 50 may have a laminated structure of any of these metals, metal nitrides, and nitrogen-containing metals and silicide.

  For example, when silicide is formed, a nickel (Ni) thin film is deposited on the entire surface of the semiconductor substrate 1 to a thickness of 10 nm, and titanium nitride (TiN) for preventing oxidation is covered with a thickness of 30 nm. Then, by performing heat treatment at 400 ° C. for 120 seconds, a low resistance nickel silicide is formed in a self-aligned manner only in a portion where silicon is present under nickel (Ni). In this case, the nickel film thickness is adjusted according to the amount of the underlying silicon. After the silicide is formed, unreacted nickel (Ni) and titanium nitride (TiN) are removed by performing an acid chemical treatment such as sulfuric acid. Although an example in which nickel silicide is formed is shown here, the present invention is not limited to this, and silicide such as titanium (Ti), cobalt (Co), molybdenum (Mo), or platinum (Pt) may be formed.

  Next, by ion implantation, an impurity is added to the annular protrusion 2 using the gate electrode 50 as a mask, thereby forming a source region and a drain region in the annular protrusion 2. In this case, different types of impurities are added to the annular protrusions 2 from different directions by ion implantation, whereby different types of source and drain regions are formed in the annular protrusions 2.

A p-type source region and a p-type drain region are formed in the annular protrusion 2 by injecting a p-type impurity from the oblique direction into the annular protrusion 2 on the side where the p-type channel region is formed. To do. Examples of p-type impurities include boron (B) and boron compounds (BF ₂ , BxHy).
). A pMOS transistor is formed on the semiconductor substrate 1 by forming a p-type source region and a p-type drain region on the annular protrusion 2.

  Further, an n-type impurity is implanted into the annular protrusion 2 on the side where the n-type channel region is formed from an oblique direction, so that an n-type source region and an n-type drain region are formed in the annular protrusion 2. Form. The n-type impurity is, for example, phosphorus (P) or arsenic (As), or a compound of phosphorus or arsenic. By forming an n-type source region and an n-type drain region on the annular protrusion 2, an nMOS transistor is formed on the semiconductor substrate 1.

  It should be noted that a resist pattern is formed on the annular protrusion 2 in which only the p-type channel region is formed, and an n-type impurity is not added, so that the p-type source is added to the annular protrusion 2. A region and a p-type drain region are formed. In addition, for the annular protrusion 2 in which only the n-type channel region is formed, a resist pattern is formed so that p-type impurities are not added, so that an n-type source is added to the annular protrusion 2. A region and an n-type drain region are formed.

After the p-type and n-type impurities are added to the annular protrusion 2, the p-type and n-type impurities are activated by a low budget heat treatment (laser annealing or the like).

  Next, in order to connect the semiconductor channel of the annular protrusion 2, one semiconductor channel of the protrusion 2 divided into two thin lines, the source / drain region, etc., it is formed at a predetermined position of the annular protrusion 2. The gate insulating film is peeled off. For example, the gate oxide film is removed by plasma etching using plasma generated by applying a high frequency to a fluorocarbon gas (CxFy) gas to expose the semiconductor channel.

  Then, as shown in FIG. 12, a connection wiring 40 is formed to electrically connect the semiconductor channel of the annular protrusion 2 and one semiconductor channel of the protrusion 2 divided into two thin lines. FIG. 12 is a partial top view of the semiconductor device when the connection wiring 40 is formed on the semiconductor substrate 1. For example, the connection wiring 40 is formed by the PVD method or the CVD method. The connection wiring 40 uses a low-resistance material. For example, the connection wiring 40 may be silicon or metal to which a high concentration impurity is added. The connection wiring 40 is patterned by forming a photoresist film on the semiconductor substrate 1 by a spin coating method, patterning the photoresist film using a photolithography technique, and etching the connection wiring 40 using the patterned photoresist film as a mask. Is done. Here, silicide may be formed on the exposed semiconductor channel to lower the contact resistance.

Next, an interlayer insulating film is formed on the semiconductor substrate 1. The interlayer insulating film is, for example, a silicon oxide film (SiO ₂ film), and the silicon oxide film is formed by, for example, silane gas and nitrous oxide (
This is performed by a CVD method using N ₂ O) gas. Then, contact holes are formed in the interlayer insulating film by performing anisotropic etching. Next, a contact is formed in the interlayer insulating film by burying a metal such as tungsten (W) or copper (Cu) in the contact hole formed in the interlayer insulating film.

  FIG. 13 is a partial top view of the semiconductor device when an interlayer insulating film is formed on the semiconductor substrate 1 and a contact is formed on the interlayer insulating film. In FIG. 13, illustration of the interlayer insulating film is omitted. FIG. 13 shows SRAM elements for four cells, and SRAM elements for one cell are shown in a region surrounded by a dotted line shown in FIG. In the region surrounded by the dotted line shown in FIG. 13, two sets of CMOS inverters having nMOS transistors and pMOS transistors as complementary types are formed.

  On the n-type source region S1 of the nMOS transistor Tr1, a contact C1 for connecting to the power supply voltage line (Vdd) is formed. A contact C2 for connecting to the ground voltage line (Vss) is formed on the p-type source region S2 of the pMOS transistor Tr2. The nMOS transistor Tr1 and the pMOS transistor Tr2 have a common gate electrode 50A.

  A contact C3 for connection to the word line (WL) is formed on the gate electrode 50B of the transistor Tr3. A contact C4 for connecting to the bit line (BL) is formed on the source region S3 of the transistor Tr3.

  A contact C5 for connecting to the power supply voltage line (Vdd) is formed on the n-type source region S4 of the nMOS transistor Tr4. A contact C6 for connecting to the ground voltage line (Vss) is formed on the p-type source region S5 of the pMOS transistor Tr5. The nMOS transistor Tr4 and the pMOS transistor Tr5 have a common gate electrode 50A.

A contact C7 for connecting to the word line (WL) is formed on the gate electrode 50B of the transistor Tr6. A contact C8 for connecting to the inverted bit line (/ BL) is formed on the source region S6 of the transistor Tr6.

  Then, by forming wiring such as a word line (WL), a bit line (BL), and an inverted bit line (/ BL) that are electrically connected to the contact formed in the interlayer insulating film, a semiconductor device having an SRAM is formed. . In addition, although the code | symbol of each element in cells other than the area | region enclosed with the dotted line shown in FIG. 13 is abbreviate | omitted, it is the same as that of the cell of the area | region enclosed with the dotted line shown in FIG.

  In this embodiment, the channel region, the source region, and the drain region of the nMOS transistor and the pMOS transistor are formed on the common annular protrusion 2. For example, as shown in FIG. 13, the n-type channel region, n-type source region S1 and n-type drain region D1 of the nMOS transistor Tr1, and the p-type channel region, p-type source region S2 and p-type drain region of the pMOS transistor Tr2. D2 and the common annular protrusion 2 are formed. That is, the nMOS transistor Tr1 and the pMOS transistor Tr2 are formed on the common annular protrusion 2. According to the method for manufacturing a semiconductor device according to the present embodiment, compared to the case where the nMOS transistor and the pMOS transistor are not formed on the common annular protrusion 2, the formation area of the nMOS transistor and the pMOS transistor in the semiconductor device is reduced. Can be reduced. As a result, according to the manufacturing method of the semiconductor device according to the present embodiment, the SRAM element for one cell in the semiconductor device is compared with the case where the nMOS transistor and the pMOS transistor are not formed on the common annular protrusion 2. The formation area of can be reduced.

  In this embodiment, the nMOS transistor and the pMOS transistor in two adjacent cells are formed on the common annular protrusion 2. For example, as shown in FIG. 13, the nMOS transistor Tr1 and the pMOS transistor Tr2 in the cell surrounded by the dotted line and the nMOS transistor Tr7 and the pMOS transistor Tr8 in the cell adjacent to the cell surrounded by the dotted line are common. The protrusion 2 is formed. According to this embodiment, the formation area of the SRAM element in the semiconductor device can be reduced as compared with the case where the nMOS transistor and the pMOS transistor in two adjacent cells are not formed on the common protrusion 2.

  When the light source wavelength of an exposure apparatus used for photolithography is shortened to reduce the formation area of the nMOS transistor and the pMOS transistor in the semiconductor device, roughness (unevenness) is likely to occur in the resist pattern. According to the method for manufacturing a semiconductor device according to the present embodiment, the formation area of the nMOS transistor and the pMOS transistor in the semiconductor device can be reduced without shortening the light source wavelength of the exposure apparatus used for photolithography. Therefore, according to the method for manufacturing a semiconductor device according to the present embodiment, the formation area of the nMOS transistor and the pMOS transistor in the semiconductor device can be reduced while suppressing the occurrence of roughness (unevenness) in the resist pattern.

  Although a method for manufacturing a semiconductor device having an SRAM element by applying the method for manufacturing a semiconductor device according to the present embodiment has been described, the present embodiment is not limited to this. For example, the semiconductor device manufacturing method according to the present embodiment may be applied to manufacturing a semiconductor device having a CMOS transistor. Further, for example, the method for manufacturing a semiconductor device according to the present embodiment may be applied to a case where a semiconductor device having a latch circuit formed by spreading a CMOS inverter is manufactured.

DESCRIPTION OF SYMBOLS 1 Semiconductor substrate 2 Protrusion part 3, 11, 12, 21 Thin film 4, 10, 20 Semiconductor film 5, 13 Silicon oxide film 30 Resist pattern 40 Connection wiring 50, 50A, 50B Gate electrode

Claims (6)

Forming an annular protrusion on the substrate;
Forming a first n-type channel region on the annular protrusion;
Forming a first p-type channel region on the annular protrusion;
A first nMOS transistor and a first pMOS transistor are formed by forming a first gate electrode straddling the first n-type channel region and the first p-type channel region formed in the annular protrusion. Forming a step;
A method for manufacturing a semiconductor device, comprising: Forming a second n-type channel region on the annular protrusion;
Forming a second p-type channel region on the annular protrusion;
A second nMOS transistor and a second pMOS transistor are formed by forming a second gate electrode straddling the second n-type channel region and the second p-type channel region formed in the annular protrusion. Forming a step;
The method of manufacturing a semiconductor device according to claim 1, further comprising: Forming the first n-type channel region in the annular protrusion includes ion implantation of a p-type impurity from the first oblique direction into the annular protrusion;
The step of forming the first p-type channel region in the annular protrusion includes ion implantation of an n-type impurity from the second oblique direction with respect to the annular protrusion,
3. The method of manufacturing a semiconductor device according to claim 1, wherein the first oblique direction and the second oblique direction are different directions. The step of forming the second n-type channel region in the annular protrusion includes ion implantation of p-type impurities into the annular protrusion from the first oblique direction,
The step of forming the second p-type channel region in the annular protrusion includes ion implantation of n-type impurities from the second oblique direction with respect to the annular protrusion. A method for manufacturing a semiconductor device according to claim 3. A first pMOS transistor;
A first nMOS transistor;
An annular protrusion,
An n-type channel region of the first nMOS transistor and a p-type channel region of the first pMOS transistor are formed in the annular protrusion. A second nMOS transistor;
A second pMOS transistor,
6. The semiconductor device according to claim 5, wherein an n-type channel region of the second nMOS transistor and a p-type channel region of the second pMOS transistor are formed in the annular protrusion.

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