JP2011034990A - Wiring board and semiconductor device - Google Patents

Wiring board and semiconductor device Download PDF

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JP2011034990A
JP2011034990A JP2009176731A JP2009176731A JP2011034990A JP 2011034990 A JP2011034990 A JP 2011034990A JP 2009176731 A JP2009176731 A JP 2009176731A JP 2009176731 A JP2009176731 A JP 2009176731A JP 2011034990 A JP2011034990 A JP 2011034990A
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power supply
supply wiring
wiring
insulating substrate
semiconductor chip
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Nobuo Watanabe
信夫 渡辺
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Toshiba Corp
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Toshiba Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
    • H01L2224/49112—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting a common bonding area on the semiconductor or solid-state body to different bonding areas outside the body, e.g. diverging wires
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3011—Impedance
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3011—Impedance
    • H01L2924/30111—Impedance matching

Abstract

<P>PROBLEM TO BE SOLVED: To provide a wiring board having less noise generated in power supply wiring because of a change in an operating current, and to provide a semiconductor device using the wiring board. <P>SOLUTION: The semiconductor device includes: an insulating substrate 11; a semiconductor chip 12 placed on a first surface 11a of the insulating substrate 11; first power supply wiring 16 which is formed on the first surface 11a of the insulating substrate 11, in which one end is electrically connected to a power supply pad 14 of the semiconductor chip 12 through a wire 13 and the other end is connected to an external power supply terminal 15 formed on a second surface 11b opposite to the first surface 11a of the insulating substrate 11; and second power supply wiring 17 which is formed on the first surface 11a of the insulating substrate 11, in which one end is connected to one end of the first power supply wiring 16 and is extended to an empty region around the semiconductor chip 12, the other end is opened, and signal propagation time from one end to the other end is longer than signal propagation time from one end to the other end of the first power supply wiring 16. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

本発明は、配線基板および半導体装置に関する。   The present invention relates to a wiring board and a semiconductor device.

従来、複数の半導体チップが積層された、所謂ＭＣＰ（Multi Chip Package）タイプの半導体装置においては、積層する半導体チップの数に応じて、半導体チップを載置する基板上に形成される信号配線、電源配線、接地配線などの配線数が多くなるので、信号の伝送速度を確保するために信号配線が優先して最短で配置され、電源配線は信号配線を迂回するように引き回されて配置されていた。   Conventionally, in a so-called MCP (Multi Chip Package) type semiconductor device in which a plurality of semiconductor chips are stacked, according to the number of semiconductor chips to be stacked, signal wiring formed on a substrate on which the semiconductor chips are mounted, Since the number of power lines, ground lines, etc. increases, the signal lines are arranged with the shortest priority in order to secure the signal transmission speed, and the power lines are routed around the signal lines. It was.

そのため、電源配線が長くなるので、半導体チップの動作電流の変化に起因したノイズが電源配線に発生し、内部回路が誤作動するという問題がある。
通常、電源配線に生じたノイズを除去するために、電源配線の外部接続端子に大容量のバイバスコンデンサが接続されるが、実装面積が増加するので、半導体装置を内蔵する機器の小型化の障害になる問題がある。 For this reason, since the power supply wiring becomes long, noise due to a change in the operating current of the semiconductor chip occurs in the power supply wiring, causing a problem that the internal circuit malfunctions.
Normally, a large-capacity bypass capacitor is connected to the external connection terminal of the power supply wiring in order to eliminate noise generated in the power supply wiring. However, since the mounting area increases, it is an obstacle to downsizing of devices incorporating semiconductor devices. There is a problem to become.

これに対して、電源配線で主に発生する電磁波を減少させる信号伝送部材が知られている。（例えば、特許文献１参照。）。
特許文献１に開示された信号伝送部材は、ベースフィルムと、ベースフィルムに実装され、第１信号が入力されて第２信号を出力する半導体チップと、ベースフィルムに形成されて半導体チップと電気的に接続され、一部分が蛇行形状を有するように折れ曲がり、第１信号を半導体チップに供給する入力配線部と、ベースフィルムに形成されて半導体チップと電気的に接続され、半導体チップから第２信号を受信しこれを送信する出力配線部とを具備している。 On the other hand, a signal transmission member that reduces electromagnetic waves mainly generated in power supply wiring is known. (For example, refer to Patent Document 1).
The signal transmission member disclosed in Patent Document 1 is a base film, a semiconductor chip that is mounted on the base film and receives a first signal and outputs a second signal, and is formed on the base film and electrically connected to the semiconductor chip. Is connected to the semiconductor chip, and is bent so that a part thereof has a meandering shape. The input wiring section supplies the first signal to the semiconductor chip, and is formed on the base film and electrically connected to the semiconductor chip. And an output wiring section for receiving and transmitting the same.

入力配線部のなかの蛇行形状を有する電源ラインの長さを調節することにより、電源を供給する外部入力装置とのインピーダンスマッチングを向上させ、電源ラインに生じる電磁波を減少させている。   By adjusting the length of the power supply line having a meandering shape in the input wiring portion, impedance matching with an external input device that supplies power is improved, and electromagnetic waves generated in the power supply line are reduced.

然しながら、特許文献１に開示された信号伝送部材は、電源ラインを意図的に長くしているので、電源ラインの抵抗が増加し、電力損失が増加するという問題がある。   However, since the signal transmission member disclosed in Patent Document 1 intentionally lengthens the power supply line, there is a problem that the resistance of the power supply line increases and the power loss increases.

特開２００８−７２０８４号公報JP 2008-72084 A

本発明は、動作電流の変化により電源配線に生じるノイズの少ない配線基板およびそれを用いた半導体装置を提供する。   The present invention provides a wiring board with less noise generated in power supply wiring due to a change in operating current, and a semiconductor device using the wiring board.

本発明の一態様の半導体積装置は、絶縁性基板と、前記絶縁性基板の第１の面に載置された半導体チップと、前記絶縁性基板の第１の面に形成され、一端が接続導体を介して前記半導体チップの電源パッドに電気的に接続され、他端が前記絶縁性基板の前記第１の面と反対の第２の面に形成された外部電源端子に接続された第１電源配線と、前記絶縁性基板の第１の面に形成され、一端が前記第１電源配線の一端に連接して前記半導体チップの周りの空き領域に延伸し、他端が開放されるとともに、一端から他端までの信号伝播時間が前記第１電源配線の一端から他端までの信号伝播時間より長い第２電源配線と、を具備することを特徴としている。   A semiconductor product of one embodiment of the present invention includes an insulating substrate, a semiconductor chip mounted on the first surface of the insulating substrate, and a first surface connected to the first surface of the insulating substrate. A first electrically connected to the power supply pad of the semiconductor chip via a conductor and the other end connected to an external power supply terminal formed on a second surface opposite to the first surface of the insulating substrate. Formed on the first surface of the power supply wiring and the insulating substrate, one end is connected to one end of the first power supply wiring and extends to an empty area around the semiconductor chip, the other end is opened, And a second power supply wiring having a signal propagation time from one end to the other end longer than a signal propagation time from one end to the other end of the first power supply wiring.

本発明の一態様の配線基板は、絶縁性基板と、前記絶縁性基板の第１の面に形成され、一端が接続導体を介して前記絶縁性基板に載置される半導体チップの電源パッドに電気的に接続され、他端が前記絶縁性基板の前記第１の面と反対の第２の面に形成された外部電源端子に接続された第１電源配線と、前記絶縁性基板の第１の面に形成され、一端が前記第１電源配線の一端に連接して前記半導体チップの周りの空き領域に延伸し、他端が開放されるとともに、一端から他端までの信号伝播時間が前記第１電源配線の一端から他端までの信号伝播時間より長い第２電源配線と、を具備することを特徴としている。   The wiring substrate of one embodiment of the present invention is formed on an insulating substrate and a power pad of a semiconductor chip formed on the first surface of the insulating substrate and having one end mounted on the insulating substrate via a connection conductor. A first power supply line electrically connected and having the other end connected to an external power supply terminal formed on a second surface opposite to the first surface of the insulating substrate; The one end is connected to one end of the first power supply wiring and extends to an empty area around the semiconductor chip, the other end is opened, and the signal propagation time from one end to the other end is And a second power supply wiring longer than a signal propagation time from one end to the other end of the first power supply wiring.

本発明によれば、動作電流の変化により電源配線に生じるノイズの少ない配線基板およびそれを用いた半導体装置が得られる。   According to the present invention, it is possible to obtain a wiring board with less noise generated in power supply wiring due to a change in operating current and a semiconductor device using the wiring board.

本発明の実施例１に係る半導体集置を示す図で、図１（ａ）はその平面図、図１（ｂ）は図１（ａ）のＡ−Ａ線に沿って切断し矢印方向に眺めた断面図。BRIEF DESCRIPTION OF THE DRAWINGS It is a figure which shows the semiconductor arrangement | positioning based on Example 1 of this invention, FIG. 1 (a) is the top view, FIG.1 (b) cuts along the AA line of FIG. A cross-sectional view. 本発明の実施例１に係る配線基板を示す図で、図２（ａ）はその平面図、図２（ｂ）は図２（ａ）のＢ−Ｂ線に沿って切断し矢印方向に眺めた断面図。FIG. 2A is a plan view of the wiring board according to the first embodiment of the present invention, FIG. 2B is a plan view thereof, and FIG. 2B is cut along the line BB in FIG. Sectional view. 本発明の実施例１に係る半導体装置の要部の等価回路を示す図。1 is a diagram showing an equivalent circuit of a main part of a semiconductor device according to Embodiment 1 of the present invention. 本発明の実施例１に係る半導体装置の要部の動作を比較例と対比して示す図で、図４（ａ）が実施例の動作を示す図、図４（ｂ）が比較例の動作を示す図。FIG. 4A is a diagram illustrating the operation of the main part of the semiconductor device according to the first embodiment of the present invention in comparison with the comparative example, FIG. 4A is a diagram illustrating the operation of the embodiment, and FIG. 4B is the operation of the comparative example. FIG. 本発明の実施例１に係る比較例の半導体装置を示す図。1 is a view showing a semiconductor device of a comparative example according to Example 1 of the present invention. 本発明の実施例２に係る半導体集積装置を示す図。FIG. 6 is a diagram illustrating a semiconductor integrated device according to a second embodiment of the present invention. 本発明の実施例３に係る半導体集積装置を示す図。FIG. 6 is a diagram illustrating a semiconductor integrated device according to a third embodiment of the present invention.

以下、本発明の実施例について図面を参照しながら説明する。   Embodiments of the present invention will be described below with reference to the drawings.

本発明の実施例１に係る配線基板および半導体装置について図１乃至図４を用いて説明する。図１は本実施例の半導体装置を示す図で、図１（ａ）はその平面図、図１（ｂ）は図１（ａ）のＡ−Ａ線に沿って切断し矢印方向に眺めた断面図、図２は配線基板を示す図で、図２（ａ）はその平面図、図２（ｂ）は図２（ａ）のＢ−Ｂ線に沿って切断し矢印方向に眺めた断面図である。   A wiring board and a semiconductor device according to Example 1 of the present invention will be described with reference to FIGS. 1A and 1B are diagrams showing the semiconductor device of this embodiment, FIG. 1A is a plan view thereof, and FIG. 1B is cut along the line AA in FIG. FIG. 2A is a plan view of the wiring board, FIG. 2B is a plan view thereof, and FIG. 2B is a cross-sectional view taken along the line BB in FIG. FIG.

始に、配線基板について説明する。図２に示すように、本実施例の配線基板３０は、中央部に半導体チップが載置される第１の領域３１と、第１の領域の周りに信号配線、電源配線、接地配線と、信号配線、電源配線、接地配線を外部に引き出すための外部接続端子などが形成される第２の領域３２とを具備している。   First, the wiring board will be described. As shown in FIG. 2, the wiring board 30 of the present embodiment includes a first region 31 where a semiconductor chip is placed in the center, signal wiring, power supply wiring, ground wiring around the first region, And a second region 32 in which external connection terminals for drawing signal wiring, power supply wiring, and ground wiring to the outside are formed.

配線基板３０は、絶縁性基板１１と、絶縁性基板１１の第１の面１１ａに形成され、一端が接続導体を介して絶縁性基板１１の中央部に載置される予定の半導体チップの電源パッドに電気的に接続され、他端が絶縁性基板１１の第１の面１１ａと反対の第２の面１１ｂの外周部に形成された外部電源端子１５に接続された第１電源配線１６と、絶縁性基板１１の第１の面１１ａに形成され、一端が第１電源配線１６の一端に連接して半導体チップの周りの空き領域に延伸し、他端が開放されるとともに、一端から他端までの信号伝播時間が第１電源配線１６の一端から他端までの信号伝播時間より長い第２電源配線１７と、を具備している。   The wiring substrate 30 is formed on the insulating substrate 11 and the first surface 11 a of the insulating substrate 11, and one end of the power supply for the semiconductor chip that is to be placed on the central portion of the insulating substrate 11 via the connection conductor. A first power supply wiring 16 electrically connected to the pad and having the other end connected to an external power supply terminal 15 formed on the outer peripheral portion of the second surface 11b opposite to the first surface 11a of the insulating substrate 11; Formed on the first surface 11a of the insulating substrate 11, with one end connected to one end of the first power supply wiring 16 and extending to a free area around the semiconductor chip, the other end being opened, and the other from one end to the other. And a second power supply wiring 17 having a signal propagation time to one end longer than a signal propagation time from one end to the other end of the first power supply wiring 16.

図１に示すように、本実施例の半導体装置１０は、配線基板３０の第１の領域３１に半導体チップが載置され、第２の領域に信号配線、電源配線、接地配線と、信号配線、電源配線、接地配線を外部に引き出すための外部接続端子などが形成され、半導体チップと信号配線、電源配線、接地配線はワイヤを介して電気的に接続されている。   As shown in FIG. 1, in the semiconductor device 10 of this embodiment, a semiconductor chip is placed in a first region 31 of a wiring board 30, and signal wiring, power supply wiring, ground wiring, and signal wiring are arranged in a second region. External connection terminals for leading out the power supply wiring and the ground wiring are formed, and the semiconductor chip and the signal wiring, the power supply wiring, and the ground wiring are electrically connected through the wires.

半導体装置１０は、絶縁性基板１１と、絶縁性基板１１の第１の面１１ａの中央部に載置された半導体チップ１２と、絶縁性基板１１の第１の面１１ａに形成され、一端がワイヤ（接続導体）１３を介して半導体チップ１２の電源パッド１４に電気的に接続され、他端が絶縁性基板１１の第１の面１１ａと反対の第２の面１１ｂの外周部に形成された外部電源端子１５に接続された第１電源配線１６と、絶縁性基板１１の第１の面１１ａに形成され、一端が第１電源配線１６の一端に連接して半導体チップ１２の周りの空き領域に延伸し、他端が開放されるとともに一端から他端までの信号伝播時間が第１電源配線１６の一端から他端までの信号伝播時間より長い第２電源配線１７と、を具備している。   The semiconductor device 10 is formed on an insulating substrate 11, a semiconductor chip 12 placed in the center of the first surface 11 a of the insulating substrate 11, and the first surface 11 a of the insulating substrate 11, one end of which is formed. The other end is formed on the outer peripheral portion of the second surface 11 b opposite to the first surface 11 a of the insulating substrate 11 and is electrically connected to the power supply pad 14 of the semiconductor chip 12 through the wire (connection conductor) 13. The first power supply wiring 16 connected to the external power supply terminal 15 and the first surface 11a of the insulating substrate 11 are formed on the first surface 11a. One end of the first power supply wiring 16 is connected to one end of the first power supply wiring 16 and is free around the semiconductor chip 12. A second power supply wiring 17 extending in a region, the other end being opened, and a signal propagation time from one end to the other end being longer than a signal propagation time from one end to the other end of the first power supply wiring 16. Yes.

絶縁性基板１１は、例えば板状のセラミックス基板である。半導体チップ１２は、例えば入力信号に対して所定の処理を施し、処理結果をＰチャネルＭＯＳトランジスタとＮチャネルＭＯＳトランジスタが直列接続された出力バッファ回路を介して出力する半導体集積回路である。   The insulating substrate 11 is a plate-shaped ceramic substrate, for example. The semiconductor chip 12 is a semiconductor integrated circuit that performs predetermined processing on an input signal, for example, and outputs a processing result via an output buffer circuit in which a P-channel MOS transistor and an N-channel MOS transistor are connected in series.

外部電源端子１５は、例えばハンダボールで、ビア１８を介して第１電源配線１６に接続されている。同様に、その他の外部接続端子もハンダボールで、ビアを介して信号配線、接地配線などに接続されている。   The external power supply terminal 15 is a solder ball, for example, and is connected to the first power supply wiring 16 through the via 18. Similarly, other external connection terminals are also solder balls and are connected to signal wiring, ground wiring, and the like through vias.

第１電源配線１６、第２電源配線１７は、例えばフォトリソグラフィ法によりパターニングされた金配線である。第１電源配線１６の一端と、第２電源配線１７との連接部には、ワイヤ１３をボンディングするための接続パッド１９が形成されている。   The first power supply wiring 16 and the second power supply wiring 17 are gold wirings patterned by, for example, a photolithography method. A connection pad 19 for bonding the wire 13 is formed at a connecting portion between one end of the first power supply wiring 16 and the second power supply wiring 17.

第１電源配線１６は、電源パッド１４と外部電源端子１５とを最短距離で接続するように直線的に配置されている。
第２電源配線１７は、図では便宜上直線的なＬ字状に表示されているが、実際には種々蛇行して配置されている。即ち、図示しない信号配線、接地配線、別の電源配線などを迂回し、信号配線、接地配線、別の電源配線などが配置されていない空き領域を縫う様に引き回して配置されている。 The first power supply wiring 16 is linearly arranged so as to connect the power supply pad 14 and the external power supply terminal 15 with the shortest distance.
The second power supply wiring 17 is displayed in a straight L-shape for convenience in the drawing, but is actually arranged in a meandering manner. In other words, the signal wiring, ground wiring, another power supply wiring, etc. (not shown) are detoured and arranged so as to sew an empty area where the signal wiring, ground wiring, another power supply wiring, etc. are not arranged.

蛇行パターンには、Ｓ字状のパターンだけでなく、九十九折状のパターン、渦巻き状のパターン、空き領域の形状に応じて各種のパターンを種々組み合わせたパターンなどが含まれる。   The meandering pattern includes not only an S-shaped pattern but also a 99-fold pattern, a spiral pattern, a pattern in which various patterns are combined in accordance with the shape of the empty area, and the like.

第２電源配線１７の一端から他端までの信号伝播遅延時間τ２が第１電源配線１６の一端から他端までの信号伝播遅延時間τ１より大きくなるように（τ１＜τ２）、第２電源配線１７の長さＬ２は、第１電源配線１６の長さＬ１より大きく設定されている（Ｌ１＜Ｌ２）。   The second power supply wiring is set so that the signal propagation delay time τ2 from one end to the other end of the second power supply wiring 17 is longer than the signal propagation delay time τ1 from one end to the other end of the first power supply wiring 16 (τ1 <τ2). The length L2 of 17 is set larger than the length L1 of the first power supply wiring 16 (L1 <L2).

図３は半導体装置１０の要部の等価回路を示す図である。図３に示すように、半導体装置１０は、外部電源端子１５が、例えば出力電圧が１．８Ｖの安定化された電源４１に接続され、電源４１から第１電源配線１６を通して半導体チップ１２に動作電流が供給される。
外部電源端子１５には、動作電流の変化に起因して第１電源配線１６に生じたノイズを吸収するための大容量、例えば０．１μＦのバイパスコンデンサ４２が接続されている。 FIG. 3 is a diagram showing an equivalent circuit of a main part of the semiconductor device 10. As shown in FIG. 3, in the semiconductor device 10, the external power supply terminal 15 is connected to a stabilized power supply 41 having an output voltage of, for example, 1.8 V, and operates from the power supply 41 to the semiconductor chip 12 through the first power supply wiring 16. Current is supplied.
The external power supply terminal 15 is connected to a bypass capacitor 42 having a large capacity, for example, 0.1 μF, for absorbing noise generated in the first power supply wiring 16 due to a change in operating current.

第１電源配線１６は、例えば特性インピーダンスが５０Ωで、長さＬ１の同軸ケーブルで表わされる。同様に、第２電源配線１７は特性インピーダンスが５０Ωで、長さＬ２の同軸ケーブルで表わされる。長さＬ２は長さＬ１より大きいので、第２電源配線１７の信号伝播遅延時間τ２は第１電源配線１６の信号伝播遅延時間τ１より大きく設定されている。   The first power supply wiring 16 is represented by a coaxial cable having a characteristic impedance of 50Ω and a length L1, for example. Similarly, the second power supply wiring 17 is represented by a coaxial cable having a characteristic impedance of 50Ω and a length L2. Since the length L2 is larger than the length L1, the signal propagation delay time τ2 of the second power supply wiring 17 is set to be longer than the signal propagation delay time τ1 of the first power supply wiring 16.

半導体チップ１２は、５０Ωの内部抵抗４３を有するノイズ発生源４４で表わされる。ＰチャネルＭＯＳトランジスタＭ１とＮチャネルＭＯＳトランジスタＭ２とが直列接続された出力バッファ回路４５は、ＮＭＯＳトランジスタＭ２がオフし、ＰＭＯＳトランジスタＭ１がオンすると、外部の容量性負荷４６を充電するための電流が増加して出力バッファ回路４５にかかる電圧が過渡的に降下し、降下した電圧を補償するように電源４１側から電力が供給されて出力バッファ回路４５にかかる電圧が上昇するという動作電流の変化に起因してパルスノイズを発生する。   The semiconductor chip 12 is represented by a noise generation source 44 having an internal resistance 43 of 50Ω. In the output buffer circuit 45 in which the P-channel MOS transistor M1 and the N-channel MOS transistor M2 are connected in series, when the NMOS transistor M2 is turned off and the PMOS transistor M1 is turned on, a current for charging the external capacitive load 46 is generated. The voltage applied to the output buffer circuit 45 increases and the voltage applied to the output buffer circuit 45 rises as the voltage applied to the output buffer circuit 45 is increased by compensating for the dropped voltage. As a result, pulse noise is generated.

ここで、Ｖｉｎはノイズ発生源４４の出力電圧、Ｖｂは第１電源配線１６と第２電源配線１７との接続ノードＮ１の電圧、Ｖｃは外部電源端子１５とバイパスコンデンサ４２との接続ノードＮ２の電圧を表している。   Here, Vin is an output voltage of the noise generation source 44, Vb is a voltage at the connection node N1 between the first power supply wiring 16 and the second power supply wiring 17, and Vc is at a connection node N2 between the external power supply terminal 15 and the bypass capacitor 42. Represents voltage.

図４は半導体装置１０の要部の動作を比較例と対比して示す図で、図４（ａ）が本実施例の動作を示す図、図４（ｂ）が比較例の動作を示す図である。比較例とは、図５に示すように、第２電源配線１７が形成されていない半導体装置６０のことである。   4A and 4B are diagrams showing the operation of the main part of the semiconductor device 10 in comparison with the comparative example. FIG. 4A is a diagram showing the operation of this embodiment, and FIG. 4B is the diagram showing the operation of the comparative example. It is. As shown in FIG. 5, the comparative example is a semiconductor device 60 in which the second power supply wiring 17 is not formed.

半導体装置の要部の動作は、電源４１の電圧が１．８Ｖ、第１電源配線１６の信号伝播遅延時間が２ｎｓ、第２電源配線１７の信号伝播遅延時間が５ｎｓとしてシミュレーションにより求めた。出力バッファ回路４５がオフしている初期状態では、電圧Ｖｉｎ、電圧Ｖｂ、電圧Ｖｃはともに電源４１の電圧１．８Ｖである。   The operation of the main part of the semiconductor device was obtained by simulation with the voltage of the power supply 41 being 1.8 V, the signal propagation delay time of the first power supply wiring 16 being 2 ns, and the signal propagation delay time of the second power supply wiring 17 being 5 ns. In the initial state in which the output buffer circuit 45 is off, the voltage Vin, the voltage Vb, and the voltage Vc are all the voltage 1.8V of the power supply 41.

始に、比較例について説明する。図４（ｂ）に示すように、比較例では、出力バッファ回路４５がオンして容量性負荷４６を充電する電流が流れると、電圧Ｖｉｎは破線５１に示すように１．８Ｖから１Ｖまで過渡的に低下する。   First, a comparative example will be described. As shown in FIG. 4B, in the comparative example, when the output buffer circuit 45 is turned on and a current for charging the capacitive load 46 flows, the voltage Vin changes from 1.8 V to 1 V as indicated by the broken line 51. Decline.

次に、電圧Ｖｉｎの低下量０．８Ｖは内部抵抗４３と第１電源配線１６のインピーダンスに応じて１／２に分圧され、電圧Ｖｂは実線５２に示すように０．４Ｖ減少し、１．８Ｖから１．４Ｖまで過渡的に低下する。   Next, the decrease amount 0.8V of the voltage Vin is divided by half according to the impedance of the internal resistor 43 and the first power supply wiring 16, and the voltage Vb decreases by 0.4V as shown by the solid line 52. .Transiently decreases from 8V to 1.4V.

次に、電圧Ｖｂの低下が第１電源配線１６の信号伝播遅延時間τ１後に、電源４１に伝わり、電圧Ｖｂの低下を補うように電源４１から電力が供給されるので、反動として２τ１後に、電圧Ｖｂは実線５３に示すように０．４３Ｖ増加し、２．２４Ｖまで過渡的に上昇する。   Next, the decrease in the voltage Vb is transmitted to the power supply 41 after the signal propagation delay time τ1 of the first power supply wiring 16, and power is supplied from the power supply 41 so as to compensate for the decrease in the voltage Vb. As shown by the solid line 53, Vb increases by 0.43V and rises transiently to 2.24V.

その結果、第１接続ノードＮ１に振幅が０．８４Ｖのパルス状のノイズＶｎ２が生じる。第２接続ノードＮ２の電圧Ｖｃは、安定化された電源４１に接続されているので、基本的に一定である。   As a result, pulsed noise Vn2 having an amplitude of 0.84V is generated at the first connection node N1. Since the voltage Vc of the second connection node N2 is connected to the stabilized power supply 41, it is basically constant.

一方、図４（ａ）に示すように、本実施例では、第１電源配線１６と第２電源配線１７が並列に接続されているので、特性インピーダンスが１／２になっている。
そのため、電圧Ｖｉｎの低下量０．８Ｖは内部抵抗４３と並列接続された第１電源配線１６と第２電源配線１７のインピーダンスに応じて１／３に分圧され、電圧Ｖｂは実線５４に示すように０．２６Ｖ減少し、１．８Ｖから１．５４Ｖまで過渡的に低下する。電圧Ｖｂの低下は、比較例に比べて少ないことが分かる。 On the other hand, as shown in FIG. 4A, in the present embodiment, since the first power supply wiring 16 and the second power supply wiring 17 are connected in parallel, the characteristic impedance is halved.
Therefore, the decrease amount 0.8V of the voltage Vin is divided by 1/3 according to the impedance of the first power supply wiring 16 and the second power supply wiring 17 connected in parallel with the internal resistor 43, and the voltage Vb is indicated by a solid line 54. Thus, the voltage decreases by 0.26V and decreases transiently from 1.8V to 1.54V. It can be seen that the decrease in the voltage Vb is less than that in the comparative example.

次に、反動として２τ１後に、電圧Ｖｂは実線５５に示すように０．２Ｖ増加し、２Ｖまで過渡的に上昇するのは比較例と同様である。電圧Ｖｂの上昇は、比較例に比べて少ないことが分かる。   Next, after 2τ1 as a reaction, the voltage Vb increases by 0.2 V as shown by the solid line 55 and rises transiently to 2 V, as in the comparative example. It can be seen that the increase in the voltage Vb is smaller than that in the comparative example.

その結果、第１接続ノードＮ１に振幅が０．４６Ｖのパルス状のノイズＶｎ１が生じる。ノイズＶｎ１は比較例のノイズＶｎ２に比べて少なくなり、ほぼ半減している。
これにより、第１接続ノードＮ１の電圧Ｖｂが安定化され、電源配線に生じるノイズが内部回路へ与える影響を低減することが可能である。 As a result, pulsed noise Vn1 having an amplitude of 0.46V is generated at the first connection node N1. The noise Vn1 is smaller than the noise Vn2 of the comparative example and is almost halved.
Thereby, the voltage Vb of the first connection node N1 is stabilized, and it is possible to reduce the influence of noise generated in the power supply wiring on the internal circuit.

更に、発生したノイズＶｎ１は、第２電源配線１７を伝播し、開放されている他端で反射して２τ２後にほぼそのまま戻ってくるので、第１接続ノードＮ１に振幅が０．４３Ｖのパルス状のノイズＶｎ１ａが生じる。実線５４に示す負極性ノイズの反射が実線５７に示すノイズであり、実線５５に示す正極性ノイズの反射が実線５８に示すノイズである。   Further, the generated noise Vn1 propagates through the second power supply wiring 17, is reflected at the other open end, and returns almost as it is after 2τ2, so that a pulse shape having an amplitude of 0.43 V is applied to the first connection node N1. Noise Vn1a occurs. Reflection of negative polarity noise indicated by a solid line 54 is noise indicated by a solid line 57, and reflection of positive polarity noise indicated by a solid line 55 is noise indicated by a solid line 58.

信号伝播遅延時間τ１が信号伝播遅延時間τ２より短かく、接続ノードＮ１にノイズＶｎ１ａが到着する前に信号の授受が完了しているので、ノイズＶｎ１ａが内部回路の動作に影響を及ぼすことは無い。   Since the signal propagation delay time τ1 is shorter than the signal propagation delay time τ2, and the signal exchange is completed before the noise Vn1a arrives at the connection node N1, the noise Vn1a does not affect the operation of the internal circuit. .

更に、ノイズＶｎ１ａが到着しても、ノイズＶｎ１はバイパスコンデンサ４２により消された状態に有るので、ノイズＶｎ１とノイズＶｎ１ａが干渉することはなく、ノイズＶｎ１ａが内部回路の動作に影響を及ぼすことは無い。   Furthermore, even if the noise Vn1a arrives, the noise Vn1 is in a state of being canceled by the bypass capacitor 42, so the noise Vn1 and the noise Vn1a do not interfere with each other, and the noise Vn1a does not affect the operation of the internal circuit. No.

以上説明したように、本実施例では絶縁性基板１１の第１の面１１ａに形成され、一端がワイヤ１３を介して半導体チップ１２の電源パッド１４に電気的に接続され、他端が絶縁性基板１１の第１の面１１ａと反対の第２の面１１ｂに形成された外部電源端子１５に接続された第１電源配線１６と、絶縁性基板１１の第１の面１１ａに形成され、一端が第１電源配線１６の一端に連接して半導体チップ１２の周りの空き領域に延伸し、他端が開放されるとともに、一端から他端までの信号伝播時間τ２が第１電源配線１６の一端から他端までの信号伝播時間τ１より長い第２電源配線１７と、を具備している。   As described above, in this embodiment, the first surface 11a of the insulating substrate 11 is formed, one end is electrically connected to the power pad 14 of the semiconductor chip 12 through the wire 13, and the other end is insulative. A first power supply wiring 16 connected to the external power supply terminal 15 formed on the second surface 11b opposite to the first surface 11a of the substrate 11, and a first surface 11a of the insulating substrate 11 formed on one end Is connected to one end of the first power supply wiring 16 and extends to an empty area around the semiconductor chip 12, the other end is opened, and the signal propagation time τ 2 from one end to the other end is one end of the first power supply wiring 16. And a second power supply wiring 17 longer than the signal propagation time τ1 from the other end to the other end.

その結果、第１電源配線１６と第２電源配線１７とが並列接続されて電源配線のインピーダンスが低下するので、動作電流の変化に起因するノイズＶｎ１の振幅を低減することができる。
従って、動作電流の変化により電源配線に生じるノイズの少ない配線基板およびそれを用いた半導体装置が得られる。 As a result, the first power supply wiring 16 and the second power supply wiring 17 are connected in parallel and the impedance of the power supply wiring is lowered, so that the amplitude of the noise Vn1 due to the change in operating current can be reduced.
Accordingly, it is possible to obtain a wiring board with less noise generated in the power supply wiring due to a change in operating current and a semiconductor device using the wiring board.

第１電源配線１６は、最短で配置しているので、特許文献１に記載された信号伝送部材に比べて配線抵抗の増加によりムダに消費される電力を抑制することができる。更に、第２電源配線１７は他端が開放されているので、第２電源配線１７による消費電力は無視できるレベルである。   Since the 1st power supply wiring 16 is arrange | positioned in the shortest, compared with the signal transmission member described in patent document 1, the electric power consumed by waste by the increase in wiring resistance can be suppressed. Further, since the other end of the second power supply wiring 17 is open, the power consumption by the second power supply wiring 17 is at a negligible level.

ここでは、第１電源配線１６と第２電源配線１７の特性インピーターンスが等しい場合に説明したが、異なっていても構わない。その場合は、第２電源配線１７の特性インピーターンスが第１電源配線１６の特性インピーターンスより小さいことが望ましい。第１電源配線１６と第２電源配線１７が並列接続された電源配線の特性インピーダンスをより小さくできるからである。   Here, the case where the characteristic impedances of the first power supply wiring 16 and the second power supply wiring 17 are the same is described, but they may be different. In that case, it is desirable that the characteristic impedance of the second power supply wiring 17 is smaller than the characteristic impedance of the first power supply wiring 16. This is because the characteristic impedance of the power supply wiring in which the first power supply wiring 16 and the second power supply wiring 17 are connected in parallel can be further reduced.

第２電源配線１７の特性インピーターンスを第１電源配線１６の特性インピーターンスより小さくするには、例えば第２電源配線１７の幅を第１電源配線の幅より大きくすることが考えられる。   In order to make the characteristic impedance of the second power supply wiring 17 smaller than the characteristic impedance of the first power supply wiring 16, for example, it is conceivable to make the width of the second power supply wiring 17 larger than the width of the first power supply wiring.

外部電源端子１５がハンダボールである場合について説明したが、リード端子とすることも可能である。   Although the case where the external power supply terminal 15 is a solder ball has been described, it may be a lead terminal.

本発明の実施例２に係る半導体装置について図６を用いて説明する。図６は本実施例の半導体装置を示す図である。本実施例において、上記実施例１と同一の構成部分には同一符号を付してその部分の説明は省略し、異なる部分について説明する。本実施例が実施例１と異なる点は、第１電源配線の一端と第２電源配線の一端とが離間していることにある。   A semiconductor device according to Embodiment 2 of the present invention will be described with reference to FIG. FIG. 6 is a diagram showing the semiconductor device of this embodiment. In the present embodiment, the same components as those in the first embodiment are denoted by the same reference numerals, description thereof will be omitted, and different portions will be described. This embodiment is different from the first embodiment in that one end of the first power supply wiring and one end of the second power supply wiring are separated from each other.

即ち、図６に示すように、本実施例の半導体集積装置７０は、一端が第１電源配線１６の一端と離間し、ワイヤ（第２接続導体）７１を介して電源パッド１４に共通に接続され、他端が開放された第２電源配線７２を具備している。   That is, as shown in FIG. 6, in the semiconductor integrated device 70 of this embodiment, one end is separated from one end of the first power supply wiring 16, and is commonly connected to the power supply pad 14 via the wire (second connection conductor) 71. The second power supply wiring 72 is open at the other end.

第２電源配線７２の一端にはワイヤ７１をボンディングするための接続パッド７３が形成されている。第２電源配線７２は、図１に示した第２電源配線１７と同様に蛇行して配置されている。第２電源配線７２の信号伝播遅延時間τ２が第１電源配線１６の信号伝播遅延時間τ１より大きくなるように（τ１＜τ２）、第２電源配線７２の長さＬ２は、第１電源配線１６の長さＬ１より大きく設定されている（Ｌ１＜Ｌ２）。   A connection pad 73 for bonding the wire 71 is formed at one end of the second power supply wiring 72. The second power supply wiring 72 is arranged meandering like the second power supply wiring 17 shown in FIG. The length L2 of the second power supply wiring 72 is set so that the signal propagation delay time τ2 of the second power supply wiring 72 is longer than the signal propagation delay time τ1 of the first power supply wiring 16 (τ1 <τ2). Is set to be larger than the length L1 (L1 <L2).

これにより、半導体チップ１２の電源パッド１４でのノイズ量が少なくなる利点がある。図１に示す第１、第２電源配線１６、１７が分離されていない場合は、ワイヤが共通なので、半導体チップ１２の電源パッド部１４にはワイヤ１３による影響が生じる。   This has the advantage that the amount of noise at the power supply pad 14 of the semiconductor chip 12 is reduced. When the first and second power supply wirings 16 and 17 shown in FIG. 1 are not separated, the wires are common, and therefore, the power supply pad portion 14 of the semiconductor chip 12 is affected by the wires 13.

更に、第１電源配線１６と第２電源配線７２との間の空き領域７４には、信号配線、別の電源配線、接地配線などを配置することが可能である。   Furthermore, a signal line, another power line, a ground line, and the like can be arranged in the empty area 74 between the first power line 16 and the second power line 72.

以上説明したように、本実施例では、第１電源配線１６の一端と第２電源配線７２の一端とが離間し、それぞれワイヤ１３、７１を介して電源パッド１４に接続されているので、電源パッド１４でのノイズ量が少なくなる利点がある。更に、空き領域７４に別の配線などを配置することができる利点がある。そのため、優先的に信号配線を最短で配置し、信号の伝送速度を確保するのに支障をきたす恐れがない。   As described above, in this embodiment, one end of the first power supply wiring 16 and one end of the second power supply wiring 72 are separated from each other and connected to the power supply pad 14 via the wires 13 and 71, respectively. There is an advantage that the amount of noise at the pad 14 is reduced. Further, there is an advantage that another wiring or the like can be arranged in the empty area 74. For this reason, there is no fear that the signal wiring is preferentially arranged in the shortest time and there is no problem in securing the signal transmission speed.

本発明の実施例３に係る半導体装置について図７を用いて説明する。図７は本実施の半導体装置を示す図である。本実施例において、上記実施例１と同一の構成部分には同一符号を付してその部分の説明は省略し、異なる部分について説明する。本実施例が実施例１と異なる点は、複数の半導体チップを積層し、各半導体チップに第１および第２電源配線を接続したことにある。   A semiconductor device according to Example 3 of the present invention will be described with reference to FIG. FIG. 7 shows the semiconductor device of this embodiment. In the present embodiment, the same components as those in the first embodiment are denoted by the same reference numerals, description thereof will be omitted, and different portions will be described. The present embodiment is different from the first embodiment in that a plurality of semiconductor chips are stacked and first and second power supply wirings are connected to each semiconductor chip.

即ち、図７に示すように、本実施例の半導体装置８０は、半導体チップ１２の上に電源パッド１４を露出するように半導体チップ８１が積層され、第１電源配線８２および第２電源配線８３がワイヤ８４介して半導体チップ８１の電源パッド８５に電気的に接続されている。第１電源配線８２および第２電源配線８３の連接部には、ワイヤ８４をボンディングするための接続パッド８６が形成されている。   That is, as shown in FIG. 7, in the semiconductor device 80 of this embodiment, the semiconductor chip 81 is laminated on the semiconductor chip 12 so as to expose the power supply pad 14, and the first power supply wiring 82 and the second power supply wiring 83 are formed. Is electrically connected to the power supply pad 85 of the semiconductor chip 81 through a wire 84. A connection pad 86 for bonding the wire 84 is formed at the connecting portion of the first power supply wiring 82 and the second power supply wiring 83.

第１電源配線８２および第２電源配線８３は、第１電源配線１６および第２電源配線１７と同様に蛇行して配置され、第２電源配線８３の信号伝播遅延時間τ２が第１電源配線８２信号伝播遅延時間τ１より大きくなるように（τ１＜τ２）、第２電源配線８３の長さＬ４は、第１電源配線８２の長さＬ３より大きく設定されている（Ｌ３＜Ｌ４）。   The first power supply wiring 82 and the second power supply wiring 83 are arranged meandering like the first power supply wiring 16 and the second power supply wiring 17, and the signal propagation delay time τ 2 of the second power supply wiring 83 is set to the first power supply wiring 82. The length L4 of the second power supply wiring 83 is set to be greater than the length L3 of the first power supply wiring 82 (L3 <L4) so as to be longer than the signal propagation delay time τ1 (τ1 <τ2).

積層する半導体チップの数に応じて、絶縁性基板１１上に形成される信号配線、電源配線、接地配線などの配線数が多くなり、必然的に電源配線が長くなるが、半導体チップの周りの空き領域を有効に利用し、半導体チップ毎に動作電流の変化に起因して電源配線に生じるノイズを低減することができる。   Depending on the number of semiconductor chips to be stacked, the number of signal lines, power supply lines, ground lines, etc. formed on the insulating substrate 11 increases, and the power supply lines are inevitably longer. It is possible to effectively use the vacant area and reduce noise generated in the power supply wiring due to a change in operating current for each semiconductor chip.

以上説明したように、本実施例の半導体装置８０は、半導体チップ１２、８１が積層され、半導体チップ１２に第１および第２電源配線１６、１７が接続され、半導体チップに第１および第２電源配線８２、８３が接続されているので、半導体チップ毎に動作電流の変化に起因して第１電源配線に生じるノイズを低減できる利点がある。   As described above, in the semiconductor device 80 of this embodiment, the semiconductor chips 12 and 81 are stacked, the first and second power supply wirings 16 and 17 are connected to the semiconductor chip 12, and the first and second power supplies are connected to the semiconductor chip. Since the power supply wirings 82 and 83 are connected, there is an advantage that noise generated in the first power supply wiring due to the change in the operating current for each semiconductor chip can be reduced.

本発明は、以下の付記に記載されているような構成が考えられる。
（付記１） 複数の前記半導体チップが互いに前記電源パッドを露出するように積層され、各前記半導体チップの前記電源パッドに前記第１電源配線および前記第２電源配線がそれぞれ前記第１および第２接続導体を介して電気的に接続されている請求項２に記載の半導体装置。 The present invention can be configured as described in the following supplementary notes.
(Appendix 1) A plurality of the semiconductor chips are stacked so as to expose the power supply pads, and the first power supply wiring and the second power supply wiring are respectively connected to the power supply pads of the semiconductor chips. The semiconductor device according to claim 2, which is electrically connected via a connection conductor.

（付記２） 前記第２電源配線が蛇行している請求項１、２、３、付記１に記載の半導体装置。 (Supplementary Note 2) The semiconductor device according to any one of Claims 1, 2, 3, and Supplementary 1, wherein the second power supply wiring meanders.

（付記３） 前記第２電源配線の特性インピーダンスが、前記第１電源配線の特性インピーダンスより小さい請求項１、２、３、付記１、２に記載の半導体装置。 (Supplementary note 3) The semiconductor device according to any one of claims 1, 2, 3, and 1, and 2, wherein a characteristic impedance of the second power supply wiring is smaller than a characteristic impedance of the first power supply wiring.

（付記４） 前記第２電源配線の長さが、前記第１電源配線の長さより大きい請求項５に記載の配線基板。 (Supplementary Note 4) The wiring board according to claim 5, wherein a length of the second power supply wiring is larger than a length of the first power supply wiring.

（付記５） 前記第１電源配線の一端と前記第２電源配線の一端とが離間していることを特徴とする請求項５、付記４に記載の配線基板。 (Supplementary note 5) The wiring board according to claim 5, wherein one end of the first power supply wiring and one end of the second power supply wiring are separated from each other.

（付記６） 前記第２電源配線が蛇行している請求項５、付記４、５に記載の配線基板。 (Additional remark 6) The wiring board of Claim 5, Additional remarks 4, 5, and the said 2nd power supply wiring meander.

（付記７） 前記第２電源配線の特性インピーダンスが、前記第１電源配線の特性インピーダンスより小さい請求項５、付記４、５、６に記載の半導体装置。 (Additional remark 7) The semiconductor device of Claim 5, Additional remarks 4, 5, and 6 with the characteristic impedance of the said 2nd power supply wiring being smaller than the characteristic impedance of the said 1st power supply wiring.

（付記８） 一対の前記第１電源配線および前記第２電源配線を、複数具備する請求項５または付記４、５、６、７に記載の配線基板。 (Additional remark 8) The wiring board of Claim 5 or Additional remarks 4, 5, 6, and 7 which comprises two or more pairs of said 1st power supply wiring and said 2nd power supply wiring.

１０、４０、６０、７０、８０ 半導体装置
１１ 絶縁性基板
１２、８１ 半導体チップ
１３、７１、８４ ワイヤ（接続導体）
１４、８５ 電源パッド
１５ 外部電源端子
１６、８２ 第１電源配線
１７、６１、７２、８３ 第２電源配線
１８ ビア
１９、７３、８６ 接続パッド
３０ 配線基板
３１ 第１の領域
３２ 第２の領域
４１ 電源
４２ バイパスコンデンサ
４３ 内部抵抗
４４ ノイズ発生源
４５ 出力バッファ
４６ 容量性負荷
７４ 空き領域
Ｎ１、Ｎ２ 接続ノード
Ｍ１ ＰＭＯＳトランジスタ
Ｍ２ ＮＭＯＳトランジスタ 10, 40, 60, 70, 80 Semiconductor device 11 Insulating substrate 12, 81 Semiconductor chip 13, 71, 84 Wire (connection conductor)
14, 85 Power supply pad 15 External power supply terminals 16, 82 First power supply wiring 17, 61, 72, 83 Second power supply wiring 18 Via 19, 73, 86 Connection pad 30 Wiring board 31 First region 32 Second region 41 Power supply 42 Bypass capacitor 43 Internal resistance 44 Noise source 45 Output buffer 46 Capacitive load 74 Free area N1, N2 Connection node M1 PMOS transistor M2 NMOS transistor

Claims (5)

絶縁性基板と、
前記絶縁性基板の第１の面に載置された半導体チップと、
前記絶縁性基板の第１の面に形成され、一端が接続導体を介して前記半導体チップの電源パッドに電気的に接続され、他端が前記絶縁性基板の前記第１の面と反対の第２の面に形成された外部電源端子に接続された第１電源配線と、
前記絶縁性基板の第１の面に形成され、一端が前記第１電源配線の一端に連接して前記半導体チップの周りの空き領域に延伸し、他端が開放されるとともに、一端から他端までの信号伝播時間が前記第１電源配線の一端から他端までの信号伝播時間より長い第２電源配線と、
を具備することを特徴とする半導体装置。 An insulating substrate;
A semiconductor chip mounted on the first surface of the insulating substrate;
Formed on the first surface of the insulating substrate, one end electrically connected to the power supply pad of the semiconductor chip via a connecting conductor, and the other end opposite to the first surface of the insulating substrate. A first power supply wiring connected to an external power supply terminal formed on the surface of 2,
Formed on the first surface of the insulating substrate, one end is connected to one end of the first power supply wiring and extends to a vacant area around the semiconductor chip, the other end is opened, and the other end to the other end A second power supply wiring whose signal propagation time is longer than a signal propagation time from one end of the first power supply wiring to the other end;
A semiconductor device comprising: 前記第１電源配線の一端と前記第２電源配線の一端とが離間し、前記第２電源配線の一端が第２接続導体を介して前記電源パッドに共通に接続されていることを特徴とする請求項１に記載の半導体装置。   One end of the first power supply wiring and one end of the second power supply wiring are separated from each other, and one end of the second power supply wiring is commonly connected to the power supply pad via a second connection conductor. The semiconductor device according to claim 1. 複数の前記半導体チップが互いに前記電源パッドを露出するように積層され、各前記半導体チップの前記電源パッドに前記第１電源配線および前記第２電源配線が前記接続導体を介して電気的に接続されている請求項１に記載の半導体装置。   A plurality of the semiconductor chips are stacked such that the power supply pads are exposed to each other, and the first power supply wiring and the second power supply wiring are electrically connected to the power supply pads of each of the semiconductor chips via the connection conductors. The semiconductor device according to claim 1. 前記第２電源配線の長さが、前記第１電源配線の長さより大きいことを特徴とする請求項１または請求項２に記載の半導体装置。   3. The semiconductor device according to claim 1, wherein a length of the second power supply wiring is larger than a length of the first power supply wiring. 絶縁性基板と、
前記絶縁性基板の第１の面に形成され、一端が接続導体を介して前記絶縁性基板に載置される半導体チップの電源パッドに電気的に接続され、他端が前記絶縁性基板の前記第１の面と反対の第２の面に形成された外部電源端子に接続された第１電源配線と、
前記絶縁性基板の第１の面に形成され、一端が前記第１電源配線の一端に連接して前記半導体チップの周りの空き領域に延伸し、他端が開放されるとともに、一端から他端までの信号伝播時間が前記第１電源配線の一端から他端までの信号伝播時間より長い第２電源配線と、
を具備することを特徴とする配線基板。 An insulating substrate;
Formed on the first surface of the insulating substrate, one end is electrically connected to a power supply pad of a semiconductor chip mounted on the insulating substrate via a connection conductor, and the other end is connected to the insulating substrate. A first power supply wiring connected to an external power supply terminal formed on a second surface opposite to the first surface;
Formed on the first surface of the insulating substrate, one end is connected to one end of the first power supply wiring and extends to a vacant area around the semiconductor chip, the other end is opened, and the other end to the other end A second power supply wiring whose signal propagation time is longer than a signal propagation time from one end of the first power supply wiring to the other end;
A wiring board comprising:
JP2009176731A 2009-07-29 2009-07-29 Wiring board and semiconductor device Pending JP2011034990A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2013135225A (en) * 2011-12-22 2013-07-08 Samsung Electronics Co Ltd Semiconductor package having re-wiring layer

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2013135225A (en) * 2011-12-22 2013-07-08 Samsung Electronics Co Ltd Semiconductor package having re-wiring layer
US9496216B2 (en) 2011-12-22 2016-11-15 Samsung Electronics Co., Ltd. Semiconductor package including stacked semiconductor chips and a redistribution layer

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